Miller, Edward B. (West Warwick, RI)
Eichelberger, Charles W. (Schenectady, NY)

Plaque It!

06/324640

04/16/1985

11/24/1981

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General Electric Company (Bridgeport, CT)

370/462

340/825.520

H02J13/00; H05B37/02; H04Q9/00

340/825.5, 340/825.52

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3491263	LIGHTING SYSTEMS WITH CONTROLLED DIMMING	January, 1970	Isaacs
3508113	INFORMATION-TRANSFER APPARATUS	April, 1970	Isaacs
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3555251	OPTIMIZING SYSTEM FOR A PLURALITY OF TEMPERATURE CONDITIONING APPARATUSES	January, 1971	Shavit
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3582896	METHOD OF CONTROL FOR A DATA PROCESSOR	June, 1971	Silber
3590271	REMOTE CONTROL SYSTEM	June, 1971	Peters
3603961	PROGRAMMED TIMING SYSTEM	September, 1971	Duris
3614378	FLUXLESS HIGH-FREQUENCY ALUMINUM TUBE WELDING WITHOUT INSERTS	October, 1971	Goodell et al.
3622992	SUPERVISION AND CONTROL APPARATUS WITH SELECTIVE DISPLAY	November, 1971	Schoenwitz
3622994	CONTROL AND SUPERVISION SYSTEM HAVING DATA STORAGE	November, 1971	Schoenwitz
3626370	AIR-CONDITIONING CONTROL SYSTEM HAVING DISPLAY MEANS TO SHOW APPARATUS BEING SUPERVISED AND/OR CONTROLLED	December, 1971	Stubbs
3633166	DATA TRANSMISSION METHOD AND SERIAL LOOP DATA TRANSMISSION SYSTEM	January, 1972	Picard
3649873	ARRANGEMENT FOR REMOVAL OF FAULT CONDITIONS IN DIRECT COUPLED INFORMATION TRANSFER SYSTEMS	March, 1972	Vlack
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3706914	LIGHTING CONTROL SYSTEM	December, 1972	VanBuren
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3716096	TEMPERATURE CONTROL AND SUPERVISION SYSTEM FOR A BUILDING AIR CONDITIONING SYSTEM	February, 1973	Berrett et al.
3723753	PROGRAMMABLE IRRIGATION COMPUTER	March, 1973	Davis
3729581	COMPUTER ASSISTED DIAL ACCESS VIDEO RETRIEVAL FOR AN INSTRUCTIONAL TELEVISION SYSTEM	April, 1973	Anderson
3766431	A LIGHTING CONTROL SYSTEM INCLUDING AN ANALOGUE TO DIGITAL CONVERTER	October, 1973	Isaacs
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3796995	REMOTE CODED DUAL STATE CONTROLLER APPARATUS	March, 1974	Stronjny
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3819932	MULTI-COMPUTER AUTOMATIC VEHICLE CONTROL SYSTEM	June, 1974	Auer et al.
3820073	SOLID STATE REMOTE METER READING SYSTEM HAVING NON-VOLATILE DATA ACCUMULATION	June, 1974	Vercellotti
3820078	MULTI-LEVEL STORAGE SYSTEM HAVING A BUFFER STORE WITH VARIABLE MAPPING MODES	June, 1974	Curley et al.
3831059	TIME INTERVAL LIGHTING SYSTEM	August, 1974	LoNigro
3832688	STATUS SENSING AND TRANSMITTING CIRCUIT	August, 1974	Strojny
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3906242	Computerized peak-shaving system for alleviating electric utility peak loads	September, 1975	Stevenson
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3925680	Method and system for regulating peak residential power demand	December, 1975	Dixon
3925704	Lighting system with variable flashing rate	December, 1975	Camic
3940660	Circuitry for load connection and disconnection	February, 1976	Edwards
3942170	Distribution network powerline carrier communication system	March, 1976	Whyte
3964023	Method of and apparatus for selectively controlling a plurality of remotely located loads	June, 1976	Fauchez
3964047	Fire-alarm audible signaling system permitting selective communications and signaling	June, 1976	Antonaccio
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3965336	Radio or television receiver with an automatic station finding arrangement	June, 1976	Grahmann
3971010	Ballasted load control system and method	July, 1976	Falhn
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4001557	Stored program digital process controller	January, 1977	Stephenson
4007458	Digital two-wire irrigation control system	February, 1977	Hollabaugh
4008458	Remote automatic reading system	February, 1977	Wensley
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4177450	Process and method to initiate a receiving and transmitting station linked by a connecting channel of an information exchange system consisting of several transmitting and receiving stations	December, 1979	Sarrand	340/825.5
4259663	Contention interference detection by comparison of transmitted and received signal information	March, 1981	Gable	340/825.5
4376278	Apparatus and method for collision avoidance	March, 1983	Jacobsthal	340/825.5
3697821	LIGHT DIMMING SYSTEM HAVING MULTIPLE CONTROL UNITS	October, 1972	Johnson
3702460	COMMUNICATIONS SYSTEM FOR ELECTRIC POWER UTILITY	November, 1972	Blose

Yusko, Donald J.

Cushman, Darby And Cushman

This is a division of application Ser. No. 89,478 filed Oct. 30, 1979now abandoned.

What is claimed is:

1. Apparatus at plural remote locations permitting non-interfering randomly occurring digital data communication between plural locations via a common data communications link, said apparatus being situated at each of said plural locations and comprising:

data transmitting means for serially transmitting digital binary bit information conveying signals having first and second states onto said communications link as described, one of said first and second states being dominant when transmitted on said link even if simultaneous transmission of the other state on the same link is attempted from another location, said binary bit information conveying signals including unique duration or sequence patterns of said first and second states identifying respective ones of a plurality of output modes of said data transmitting means, said

arbitatration means for monitoring the existence of and first and second states on the link during the time required for the transmission of said binary bit of information, for comparing the state value then being transmitted from its respective remote location with the state value then existing on said link, and for inhibiting further transmission of the data onto said link by its respective data transmission means if there is a difference between the value then being transmitted and the actual state then existing thus eventually leaving only one remote location transmitting on said link.

2. Apparatus as in claim 1 wherein:

said communication link comprises two electrical conductors, and said first and second states comprise high and low impedance states respectively between said conductors.

3. Apparatus as in claim 1 wherein:

said communication link is a bi-directional data communication channel.

4. Apparatus as in claim 1, 2 or 3 wherein said information conveying signals comprise width modulated pulses of electrical signals where the two binary values are represented by different pulse widths occurring as required to represent desired data values within successive bit cells or time periods.

5. Apparatus as in claim 4 wherein said bit cells or time periods have varying total time durations corresponding respectively to the binary value encoded therein.

6. In a programmable system for controlling plural distributed electrical loads including plural relays, each connected to control a respectively corresponding one of said plural distributed electrical loads; plural remotely located transceiver decoder circuits all connected in common to a data link for controlling a predetermined subset of said relays in response to received data signals and for transmitting data signals relating to such control onto said data link; and a programmable central controller connected to provide said received data signals to each of said transceiver decoders via said data link; the improvement comprising:

access means at each transceiver decoder site for monitoring the busy or free status of said data line and for inhibiting initial transmitting access thereto from the respectively associated transceiver decoder unless a free status exists;

data transmitting means within each transceiver decoder for serially transmitting digital binary bit information conveying signals having first and second states onto said data link as desired only if permitted by said access means, one of said first and second states being dominant when transmitted on said link even if simultaneous transmission of the other state on the link is attempted by another transceiver decoder; and

arbitration means at each transceiver decoder site for monitoring the existence of said first and second states on the link during the time required for the transmission of each binary bit of information, for comparing the state value then being transmitted from its respective transceiver decoder with the state value then existing on said link, and for inhibiting further transmission of data onto said link by its respective said data tansmission means if there is a difference thus eventually leaving only one transceiver decoder in communication on said link and doing so without interferring with the communication from said one transceiver decoder.

7. An improvement as in claim 6 wherein:

said data link comprises two electrical conductors, and

said first and second states comprise high and low impedance states respectively between said conductors.

8. An inprovement as in claim 6 wherein said data link is a bi-directional data communication channel.

9. An improvement as in claim 6 wherein central processor controls a relays in at least one pre-programmed time-dependent sequence.

10. An improvement as in claim 6, 7, 8 9 wherein said information conveyng signals comprise width modulated pulses of electrical signals where the two binary values are represented by different pulse widths occurring as required to represent desired data values within successive bit cells or time periods.

11. An improvement as in claim 10 wherein said bit cells or time periods have varying total time durations corresponding respectively to the binary value encoded therein.

12. Apparatus at plural remote locations permit non-interferring randomly occurring digital data communication between plural remote locations via a common data communication link, said apparatus being situated at each of said plural remote locations and comprising:

access means for monitoring the busy or free status of said communication link for inhibiting initial access thereto from its respective remote location unless a free status exists,

data transmitting means for serially transmitting digital binary bit information conveying signals having first and second states onto said communications link as desired only if permitted by said access means, one of said first and second states being dominant when transmitted on said link even if simultaneous transmission of the other state on the same link is attempted from another remote location,

arbitration means for monitoring the existence of said first and second states on the link during the time required for the transmission of each binary bit of information, for comparing the state value then being transmitted from its respective remote location with the state value respective remote location with the state value then existing on said link, and for inhibiting further transmission of data onto said link by its respective said data transmission means if there is a difference thus eventually leaving only one remote location in communication on said link and doing so without interferring with the communication from said one remote location, and

wherein said information conveying signals comprise width modulated pulses of electrical signals where the two binary values are represented by different pulse widths in said first state as required to represent desired data values within successive bit cells or time periods, each such width modulated pulse being separated from the next such pulse by a period of said second state, said period of said second state providing said apparatus at each of said plural locations time to process the preceding information bit.

13. Apparatus as in claim 12 wherein said period of said second state is of a fixed duration thereby making the total time required to tansmit a binary bit of information vary as a function of the information value being transmitted.

14. Apparatus as in claim 13 wherein said communication link comprises two electrical conductors, and said first and second states comprise high and low impedance states respectively between said conductors.

15. Apparatus at plural remote locations permitting non-interfering randomly occuring bi-directional digital data communication via a common communication channel between a master apparatus and a plurality of master/slave apparatuses, said apparatus comprising:

master apparatus operating in a master mode wherein it can access the common communication channel whereever free and without regard to any predetermined time schedule, said apparatus being adapted to transmit master and slave mode commands to a master/slave apparatus;

means for receiving and decoding a data signal on said communication channel, said digital data signal including a command for a master/slave apparatus to operate either in said master mode or in a slave mode; and

means for inhibiting transmitting access to said communication channel for a predetermined period of time in response to a slave mode command from said master apparatus.

16. Apparatus according to claim 15 wherein said communication channel is bi-directional.

17. Apparatus according to either of claims 15 or 16 wherein said master and slave mode commands are width modulated pulses.

18. Apparatus according to claim 1 further including access means for monitoring the busy or free status of said communication link for inhibiiting access thereto from a remote location unless a free status exists.

INTRODUCTION

This invention generally relates to methods and apparatus for controlling distributed electrical loads. This invention also relates to novel components, combinations and sub-combinations capable of implementing such control. More particularly, it relates to a programmable microprocessor based system having a central controller under program control which communicates with plural distributed microprocessor-based transceiver decoders (also referred to as transceivers) connected together through a common communication channel (e.g. an unshielded twisted pair of wires in the presently preferred embodiment). Remotely located switches and/or sensor devices can be employed throughout the system for modifying the nominally defined time-dependent schedule of load control functions and for rendering the system condition responsive. Control inputs may also be received at the central processor site via telephone connections. As disclosed in the presently preferred, nonlimiting, specific exemplary embodiment, the system is used to control the distributed lighting loads throughout a building, cluster of related buildings, a building site, etc. However, the system is capable of controlling virtually any type of electrical load according to a user defined schedule and/or according to conditions sensed at remote locations. Such loads could include heating systems, air-conditioning systems, etc.

Programmable electrical load control systems of this general type have been known and proposed heretofore by the applicants and/or their assignee. For example, a microprocessor based distributed control system for lighting loads in a building was disclosed by T. K. McGowan and G. E. Feiker in an article entitled "A New approach to Lighting System Control" published in the Journal of IES, Oct. 1976 (pages 38-43) and a subsequent discussion of this article by others appears at pages 125-126 of the January 1977 issue of that Journal.

An early approach is described in two pending, commonly assigned, U.S. patent applications:

a. Ser. No. 809,939, filed June 24, 1977, entitled Distribution Control System and naming George E. Feiker as inventor now issued as U.S. Pat. No. 4,173,754; and b. Ser. No. 029,614, filed Apr. 13, 1979, as a division of Ser. No. 809,939, entitled Distribution Control System and filed Apr. 13, 1979, naming George E. Feiker as inventor now issued as U.S. Pat. No 4,185,272.

Feiker was instrumental in having a first rudimentary lighting control system developed and installed in a single room at the Nela Park Plant of General Electric in Cleveland, OH. Some of the actual design work was done by C. Eichelberger for this first rudimentary lighting control. This installation is described in the article entitled "A New Approach to Lighting System Control" by T. K. McGowan and G. E. Feiker along with some projections of alternative ways to achieve similar results.

A system for reducing noise error was developed and is the subject matter of Pat. No. 4,091,361 issued on application Ser. No. 748,932, filed Dec. 9, 1976 for Noise-Immune Carrier Current Actuated Control; naming Charles W. Eichelberger and Philip M. Garratt inventors.

Based on a substantially different approach to lighting control, the present applicants designed and installed an experimental "first generation" system which incorporates several improvements. This first generation system and several features thereof are described in earlier copending, commonly assigned, patent applications or issued patents the texts of which are incorporated herein by reference:

a. application Ser. No. 966,816 filed Dec. 6, 1978 entitled Programmable Energy Load Controller System & Methods and naming Charles W. Eichelberger and Edward B. Miller as inventor now issued as U.S. Pat. No. 4,213,182;

b. application Ser. No. 871,988, filed Jan. 24, 1978 entitled Load Control Processor and naming Edward B. Miller and Charles W. Eichelberger as inventors; now issued as U.S. Pat. No. 4,167,786.

c. application Ser. No. 871,991, filed Jan. 24, 1978 entitled Interface Driver Circuit and naming Edward B. Miller and Charles W. Eichelbeger as inventors;

d. application Ser. No. 871,990, filed Jan. 24, 1978, and entitled Programmable Real Time Clock and naming Charles E. Eichelberger and Edward B. Miller as inventors now issued as U.S. Pat. 4,168,531.

While the prior art load control systems just referenced have been successfully operated at an experimental test site so as to produce significant energy savings which permit the cost of such a system to be recovered in a very short time, operating experience with these earlier prior art systems has also revealed several areas where further significant improvements in operating convenience and capability would be highly advantageous. We have now discovered many such improved features which are incorporated in the "second generation" control system of this invention.

One of the primary commercial applications for programmable load control is for the control of lighting, particularly for large office bui.ldings, or groups of office buildings. Effective lighting control requires achieving the right amount of light where it is needed and when it is needed. Energy and money are wasted when there is too much or too little light for a particular task, when lights are on where not needed and when lights are not on when needed. In a typical office, lighting accounts for 30-40% of the total electrical load and in many cases a substantial amount of this light is wasted by having lights on when not needed or on at higher levels than required.

In addition to energy savings, better lighting control can increase flexibility in future use of office space. Control of individual fixtures can allow offices, classrooms or other space to be rearranged and partitions moved without expensive, hard wiring changes. With adequate control, ceiling systems can remain unchanged even when work areas are rearranged. Furthermore, the ability to control individual fixtures also permits finely tuned lighting arrangements for different activities, for example, normal lighting or desk work; reduced lighting for conferences; and dim lighting for slides, security lighting, etc.

Since lighting relates to people and tasks, the ability to control lighting can be used to control the use of space. For example, unwanted use of an area can be minimized by not allowing the lighting to be controlled by unauthorized personnel. Thus, the use of conference rooms can be curtailed for unauthorized meetings or as temporary work areas for tasks which should be performed in offices.

In a typical office building, using circuit breaker control, around 6:00 a.m. when people start arriving, the lights on each floor would be turned on by the first person to arrive. The lights would stay on, at full intensity all day. About 6:30 p.m. when most offices are empty, a guard would begin to switch off lights. A cleaning crew would begin work about this time and hopefully switches off each floor as they finish. By 11:30 p.m. when the cleaning crew is finished, all lights should be off. This scenario for a typical office building inherently includes a significant degree of energy waste. For example, lights are on when people are not in the area, near the beginning of each working day and during lunch hour. There is no way to provide a lower light level for tasks which do not require strong lighting. It may be appropriate that cleaning and maintenance chores in the evening be performed at a lower light level than could be used for the routine work of office workers during the day. In addition, the amount of daylight near window areas is not taken into account. It is not necessary to light areas near windows to the same extent that more internal ofice areas must be lit.

The programmable load control system as set forth herein allows for control over these built-in energy wasting situations. It calls for the automatic shutting off of lights during the progammed non-use times while permitting selected overrides for providing light in the immediate area of a person working outside his normal hours. It allows light levels to be altered in accordance with a pre-defined schedule such that tasks performed at or during preset times requiring a lower light level than normal will not waste power. Futhermore, in areas near windows, where daylight adds a substantial amount of light, a photo relay is used to automatically reduce lighting levels when adequate sunlight is available.

The difference in energy cost for the normal electrical load for a typical office building and that for a building controlled by the present invention is substantial. A typical payback time for the cost of installation of the control system is 1-2 years.

The presently described system for distributed electrical load control for lighting provides a degree of flexibility and economy not previously available with any prior system. It uses mechanically latching relays to control groups of lighting fixtures or other loads. These relays are turned on or off by a 24-volt pulse. However, the relays are not hard wired to manual switches, time switches, photocells, etc. All control comes from a central controller, through a data line to a transceiver decoder associated with the relay to be operated.

The central controller utilized in the present system is micro-computer based and has an internal program providing the function of a user programmable load control system. It incorporates a 7-day clock and provides minute-by-minute control of the entire load system including up to 8000 separate relays according to a predetermined schedule when operating in its automatic mode. The data format selected would allow the use of up to 16,000 relays. However, the memory space available in the memories selected for this presently preferred embodiment limits the number of relays to 8,000. A load control schedule can be entered manually through a keyboard or by reading mark-sense cards through a cardreader. In addition to the automatic schedule, any lighting circuit can be controlled manually from the keyboard of the central controller when operating in its manual mode. The central controller also provides monitoring of the system and can display the on/off state of each relay. If hard copy records are desired, the controller can print data out through a standard printer.

A low voltage twisted pair data line running throughout a building under load control forms a communication channel which connects the central controller to a plurality of transceiver decoders and provides for two-way (bi-directional) communications between the controller and each of the transceiver decoders.

Up to 32 relays are coupled to each transceiver decoder. Each relay turns on and off a particular load in response to a command from the central controller, propagated through the data line to its associated transceiver decoder. The transceiver decoder is generally located near the loads to be controlled by its relays so as to minimize the amount of hard wiring needed. The transceiver decoder receives a signal from the central controller over the data line when one of its relays is to be opened or closed and transmits an activating pulse to the relay.

Communication between the controller and each of the transceivers is bi-directional. Each transceiver decoder can send a message to the controller requesting that the controller issue a command to alter the state of a particular load.

Each transceiver decoder has 8 switchleg inputs which can be connected to manually operable or condition responsive switches, either of the momentary or maintained contact type. Each switch can control "on" or "off" a designated subset of lighting control relays, known as a sector, anywhere in the building. This is accomplished by activating a switch causing the transceiver decoder to send a signal through the data line to the central controller. The central controller interprets that signal and determines which relays require activation and in turn sends a signal to the transceiver decoder involved for actuating the relays associated with the lights to be turned on or off. Automatically actuated switches such as photo-relays can be connected to a switchleg input of a transceiver decoder for condition responsive automatic control such as fire and smoke detection.

Analog sensors such as thermistors or photo-transistors can be wired to a transceiver decoder through an analog sensor input circuit in each transceiver decoder. These analog sensing devices are interrogated (polled) by the central controller which may decide to send a command to a transceiver decoder to operate selected relays. The analog sensors enhance the condition responsive capability of the system. Any condition that can be sensed and transformed into a variable impedance or variable voltage condition can be polled by the central controller so as to make the system responsive to that condition.

The central controller can also accept manual override from a standard telephone of those sectors that have been user defined.to have "priority" status. By connecting the telephone system to the central controller, any group of relays can be controlled by any Touchtone™ or push-botton telephone (with appropriate interface equipment a standard dial telephone access is possible).

The system is highly adaptable to changes in space utilization and to personnel shifts. Simply by altering the data base originally defined by the user, time dependent schedule changes can be made, different subsets of loads to be controlled simultaneously can be defined and switches can be programmed to control different loads. This flexibility is achieved by the entry of new data to replace previously entered data. Such data replacement can be accomplished either by reading cards or by making keyboard entries and does not require expensive re-wiring. The system can be easily expanded by extending the twisted pair data line and adding more transceiver decoders without affecting the existing installation. For excessively long data lines, repeaters (boosters) can be used. Therefore there is no practical limitation of system size other than the address space of the data structure (a ten bit address specifies 1024 unique devices). More than 1024 transceiver decoders can be used if multiple transceiver decoders are to respond to an identical address.

In the earlier referenced prior art systems, the central controller was generally in one way communication with the remote distributed receiver/decoders which, in turn, controlled a bank of up to 16 relays. However, the present second generation system of this invention now provides for bi-directional data communication between the central controller and plural remote distributed transceiver decoder units which can each control a plurality of relays. Futhermore, provisions are now made for remotely located switchlegs connected to any desired transceiver decoder as remote inputs to the central controller. That is, the actuation of a specific remotely located switchleg will cause a unique signal to be transmitted back to the central controller. The controller, in turn, will interpret such actuation in accordance with a desired programmable function. Typically, such a remote switchleg might be used by the controller to modify the lighting load in a predetermined area of the building. However, with subsequent reorganization of furniture, office walls, etc., the particular sector of lighting load affected by the switchleg can be redefined (i.e., different relays associated with a sector number) as desired. Furthermore, the function controlled by such a remote switchleg could be re-programmed at will to control other lighting loads remote from the switchleg, heating or air conditioning loads, or any other control functions as might be appropriate.

Bi-directional communcation with the central processor also permits the use of remotely located electrical sensors (i.e., photocells, thermisters, etc.) so as to remotely control selected, programmable functions. For example, light sensors at the periphery of a building might be used to control the lighting load at the periphery of the building in response to ambient light levels incident through transparent window panes or the like. Proximity sensors might also be used to control loads as a function of human presence.

The microprocessors used in the present exemplary embodiment of this invention (one microprocessor is each transceiver decoder and one in the controller) are controlled by programs permanently embodied as firmware in a read only memory (ROM). Accordingly, once the ROM has been appropriately structured, e.g., by initial IC manufacturing techniques or by selectively severing fusable links within the ROM or by injecting charge under oxides (floating gate avalanche injected metal oxide semiconductor), the entire system of interconnected integrated circuits, discrete components, and the like becomes a fixed-purpose control system defined by a unique physical structure--albeit certain control functions remain "programmable" by altering the user defined data base stored in RAM devices or the like. However, as those in the art will appreciate, similar systems can be realized by storing the control determining program in other forms of memory devices which are not permanently altered by their content values (e.g., read/write memory devices such as a RAM or a PROM). Furthermore, many of the digital microprocessor-based circuit operations in the present exemplary embodiment could be realized in analog discrete and/or integrated circuits (e.g., a phase-lock oscillator loop as described below). While the presently preferred exemplary embodiment thus includes a fixed-purpose computer, it should be appreciated that this invention can be realized in many other equivalent forms without in any way departing from the novel and patentable features of this invention.

The data structures employed for controlling loads have been organized in this invention so as to provide a more flexible, convenient and comprehensive system operation. For example, a greater number of load control patterns than were feasible using the referenced prior art teachings (e.g., the "on" and "off" state of each controlled relay in the system or part of a system may comprise a pattern) are realized by using variable length records, by permitting the definition of partial load definition patterns and by dynamically allocating the available memory locations for such pattern data.

Furthermore, in the present invention as contrasted with prior art inventions referenced above greater system flexibility is achieved by pemitting the time dependent scheduling of sectors rather than of entire load patterns. A sector is defined as a particular sub-set of all the system relays. In turn, when a particular sector is scheduled (for a particular day of the week and time of the day) a particular one of a plurality of separate available and predefined patterns is also identified. Since patterns can be defined as sub-patterns to include less than all of the system transceivers (but all relays for any transceiver included in a given pattern or sub-pattern must be defined therein) and since there is virtually no limit to the number of sectors that can be defined (including overlapping sub-sets of relays), the actual programming of desired load control functions for a given building can be defined with virtually unlimited flexibility.

According to the commonly assigned prior art system referred to above, one was limited to the scheduling of a relatively small number of patterns where each pattern included all relays in the system. However, using the new virtually unlimited flexibility of the second generation system of this invention, all kinds of peculiar operating conditions can be easily accommodated. For example, employees on different "flex time" hours of work can be easily accommodated. Furthermore, when one group of employees at some location in the building changes its desired flex time hours, such changes may be easily accommodated. Applicants know of no other system providing a degree of flexibility adaptable to "flex time". Furthermore, where a building has many different tenants, the peculiar operting modes for any given tenant can be more easily accommodated with this second generation system of scheduling sectors rather than patterns.

Accordingly, the novel organization of data storge structures, their identification, and their intended meaning within the second generation system of this invention offer significant advantages over the prior art.

The second generation system of this invention also permits sectors to be defined and controlled, if desired, such that no remote input can achieve a priority override.

In the normal (automatic control) mode of this invention, the central controller constantly self-diagnoses the system for various types of faults or errors. For example, the integrity of the data communications circuit is tested from time to time. After instructing a remote transceiver to control a relay to a particular state, the central controller can obtain feedback information from the transceiver so that it may verify that the intended relay actually was controlled as intended. If any of these automated system testing procedures detects a problem, the system operator is notified via communcations on the processor console. At that time, the operator may enter a manual control mode during which normal scheduling and automatic functioning of the processor is temporarily interrupted. In the manual control mode, the operator can cause any sector to assume a desired relay state without regard to the scheduled program.

In the presently preferred exemplary embodiment, all of the transceivers are interconnected to the central controller over a common twisted pair of electrical conductors which are typically unshielded. Communications are bidirectional between the central controller and any of the transceivers (possibly as many as a thousand or so). Furthermore, each transceiver is also microprocessor-based and may initiate a transmission at any arbitrary time (asynchronously) in response to control inputs from connected switchlegs, electrical transducers, etc.

A form of pulse width modulation (modified ratio signalling) is used to transmit a serial bit stream. The data is transmitted in blocks of 40 bits and preceded by an inter-block gap and a predefined preamble.

Prior to transmission on the common party line, ny given device first of all monitors the line to see if it is free. A desired transmission is delayed until the line is found to be free. Nevertheless, with so many separate devices all independently capable of arbitrary communication initiation times, it will not be uncommon for two or more transceiver decoders to simultaneously sense a free line and to begin simultaneous transmissions. Indeed, if two or more devices have data to send and are waiting to send such data because the line is currently being used by another device, they may well both find the line free at the same time and begin transmitting simultaneously.

A special bus arbitration technique is therefore employed in such circumstances to cause all but one of the interferring transceivers to drop out of operation while yet permitting the one selected transceiver to continue its data transmission without any loss of any of the data which any transceiver has begun transmiting For example, if two transceivers begin simultaneous transmission, the state of the transmission line will be identical anyway through the inter-block gap (2-6 milliseconds) and the preamble of 50% duty cycle pulses (during which a phase lock loop is used to lock a clock oscillator onto the correct frequency for interpreting the following 40 bits of data). While the data is actually being transmitted, each transceiver does a bit-wise read-after-write sampling of the common transmission line. If the bit that is read is not the same as that which the transceiver must attempted to transmit, then this is taken as an indication that another transceiver is transmitting different data (by holding the transmission line at a low impedance level for a longer time or sending different data bits during the pulse width modulation transmission of a single bit) and the transceiver which has detected this difference then drops out, aborts its attempted data transmission, saves its data, and waits to try again the next time it detects the data line as being free.

Accordingly, as soon as competing transceivers attempt to transmit differing data bits during the same bit cell, the transceiver decoder which has attempted unsuccessfully to transmit a high impedance signal on the data bus (which is still being held at a low impedance value by another transceiver) will immediately detect this condition and abort any further transmission attempts until the line is again detected as being free (such as by detecting a high impedance bus line condition which persists for more than three nominal bit periods). In this way, only one of the transceivers will continue to transmit all of its 40 bits and they will be transmitted without any interference from other transceivers in spite of the fact that the other transceivers may have initially been competing to transmit their own data at the same time.

Each transceiver in this second generation system of this invention is capable of several different modes of opeation. For example, in one mode it may accept data transmitted from the central controller relating to desired controlled relay states. In another mode, it may transmit the existing controlled relay states back to the central processor. In yet another mode, it may transmit data to the central processor repesenting the current value of a connected electrical sensor (e.g., photocell, thermistor, etc.). In yet another mode, it may transmit data back to the central processor indicating that a particular connected switchleg has been activated. In the presently preferred exemplary embodiment, the data bit stream (e.g., 40 bits) includes a special function word (e.g., 3 bits) which is utilized to select the different modes of transceiver operation and/or to provide for enhanced data security or for specifying the correct interpretation to be accorded the remaining bits of a given data block.

The self-diagnosis of transceiver decoder failures (i.e., failure of a transceiver to confirm that it has carried out a prior instruction with respect to a particular relay or respond to any command or status check from the central controller) is followed by continuous reinterrogation of that particular transceiver until either the manual mode is entered by the operator or until the diagnosed transceiver failure is self-cleared by successfully receiving a transmission from that paticular transceiver. Thereafter, if the transceiver has not confirmed a correct state for the relay in question, appropriate instructions are re-transmitted and the whole cycle of relay state verification and . failure self-diagnosis is carried out again.

If the data line becomes stuck in a low impedance state, then it is assumed that one of the connected transceiver decoders has seriously malfunctioned or that there is an electrical short on the data line. Each of the transceiver decoders is connected to the common data line through a fusable link. Accordingly, if the low impedance condition exists in a given transceiver, it may be physically disconnected from the data line by driving a relatively high current (e.g., 1 amp) pulse down the data line. The central processor is programmed so as to carry out this self-correcting function whenever the data bus is detected as being stuck in a low impedance state.

If a whole sequence of successive transceivers are self-diagnosed as failing to communicate, it probably indicates an open condition in the common data line and the approximate location of the open condition can be deduced by noting the location of the group of transceivers for which failures are indicated.

A non-volatile storage system such as a magnetic tape micro-cassette device is utilized for storing programmable data (i.e., schedules, patterns, sector identification, etc. In the event of power failures or for any other desired reason, the program information for a particular system can then be read into the central processor from this micro-cassette. However, because the micro-cassette tape drives presently available are not of very high quality for use in digital systems special clocking techniques have been employed. For example, because the frequency of digital signals read off the micro-cassette will normally vary significantly during the course of a given reading of the tape, special resynchronization self-clocking techniques are utilized to keep a clock circuit synchronized with the data being read from the tape. In the presently preferred exemplary embodiment, a continuous weighted average of detected data pulses is used to resynchronize the clock circuit. This results in a continuous lock on the clock frequency with the most recently detected bit frequency being the most effective in controlling the clock frequency. Using this technique, variations of bit frequency approaching 50% in only a single clock cycle may still be successfully read.

BRIEF DESCRIPTION OF THE DRAWINGS

These and other objects and advantages of this invention will be more completely understood by study of the following detailed description of the presently preferred exemplary embodiment of this invention in conjunction with the accompanying drawings, wherein:

FIG. 1 is a general block and pictorial diagram of the apparatus for controlling distributed electrical loads according to the present invention;

FIG. 2 is a graphical representation of various hypothetical data wave forms illustrating the communication protocol;

FIG. 3 is a flow chart illustrating the transmission sequence utilized by a transceiver decoder for communicating with the controller;

FIG. 4 is a flow chart illustrating the data line arbitration protocol;

FIG. 5 is a general block diagram of a transceiver decoder;

FIG. 6 is a diagrammatic representation of the format of a data stream;

FIG. 7 is a detailed signal and pin assignment for the microcomputer in a transceiver decoder;

FIG. 8 is a schematic diagram of the data input and output circuit of a transceiver decoder;

FIG. 9 is a schematic and block diagram of the analaog sensor section of a transceiver decoder;

FIG. 10 is a schematic diagram of the watchdog reset circuit of a transceiver decoder;

FIG. 11 is a schematic diagram of the switchleg input circuit and switchleg jumper circuit of a transceiver decoder;

FIG. 12 is a schematic diagram of the relay drive circuitry of transceiver decoder.

FIG. 13 is a functional block diagram of the microcomputer in each transceiver decoder;

FIG. 14 is a more detailed block diagram of the receiver handler block shown in FIG. 13;

FIGS. 15 and 15a show a flow chart illustrating the logic flow of the receiver function of a transceiver decoder;

FIG. 16 is a more detailed block diagram of the transmitter handler block shown in FIG. 13;

FIG. 17 is a more detailed block diagram of switchleg data register and control block shown in FIG. 13;

FIG. 18 is a general block diagram of the controller;

FIG. 19 is a schematic diagram of the data I/O circuit of the controller;

FIG. 20 is a functional block diagram of magnetic tape device 72, magnetic tape interface 73 and the logic built into the controller's microprocessor related to the reading of data from magnetic tape device 72;

FIG. 21 is a flow chart of the weighted averaging technique implemented by the phase lock loop of the transceiver decoder;

FIG. 22 is a graphical representation of serial data read from a magnetic tape illustrating the self adjustment of threshold levels;

FIGS. 23 and 23a is a flow chart showing the updating function of the pseudo clock interrupt;

FIG. 24 is a diagram showing the various memory storage areas associated with the controller;

FIG. 25 is a more detailed diagram of the memory storage areas within the controller's RAM;

FIGS. 26 to 26c show a flow chart of the executive associated with the controller;

FIG. 27 is a flow chart illustrating the telephone answering task;

FIG. 28 is a flow chart illustrating the telephone maintenance task;

FIG. 29 is a flow chart illustrating the telephone decoder task;

FIG. 30 is a flow chart illustrating the telephone service task;

FIGS. 31 and 31a show a flow chart illustrating the data line checker task;

FIG. 32 is a diagram illustrating the dynamic allocation of memory storage areas within the controller's RAM;

FIGS. 33 (a), 33(b), 33(c), and 33(d), are photocopies of mark-sense data input cards (partially completed for particular data) for use with the exemplary embodiment.

FIGS. 34 and 34a show a schematic diagram of the keyboard and interface; and

FIG. 35 is a perspective view of the console of the central controller.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

System Overview

Referring now to FIG. 1, there is shown a general block and pictorial diagram of the apparatus for controlling distributed electrical loads according to the present invention.

The heart of the apparatus for controlling distributed electrical loads is a central controller 50 which automatically controls a user-defined, time-dependent lighting schedule in accordance with a built-in 7-day clock. Operating in a manual mode, controller 50 provides for control of any lighting circuit through its keyboard (not shown in this Figure). For operation in its automatic mode, controller 50 accepts a user defined data base specifying sectors to be controlled (which relays are defined to be in each sector), patterns specifying the states of all relays or any subset of relays, time schedules (when a particular sector or sectors will assume the relay states defined by a particular pattern), switches and condition responsive switchleg inputs (which relays will be activated in response to each particular switch), and condition responsive relationships controlled by analog sensors (a user determines the criteria for analog sensor activation). This data is entered through its keyboard or via mark-sense data cards. Mark-sense data cards carrying scheduling, sector and priority status (including priority erase time), switch, and pattern information are read by a card reader 52 coupled to controller 50. A printer 54 can be coupled to controller 50 to provide a hard copy printout of the user supplied data base, a list of the status of all relays, any priority sector overrides that are in effect and the total number of relays in an "on" state along with the day and time.

Controller 50 is coupled to a plurality of transceiver decoders 56 (labeled 56 (1), 56 2), . . . 56 (N)) in the figure. The coupling from controller 50 to transceiver decoders 56 is achieved via a data line 58 constituted by a twisted pair of wires. Data line 58 provides a bi-directional communications channel for communication between controller 50 and any of transceiver decoders 56. Associated with each transceiver decoder 56 are a plurality of relays 60 (up to 32 relays) for turning "on" or "off" individual loads 62.

All commands including those resulting from a condition response for changing the state of a relay 60 (and its associated load 62) come from controller 50. However, controller 50 can be requested by a user to initiate a command for changing the status of a particular relay 60 and its associated load 62. Through telephone data sets 64, up to three users can simultaneously access controller 50 via telephones 66. Telephone data sets 64-0, 64-1 and 64-2 provide for interface between controller 50 and the standard public telephone system so that a user can call controller 50 from any location desired. For example, a user could initiate a lighting control function from his home by calling controller 50 through data set 64 before he leaves for the office. Secret codes can be employed to restrict telephone access to authorized persons only.

It is also possible to communicate with controller 50 via transceiver decoders 56. Each transceiver decoder 56 includes provisions for remote switches 68 to be coupled to switchleg inputs thereof. Activation of a remote switch 68, either of the momentary type or maintain type, will cause its associated transceiver decoder 56 to communicate with central controller 50 so as to request a lighting control command to be issued thereby. Sensors having a switch output can be substituted for a manually operable switch (such as switch 68 shown in FIG. 1) to permit a condition responsive override (i.e., fire or smoke detector having a relay output that closes when heat or smoke levels exceed predetermined thresholds).

In addition, analog sensing devices such as a light sensor 70 can be coupled to an analog sensor input section of transceiver decoder 56. These sensors can be polled (interrogated) by controller 50 to provide information related to light levels, heat levels, etc. Based upon the information provided by these analog sensors, controller 50 can issue appropriate commands for altering the status of selected relays. The incorporation of analog sensors and associated information generating capability in transceiver decoders 56 and the use of condition responsive switches coupled to switchleg inputs of the transceiver decoders provide a condition responsive capability for the system.

Controller 50 can be coupled to a non-volatile memory storage system such as a magnetic tape device 72 for storing sector, pattern switch, priority erase time and schedule information. Thus, if controller 50 were to lose power for a substantial period of time, such that all data stored in a volatile form of memory were lost, the data could be easily recovered through the magnetic tape device 72. Means are provided within controller 50 for reading the data stored within magnetic tape device 72.

Because the micro-cassette tape drives presently available for tape device 72 are not of very high quality for use in digital systems, special clocking techniques are employed. For example, because the frequency of digital signals read off the micro-cassette will normally vary significantly during the course of a given reading of the tape, special resynchronization self-clocking techniques are utilized to keep a clock circuit synchronized with the data being read from the tape. A continuous weighted average of detected data pulses is used to resynchronize the clock circuit. This results in a continuous lock on the clock frequency with the most recently detected bit frequency being the most effective in controlling the clock frequency. Using this technique, variations of bit frequency approaching 50% in only a single clock cycle may still be successfully read.

Communications Link

As stated, communication between controller 50 and each of transceiver decoders 56 is via a data line 58 formed by a single twisted pair of wires, constituting a bi-directional data communication link or bi-directional communications channel. Both controller 50 and each of transceiver decoders 56 include circuitry for transmitting and circuitry for receiving information. The communication link provides a protocol for the transfer of information to and from these communicating points. The protocol insures that information transmitted and received is free of errors and will not be garbled or interfered with by other communication devices also connected to the data communication link. The communication link, since it can be coupled to different types of synchronized machines each running on an independent clock, is independent of any system timing. The communication link is bi-directional in nature and in one selected mode provides for the utilization of data verification as well as interactive data processing to insure data security while maintaining system throughput.

Arbitration is provided for resolving any bus conflicts arising during simultaneous transmission of two or more control points without garbling, degrading, or interferring with any data being transmitted. The arbitration scheme is suitable for use with the load control system described herein or independently thereof.

As used throughout the description of the communication link, the term "communication point" will be used to refer to any point connected to the data link that has transmitting and/or receiving capability; thus including both controller 50 and all of transceiver decoders 56. The terms "data communication link" and "communication link" include both data line 58 and the protocol in which data is transferred between communication points. The terms "time to compute mode" and "time to compute state" define a time period during which a communication point is not monitoring the communication link. This time is overhead to allow a receiving device sufficient time to process and decode the incoming signal. The term "lockout" is defined to be a mode in which specific communication points are using the communication link in an interactive manner locking out other points from interfering.

The protocol of the communication link defines two possible signal states of the communication link. An active state refers to the state in which the actual information and clock are found during a transmission. As applied to data line 58, the "active" state is defined to be the existence of a voltage potential of 10-30 volts between the two wires of data line 58. The "inactive" state refers to a state wherein the voltage between the two wires of data line 58 is less than 10 volts. The inactive state is of arbitrary duration and is essentially ignored during a transmission sequence. By utilizing a dedicated twisted pair of wires for data line 58, a bus arbitration technique and the data communication protocol, base band signals are transmitted between communication points without the need of extra modulating and demodulating devices. Of course, other communications channels such as power lines, radio channels, etc., could be utilized with appropriate modulating and demodulating devices. The use of an interactive data communication link allows a single communication point to be polled and interrogated without interferring with other communication points. However, other communication points can be actuated asynchronously to use the data line and send information on command from a remote user.

The protocol is based upon a modified form of a standard 1/3, 2/3 pulse-width modulated signaling technique. This modified pulse width modulated signaling technqiue is hereafter referred to as "modified ratio signaling".

Controller 50 is coupled to a plurality of transceiver decoders 56 via data line 58. Controller 50 is utilized as the command controller that transmits load control information over the data communication link (including data line 58) to the remote transceiver decoders.

Controller 50 is also responsible for normal system maintenance, i.e., the controller interrogates the transceiver decoders in order to verify the state of their relays as well as transceiver decoder operation. This maintenance function is achieved through the same bi-directional communication link between transceiver decoders 56 and the controller 50. At the time when controller 50 is interrogating a particular transceiver decoder 56 for either specifying relay information or checking the status of the transceiver decoder, individual polling is used. Individual polling refers to a transceiver decoder answering a specific question by controller 50 immediately upon receipt of the question. No other transceiver decoder 56 will be allowed to respond to a question directed to a particular transceiver decoder. This condition is defined to be transceiver decoder lock-out as will be further described.

Transceiver decoders 56 are capable of transmitting switch input information from a remote switch 68 coupled to a switchleg input thereof immediately upon its actuation by a user. In this mode, the transceiver decoder 56, to which the remote switch 68 is coupled, responds to a switch input on command of the remote user and does not wait for or require controller 50 to poll for information. This form of data line control is known as asynchronous access of the data communication link. Accessing the data communication link by this method eliminates the need for polling schemes that take much mode time and degrade system throughput. The throughput that is realizable by this asynchronous bus access is solely dependent on the current activity on the data link. Therefore, if the data link is not being utilized by another transceiver decoder 56 found on the data bus, the transfer of information from the closure of a remote switch 68 will occur immediately from the particular transceiver decoder 56 to which the switch is connected to controller 50.

In summary, a transceiver decoder 56 will use data line 58 when there is information requested by controller 50 or it will use the data line asynchronously upon a switch input command at its remote control point. Information is transferred in a half duplex form of communication.

The data communication link can couple controller 50 with up to 1,024 transceiver decoders 56. This limitation results from the data bit stream format described hereafter.

Referring now to FIG. 2 there is shown a graphical representation of various hypothetical data waveforms describing the communication protocol. FIG. 2A illustrates that a transmission sequence starts with the data line deemed "free for access or usage". The line free condition is an active (high impedance) state of the line and corresponds to a voltage between the two wires of data line 58 of from 10 to 30 volts. The communication point in need of gaining access of the data communication link sends a long interblock gap (IBG) to grab the line. After the data line has been accessed, a preamble is sent so that the other communication points receiving the data will lock in on the data signal and establish the data rate. The regular IBG follows so that the system may be synchronized thereon. Then the data is transmitted serially as digital information comprising logic level 1's and 0's. Forty bits of information are transmited during the data segment. The forty bits of information correspond to five bytes (eight bits/byte). An IBG follows the data block of forty bits and if more data needs to be sent, another forty bit data stream is sent and if there is no more data, then the line is released.

FIG. 2B shows a data block of forty bits preceded by and followed by an interblock gap. Note that at the end of the final interblock gap, a line free condition exists wherein the line is returned to the active (high impedance) state.

Referring now to FIG. 3 there is shown a flow chart of the transmission sequence utilized by a transceiver decoder 56 to communicate with controller 50. In the "data line free" mode the data line is in a dormant state. It is not being used by any communication point. Protocol to deem the line as being in a free mode as opposed to being accessed is achieved by timing out the inactivity of the data line in the active state for a minimum of three (3) bit periods T. Timeout can be 6-25 msec. depending upon whether phase lock is achieved. With phase lock, timeout can be as short as 6 msec. In the absence of phase lock, timeout automatically occurs at 25 msec. If a signal is to be sent during this time out period for the line free protocol then the previous data rate just received is used to receive the next transmission sequence. It uses the last data rate established and does not expect to see a new preamble. When the line is free it is released for general access and any communication point can attempt to gain control of the line. Therefore, if the state of the data line remains active for a period of time, then the line will be deemed free of data and can be accessed by any communication point.

There are two types of IBG's, one for grabbing the line, and the second for delineation of data blocks within the data stream by an IBG between each block of forty bits of data. In order for a communication point to grab the data line, it accesses the line by forcing an initial IBG (long IBG). The duration of the IBG must be long enough to allow all devices maintained on the line time to set up for receiving the data stream that is to follow. Since the devices on the data line are sequential machines (microcomputers), it is necessary that this duration be a minimum of two msecs. so as to gain the attention of these machines. The duration of the IBG must be long enough so that any communication point will have time to compute before the IBG is recognized. The normal IBG is a minimum of three bit periods (3T) of the data rate. The IBG serves as a synchronizing signal to delineate the data blocks being transmitted. When a receiver is out of sync with the transmission, the IBG serves to justify the system and resync a receiver.

The preamble is sent only once during a transmission sequence independent of the number of the data blocks being transmitted. Preamble includes a minimum of four bits at the receiver, a weighted average is taken during each bit period from which the data rate is calculated and its logic threshold determined. The preamble is a sequence of 50 percent duty cycle pulses which a receiver utilizes in order to lock in the data rate (generally 350-4000 bits/second).

A data block includes 40 bits of information using modified ratio signalling for transmitting a series of logic 1's and 0's. The duration and decoding of each received bit is referenced to the previously received preamble. The decoding of the logic levels are not determined by any present condition internal to a receiver. Any number of data blocks separated by IBG's may be transmitted during the time that a communication's point has control of the line.

As stated, the logic levels are transmitted using a modified ratio signalling scheme. The signalling scheme utilizes the active state of the data line for the exchange of information and clock. The duration of the active state during the data block sequence is compared to the previously transmitted preamble which has been stored in memory. This comparison is used to determine the actual logic level being received. Since the data bit input is being referenced to a previous data input, i.e., preamble, it is said to be a ratioed reception. Therefore, common mode distortions caused by parametric shifts in the receiver electronics or in the data line cancel. Since both preamble and data are coupled through data line 58 to a particular control point acting as a receiver, the elimination of parametric variations allow the use of a more simple receiver circuit than might normally be required since tolerances need not be very strict. The logic level thresholds of the received signals are calculated from the preamble.

Modified Ratio Signaling

Referring back to FIG. 2 and specifically to FIG. 2(c), there is shown a signal diagram illustrating the modified ratio signalling scheme and particularly illustrating the effective calculation of the minimum and maximum pulse width value and defining dead bands where no signals are permitted.

The receiver of a communication point has an initial band width of 4-5 Khz for receiving the preamble. After the preamble has been received and data logic thresholds have been calculated, the bandwidth of the receiver is narrowed to reject signals outside of that narrowed bandwidth. This bandwidth narrowing is achieved by a digitally simulated phase locked loop in each transceiver decoder 56, or controller 50. The rejection of signals outside the narrowed bandwidth is achieved by dynamically setting the bandwidth of filters in accordance with the preamble.

Logic levels are defined in terms of the percentage of a total bit period (T) where a bit period is defined to be two (2) times the period of the active state of the 50% duty cycle preamble signal (T50). The duration of the active state as a percentage of the total bit period that determines whether the logic 1 or the logic 0 is present. The preamble is defined to have a bit period of 50 percent of the total clock period (a fifty percent duty cycle signal) and this reference time is used as the basis for making all logic level decisions. As shown in FIG. 2(c), the dead band corresponds to 12.5 percent of the total bit period. The logic "1" and "0" levels are calculated as follows:

The total data bit period (T)=2×T50=100% (i.e, total duration of the active state).

Let the deadband=T50/4=12.5% of the duration of the active state.

Then logic "1" level (threshold determination filtering) is defined by:

______________________________________

T50 + deadband ≥ logic 1 ≥ T - deadband T50 + T50/4 ≥ logic 1 ≥ T - T50/4 62.5% ≥ logic 1 ≥ 87.5%

______________________________________

Similarly, logic "0" level (threshold determination filtering) is defined by:

______________________________________

Deadband ≥ logic 0 ≥ T50 - deadband T50/4 ≥ logic 0 ≥ T50 - T50/4 12.5% ≥ logic 0 ≥ 37.5%

______________________________________

Since the data logic levels are determined only by the active state of the line, the inactive state is ignored and is used to provide a time needed by the microcomputer to compute. This period of the inactive state between bits is constant but cannot exceed two bit periods. Thus, it can not be mistaken for an IBG. A bit period (T) is defined as two active state preamble bits. Of course, regardless of the particular data bit, logic "1" and "0" interpretations are made with respect to the bit period established by the preamble received immediately prior to the data. Information is only carried by the duration of the active state. The inactive state is the time between bits and its minimum duration is determined by the time needed to compute at the communication point acting as a receiver. The inactive state is approximately 160 microseconds in duration. The use of a constant inactive state duration while modulating the active state of the line for the transfer of information provides for a varying bit transfer rate. A logic "0" bit period is approximately 1/3 less in duration than a logic 1 bit period. Therefore, a word transmitted with logic zeros will be transmitted at a higher baud rate than a word with a logic ones. Thus it is possible to communicate with a central point faster that would be possible using a conventional pulse width modulation scheme. Faster throughput is achieved by carrying information only on one state (active) of the data line while making the other state an "I don't care" state. In conventional pulse width schemes, the inactive state period is varied to maintain a fixed clock rate. It takes the same length of time to send eight "1"'s as it does to send eight "0 "'s. However, in this system eight "0"'s will be sent faster because the inactive state is not lengthened to maintain a constant clock rate.

Data Line Arbitration

The communication link which is a bi-directional communications channel is able to arbitrate any data line contention without interferring with the current communication sequence. When two or more communication points access the data line for transmission of information there is a bus conflict. This conflict is arbitrated so that there is no loss of information or interference with the current transmission. The arbitration of the data line is achieved either during the line access level or bit transmission level at the communication point. The flow of the arbitration logic is set forth in FIG. 4.

Referring now to FIG. 4 there is shown a flow chart of the data line arbitration protocol. When a communication point has information to be transferred over the data line it must first access data line 58. Data line 58 must be in a free state (high impedence, active state) for the communication point to begin the transmission sequence. If the data line is currently being used by another communication point, the point desiring access automatically holds until the data line is deemed free. During this holding period, the communications point is also receiving whatever data is being sent during the current transmission on the data line. The data held in the communications point needing to be transferred is stored and therefore not lost until the transfer of the information can take place. This stored data can be held indefinitely until the data line has been released and is deemed free for subsequent transmission.

Since the communication points consist of identical electronics and sequential logic, it is possible for two or more transmitting devices to be synchronized with each other. If two devices are synchronized, then they will attempt to access the data line at the same time and not realize that other devices are using it as well. To guard against multiple simultaneous transmissions interferring with the integrity of the data being transferred over the data line, a bit level arbitration scheme has been developed.

The bit level arbitration flow charted in FIG. 4 is achieved by reading the data line on a bit-wise basis after driving the line to a particular state, i.e., the inactive or active state. If there is a discrepancy between the state desired and the actual state of the line as read, then that transmitting device will automatically realize the line is in use and drop off the line into the hold data mode for subsequent transmission when the line is deemed free. The selection of the device driven off the line is achieved dynamically during the course of the transmission sequence and not by a predetermined priority and queuing scheme. As two or more communications points transmit, the first bit of information that is different between the two devices will immediately resolve the bus conflict. Since each communication point is uniquely addressable, having its own name, then there is guaranteed to be a sequence of bits during the course of the transmission that will differ. Therefore, there will only be one device left transmitting on the data line at the completion of this transmission sequence. During the arbitration of this information, no data is inteferred with or garbled by this data line conflict since it is being achieved on a bit wise level.

The arbitration tecnnique is dependent on the impedance levels of the active and inactive states of the data communications line. The inactive state, is the low impedance state of the line (e.g., the DC resistance of the line in the inactive state is less than 50 ohms). The active state is a higher impedance (e.g., greater than 90 ohms). The impedance of data line 58 is relative to the driver circuit found on the communication point. When there is a conflict between two devices (where one is driving the line to the active state), while the other is driving the line to the inactive state, it is the latter that will win the bus. The device driving the line to the active state is driven off the line since the active state is of higher impedance and, therefore, yields to the low impedance state of the line. Thus, during the bit level arbitration mode, the device that drives the line to the inactive state when the other devices are driving it to the active state, will gain full and uncontested access of the data line.

Performing this arbitration technique dynamically at the time of the actual transmission, provides the utmost in system throughput; i.e., the actual throughput is solely dependent upon the activity on the data communications line at any given time. Furthermore, this also eliminates the need for lengthly polling techniques when information must immediately be transferred and processed upon demand.

The arbitration technique may also be used to freeze or hold the current status of the system without any loss of information. This may be desired during maintenance or downtime procedures. This freezing is achieved by holding the data line in the inactive state for an indefinite period of time so that maintenance procedures can be performed. Since the data line is being held in the inactive state, all information will be held at the communications point and, therefore, not be lost until the information can be effectively transferred.

There is a mode of operation during which controller 50, which is an overriding master device, holds an interactive uninterrupted data conversation with a transceiver decoder 56 (slave). During this interactive interchange of information to a particular transceiver decoder 56, no other transceiver decoder can contest the use of the data line. The other transceiver decoders 56 are said to be locked out and yield the data line to the control of controller 50. This is achieved by defining a master device and slave devices in the system.

The determination of the master/slave relationship of the system components are built into each of the communication points, i.e., controller 50 is the master and the remote transceiver decoders 56 are the slaves. Controller 50 has overriding control of the data communication line such that it can interrupt, stop, or access data line 58 over any of the other slave devices.

The master/slave mode of operation is achieved through the line free determination logic. In this logic the deeming of a line to be free has a different timeout period in masters and slaves. A master device will have a shorter time out period (4 msec.), so that it can slip in and grab the line before a slave device times out (slave time out is 6 msec.). Furthermore, the slave device may become a master upon command of the actual master device. During an interactive conversation between controller 50, a master, and a transceiver decoder 56, a slave, control of data line 58 is automatically transferred to the slave device being accessed. This transfer allows controller 50 to select or poll a specific transceiver decoder 56 without being endangered by a response from an arbitrary device transmitting data.

Therefore, the master device is capable of transferring the control of data line 58 to a specific slave device without any interference.

Transceiver decoder--hardware

Referring now to FIG. 5, there is shown a general block diagram of a transceiver decoder 56. Each transceiver decoder 56 is built around a single chip microcomputer 100, suitably a 3870, which performs all of the logic control functions of the transceiver decoder including the encoding of data from switch and analog sensor inputs for ultimate transmission to the central controller, and the interpretation and execution of the instructions from the central controller. The address of each transceiver decoder 56 is jumper-selectable by an address selection bus 102 which sets a 10-bit binary word giving each transceiver decoder an address from "0" to "1023". A switchleg jumper 104 allows the user to select the type of switchleg (momentary or maintain) 68 to be coupled to microcomputer 100 of transceiver decoder 56 through a plurality of switchleg inputs 106. A data input and output circuit 108 couples the data line (data line 58) to microcomputer 100. Data input and output circuit 108 includes optoisolators for providing an isolated differential data input and output for enhancing noise immunity against electromagnetically coupled noise sources. As previously stated, the data communications link is bi-directional. An analog sensor section 110 allows the coupling to a transceiver decoder 56 of up to eight analog sensors (temperature, light sensors, snow, ice, humidity, wind, smoke, etc.) using an 8-channel analog multiplexer and a dual-slope A/D converter. The analog sensors are of the variable impedance type and are represented by transducer 112 in the Figure (analogous to light sensor 70 shown in FIG. 1). These analog sensors can be polled by controller 50 and in response to such polling, send data via their associated transceiver decoder 56 through data line 58 to the controller providing information related to ambient lights, temperature conditions, etc. for initiating an appropriate response to such conditions.

The use of analog sensors and switches renders the system "condition responsive". The time dependent scheduling of relays of selected sectors responding to a pattern of relay states illustrates the use of time as a condition. However, the system can also be condition responsive through its switchleg inputs and analog sensor inputs. Analog sensor section 110 (see FIG. 5) provides connection for up to eight (8) analog sensors, i.e., devices providing a range of impedances or voltages responsive to ambient conditions such as light level, temperature, humidity, etc. Controller 50 can poll (interrogate) these sensors periodically and issue programmed commands in response to their status. There are also available on the commercial market switch type sensors. Such sensors detect thresholds of temperature, light, humidity, etc. and close switch contacts when their predetermined threshold is exceeded. These switch type sensors can be treated as substitutes for switches 68 coupled to the switchleg inputs of a transceiver decoder 56. The response to the actuation of a switchleg is defined by the user regardless of the particular device utilized to close the contacts of the switchleg. Thus a smoke detector having a switch-type output can be coupled to a switchleg of a transceiver decoder 56 and programmed to activate a specific lighting pattern for an emergency sector.

Watchdog reset circuit 120 provides reset and preset capability for transceiver decoder 56. When microcomputer 100 is operating normally, i.e., sequencing through its instructions beginning at its base (zero) address and proper sequence of instructions it sends a STROBE signal to watchdog reset circuit 120. Whenever the STROBE signal ceases, watchdog reset 120 senses that microcomputer 100 is malfunctioning. Either it has lost a bit and is executing an improper instruction or it has locked into a loop and is not following its proper sequence of instructions. Watchdog reset circuit 120, in response, sends a RESET signal to microcomputer 100 forcing it back to its zero address to begin its instruction sequence again. Watchdog reset circuit 120 also includes a preset switch for giving a user the ability to override a transceiver decoder 56 by turning on all relays. The present switch would be utilized in the event of a data line 58 or controller 50 failure and permits circuit breaker control of all relays without the present necessity of hard wiring changes.

Microcomputer 100 is clocked by an external clock crystal 114.

Commands to specific loads issue from microcomputer 100 through drive matrix lines 124 and are coupled to a bank of relay drivers 126 for activating individual relays associated one with each specific load.

The general block diagram shown in FIG. 1 shows several transceiver decoders 56 coupled along data line 58 serving as the bi-directional data link. Transceiver decoders 56 are individually addressable and are utilized to directly control relays specified on command of controller 50.

The system is a closed loop wherein controller 50 can interrogate the status of the remote transceiver decoder 56. This status information can be the current relay pattern in force such that justification of system activity can be made and verified. A command from controller 50 can either initiate load actuation or be in a responsive mode for interrogation and self-diagnosis. Data sent to controller 50 from a transceiver decode 56 can either be in response to an interrogation command from the controller or it can be asynchronously sent in response to a remote user input, such as the activation of a switchleg by a switch 68 or a condition responsive device coupled to a switchleg input. Since there is no critical system timing, a user can actuate an input to a transceiver decoder 56 at any time. When an input is recognized, the appropriate information is transmitted to controller 50 which in turn decodes the switchleg signal and sends the appropriate command to actuate the proper relays and loads.

The transfer of data between controller 56 and a transceiver decoder 56 is achieved over data line 58. Data is transmitted in a serial fashion as described in great detail above.

Data Stream Format

Referring to FIG. 6, there is shown a diagrammatic representation of the format of the data stream. FIG. 6(a) shows a transmission block of 40-bits (5-bytes) including multiple fields. The data stream includes a function word, an address word, a data field zero, a data field 1, and an error check work. A word refers to one byte of 8 bits of binary information.

The first byte of the 40-bit data stream is the function word. Three bits called F0, F1 and F2, shown in FIG. 6(a), comprise the binary pattern that is used to dynamically set the type of transmission sequence. Since the decoding of this function word is critical to the accurate transfer of data, it is complementary-redundant bit-wise error-checked. The error checking for the function bits is in the three bits following F0, F1 and F2 called F0, F1 and F2. Before the data is decoded, the function words are error-checked for accuracy. These six bits are exclusively OR'ed together in the appropriate bit positions such that valid data exist when they differ in logic level in each bit position. This will produce a logic one in the exclusively OR'ed section indicating that data is valid.

The function word is present in all data transfers between the controller 50 and a transceiver decoder 56. The three bits provided in the function word provide a binary number from 0 through 7 which indicates one of eight possible modes. Modes 0 through 4 indicate that the data stream was transmitted by controller 50. Modes 5 through 7 indicate that the transmission emanated from a remote transceiver decoder 56. Table 1 summarizes the different modes specified in the function word. In general, the function word specifies the type of data being transferred and the data security which affects the system throughput.

TABLE 1

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FUNCTION WORD - TRANSMITTED BY CENTRAL CONTROLLER F 2 F 1 F 0

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0 0 0 Mode 0 Install Specified Relay States in Data Fields 0 and 1 0 0 1 Mode 1 First Transmission of Relay States in Data Fields 0 and 1 0 1 0 Mode 2 Second Transmission of Complementary Relay States in Mode 1 0 1 1 Mode 3 Interactive Data Verifi- cation 1 0 0 Mode 4 Data Interrogation Mode- Use (Auxiliary Function Word in Data Field 0)

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FUNCTION WORD - TRANSMITTED BY TRANSCEIVER DECODER 56 F 2 F 1 F 0

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1 0 1 Mode 5 Current Relay States in Data Fields 0 and 1 1 1 0 Mode 6 Remote User Activated Switchleg 1 1 1 Mode 7 Data Type Found in Data Field 0 Analog Sensor Data Transceiver Decoder 56 Status for Testing (Secondary Auxiliary Function Word in Data Field 0)

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Continuing to refer to FIG. 6(a), the address of the transceiver decoder 56 includes 10 binary bits which provide 1024 unique addresses that exist on a single data communication line. The high order address bits, A8 and A9, exist in the least two significant bits of the function word. The remaining address bits, A0 to A7, are contained in the second byte of the transmission block, the address word.

The type of data that is contained in data field 0, which is the third byte of the transmission block, is specified in the function word. For modes 0 to 3, data fields 0 and 1 contain the appropriate loading pattern for 16 relays specified by controller 50. In mode 4 (see Table 1) data field 0 contains an auxiliary function word which is decoded similarly to the function word of the first transmission byte. Each auxiliary function word includes a lower and upper order nibble of 4 bits each. The lower order nibble of the auxiliary function word, (see FIG. 6(b)), f0-f3, specifies the particular flag which must be decoded. The higher order nibble, fO-f3, consists of the complementary redundant bits of the auxiliary function word which is used for error checking. These bits are exclusively OR'ed with the auxiliary flag to determine their validity. Table 2 is a summary of the auxiliary function words.

TABLE 2

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AUXILIARY FUNCTION WORD TABLE FOR MODE 4 (Decoded in Data Field 0 Transmitted by Central Controller) f 3 f 2 f 1 f 0

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0 0 0 0 Individual relay override, force to OPEN state. Relay number in data field 1. 0 0 0 1 Individual relay override, force to CLOSE state. 0 0 1 0 Acknowledge of valid loading pattern - Mode 3 response (See Table 1) 0 0 1 1 Negative acknowledge indica- tion of erroneous relay pattern data, Mode 3 response. 0 1 0 0 Interrogate current status of relays. NOTE - Does not over- ride pending switchleg request. 0 1 0 1 Reserved for future use. 0 1 1 0 Interrogate system status used in debugging. Does not over- ride pending switchleg request. 0 1 1 1 Reserved for future use. 1 0 0 0 Request for analog sensor reading whose sensor address is in data field 1. 1 0 0 1 Interrogate relay status- overrides any pending switchleg request. 1 0 1 0 Interrogate current system status - override any pending switchleg request. 1 0 1 1 Not used 1 1 1 1

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Modes 5 and 6 (see Table 1) are transmitted by tranceiver decoder 56. Data fields 0 and 1 contain either the current state of the relays or the activated switchlegs by the remote user.

Referring now to FIG. 6(c) mode 7 is also sent by the transceiver decoder 56 and indicates, in the high order nibble of data field 0, a second set of auxiliary function words f0 and sf1 specifying the type of data found in data field 1 and in the low order nibble of data field 0. This second auxiliary function word is used to send the analog sensor reading as well as information used in testing the transceiver decoder 56. Table 3 summarizes this second auxiliary function word.

TABLE 3

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SECOND AUXILIARY FUNCTION WORD sf 1 sf 0

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0 1 System status contained in low nibble of data field 0 and in data field 1. 1 0 Analog Data enclosed in data field 1 - addressed in low nibble of data field 0.

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The fifth and last byte of the transmission block (see FIG. 6(a)) is the parity error check word. This generates even parity for every four bits of data of the previous four bytes of the transmission block. Before any action is taken by transceiver decoder 56, a parity check on the previous bytes is performed with the error check word to determine the validity of the transmission block. If an error is detected, no action will occur and the transceiver decoder will continue its normal activity and wait for a new command from the controller 50, or remote user input.

Mode 0 is the binary bit pattern 000 shown in Table 1. This is the fastest mode providing the highest degree of system throughput. This mode, sent by the controller 50, informs a transceiver decoder 56 that load control data is contained in data fields 0 and 1. Transceiver decoder 56, upon receipt of this data block, performs an address and error check using the error check word and immediately installs the specified states of relays 60.

Modes 1 and 2 provide a higher level of data security at a reduced system throughput than mode 0. Mode 1 indicates to transceiver decoder 56 that load control information is contained in data fields 0 and 1, as in mode 0. However, no action occurs until after a second transmission, mode 2, which must follow immediately. The mode 2 transmission consists of complementary redundant load control information in data fields 0 and 1. After the reception of mode 2, data fields 0 and 1 of mode 1 and mode 2 are exclusively OR'ed together to insure that each appropriate bit position differs in logic level indicating valid data before actuation occurs. If the transmission is made out of sequence, that is, mode 2 before mode 1, or if the data field bits agree in logic level, then an error condition is said to exist and no action by the transceiver decoder will take place.

Mode 3 is an interactive sequence of data transfer to and from transceiver decoder 56. It provides the highest degree of data security at the slowest system throughput. The sequence of events in this communication scheme are in the following order.

a. Controller 50 specifies load control information in data fields 0 and 1 as in mode 0.

b. Transceiver decoder 56 performs an address and error check on this transmission block and immediately responds by transmitting the load control information from data fields 0 and 1 back to controller 50.

c. Controller 50, upon receipt of this data, verifies that the loading pattern is correct and then immediately transmits a positive acknowledge so that load actuation can take place. If controller 50 receives conflicting load control data, it will issue a negative acknowledge signal indicating to transceiver decoder 56 to abort the transmission sequence.

d. Transceiver decoder 56, upon receiving a positive acknowlegement, will then install the specified loading pattern. If at any time the transmission of this information is out of sequence or a negative acknowledgement is received, transceiver decoder 56 will abort this operation.

Mode 4 specifies a particular task to be performed which may require a response by the transceiver decoder 56 to controller 50. The mode 4 task is described in Table 2 and is specified in data field 0.

The state of an individual relay can be modified by controller 50 without affecting the other loads connected to a transceiver decoder 56. Controller 50 can also request a reading of an analog sensor whose address appears in data field 1. Controller 50 can interrogate the status of the loads controlled by transceiver decoder 56.

Mode 5 is transmitted by transceiver decoder 56 and contains the current state of the relays in force in response to a read request from controller 50.

In mode 6, the state of an activated switchleg is transmitted to controller 50 by transceiver decoder 56. A switchleg 68 is activated by a user and indicates whether the position is on or off.

Mode 7 contains status information requested by controller 50. Transceiver decoder responds in this mode for the following two cases:

a. Analog Sensor Reading An analog sensor (such as transducer 112 shown in FIG. 5) whose address is in the low order nibble of data field 0 is supplied in data field 1. This is only sent back to controller 50 after it has requested the analog sensor reading.

b. System Inquiry Mode

This mode is used for testing and debugging transceiver decoder 56. When controller 50 asks for system status, the low order nibble of data field 0 will contain the condition of several user selectable jumpers. Data field 1 will contain the value of the data rate counter used in determining the logic level inputs from data line.

Up to eight switches 68 can be connected to switchleg input circuit 106 of transceiver decoder 56 providing programmable remote user inputs to controller 50. Switches 68 can be either maintain or momentary type. The type of switchleg is determined at the time of installation a jumper selection at switchleg jumper 104 (see FIG. 5). When momentary switches are selected, transceiver decoder 56 will only transmit data indicating the state or direction of the contact when there is a MAKE condition or on positive action only. For the maintain switches, transmission to controller 50 will occur on a MAKE or BREAK condition, i.e., whenever the switchleg changes state. Switchleg actuation is achieved asynchronously and independently of any activity of controller 50 and other transceiver decoder 56 connected with data line 58. This independence allows each transceiver decoder 56 to function without any critical system timing and thereby reduces system complexity and its susceptibility to erroneous action while increasing system throughput. Activation of a switchleg input by the closure of a switch 68 asynchronously causes a signal to be sent to controller 50 requesting an override instruction for a particular relay 60 and its associated load. If controller 50 has been programmed to respond to the activation of switch 68, a command will be sent to the transceiver decoder 56 associated with the relay requiring activation.

Transceiver decoder 56 contains filtering and debouncing logic for eliminating multiple switchleg actuations and for rejecting errors caused by noise. Switchleg inputs are read at 80 msec intervals and require that the user enable a switch for at least 100 msec to guarantee a true reading.

When a switch 68 is activated by a remote user, a switchleg output word is formed in data fields 0 and 1 of a transmitter buffer in transceiver decoder 56. The switchleg word is then transmitted to controller 50 as soon as the data line is deemed free. Data field 0 will contain the particular switchlegs that have been activated and data field 1 contain the desired state. The bit positions that are set in data field 0 indicate which switchlegs were activated by the remote user. The corresponding bit positions in data field 1 indicate the state of the activated switch 68 (on or off). For example, referring to FIGS. 6(d) and 6(e), if switchleg 6 has been activated, then data bit 6 will contain a 1 in data fields 0 and the corresponding bit position in data field 1 will contain the state of the switchleg (logic 1 for on and logic 0 for off).

If data line 58 is in use, transceiver decoder 56 will standby, latching the switchleg request until the information can be sent. Therefore, the switchleg actuation is not lost and does not require multiple actuations by the user. If while transceiver decoder 56 is standing by another switchleg is activated or if multiple switchleg inputs occur at the same time or if the same switchleg is reactivated, then all the inputs will be added to the current switchleg output word waiting to be sent to controller 50. All inputs are latched and provide "N-key rollover" insuring accurate readings even if multiple switches are simultaneously actuated. This will guarantee that no data is lost due to the interaction of the other devices.

The transmission of the switchleg data occurs asynchronously with controller 50. This eliminates the need for slow polling methods. The throughput is therefore a function of the current activity on the data bus.

FIGS. 7-17 detail the specific circuitry and logic functions performed by transceiver decoder 56. The heart of each transceiver decoder 56 is a 3870 single chip microcomputer 100 which contains a 2K ROM program providing all required logic functions.

Transceiver Decoder Microcomputer-Connections

Microcomputer 100 is a general purpose microcomputer that is transformed into a special purpose microcomputer by its particular program burned into read only memory (ROM). All logic functions of transceiver decoder 56 are carried out by microcomputer 100. Signal or pin names as used throughout this specification can be correlated to those shown on FIG. 7.

Referring now to FIG. 7, there is shown a detailed signal and pin assignment for microcomputer 100. The address bus includes pins 3-6, 19-16 and 33-32, respectively. Serial input data from data line 58 is coupled into SID on pin 38. Serial output data to data line 58 is coupled from SOD pin 26. The digital signal representing the status of the analog sensors coupled to analog sensor section 110 (see FIG. 6) is coupled into ANINP pin 27. Selection of particular banks of relay drivers is made by signals on a relay bank selection bus including RESEL0 . . . RESEL7 at pins 8-15 respectively. Particular relay drivers within each bank are selected by MD0-MD7 at pins 37-34 and 22-25 respectively. Switchleg inputs 106 are multiplexed onto the MD0-MD7 lines.

Referring now to FIG. 8, there is shown a schematic diagram of data input and output circuit 108.

Transceiver Decoder Data I/O

Data input and output circuit 108 provides isolation between data line 58 and microcomputer 100. Specifically, isolation from data line 58 to input SID (pin 38 of microcomputer 100) is provided by an optoisolator 150. Isolation from the data output SOD (pin 26 of microcomputer 100) to data line 58 is provided by a second optoisolator 152. All circuitry from the data line side of optoisolators 150 and 152 to data line 58 are powered by an isolated power supply providing voltages +P and -P.

Data is coupled to and from data input and output circuit 108 via a fusable link 154. A high impedance is provided to the data line by a series resistor 160 in the data path. A small amount of filtering is provided by a capacitor 158 a