Lee, Terry R. (Boise, ID, US)
Jeddeloh, Joseph M. (Shoreview, MN, US)

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11/510150

08/12/2008

08/24/2006

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Micron Technology, Inc. (Boise, ID, US)

711/137

709/250

G06F12/08

709/229, 709/104, 709/250, 710/22, 711/154, 711/113, 711/114, 710/3, 710/100, 709/233, 711/145, 711/137, 711/118, 711/213, 711/112

0751703		February, 1904	Chilton et al.	137/190
3742253	THREE STATE LOGIC DEVICE WITH APPLICATIONS	June, 1973	Kronies	307/247
4045781	Memory module with selectable byte addressing for digital data processing system	August, 1977	Levy et al.	364/200
4240143	Hierarchical multi-processor network for memory sharing	December, 1980	Besemer et al.	364/200
4245306	Selection of addressed processor in a multi-processor network	January, 1981	Besemer et al.	364/200
4253144	Multi-processor communication network	February, 1981	Bellamy et al.	364/200
4253146	Module for coupling computer-processors	February, 1981	Bellamy et al.	364/200
4608702	Method for digital clock recovery from Manchester-encoded signals	August, 1986	Hirzel et al.	375/110
4707823	Fiber optic multiplexed data acquisition system	November, 1987	Holdren et al.	370/1
4724520	Modular multiport data hub	February, 1988	Athanas et al.	364/200
4831520	Bus interface circuit for digital data processor	May, 1989	Rubinfeld et al.	364/200
4891808	Self-synchronizing multiplexer	January, 1990	Williams	370/112
4930128	Method for restart of online computer system and apparatus for carrying out the same	May, 1990	Suzuki et al.	371/12
4953930	CPU socket supporting socket-to-socket optical communications	September, 1990	Ramsey et al.	350/96.11
5133059	Computer with multiple processors having varying priorities for access to a multi-element memory	July, 1992	Ziegler et al.	395/425
5241506	Semiconductor memory circuit apparatus	August, 1993	Motegi et al.	365/210
5243703	Apparatus for synchronously generating clock signals in a data processing system	September, 1993	Farmwald et al.	395/325
5251303	System for DMA block data transfer based on linked control blocks	October, 1993	Fogg, Jr. et al.	395/275
5269022	Method and apparatus for booting a computer system by restoring the main memory from a backup memory	December, 1993	Shinjo et al.	395/700
5313590	System having fixedly priorized and grouped by positions I/O lines for interconnecting router elements in plurality of stages within parrallel computer	May, 1994	Taylor	395/325
5317752	Fault-tolerant computer system with auto-restart after power-fall	May, 1994	Jewett et al.	395/750
5319755	Integrated circuit I/O using high performance bus interface	June, 1994	Farmwald et al.	395/325
5327553	Fault-tolerant computer system with /CONFIG filesystem	July, 1994	Jewett et al.	395/575
5355391	High speed bus system	October, 1994	Horowitz et al.	375/36
5432823	Method and circuitry for minimizing clock-data skew in a bus system	July, 1995	Gasbarro et al.	375/356
5432907	Network hub with integrated bridge	July, 1995	Picazo, Jr. et al.	395/200
5442770	Triple port cache memory	August, 1995	Barratt	395/403
5461627	Access protocol for a common channel wireless network	October, 1995	Rypinski	370/95.2
5465229	Single in-line memory module	November, 1995	Bechtolsheim et al.	345/477
5479370	Semiconductor memory with bypass circuit	December, 1995	Furuyama et al.	365/189.12
5497476	Scatter-gather in data processing system	March, 1996	Oldfield et al.	395/439
5502621	Mirrored pin assignment for two sided multi-chip layout	March, 1996	Schumacher et al.	361/760
5544319	Fiber optic memory coupling system with converter transmitting and receiving bus data in parallel fashion and diagnostic data in serial fashion	August, 1996	Acton et al.	395/200.07
5566325	Method and apparatus for adaptive memory access	October, 1996	Bruce, II et al.	395/494
5577220	Method for saving and restoring the state of a CPU executing code in protected mode including estimating the value of the page table base register	November, 1996	Combs et al.	395/416
5581767	Bus structure for multiprocessor system having separated processor section and control/memory section	December, 1996	Katsuki et al.	395/800
5606717	Memory circuitry having bus interface for receiving information in packets and access time registers	February, 1997	Farmwald et al.	395/856
5638334	Integrated circuit I/O using a high performance bus interface	June, 1997	Farmwald et al.	365/230.03
5638534	Memory controller which executes read and write commands out of order	June, 1997	Mote, Jr.	395/485
5659798	Method and system for initiating and loading DMA controller registers by using user-level programs	August, 1997	Blumrich et al.	395/846
5687325	Application specific field programmable gate array	November, 1997	Chang	395/284
5706224	Content addressable memory and random access memory partition circuit	January, 1998	Srinivasan et al.	365/49
5710733	Processor-inclusive memory module	January, 1998	Chengson et al.	365/52
5715456	Method and apparatus for booting a computer system without pre-installing an operating system	February, 1998	Bennett et al.	395/652
5729709	Memory controller with burst addressing circuit	March, 1998	Harness	395/405
5748616	Data link module for time division multiplexing control systems	May, 1998	Riley	370/242
5796413	Graphics controller utilizing video memory to provide macro command capability and enhanched command buffering	August, 1998	Shipp et al.	345/522
5818844	Address generation and data path arbitration to and from SRAM to accommodate multiple transmitted packets	October, 1998	Singh et al.	370/463
5819304	Random access memory assembly	October, 1998	Nilsen et al.	711/5
5822255	Semiconductor integrated circuit for supplying a control signal to a plurality of object circuits	October, 1998	Uchida	365/194
5832250	Multi set cache structure having parity RAMs holding parity bits for tag data and for status data utilizing prediction circuitry that predicts and generates the needed parity bits	November, 1998	Whittaker	395/471
5875352	Method and apparatus for multiple channel direct memory access control	February, 1999	Gentry et al.	395/843
5875454	Compressed data cache storage system	February, 1999	Craft et al.	711/113
5887159	Dynamically determining instruction hint fields	March, 1999	Burrows	395/567
5889714	Adaptive precharge management for synchronous DRAM	March, 1999	Schumann et al.	365/203
5928343	Memory module having memory devices containing internal device ID registers and method of initializing same	July, 1999	Farmwald et al.	710/104
5963942	Pattern search apparatus and method	October, 1999	Igata	707/6
5966724	Synchronous memory device with dual page and burst mode operations	October, 1999	Ryan	711/105
5973935	Interdigitated leads-over-chip lead frame for supporting an integrated circuit die	October, 1999	Schoenfeld et al.	361/813
5973951	Single in-line memory module	October, 1999	Bechtolsheim et al.	365/52
5978567	System for distribution of interactive multimedia and linear programs by enabling program webs which include control scripts to define presentation by client transceiver	November, 1999	Rebane et al.	395/200.49
5987196	Semiconductor structure having an optical signal path in a substrate and method for forming the same	November, 1999	Noble	385/14
6011741	Computer memory cards using flash EEPROM integrated circuit chips and memory-controller systems	January, 2000	Wallace et al.	365/221
6023726	User configurable prefetch control system for enabling client to prefetch documents from a network server	February, 2000	Saksena	709/219
6029250	Method and apparatus for adaptively adjusting the timing offset between a clock signal and digital signals transmitted coincident with that clock signal, and memory device and system using same	February, 2000	Keeth	713/400
6031241	Capillary discharge extreme ultraviolet lamp source for EUV microlithography and other related applications	February, 2000	Silfvast et al.	250/504R
6033951	Process for fabricating a storage capacitor for semiconductor memory devices	March, 2000	Chao	438/253
6038630	Shared access control device for integrated system with multiple functional units accessing external structures over multiple data buses	March, 2000	Foster et al.	710/132
6061263	Small outline rambus in-line memory module	May, 2000	Boaz et al.	365/51
6061296	Multiple data clock activation with programmable delay for use in multiple CAS latency memory devices	May, 2000	Ternullo, Jr. et al.	365/233
6067262	Redundancy analysis for embedded memories with built-in self test and built-in self repair	May, 2000	Irrinki et al.	365/201
6067649	Method and apparatus for a low power self test of a memory subsystem	May, 2000	Goodwin	714/718
6073190	System for dynamic buffer allocation comprising control logic for controlling a first address buffer and a first data buffer as a matched pair	June, 2000	Rooney	710/56
6076139	Multimedia computer architecture with multi-channel concurrent memory access	June, 2000	Welker et al.	711/104
6079008	Multiple thread multiple data predictive coded parallel processing system and method	June, 2000	Clery, III	712/11
6092158	Method and apparatus for arbitrating between command streams	July, 2000	Harriman et al.	711/151
6098158	Software-enabled fast boot	August, 2000	Lay et al.	711/162
6105075	Scatter gather memory system for a hardware accelerated command interpreter engine	August, 2000	Ghaffari	710/5
6111757	SIMM/DIMM memory module	August, 2000	Dell et al.	361/737
6125431	Single-chip microcomputer using adjustable timing to fetch data from an external memory	September, 2000	Kobayashi	711/154
6128703	Method and apparatus for memory prefetch operation of volatile non-coherent data	October, 2000	Bourekas et al.	711/138
6128706	Apparatus and method for a load bias--load with intent to semaphore	October, 2000	Bryg et al.	711/141
6131149	Apparatus and method for reading data from synchronous memory with skewed clock pulses	October, 2000	Lu et al.	711/167
6134624	High bandwidth cache system	October, 2000	Burns et al.	710/113
6137709	Small outline memory module	October, 2000	Boaz et al.	365/51
6144587	Semiconductor memory device	November, 2000	Yoshida	365/189.05
6145033	Management of display FIFO requests for DRAM access wherein low priority requests are initiated when FIFO level is below/equal to high threshold value	November, 2000	Chee	710/57
6157743	Method for retrieving compressed texture data from a memory system	December, 2000	Goris et al.	382/233
6157962	Multipath I/O storage systems with multiipath I/O request mechanisms	December, 2000	Hodges et al.	710/1
6167465	System for managing multiple DMA connections between a peripheral device and a memory and performing real-time operations on data carried by a selected DMA connection	December, 2000	Parvin et al.	710/22
6167486	Parallel access virtual channel memory system with cacheable channels	December, 2000	Lee et al.	711/120
6175571	Distributed memory switching hub	January, 2001	Haddock et al.	370/423
6185352	Optical fiber ribbon fan-out cables	February, 2001	Hurley	385/114
6185676	Method and apparatus for performing early branch prediction in a microprocessor	February, 2001	Poplingher et al.	712/239
6186400	Bar code reader with an integrated scanning component module mountable on printed circuit board	February, 2001	Dvorkis et al.	235/462.45
6191663	Echo reduction on bit-serial, multi-drop bus	February, 2001	Hannah	333/17.3
6201724	Semiconductor memory having improved register array access speed	March, 2001	Ishizaki et al.	365/49
6208180	Core clock correction in a 2/N mode clocking scheme	March, 2001	Fisch et al.	327/141
6212590	Computer system having integrated bus bridge design with delayed transaction arbitration mechanism employed within laptop computer docked to expansion base	April, 2001	Melo et al.	710/119
6219725	Method and apparatus for performing direct memory access transfers involving non-sequentially-addressable memory locations	April, 2001	Diehl et al.	710/26
6223301	Fault tolerant memory	April, 2001	Santeler et al.	714/6
6233376	Embedded fiber optic circuit boards and integrated circuits	May, 2001	Updegrove	385/14
6243769	Dynamic buffer allocation for a computer system	June, 2001	Rooney	710/56
6243831	Computer system with power loss protection mechanism	June, 2001	Mustafa et al.	714/24
6246618	Semiconductor integrated circuit capable of testing and substituting defective memories and method thereof	June, 2001	Yamamoto et al.	365/200
6247107	Chipset configured to perform data-directed prefetching	June, 2001	Christie	711/216
6249802	Method, system, and computer program product for allocating physical memory in a distributed shared memory network	June, 2001	Richardson et al.	709/200
6252821	Method and apparatus for memory address decode in memory subsystems supporting a large number of memory devices	June, 2001	Nizar et al.	365/238.6
6256692	CardBus interface circuit, and a CardBus PC having the same	July, 2001	Yoda et al.	710/104
6266730	High-frequency bus system	July, 2001	Perino et al.	710/126
6272609	Pipelined memory controller	August, 2001	Jeddeloh	711/169
6285349	Correcting non-uniformity in displays	September, 2001	Smith	345/147
6286083	Computer system with adaptive memory arbitration scheme	September, 2001	Chin et al.	711/151
6294937	Method and apparatus for self correcting parallel I/O circuitry	September, 2001	Crafts et al.	327/158
6301637	High performance data paths	October, 2001	Krull et al.	711/112
6327642	Parallel access virtual channel memory system	December, 2001	Lee et al.	711/120
6330205	Virtual channel synchronous dynamic random access memory	December, 2001	Shimizu et al.	365/230.06
6347055	Line buffer type semiconductor memory device capable of direct prefetch and restore operations	February, 2002	Motomura	365/189.05
6349363	Multi-section cache with different attributes for each section	February, 2002	Cai et al.	711/129
6356573	Vertical cavity surface emitting laser	March, 2002	Jonsson et al.	372/46
6367074	Operation of a system	April, 2002	Bates et al.	717/11
6370068	Semiconductor memory devices and methods for sampling data therefrom based on a relative position of a memory cell array section containing the data	April, 2002	Rhee	365/196
6370611	Raid XOR operations to synchronous DRAM using a read buffer and pipelining of synchronous DRAM burst read data	April, 2002	Callison et al.	711/105
6373777	Semiconductor memory	April, 2002	Suzuki	365/230.03
6381190	Semiconductor memory device in which use of cache can be selected	April, 2002	Shinkai	365/230.03
6389514	Method and computer system for speculatively closing pages in memory	May, 2002	Rokicki	711/136
6392653	Device for processing acquisition data, in particular image data	May, 2002	Malandain et al.	345/501
6401149	Methods for context switching within a disk controller	June, 2002	Dennin et al.	710/58
6401213	Timing circuit for high speed memory	June, 2002	Jeddeloh	713/401
6405280	Packet-oriented synchronous DRAM interface supporting a plurality of orderings for data block transfers within a burst sequence	June, 2002	Ryan	711/105
6421744	Direct memory access controller and method therefor	July, 2002	Morrison et al.	710/22
6430696	Method and apparatus for high speed data capture utilizing bit-to-bit timing correction, and memory device using same	August, 2002	Keeth	713/503
6433785	Method and apparatus for improving processor to graphics device throughput	August, 2002	Garcia et al.	345/531
6434639	System for combining requests associated with one or more memory locations that are collectively associated with a single cache line to furnish a single memory operation	August, 2002	Haghighi	710/39
6434696	Method for quickly booting a computer system	August, 2002	Kang	713/2
6434736	Location based timing scheme in memory design	August, 2002	Schaecher et al.	716/17
6438622	Multiprocessor system including a docking system	August, 2002	Haghighi et al.	710/1
6438668	Method and apparatus for reducing power consumption in a digital processing system	August, 2002	Esfahani et al.	711/165
6449308	High-speed digital distribution system	September, 2002	Knight, Jr. et al.	375/212
6453393	Method and apparatus for interfacing to a computer memory	September, 2002	Holman et al.	711/154
6457116	Method and apparatus for controlling contexts of multiple context processing elements in a network of multiple context processing elements	September, 2002	Mirsky et al.	712/16
6460108	Low cost data streaming mechanism	October, 2002	McCoskey et al.	710/310
6460114	Storing a flushed cache line in a memory buffer of a controller	October, 2002	Jeddeloh	711/120
6462978	Method of designing semiconductor integrated circuit device and semiconductor integrated circuit device	October, 2002	Shibata et al.	365/63
6463059	Direct memory access execution engine with indirect addressing of circular queues in addition to direct memory addressing	October, 2002	Movshovich et al.	370/389
6467013	Memory transceiver to couple an additional memory channel to an existing memory channel	October, 2002	Nizar	711/1
6470422	Buffer memory management in a system having multiple execution entities	October, 2002	Cai et al.	711/129
6473828	Virtual channel synchronous dynamic random access memory	October, 2002	Matsui	711/104
6477592	System for I/O interfacing for semiconductor chip utilizing addition of reference element to each data element in first data stream and interpret to recover data elements of second data stream	November, 2002	Chen et al.	710/52
6477614	Method for implementing multiple memory buses on a memory module	November, 2002	Leddige et al.	711/5
6477621	Parallel access virtual channel memory system	November, 2002	Lee et al.	711/120
6479322	Semiconductor device with two stacked chips in one resin body and method of producing	November, 2002	Kawata et al.	438/109
6487556	Method and system for providing an associative datastore within a data processing system	November, 2002	Downs et al.	707/101
6487628	Peripheral component interface with multiple data channels and reduced latency over a system area network	November, 2002	Duong et al.	710/313
6490188	Semiconductor devices having mirrored terminal arrangements, devices including same, and methods of testing such semiconductor devices	December, 2002	Nuxoll et al.	365/63
6493803	Direct memory access controller with channel width configurability support	December, 2002	Pham et al.	711/147
6496193	Method and apparatus for fast loading of texture data into a tiled memory	December, 2002	Surti et al.	345/552
6496909	Method for managing concurrent access to virtual memory data structures	December, 2002	Schimmel	711/163
6501471	Volume rendering	December, 2002	Venkataraman et al.	345/424
6502161	Memory system including a point-to-point linked memory subsystem	December, 2002	Perego et al.	711/5
6505287	Virtual channel memory access controlling circuit	January, 2003	Uematsu	711/170
6523092	Cache line replacement policy enhancement to avoid memory page thrashing	February, 2003	Fanning	711/134
6523093	Prefetch buffer allocation and filtering system	February, 2003	Bogin et al.	711/137
6526483	Page open hint in transactions	February, 2003	Cho et al.	711/154
6526498	Method and apparatus for retiming in a network of multiple context processing elements	February, 2003	Mirsky et al.	712/11
6539490	Clock distribution without clock delay or skew	March, 2003	Forbes et al.	713/401
6552564	Technique to reduce reflections and ringing on CMOS interconnections	April, 2003	Forbes et al.	326/30
6553479	Local control of multiple context processing elements with major contexts and minor contexts	April, 2003	Mirsky et al.	712/16
6564329	System and method for dynamic clock generation	May, 2003	Cheung et al.	713/322
6587912	Method and apparatus for implementing multiple memory buses on a memory module	July, 2003	Leddige et al.	711/5
6590816	Integrated memory and method for testing and repairing the integrated memory	July, 2003	Perner	365/200
6594713	Hub interface unit and application unit interfaces for expanded direct memory access processor	July, 2003	Fuoco et al.	710/31
6594722	Mechanism for managing multiple out-of-order packet streams in a PCI host bridge	July, 2003	Willke, II et al.	710/313
6598154	Precoding branch instructions to reduce branch-penalty in pipelined processors	July, 2003	Vaid et al.	712/237
6615325	Method for switching between modes of operation	September, 2003	Mailloux et al.	711/154
6622227	Method and apparatus for utilizing write buffers in memory control/interface	September, 2003	Zumkehr et al.	711/167
6628294	Prefetching of virtual-to-physical address translation for display data	September, 2003	Sadowsky et al.	345/568
6629220	Method and apparatus for dynamic arbitration between a first queue and a second queue based on a high priority transaction type	September, 2003	Dyer	711/158
6631440	Method and apparatus for scheduling memory calibrations based on transactions	October, 2003	Jenne et al.	711/105
6633959	Non-uniform memory access (NUMA) data processing system that provides notification of remote deallocation of shared data	October, 2003	Arimilli et al.	711/141
6636110	Internal clock generating circuit for clock synchronous semiconductor memory device	October, 2003	Ooishi et al.	327/565
6646929	Methods and structure for read data synchronization with minimal latency	November, 2003	Moss et al.	365/194
6647470	Memory device having posted write per command	November, 2003	Janzen	711/154
6658509	Multi-tier point-to-point ring memory interface	December, 2003	Bonella et al.	710/100
6662304	Method and apparatus for bit-to-bit timing correction of a high speed memory bus	December, 2003	Keeth et al.	713/400
6665202	Content addressable memory (CAM) devices that can identify highest priority matches in non-sectored CAM arrays and methods of operating same	December, 2003	Lindahl et al.	365/49
6667895	Integrated circuit device and module with integrated circuits	December, 2003	Jang et al.	365/63
6681292	Distributed read and write caching implementation for optimized input/output applications	January, 2004	Creta et al.	711/119
6681302	Page open hint in transactions	January, 2004	Cho et al.	711/154
6697926	Method and apparatus for determining actual write latency and accurately aligning the start of data capture with the arrival of data at a memory device	February, 2004	Johnson et al.	711/167
6704817	Computer architecture and system for efficient management of bi-directional bus	March, 2004	Steinman et al.	710/100
6715018	Computer including installable and removable cards, optical interconnection between cards, and method of assembling a computer	March, 2004	Farnworth et al.	710/300
6718440	Memory access latency hiding with hint buffer	April, 2004	Maiyuran et al.	711/137
6721195	Reversed memory module socket and motherboard incorporating same	April, 2004	Brunelle et al.	365/63
6724685	Configuration for data transmission in a semiconductor memory system, and relevant data transmission method	April, 2004	Braun et al.	365/233
6728800	Efficient performance based scheduling mechanism for handling multiple TLB operations	April, 2004	Lee et al.	710/54
6731548	Reduced power registered memory module and method	May, 2004	Pax	365/189.12
6735679	Apparatus and method for optimizing access to memory	May, 2004	Herbst et al.	711/167
6735682	Apparatus and method for address calculation	May, 2004	Segelken et al.	711/220
6745275	Feedback system for accomodating different memory module loading	June, 2004	Chang	710/305
6751113	Arrangement of integrated circuits in a memory module	June, 2004	Bhakta et al.	365/63
6751703	Data storage systems and methods which utilize an on-board cache	June, 2004	Chilton	711/113
6751722	Local control of multiple context processing elements with configuration contexts	June, 2004	Mirsky et al.	712/15
6754117	System and method for self-testing and repair of memory modules	June, 2004	Jeddeloh	365/201
6754812	Hardware predication for conditional instruction path branching	June, 2004	Abdallah et al.	712/234
6756661	Semiconductor device, a semiconductor module loaded with said semiconductor device and a method of manufacturing said semiconductor device	June, 2004	Tsuneda et al.	257/673
6760833	Split embedded DRAM processor	July, 2004	Dowling	712/34
6771538	Semiconductor integrated circuit and nonvolatile memory element	August, 2004	Shukuri et al.	365/185.05
6772295	System and method for managing data in an I/O cache	August, 2004	Spencer et al.	711/137
6775747	System and method for performing page table walks on speculative software prefetch operations	August, 2004	Venkatraman	711/137
6782466	Arrangement and method for accessing data in a virtual memory arrangement	August, 2004	Steele et al.	711/209
6785780	Distributed processor memory module and method	August, 2004	Klein et al.	711/48
6788104	Field programmable logic device with efficient memory utilization	September, 2004	Singh et al.	326/39
6789173	Node controller for performing cache coherence control and memory-shared multiprocessor system	September, 2004	Tanaka et al.	711/147
6792059	Early/on-time/late gate bit synchronizer	September, 2004	Yuan et al.	375/354
6792496	Prefetching data for peripheral component interconnect devices	September, 2004	Aboulenein et al.	710/306
6795899	Memory system with burst length shorter than prefetch length	September, 2004	Dodd et al.	711/137
6799246	Memory interface for reading/writing data from/to a memory	September, 2004	Wise et al.	711/117
6799268	Branch ordering buffer	September, 2004	Boggs et al.	712/228
6804760	Method for determining a type of memory present in a system	October, 2004	Wiliams	711/170
6804764	Write clock and data window tuning based on rank select	October, 2004	LaBerge et al.	711/170
6807630	Method for fast reinitialization wherein a saved system image of an operating system is transferred into a primary memory from a secondary memory	October, 2004	Lay et al.	713/2
6811320	System for connecting a fiber optic cable to an electronic device	November, 2004	Abbott	385/58
6816947	System and method for memory arbitration	November, 2004	Huffman	711/151
6820181	Method and system for controlling memory accesses to memory modules having a memory hub architecture	November, 2004	Jeddeloh et al.	711/169
6821029	High speed serial I/O technology using an optical link	November, 2004	Grung et al.	385/92
6823023	Serial bus communication system	November, 2004	Hannah	375/296
6829705	System information display method and apparatus	December, 2004	Smith	713/1
6845409	Data exchange methods for a switch which selectively forms a communication channel between a processing unit and multiple devices	January, 2005	Talagala et al.	710/20
6889304	Memory device supporting a dynamically configurable core organization	May, 2005	Perego et al.	711/170
6904556	Systems and methods which utilize parity sets	June, 2005	Walton et al.	714/766
6910109	Tracking memory page state	June, 2005	Holman et al.	711/156
6947672	High-speed optical data links	September, 2005	Jiang et al.	398/135
6980042	Delay line synchronizer apparatus and method	December, 2005	LaBerge	327/291
7107415	Posted write buffers and methods of posting write requests in memory modules	September, 2006	Jeddeloh et al.	711/154
7318130	System and method for thermal throttling of memory modules	January, 2008	Morrow et al.	711/154
20010039612	Apparatus and method for fast booting	November, 2001	Lee	713/2
20020112119	Dual-port buffer-to-memory interface	August, 2002	Halbert et al.	711/115
20020116588	Software management systems and methods for automotive computing devices	August, 2002	Beckert et al.	711/161
20020120709	Shared-memory controller for use in a multimedia processor system	August, 2002	Chow et al.	709/213
20020144064	Controlling cache memory in external chipset using processor	October, 2002	Fanning	711/144
20020178319	Optical bus arrangement for computer system	November, 2002	Sanchez-Olea	710/305
20030005223	System boot time reduction method	January, 2003	Coulson et al.	711/118
20030014578	Routability for memeory devices	January, 2003	Pax	710/100
20030043158	Method and apparatus for reducing inefficiencies in shared memory devices	March, 2003	Wasserman et al.	345/545
20030043426	Optical interconnect in high-speed memory systems	March, 2003	Baker et al.	359/109
20030065836	Controller data sharing using a modular DMA architecture	April, 2003	Pecone	710/62
20030093630	Techniques for processing out-of -order requests in a processor-based system	May, 2003	Richard et al.	711/154
20030095559	Systems including packet interfaces, switches, and packet DMA circuits for splitting and merging packet streams	May, 2003	Sano et al.	370/419
20030149809	Method and apparatus for timing and event processing in wireless systems	August, 2003	Jensen et al.	710/22
20030156639	Frame rate control system and method	August, 2003	Liang	375/240.01
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Bataille, Pierre-michel

Dorsey & Whitney LLP

CROSS-REFERENCE TO RELATED APPLICATION

This application is a continuation of U.S. patent application Ser. No. 10/601,252, filed Jun. 20, 2003, now U.S. Pat. No. 7,260,685.

The invention claimed is:

1. A system for prefetching data in a memory system comprising: a link interface receiving memory requests for access to memory cells in at least one of a plurality of memory devices; a memory device interface coupled to the memory devices, the memory device interface being operable to transfer memory requests to the memory devices for access to memory cells in at least one of the memory devices and to receive read data responsive to at least some of the memory requests; and a prefetch circuit coupled to the link interface to receive memory requests from the link interface and coupled to the memory device interface to receive data from the memory cells, the prefetch circuit operable to predict addresses that are likely to be accessed in the memory devices based on the memory requests and to prefetch and store data from memory cells according to the predicted addresses, the prefetch circuit further operable to provide the prefetched data to the link interface responsive to subsequent memory requests, the prefetch circuit being configured to detect a pattern from which addresses to memory requests likely to be accessed are predicted, and to generate prefetch suggestions indicative of addresses corresponding to the predicted memory requests.

2. The system of claim 1 wherein the prefetch circuit is operable to group the predicted memory request addresses into a plurality of sets corresponding to respective strides, and causes the prefetched data received from the memory cells to be stored into a plurality of sections each corresponding to a respective stride.

3. The system of claim 1 wherein the prefetch circuit is operable to selectively enable prefetching data based on the nature of the memory requests received from the link interface.

4. The system of claim 3 wherein the prefetch circuit is operable to selectively enable prefetching based on a percentage of memory requests for read data from the stored prefetch data compared to read data from the memory cells.

5. The system of claim 1 wherein the prefetch circuit comprises a plurality of prefetch buffers coupled to the memory device interface for receiving and storing prefetched data from memory cells being accessed based on the predicted addresses.

6. The system of claim 5 wherein the plurality of prefetch buffers comprises a single static random access memory device partitioned into a plurality of sections corresponding a plurality of strides.

7. The system of claim 5 wherein the prefetch circuit comprises a data read control circuit coupled to the memory device interface, the link interface, and the plurality of prefetch buffers, the data read control circuit operable to determine from the memory requests received from the link interface if the data corresponding to the memory requests are stored in the plurality of prefetch buffers, the data read control circuit further operable to transfer data from the plurality of prefetch buffers if the requested data are stored in the plurality of prefetch buffers and to transfer data from the memory device interface if the data are stored in the memory cells.

8. The system of claim 7 wherein the data read control circuit comprises a tag logic unit coupled to the link interface and the plurality of prefetched buffers, the tag logic unit operable to store addresses of the prefetched data stored in the plurality of prefetch buffers, the tag logic unit further operable to receive memory requests from the link interface, compare the addresses of the received memory requests to the addresses of the stored prefetched data, and generate a hit control signal indicative of whether an address match was determined.

9. The system of claim 7 wherein the data read control circuit comprises a multiplexer having data inputs coupled to the plurality of prefetch buffers, to the tag logic unit and to the memory device interface, and a data output coupled to the link interface, the multiplexer operable to transfer the data input from the plurality of prefetch buffers to the data output responsive to an active hit control signal received from the tag logic unit, and to transfer the data input form the memory device interface to the data output responsive to an inactive hit control signal received from the tag logic unit.

10. The system of claim 1 wherein the prefetch circuit is further operable to prefetch data from memory cells that are currently accessed such that the prefetching does not require the selected memory cells to be precharged.

11. The system of claim 1 wherein the link interface comprises an optical input/output port.

12. A system for prefetching data in a memory system comprising: a link interface receiving memory requests for access to memory cells in at least one of a plurality of memory devices; a memory device interface coupled to the memory devices, the memory device interface being operable to transfer memory requests to the memory devices for access to memory cells in at least one of the memory devices and to receive read data responsive to at least some of the memory requests; and a prefetch circuit coupled to the link interface to receive memory requests from the link interface and coupled to the memory device interface to receive data from the memory cells, the prefetch circuit operable to predict addresses that are likely to be accessed in the memory devices based on the memory requests and to prefetch and store data from memory cells according to the predicted addresses, the prefetch circuit further operable to provide the prefetched data to the link interface responsive to subsequent memory requests, the prefetch circuit comprising a single static random access memory device partitioned into a plurality of sections corresponding a plurality of strides and being coupled to the memory device interface for receiving and storing prefetched data from memory cells being accessed based on the predicted addresses.

13. A system for prefetching data in a memory system comprising: a link interface receiving memory requests for access to memory cells in at least one of a plurality of memory devices; a memory device interface coupled to the memory devices, the memory device interface being operable to transfer memory requests to the memory devices for access to memory cells in at least one of the memory devices and to receive read data responsive to at least some of the memory requests; and a prefetch circuit coupled to the link interface to receive memory requests from the link interface and coupled to the memory device interface to receive data from the memory cells, the prefetch circuit operable to predict addresses that are likely to be accessed in the memory devices based on the memory requests and to prefetch and store data from memory cells according to the predicted addresses, the prefetch circuit further operable to provide the prefetched data to the link interface responsive to subsequent memory requests, the prefetch circuit further comprising: a plurality of prefetch buffers coupled to the memory device interface for receiving and storing prefetched data from memory cells being accessed based on the predicted addresses; and a data read control circuit coupled to the memory device interface, the link interface, and the plurality of prefetch buffers, the data read control circuit operable to determine from the memory requests received from the link interface if the data corresponding to the memory requests are stored in the plurality of prefetch buffers, the data read control circuit further operable to transfer data from the plurality of prefetch buffers if the requested data are stored in the plurality of prefetch buffers and to transfer data from the memory device interface if the data are stored in the memory cells.

14. The system of claim 13 wherein the data read control circuit comprises a tag logic unit coupled to the link interface and the plurality of prefetched buffers, the tag logic unit operable to store addresses of the prefetched data stored in the plurality of prefetch buffers, the tag logic unit further operable to receive memory requests from the link interface, compare the addresses of the received memory requests to the addresses of the stored prefetched data, and generate a hit control signal indicative of whether an address match was determined.

15. The system of claim 13 wherein the data read control circuit comprises a multiplexer having data inputs coupled to the plurality of prefetch buffers, to the tag logic unit and to the memory device interface, and a data output coupled to the link interface, the multiplexer operable to transfer the data input from the plurality of prefetch buffers to the data output responsive to an active hit control signal received from the tag logic unit, and to transfer the data input form the memory device interface to the data output responsive to an inactive hit control signal received from the tag logic unit.

16. A memory hub comprising: a link interface receiving memory requests for access to memory cells in at least one of a plurality of memory device; a memory device interface coupled to the memory devices, the memory device interface being operable to transfer memory requests to the memory devices for access to memory cells in at least one of the memory devices and to receive data responsive to at least some of the memory requests; a prefetch circuit coupled to the link interface to receive memory requests from the link interface and coupled to the memory device interface to receive data from the memory cells, the prefetch circuit operable to predict addresses that are likely to be accessed in the memory devices based on the memory requests and generate prefetch suggestions indicative of the predicted addresses to prefetch data from memory cells, the prefetch circuit further operable to store the data that are prefetched and transfer the prefetch data to the link interface; and a memory sequencer coupled to the link interface, the memory device interface and the prefetch circuit, the memory sequencer operable to transfer memory requests received from the link interface to the prefetch circuit to determine if the data corresponding to the memory requests are stored in the prefetch circuit, the memory sequencer further being operable to transfer memory requests received from the link interface to the memory device interface to fetch the data corresponding to the memory requests if the data are not stored in the prefetch circuit, the memory sequencer further being operable to generate prefetch requests responsive to the prefetch suggestions received from the prefetch circuit to fetch data corresponding to the prefetch suggestions.

17. The memory hub of claim 16 wherein the prefetch circuit is operable to detect a pattern from which addresses to memory requests likely to be accessed are predicted, and operable to generate prefetch suggestions indicative of addresses corresponding to the predicted memory requests.

18. The memory hub of claim 17 wherein the prefetch circuit is further operable to group the predicted memory request addresses into a plurality of sets corresponding to respective strides, and to cause the prefetched data received from the memory cells to be stored into a plurality of sections each corresponding to a respective stride.

19. The memory hub of claim 17 wherein the prefetch circuit is further operable to selectively enable prefetching data based on the nature of the memory requests received from the link interface.

20. The memory hub of claim 19 wherein the prefetch circuit is configured to selectively enable prefetching based on a percentage of memory requests for read data from the stored prefetch data compared to read data from the memory cells.

21. The memory hub of claim 16 wherein the prefetch circuit comprises a plurality of prefetch buffers coupled to the memory device interface for receiving and storing prefetched data from memory cells being accessed based on the prefetch suggestions.

22. The memory hub of claim 21 wherein the plurality of prefetch buffers comprises a single static random access memory device partitioned into a plurality of sections corresponding a plurality of strides.

23. The memory hub of claim 21 wherein the plurality of prefetch buffers comprises a plurality of registers that are enabled and partitioned according to a plurality of respective strides.

24. The memory hub of claim 21 wherein the prefetch circuit comprises a data read control circuit coupled to the memory device interface, the link interface, and the plurality of prefetch buffers, the data read control circuit operable to determine from the memory requests received from the link interface if the data corresponding to the memory requests are stored in the plurality of prefetch buffers, the data read control circuit further operable to transfer data from the plurality of prefetch buffers if the requested data are stored in the plurality of prefetch buffers and to transfer data from the memory device interface if the data are stored in the memory cells.

25. The memory hub of claim 24 wherein the data read control circuit comprises a tag logic unit coupled to the link interface and the plurality of prefetched buffers, the tag logic unit operable to store addresses of the prefetched data stored in the plurality of prefetch buffers, the tag logic unit further operable to receive memory requests from the link interface, compare the addresses of the received memory requests to the addresses of the stored prefetched data, and generate a hit control signal indicative of whether an address match was determined.

26. The memory of hub of claim 25 wherein the tag logic unit is further coupled the memory sequencer to which the hit control signal is applied, and wherein the memory sequencer is prevented from transferring a memory request to the memory device interface responsive to receiving an active hit control signal.

27. The memory hub of claim 24 wherein the data read control circuit comprises a multiplexer having data inputs coupled to the plurality of prefetch buffers, to the tag logic unit and to the memory device interface, and a data output coupled to the link interface, the multiplexer operable to transfer the data input from the plurality of prefetch buffers to the data output responsive to an active hit control signal received from the tag logic unit, and to transfer the data input from the memory device interface to the data output responsive to an inactive hit control signal received from the tag logic unit.

28. The memory hub of claim 16 wherein the memory sequencer is operable to generate and transfer prefetch requests to the memory device interface only when memory requests are not being transferred from the link interface to the memory sequencer.

29. The memory hub of claim 16 wherein the prefetch circuit is further operable to prefetch data from memory cells that are currently accessed such that the act of prefetching data does not require the selected memory cells to be precharged.

30. The memory hub of claim 16 wherein the link interface comprises an optical input/output port.

31. A computer system, comprising: a central processing unit (“CPU”); a system controller coupled to the CPU, the system controller having an input port and an output port; an input device coupled to the CPU through the system controller; an output device coupled to the CPU through the system controller; a storage device coupled to the CPU through the system controller; a plurality of memory modules, each of the memory modules comprising: a plurality of memory devices; and a system for prefetching data comprising: a link interface receiving memory requests for access to memory cells in at least one of the memory devices; a memory device interface coupled to the memory devices, the memory device interface being operable to transfer memory requests to the memory devices for access to memory cells in at least one of the memory devices and to receive read data responsive to at least some of the memory requests; and a prefetch circuit coupled to the link interface to receive memory requests from the link interface and coupled to the memory device interface to receive data from the memory cells, the prefetch circuit operable to predict addresses that are likely to be accessed in the memory devices based on the memory requests and to prefetch and store data from memory cells according to the predicted addresses, the prefetch circuit further operable to provide the prefetched data to the link interface responsive to subsequent memory requests, the prefetch circuit being configured to detect a pattern from which addresses to memory requests likely to be accessed are predicted, and operable to generate prefetch suggestions indicative of addresses corresponding to the predicted memory requests.

32. The computer system of claim 31 wherein the prefetch circuit is operable to group the predicted memory request addresses into a plurality of sets corresponding to respective strides, and causes the prefetched data received from the memory cells to be stored into a plurality of sections each corresponding to a respective stride.

33. The computer system of claim 31 wherein the prefetch circuit is operable to selectively enable prefetching data based on the nature of the memory requests received from the link interface.

34. The computer system of claim 33 wherein the prefetch circuit is operable to selectively enable prefetching based on a percentage of memory requests for read data from the stored prefetch data compared to read data from the memory cells.

35. The computer system of claim 31 wherein the prefetch circuit comprises a plurality of prefetch buffers coupled to the memory device interface for receiving and storing prefetched data from memory cells being accessed based on the predicted addresses.

36. The computer system of claim 35 wherein the plurality of prefetch buffers comprises a single static random access memory device partitioned into a plurality of sections corresponding a plurality of strides.

37. The computer system of claim 35 wherein the prefetch circuit comprises a data read control circuit coupled to the memory device interface, the link interface, and the plurality of prefetch buffers, the data read control circuit operable to determine from the memory requests received from the link interface if the data corresponding to the memory requests are stored in the plurality of prefetch buffers, the data read control circuit further operable to transfer data from the plurality of prefetch buffers if the requested data are stored in the plurality of prefetch buffers and to transfer data from the memory device interface if the data are stored in the memory cells.

38. The computer system of claim 37 wherein the data read control circuit comprises a tag logic unit coupled to the link interface and the plurality of prefetched buffers, the tag logic unit operable to store addresses of the prefetched data stored in the plurality of prefetch buffers, the tag logic unit further operable to receive memory requests from the link interface, compare the addresses of the received memory requests to the addresses of the stored prefetched data, and generate a hit control signal indicative of whether an address match was determined.

39. The computer system of claim 37 wherein the data read control circuit comprises a multiplexer having data inputs coupled to the plurality of prefetch buffers, to the tag logic unit and to the memory device interface, and a data output coupled to the link interface, the multiplexer operable to transfer the data input from the plurality of prefetch buffers to the data output responsive to an active hit control signal received from the tag logic unit, and to transfer the data input form the memory device interface to the data output responsive to an inactive hit control signal received from the tag logic unit.

40. The computer system of claim 31 wherein the prefetch circuit is further operable to prefetch data from memory cells that are currently accessed such that the prefetching does not require the selected memory cells to be precharged.

41. The computer system of claim 31 wherein the link interface comprises an optical input/output port.

42. A computer system, comprising: a central processing unit (“CPU”); a system controller coupled to the CPU, the system controller having an input port and an output port; an input device coupled to the CPU through the system controller; an output device coupled to the CPU through the system controller; a storage device coupled to the CPU through the system controller; a plurality of memory modules, each of the memory modules comprising: a plurality of memory devices; and a memory hub comprising: a link interface receiving memory requests for access to memory cells in at least one of the memory devices; a memory device interface coupled to the memory devices, the memory device interface being operable to transfer memory requests to the memory devices for access to memory cells in at least one of the memory devices and to receive data responsive to at least some of the memory requests; a prefetch circuit coupled to the link interface to receive memory requests from the link interface and coupled to the memory device interface to receive data from the memory cells, the prefetch circuit operable to predict addresses that are likely to be accessed in the memory devices based on the memory requests and generate prefetch suggestions indicative of the predicted addresses to prefetch data from memory cells, the prefetch circuit further operable to store the data that are prefetched and transfer the prefetched data to the link interface; and a memory sequencer coupled to the link interface, the memory device interface and the prefetch circuit, the memory sequencer operable to transfer memory requests received from the link interface to the prefetch circuit to determine if the data corresponding to the memory requests are stored in the prefetch circuit, the memory sequencer further being operable to transfer memory requests received from the link interface to the memory device interface to fetch the data corresponding to the memory requests if the data are not stored, in the prefetch circuits, the memory sequencer further operable to generate prefetch requests responsive to the prefetch suggestions received from the prefetch circuit to fetch data corresponding to the prefetch suggestions.

43. The computer system of claim 42 wherein the prefetch circuit is operable to detect a pattern from which addresses to memory requests likely to be accessed are predicted, and operable to generate prefetch suggestions indicative of addresses corresponding to the predicted memory requests.

44. The computer system of claim 43 wherein the prefetch circuit is further operable to group the predicted memory request addresses into a plurality of sets corresponding to respective strides, and to cause the prefetched data received from the memory cells to be stored into a plurality of sections each corresponding to a respective stride.

45. The computer system of claim 43 wherein the prefetch circuit is further operable to selectively enable prefetching data based on the nature of the memory requests received from the link interface.

46. The computer system of claim 45 wherein the prefetch circuit is configured to selectively enable prefetching based on a percentage of memory requests for read data from the stored prefetch data compared to read data from the memory cells.

47. The computer system of claim 42 wherein the prefetch circuit comprises a plurality of prefetch buffers coupled to the memory device interface for receiving and storing prefetched data from memory cells being accessed based on the prefetch suggestions.

48. The computer system of claim 47 wherein the plurality of prefetch buffers comprises a single static random access memory device partitioned into a plurality of sections corresponding a plurality of strides.

49. The computer system of claim 47 wherein the plurality of prefetch buffers comprises a plurality of registers that are enabled and partitioned according to a plurality of respective strides.

50. The computer system of claim 47 wherein the prefetch circuit comprises a data read control circuit coupled to the memory device interface, the link interface, and the plurality of prefetch buffers, the data read control circuit operable to determine from the memory requests received from the link interface if the data corresponding to the memory requests are stored in the plurality of prefetch buffers, the data read control circuit further operable to transfer data from the plurality of prefetch buffers if the requested data are stored in the plurality of prefetch buffers and to transfer data from the memory device interface if the data are stored in the memory cells.

51. The computer system of claim 50 wherein the data read control circuit comprises a tag logic unit coupled to the link interface and the plurality of prefetched buffers, the tag logic unit operable to store addresses of the prefetched data stored in the plurality of prefetch buffers, the tag logic unit further operable to receive memory requests from the link interface, compare the addresses of the received memory requests to the addresses of the stored prefetched data, and generate a hit control signal indicative of whether an address match was determined.

52. The computer system of claim 51 wherein the tag logic unit is further coupled the memory sequencer to which the hit control signal is applied, and wherein the memory sequencer is prevented from transferring a memory request to the memory device interface responsive to receiving an active hit control signal.

53. The computer system of claim 50 wherein the data read control circuit comprises a multiplexer having data inputs coupled to the plurality of prefetch buffers, to the tag logic unit and to the memory device interface, and a data output coupled to the link interface, the multiplexer operable to transfer the data input from the plurality of prefetch buffers to the data output responsive to an active hit control signal received from the tag logic unit, and to transfer the data input from the memory device interface to the data output responsive to an inactive hit control signal received from the tag logic unit.

54. The computer system of claim 42 wherein the memory sequencer is operable to generate and transfer prefetch requests to the memory device interface only when memory requests are not being transferred from the link interface to the memory sequencer.

55. The computer system of claim 42 wherein the prefetch circuit is further operable to prefetch data from memory cells that are currently accessed such that the act of prefetching data does not require the selected memory cells to be precharged.

56. The computer system of claim 42 wherein the link interface comprises an optical input/output port.

57. A computer system, comprising: a central processing unit (“CPU”); a system controller coupled to the CPU, the system controller having an input port and an output port; an input device coupled to the CPU through the system controller; an output device coupled to the CPU through the system controller; a storage device coupled to the CPU through the system controller; a plurality of memory modules, each of the memory modules comprising: a plurality of memory devices; and a system for prefetching data comprising: a link interface receiving memory requests for access to memory cells in at least one of the memory devices; a memory device interface coupled to the memory devices, the memory device interface being operable to transfer memory requests to the memory devices for access to memory cells in at least one of the memory devices and to receive read data responsive to at least some of the memory requests; and a prefetch circuit coupled to the link interface to receive memory requests from the link interface and coupled to the memory device interface to receive data from the memory cells, the prefetch circuit operable to predict addresses that are likely to be accessed in the memory devices based on the memory requests and to prefetch and store data from memory cells according to the predicted addresses, the prefetch circuit further operable to provide the prefetched data to the link interface responsive to subsequent memory requests, the prefetch circuit comprising a single static random access memory device partitioned into a plurality of sections corresponding a plurality of strides and being coupled to the memory device interface for receiving and storing prefetched data from memory cells being accessed based on the predicted addresses.

58. A computer system, comprising: a central processing unit (“CPU”); a system controller coupled to the CPU, the system controller having an input port and an output port; an input device coupled to the CPU through the system controller; an output device coupled to the CPU through the system controller; a storage device coupled to the CPU through the system controller; a plurality of memory modules, each of the memory modules comprising: a plurality of memory devices; and a system for prefetching data comprising: a link interface receiving memory requests for access to memory cells in at least one of the memory devices; a memory device interface coupled to the memory devices, the memory device interface being operable to transfer memory requests to the memory devices for access to memory cells in at least one of the memory devices and to receive read data responsive to at least some of the memory requests; and a prefetch circuit coupled to the link interface to receive memory requests from the link interface and coupled to the memory device interface to receive data from the memory cells, the prefetch circuit operable to predict addresses that are likely to be accessed in the memory devices based on the memory requests and to prefetch and store data from memory cells according to the predicted addresses, the prefetch circuit further operable to provide the prefetched data to the link interface responsive to subsequent memory requests, the prefetch circuit further comprising: a plurality of prefetch buffers coupled to the memory device interface for receiving and storing prefetched data from memory cells being accessed based on the predicted addresses; and a data read control circuit coupled to the, memory device interface, the link interface, and the plurality of prefetch buffers, the data read control circuit operable to determine from the memory requests received from the link interface if the data corresponding to the memory requests are stored in the plurality of prefetch buffers, the data read control circuit further operable to transfer data from the plurality of prefetch buffers if the requested data are stored in the plurality of prefetch buffers and to transfer data from the memory device interface if the data are stored in the memory cells.

59. The computer system of claim 58 wherein the data read control circuit comprises a tag logic unit coupled to the link interface and the plurality of prefetched buffers, the tag logic unit operable to store addresses of the prefetched data stored in the plurality of prefetch buffers, the tag logic unit further operable to receive memory requests from the link interface, compare the addresses of the received memory requests to the addresses of the stored prefetched data, and generate a hit control signal indicative of whether an address match was determined.

60. The computer system of claim 58 wherein the data read control circuit comprises a multiplexer having data inputs coupled to the plurality of prefetch buffers, to the tag logic unit and to the memory device interface, and a data output coupled to the link interface, the multiplexer operable to transfer the data input from the plurality of prefetch buffers to the data output responsive to an active hit control signal received from the tag logic unit, and to transfer the data input from the memory device interface to the data output responsive to an inactive hit control signal received from the tag logic unit.

61. A method of prefetching data in a memory system comprising: receiving memory requests for access to memory cells in a plurality of memory devices; coupling the memory requests to the memory devices, wherein at least some of the memory requests being memory requests to read data; receiving read data responsive to the read memory requests; prefetching data from the memory devices that are likely to be accessed in the memory devices based on the received memory requests and storing the prefetched data; transferring the prefetched data responsive to subsequent memory requests; dividing the stored prefetched data into a plurality of sections each corresponding to a respective stride; and storing the prefetched data from the memory devices indicative of the predicted addresses in the section corresponding to the respective stride.

62. The method of claim 61 further comprising: storing prefetch addresses corresponding to the stored prefetched data; receiving memory request addresses corresponding to subsequent memory requests; comparing each received memory request address to the prefetch addresses; and determining that the requested read data are stored as prefetched data in the event of an address match.

63. The method of claim 62 further comprising: transferring read data stored as prefetched data responsive to determining that the requested read data are stored as prefetched data; and transferring read data from the memory devices responsive to determining that the requested read data are not stored as prefetched data.

64. The method of claim 61 further comprising prefetching data from memory cells that are currently accessed such that the prefetching does not require the selected memory cells to be precharged.

65. The method of claim 61 wherein prefetching data from the memory devices comprises prefetching data only when the memory requests are not being received.

66. The method of claim 61 further comprising selectively enabling prefetching based on the nature of the received memory requests.

67. The method of claim 61 wherein the act of receiving memory requests for access to memory cells in a plurality of memory devices comprises receiving optical signals corresponding to the memory requests.

68. A method of reading data in a memory hub comprising: receiving memory requests for access to a memory device; coupling the memory requests to the memory device responsive to the received memory request, at least some of the memory requests being memory requests to read data; receiving read data responsive to the read memory requests; predicting addresses that are likely to be accessed in the memory device based on the read memory requests; generating prefetch requests indicative of the predicted addresses; prefetching and storing the read data from the memory device responsive to the prefetch requests; determining from a read memory request if the requested read data are stored as prefetched data; transferring the prefetched data if a determination has been made; transferring data from the memory device if a determination has not been made; grouping the predicted addresses into a plurality of sets corresponding to respective strides; dividing the stored prefetched data into a plurality of sections each corresponding to a respective stride; and storing the prefetched data from the memory devices indicative of the predicted addresses in the section corresponding to the stride containing the predicted address from which the data was read.

69. The method of claim 68 further comprising: storing prefetch addresses corresponding to the stored prefetched data; receiving memory request addresses corresponding to subsequent memory requests; comparing each received memory request address to the prefetch addresses; and determining that the requested read data are stored as prefetched data in the event of an address match.

70. The method of claim 68 further comprising prefetching data from memory cells that are currently accessed such that the prefetching does not require the selected memory cells to be precharged.

71. The method of claim 68 wherein prefetching and storing the read data from the memory device responsive to the prefetch requests comprise prefetching data only when the memory requests are not being received.

72. The method of claim 68 further comprising selectively enabling prefetching based on the nature of the received memory requests.

73. The method of claim 68 wherein the act of receiving memory requests for access to memory cells in a plurality of memory devices comprises receiving optical signals corresponding to the memory requests.

TECHNICAL FIELD

This invention relates to computer systems, and, more particularly, to a computer system having a memory hub coupling several memory devices to a processor or other memory access device.

BACKGROUND OF THE INVENTION

Computer systems use memory devices, such as dynamic random access memory (“DRAM”) devices, to store data that are accessed by a processor. These memory devices are normally used as system memory in a computer system. In a typical computer system, the processor communicates with the system memory through a processor bus and a memory controller. The processor issues a memory request, which includes a memory command, such as a read command, and an address designating the location from which data or instructions are to be read. The memory controller uses the command and address to generate appropriate command signals as well as row and column addresses, which are applied to the system memory. In response to the commands and addresses, data are transferred between the system memory and the processor. The memory controller is often part of a system controller, which also includes bus bridge circuitry for coupling the processor bus to an expansion bus, such as a PCI bus.

Although the operating speed of memory devices has continuously increased, this increase in operating speed has not kept pace with increases in the operating speed of processors. Even slower has been the increase in operating speed of memory controllers coupling processors to memory devices. The relatively slow speed of memory controllers and memory devices limits the data bandwidth between the processor and the memory devices.

In addition to the limited bandwidth between processors and memory devices, the performance of computer systems is also limited by latency problems that increase the time required to read data from system memory devices. More specifically, when a memory device read command is coupled to a system memory device, such as a synchronous DRAM (“SDRAM”) device, the read data are output from the SDRAM device only after a delay of several clock periods. Therefore, although SDRAM devices can synchronously output burst data at a high data rate, the delay in initially providing the data can significantly slow the operating speed of a computer system using such SDRAM devices.

One approach to alleviating the memory latency problem is to use multiple memory devices coupled to the processor through a memory hub. In a memory hub architecture, a system controller or memory controller is coupled to several memory modules, each of which includes a memory hub coupled to several memory devices. The memory hub efficiently routes memory requests and responses between the controller and the memory devices. Computer systems employing this architecture can have a higher bandwidth because a processor can access one memory device while another memory device is responding to a prior memory access. For example, the processor can output write data to one of the memory devices in the system while another memory device in the system is preparing to provide read data to the processor. Although computer systems using memory hubs may provide superior performance, they nevertheless often fail to operate at optimum speed for several reasons. For example, even though memory hubs can provide computer systems with a greater memory bandwidth, they still suffer from latency problems of the type described above. More specifically, although the processor may communicate with one memory device while another memory device is preparing to transfer data, it is sometimes necessary to receive data from one memory device before the data from another memory device can be used. In the event data must be received from one memory device before data received from another memory device can be used, the latency problem continues to slow the operating speed of such computer systems.

One technique that has been used to reduce latency in memory devices is to prefetch data, i.e., read data from system memory before the data are requested by a program being executed. Generally the data that are to be prefetched are selected based on a pattern of previously fetched data. The pattern may be as simple as a sequence of addresses from which data are fetched so that data can be fetched from subsequent addresses in the sequence before the data are needed by the program being executed. The pattern, which is known as a “stride,” may, of course, be more complex.

Although data prefetching can reduce memory access latencies in conventional computer systems, prefetching of data has not been effectively used in a manner that provides optimum performance in computer systems using memory hubs. In particular, the vast amount of data that can be addressed in a computer system having several memory hubs makes it difficult to accurately predict which data will be subsequently needed. Furthermore, even if the data that will be required can be correctly anticipated, it can be unduly time consuming to couple the data from memory devices in a memory module, and through a memory hub in the memory module to a prefetch buffer in the system controller or memory controller. The need to couple the data from the memory module to the prefetch buffer can also reduce the memory bandwidth of the system if the data are being prefetched at a time when normal memory accesses are being attempted.

There is therefore a need for a computer architecture that provides the advantages of a memory hub architecture and also minimize the latency problems common in such systems, thereby providing memory devices with high bandwidth and low latency.

SUMMARY OF THE INVENTION

A memory module that may be used in a computer system includes a plurality of memory devices coupled to a memory hub. The memory hub includes a link interface receiving memory requests for access to memory cells in at least one of the memory devices. A memory device interface couples memory requests to the memory devices and receives read data responsive to at least some of the memory requests. A history logic unit included in the memory hub receives memory requests from the link interface and predicts on the basis of the memory requests the addresses in the memory devices that are likely to be accessed. The history logic unit then generates prefetching suggestions indicative of the predicted addresses. The memory hub also includes a memory sequencer that couples memory requests to the memory device interface responsive to memory requests received from the link interface. The memory sequencer also generates and couples prefetching requests to the memory device interface responsive to prefetching suggestions received from the history logic unit. A prefetch buffer included in the memory hub receives and stores read data from memory cells being accessed responsive to the prefetching requests. Finally, a data read control unit included in the memory hub determines from a read memory request received from the link interface if the read data are stored in the prefetch buffer. If the read data are stored in the prefetch buffer, the read data are read from the prefetch buffer. If the read data are not stored in the prefetch buffer, the read data are read from the memory devices.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram of a computer system according to one example of the invention in which a memory hub is included in each of a plurality of memory modules.

FIG. 2 is a block diagram of a memory hub used in the computer system of FIG. 1, which contains a prefetch buffer according to one example of the invention.

DETAILED DESCRIPTION OF THE INVENTION

A computer system 100 according to one example of the invention is shown in FIG. 1. The computer system 100 includes a processor 104 for performing various computing functions, such as executing specific software to perform specific calculations or tasks. The processor 104 includes a processor bus 106 that normally includes an address bus, a control bus, and a data bus. The processor bus 106 is typically coupled to cache memory 108 , which, as previously mentioned, is usually static random access memory (“SRAM”). Finally, the processor bus 106 is coupled to a system controller 110 , which is also sometimes referred to as a “North Bridge” or “memory controller.”

The system controller 110 serves as a communications path to the processor 104 for a variety of other components. More specifically, the system controller 110 includes a graphics port that is typically coupled to a graphics controller 112 , which is, in turn, coupled to a video terminal 114 . The system controller 110 is also coupled to one or more input devices 118 , such as a keyboard or a mouse, to allow an operator to interface with the computer system 100 . Typically, the computer system 100 also includes one or more output devices 120 , such as a printer, coupled to the processor 104 through the system controller 110 . One or more data storage devices 124 are also typically coupled to the processor 104 through the system controller 110 to allow the processor 104 to store data or retrieve data from internal or external storage media (not shown). Examples of typical storage devices 124 include hard and floppy disks, tape cassettes, and compact disk read-only memories (CD-ROMs).

The system controller 110 is coupled to several memory modules 130 a, b . . . n , which serve as system memory for the computer system 100 . The memory modules 130 are preferably coupled to the system controller 110 through a high-speed link 134 , which may be an optical or electrical communication path or some other type of communications path. In the event the high-speed link 134 is implemented as an optical communication path, the optical communication path may be in the form of one or more optical fibers, for example. In such case, the system controller 110 and the memory modules will include an optical input/output port or separate input and output ports coupled to the optical communication path. The memory modules 130 are shown coupled to the system controller 110 in a multi-drop arrangement in which the single high-speed link 134 is coupled to all of the memory modules 130 . However, it will be understood that other topologies may also be used, such as a point-to-point coupling arrangement in which a separate high-speed link (not shown) is used to couple each of the memory modules 130 to the system controller 110 . A switching topology may also be used in which the system controller 110 is selectively coupled to each of the memory modules 130 through a switch (not shown). Other topologies that may be used will be apparent to one skilled in the art.

Each of the memory modules 130 includes a memory hub 140 for controlling access to 8 memory devices 148 , which, in the example illustrated in FIG. 2, are synchronous dynamic random access memory (“SDRAM”) devices. However, a fewer or greater number of memory devices 148 may be used, and memory devices other than SDRAM devices may, of course, also be used. The memory hub 140 is coupled to each of the system memory devices 148 through a bus system 150 , which normally includes a control bus, an address bus and a data bus.

One example of the memory hub 140 of FIG. 1 is shown in FIG. 2. The memory hub 140 includes a link interface 152 that is coupled to the high-speed link 134 . The nature of the link interface 152 will depend upon the characteristics of the high-speed link 134 . For example, in the event the high-speed link 134 is implemented using an optical communications path, the link interface 152 will include an optical input/output port or separate input and output ports and will convert optical signals received through the optical communications path into electrical signals and electrical signals into optical signals that are transmitted to the optical communications path. In any case, the link interface 152 may include a variety of conventional interface circuitry such as, for example, a first-in, first-out buffer (not shown), for receiving and storing memory requests as they are received through the high-speed link 134 . The memory requests can then be stored in the link interface until they can be processed by the memory hub 140 .

A memory request received by the link interface 152 is processed by first transferring the request to a memory sequencer 160 . The memory sequencer 160 converts the memory requests from the format output from the system controller 110 (FIG. 1) into a memory request having a format that can be used by the memory devices 148 . These re-formatted request signals will normally include memory command signals, which are derived from memory commands contained in the memory request received by the memory hub 140 , and row and column address signals, which are derived from an address contained in the memory request received by the memory hub 140 . In the event the memory request is a write memory request, the re-formatted request signals will normally include write data signals which are derived from write data contained in the memory request received by the memory hub 140 . For example, where the memory devices 148 are conventional DRAM devices, the memory sequencer 160 will output row address signals, a row address strobe (“RAS”) signal, an active low write/active high read signal (“W*/R”), column address signals and a column address strobe (“CAS”) signal. The re-formatted memory requests are preferably output from the sequencer 160 in the order they will be used by the memory d