Jeddeloh, Joseph M. (Shoreview, MN, US)
James, Ralph (Andover, MN, US)

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11/731122

08/12/2008

03/29/2007

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Micron Technology, Inc. (Boise, ID, US)

711/151

711/158

G06F12/00

3742253	THREE STATE LOGIC DEVICE WITH APPLICATIONS	June, 1973	Kronies	307/247
4045781	Memory module with selectable byte addressing for digital data processing system	August, 1977	Levy et al.	364/200
4078228	Loop data highway communication system	March, 1978	Miyazaki	340/147R
4240143	Hierarchical multi-processor network for memory sharing	December, 1980	Besemer et al.	364/200
4245306	Selection of addressed processor in a multi-processor network	January, 1981	Besemer et al.	364/200
4253144	Multi-processor communication network	February, 1981	Bellamy et al.	364/200
4253146	Module for coupling computer-processors	February, 1981	Bellamy et al.	364/200
4608702	Method for digital clock recovery from Manchester-encoded signals	August, 1986	Hirzel et al.	375/110
4707823	Fiber optic multiplexed data acquisition system	November, 1987	Holdren et al.	370/1
4724520	Modular multiport data hub	February, 1988	Athanas et al.	364/200
4831520	Bus interface circuit for digital data processor	May, 1989	Rubinfeld et al.	364/200
4843263	Clock timing controller for a plurality of LSI chips	June, 1989	Ando	307/480
4891808	Self-synchronizing multiplexer	January, 1990	Williams	370/112
4930128	Method for restart of online computer system and apparatus for carrying out the same	May, 1990	Suzuki et al.	371/12
4953930	CPU socket supporting socket-to-socket optical communications	September, 1990	Ramsey et al.	350/96.11
4982185	System for synchronous measurement in a digital computer network	January, 1991	Holmberg et al.	340/825.21
5241506	Semiconductor memory circuit apparatus	August, 1993	Motegi et al.	365/210
5243703	Apparatus for synchronously generating clock signals in a data processing system	September, 1993	Farmwald et al.	395/325
5251303	System for DMA block data transfer based on linked control blocks	October, 1993	Fogg, Jr. et al.	395/275
5269022	Method and apparatus for booting a computer system by restoring the main memory from a backup memory	December, 1993	Shinjo et al.	395/700
5299293	Protection arrangement for an optical transmitter/receiver device	March, 1994	Mestdagh et al.	359/110
5313590	System having fixedly priorized and grouped by positions I/O lines for interconnecting router elements in plurality of stages within parrallel computer	May, 1994	Taylor	395/325
5317752	Fault-tolerant computer system with auto-restart after power-fall	May, 1994	Jewett et al.	395/750
5319755	Integrated circuit I/O using high performance bus interface	June, 1994	Farmwald et al.	395/325
5327553	Fault-tolerant computer system with /CONFIG filesystem	July, 1994	Jewett et al.	395/575
5355391	High speed bus system	October, 1994	Horowitz et al.	375/36
5432823	Method and circuitry for minimizing clock-data skew in a bus system	July, 1995	Gasbarro et al.	375/356
5432907	Network hub with integrated bridge	July, 1995	Picazo, Jr. et al.	395/200
5442770	Triple port cache memory	August, 1995	Barratt	395/403
5461627	Access protocol for a common channel wireless network	October, 1995	Rypinski	370/95.2
5465229	Single in-line memory module	November, 1995	Bechtolsheim et al.	345/477
5479370	Semiconductor memory with bypass circuit	December, 1995	Furuyama et al.	365/189.12
5497476	Scatter-gather in data processing system	March, 1996	Oldfield et al.	395/439
5502621	Mirrored pin assignment for two sided multi-chip layout	March, 1996	Schumacher et al.	361/760
5544319	Fiber optic memory coupling system with converter transmitting and receiving bus data in parallel fashion and diagnostic data in serial fashion	August, 1996	Acton et al.	395/200.07
5566325	Method and apparatus for adaptive memory access	October, 1996	Bruce, II et al.	395/494
5577220	Method for saving and restoring the state of a CPU executing code in protected mode including estimating the value of the page table base register	November, 1996	Combs et al.	395/416
5581767	Bus structure for multiprocessor system having separated processor section and control/memory section	December, 1996	Katsuki et al.	395/800
5606717	Memory circuitry having bus interface for receiving information in packets and access time registers	February, 1997	Farmwald et al.	395/856
5638334	Integrated circuit I/O using a high performance bus interface	June, 1997	Farmwald et al.	365/230.03
5659798	Method and system for initiating and loading DMA controller registers by using user-level programs	August, 1997	Blumrich et al.	395/846
5687325	Application specific field programmable gate array	November, 1997	Chang	395/284
5706224	Content addressable memory and random access memory partition circuit	January, 1998	Srinivasan et al.	365/49
5715456	Method and apparatus for booting a computer system without pre-installing an operating system	February, 1998	Bennett et al.	395/652
5729709	Memory controller with burst addressing circuit	March, 1998	Harness	395/405
5748616	Data link module for time division multiplexing control systems	May, 1998	Riley	370/242
5818844	Address generation and data path arbitration to and from SRAM to accommodate multiple transmitted packets	October, 1998	Singh et al.	370/463
5819304	Random access memory assembly	October, 1998	Nilsen et al.	711/5
5822255	Semiconductor integrated circuit for supplying a control signal to a plurality of object circuits	October, 1998	Uchida	365/194
5832250	Multi set cache structure having parity RAMs holding parity bits for tag data and for status data utilizing prediction circuitry that predicts and generates the needed parity bits	November, 1998	Whittaker	395/471
5875352	Method and apparatus for multiple channel direct memory access control	February, 1999	Gentry et al.	395/843
5875454	Compressed data cache storage system	February, 1999	Craft et al.	711/113
5928343	Memory module having memory devices containing internal device ID registers and method of initializing same	July, 1999	Farmwald et al.	710/104
5966724	Synchronous memory device with dual page and burst mode operations	October, 1999	Ryan	711/105
5973935	Interdigitated leads-over-chip lead frame for supporting an integrated circuit die	October, 1999	Schoenfeld et al.	361/813
5973951	Single in-line memory module	October, 1999	Bechtolsheim et al.	365/52
5978567	System for distribution of interactive multimedia and linear programs by enabling program webs which include control scripts to define presentation by client transceiver	November, 1999	Rebane et al.	395/200.49
5987196	Semiconductor structure having an optical signal path in a substrate and method for forming the same	November, 1999	Noble	385/14
6014721	Method and system for transferring data between buses having differing ordering policies	January, 2000	Arimilli et al.	710/129
6023726	User configurable prefetch control system for enabling client to prefetch documents from a network server	February, 2000	Saksena	709/219
6029250	Method and apparatus for adaptively adjusting the timing offset between a clock signal and digital signals transmitted coincident with that clock signal, and memory device and system using same	February, 2000	Keeth	713/400
6031241	Capillary discharge extreme ultraviolet lamp source for EUV microlithography and other related applications	February, 2000	Silfvast et al.	250/504R
6033951	Process for fabricating a storage capacitor for semiconductor memory devices	March, 2000	Chao	438/253
6038630	Shared access control device for integrated system with multiple functional units accessing external structures over multiple data buses	March, 2000	Foster et al.	710/132
6061263	Small outline rambus in-line memory module	May, 2000	Boaz et al.	365/51
6061296	Multiple data clock activation with programmable delay for use in multiple CAS latency memory devices	May, 2000	Ternullo, Jr. et al.	365/233
6064706	Apparatus and method of desynchronizing synchronously mapped asynchronous data	May, 2000	Driskill et al.	375/372
6067262	Redundancy analysis for embedded memories with built-in self test and built-in self repair	May, 2000	Irrinki et al.	365/201
6067649	Method and apparatus for a low power self test of a memory subsystem	May, 2000	Goodwin	714/718
6073190	System for dynamic buffer allocation comprising control logic for controlling a first address buffer and a first data buffer as a matched pair	June, 2000	Rooney	710/56
6076139	Multimedia computer architecture with multi-channel concurrent memory access	June, 2000	Welker et al.	711/104
6079008	Multiple thread multiple data predictive coded parallel processing system and method	June, 2000	Clery, III	712/11
6098158	Software-enabled fast boot	August, 2000	Lay et al.	711/162
6100735	Segmented dual delay-locked loop for precise variable-phase clock generation	August, 2000	Lu	327/158
6105075	Scatter gather memory system for a hardware accelerated command interpreter engine	August, 2000	Ghaffari	710/5
6125431	Single-chip microcomputer using adjustable timing to fetch data from an external memory	September, 2000	Kobayashi	711/154
6131149	Apparatus and method for reading data from synchronous memory with skewed clock pulses	October, 2000	Lu et al.	711/167
6134624	High bandwidth cache system	October, 2000	Burns et al.	710/131
6137709	Small outline memory module	October, 2000	Boaz et al.	365/51
6144587	Semiconductor memory device	November, 2000	Yoshida	365/189.05
6167465	System for managing multiple DMA connections between a peripheral device and a memory and performing real-time operations on data carried by a selected DMA connection	December, 2000	Parvin et al.	710/22
6167486	Parallel access virtual channel memory system with cacheable channels	December, 2000	Lee et al.	711/120
6175571	Distributed memory switching hub	January, 2001	Haddock et al.	370/423
6185352	Optical fiber ribbon fan-out cables	February, 2001	Hurley	385/114
6186400	Bar code reader with an integrated scanning component module mountable on printed circuit board	February, 2001	Dvorkis et al.	235/462.45
6191663	Echo reduction on bit-serial, multi-drop bus	February, 2001	Hannah	333/17.3
6201724	Semiconductor memory having improved register array access speed	March, 2001	Ishizaki et al.	365/49
6208180	Core clock correction in a 2/N mode clocking scheme	March, 2001	Fisch et al.	327/141
6219725	Method and apparatus for performing direct memory access transfers involving non-sequentially-addressable memory locations	April, 2001	Diehl et al.	710/26
6233376	Embedded fiber optic circuit boards and integrated circuits	May, 2001	Updegrove	385/14
6243769	Dynamic buffer allocation for a computer system	June, 2001	Rooney	710/56
6243831	Computer system with power loss protection mechanism	June, 2001	Mustafa et al.	714/24
6246618	Semiconductor integrated circuit capable of testing and substituting defective memories and method thereof	June, 2001	Yamamoto et al.	365/200
6247107	Chipset configured to perform data-directed prefetching	June, 2001	Christie	711/216
6249802	Method, system, and computer program product for allocating physical memory in a distributed shared memory network	June, 2001	Richardson et al.	709/200
6256325	Transmission apparatus for half duplex communication using HDLC	July, 2001	Park	370/503
6256692	CardBus interface circuit, and a CardBus PC having the same	July, 2001	Yoda et al.	710/104
6272600	Memory request reordering in a data processing system	August, 2001	Talbot et al.	711/140
6272609	Pipelined memory controller	August, 2001	Jeddeloh	711/169
6278755	Bit synchronization circuit	August, 2001	Baba et al.	375/360
6285349	Correcting non-uniformity in displays	September, 2001	Smith	345/147
6286083	Computer system with adaptive memory arbitration scheme	September, 2001	Chin et al.	711/151
6289068	Delay lock loop with clock phase shifter	September, 2001	Hassoun et al.	375/376
6294937	Method and apparatus for self correcting parallel I/O circuitry	September, 2001	Crafts et al.	327/158
6301637	High performance data paths	October, 2001	Krull et al.	711/112
6324485	Application specific automated test equipment system for testing integrated circuit devices in a native environment	November, 2001	Ellis	702/117
6327642	Parallel access virtual channel memory system	December, 2001	Lee et al.	711/120
6330205	Virtual channel synchronous dynamic random access memory	December, 2001	Shimizu et al.	365/230.06
6347055	Line buffer type semiconductor memory device capable of direct prefetch and restore operations	February, 2002	Motomura	365/189.05
6349363	Multi-section cache with different attributes for each section	February, 2002	Cai et al.	711/129
6356573	Vertical cavity surface emitting laser	March, 2002	Jonsson et al.	372/46
6367074	Operation of a system	April, 2002	Bates et al.	717/11
6370068	Semiconductor memory devices and methods for sampling data therefrom based on a relative position of a memory cell array section containing the data	April, 2002	Rhee	365/196
6373777	Semiconductor memory	April, 2002	Suzuki	365/230.03
6381190	Semiconductor memory device in which use of cache can be selected	April, 2002	Shinkai	365/230.03
6392653	Device for processing acquisition data, in particular image data	May, 2002	Malandain et al.	345/501
6401213	Timing circuit for high speed memory	June, 2002	Jeddeloh	713/401
6405280	Packet-oriented synchronous DRAM interface supporting a plurality of orderings for data block transfers within a burst sequence	June, 2002	Ryan	711/105
6421744	Direct memory access controller and method therefor	July, 2002	Morrison et al.	710/22
6430696	Method and apparatus for high speed data capture utilizing bit-to-bit timing correction, and memory device using same	August, 2002	Keeth	713/503
6434639	System for combining requests associated with one or more memory locations that are collectively associated with a single cache line to furnish a single memory operation	August, 2002	Haghighi	710/39
6434696	Method for quickly booting a computer system	August, 2002	Kang	713/2
6434736	Location based timing scheme in memory design	August, 2002	Schaecher et al.	716/17
6438622	Multiprocessor system including a docking system	August, 2002	Haghighi et al.	710/1
6438668	Method and apparatus for reducing power consumption in a digital processing system	August, 2002	Esfahani et al.	711/165
6449308	High-speed digital distribution system	September, 2002	Knight, Jr. et al.	375/212
6453393	Method and apparatus for interfacing to a computer memory	September, 2002	Holman et al.	711/154
6462978	Method of designing semiconductor integrated circuit device and semiconductor integrated circuit device	October, 2002	Shibata et al.	365/60
6463059	Direct memory access execution engine with indirect addressing of circular queues in addition to direct memory addressing	October, 2002	Movshovich et al.	370/389
6467013	Memory transceiver to couple an additional memory channel to an existing memory channel	October, 2002	Nizar	711/1
6470422	Buffer memory management in a system having multiple execution entities	October, 2002	Cai et al.	711/129
6473828	Virtual channel synchronous dynamic random access memory	October, 2002	Matsui	711/104
6477592	System for I/O interfacing for semiconductor chip utilizing addition of reference element to each data element in first data stream and interpret to recover data elements of second data stream	November, 2002	Chen et al.	710/52
6477614	Method for implementing multiple memory buses on a memory module	November, 2002	Leddige et al.	711/5
6477621	Parallel access virtual channel memory system	November, 2002	Lee et al.	711/120
6479322	Semiconductor device with two stacked chips in one resin body and method of producing	November, 2002	Kawata et al.	438/109
6487556	Method and system for providing an associative datastore within a data processing system	November, 2002	Downs et al.	707/101
6490188	Semiconductor devices having mirrored terminal arrangements, devices including same, and methods of testing such semiconductor devices	December, 2002	Nuxoll et al.	365/63
6493803	Direct memory access controller with channel width configurability support	December, 2002	Pham et al.	711/147
6496909	Method for managing concurrent access to virtual memory data structures	December, 2002	Schimmel	711/163
6501471	Volume rendering	December, 2002	Venkataraman et al.	345/424
6505287	Virtual channel memory access controlling circuit	January, 2003	Uematsu	711/170
6523092	Cache line replacement policy enhancement to avoid memory page thrashing	February, 2003	Fanning	711/134
6523093	Prefetch buffer allocation and filtering system	February, 2003	Bogin et al.	711/137
6526483	Page open hint in transactions	February, 2003	Cho et al.	711/154
6539490	Clock distribution without clock delay or skew	March, 2003	Forbes et al.	713/401
6552564	Technique to reduce reflections and ringing on CMOS interconnections	April, 2003	Forbes et al.	326/30
6564329	System and method for dynamic clock generation	May, 2003	Cheung et al.	713/322
6587912	Method and apparatus for implementing multiple memory buses on a memory module	July, 2003	Leddige et al.	711/5
6590816	Integrated memory and method for testing and repairing the integrated memory	July, 2003	Perner	365/200
6594713	Hub interface unit and application unit interfaces for expanded direct memory access processor	July, 2003	Fuoco et al.	710/31
6594722	Mechanism for managing multiple out-of-order packet streams in a PCI host bridge	July, 2003	Willke, II et al.	710/313
6598154	Precoding branch instructions to reduce branch-penalty in pipelined processors	July, 2003	Vaid et al.	712/237
6615325	Method for switching between modes of operation	September, 2003	Mailloux et al.	711/154
6622188	12C bus expansion apparatus and method therefor	September, 2003	Goodwin et al.	710/101
6622227	Method and apparatus for utilizing write buffers in memory control/interface	September, 2003	Zumkehr et al.	711/167
6628294	Prefetching of virtual-to-physical address translation for display data	September, 2003	Sadowsky et al.	345/568
6629220	Method and apparatus for dynamic arbitration between a first queue and a second queue based on a high priority transaction type	September, 2003	Dyer	711/158
6631440	Method and apparatus for scheduling memory calibrations based on transactions	October, 2003	Jenne et al.	711/105
6636110	Internal clock generating circuit for clock synchronous semiconductor memory device	October, 2003	Ooishi et al.	327/565
6636912	Method and apparatus for mode selection in a computer system	October, 2003	Ajanovic et al.	710/105
6646929	Methods and structure for read data synchronization with minimal latency	November, 2003	Moss et al.	365/194
6658509	Multi-tier point-to-point ring memory interface	December, 2003	Bonella et al.	710/100
6662304	Method and apparatus for bit-to-bit timing correction of a high speed memory bus	December, 2003	Keeth et al.	713/400
6665202	Content addressable memory (CAM) devices that can identify highest priority matches in non-sectored CAM arrays and methods of operating same	December, 2003	Lindahl et al.	365/49
6667895	Integrated circuit device and module with integrated circuits	December, 2003	Jang et al.	365/63
6667926	Memory read/write arbitration method	December, 2003	Chen et al.	365/221
6670833	Multiple VCO phase lock loop architecture	December, 2003	Kurd et al.	327/156
6681292	Distributed read and write caching implementation for optimized input/output applications	January, 2004	Creta et al.	711/119
6697926	Method and apparatus for determining actual write latency and accurately aligning the start of data capture with the arrival of data at a memory device	February, 2004	Johnson et al.	711/167
6715018	Computer including installable and removable cards, optical interconnection between cards, and method of assembling a computer	March, 2004	Farnworth et al.	710/300
6718440	Memory access latency hiding with hint buffer	April, 2004	Maiyuran et al.	711/137
6721195	Reversed memory module socket and motherboard incorporating same	April, 2004	Brunelle et al.	365/63
6721860	Method for bus capacitance reduction	April, 2004	Klein	711/154
6724685	Configuration for data transmission in a semiconductor memory system, and relevant data transmission method	April, 2004	Braun et al.	365/233
6728800	Efficient performance based scheduling mechanism for handling multiple TLB operations	April, 2004	Lee et al.	710/54
6735679	Apparatus and method for optimizing access to memory	May, 2004	Herbst et al.	711/167
6735682	Apparatus and method for address calculation	May, 2004	Segelken et al.	711/220
6742098	Dual-port buffer-to-memory interface	May, 2004	Halbert et al.	711/172
6745275	Feedback system for accomodating different memory module loading	June, 2004	Chang	710/305
6751703	Data storage systems and methods which utilize an on-board cache	June, 2004	Chilton	711/113
6754812	Hardware predication for conditional instruction path branching	June, 2004	Abdallah et al.	712/234
6756661	Semiconductor device, a semiconductor module loaded with said semiconductor device and a method of manufacturing said semiconductor device	June, 2004	Tsuneda et al.	257/673
6760833	Split embedded DRAM processor	July, 2004	Dowling	712/34
6771538	Semiconductor integrated circuit and nonvolatile memory element	August, 2004	Shukuri et al.	365/185.05
6775747	System and method for performing page table walks on speculative software prefetch operations	August, 2004	Venkatraman	711/137
6782435	Device for spatially and temporally reordering for data between a processor, memory and peripherals	August, 2004	Garcia et al.	710/33
6789173	Node controller for performing cache coherence control and memory-shared multiprocessor system	September, 2004	Tanaka et al.	711/147
6792059	Early/on-time/late gate bit synchronizer	September, 2004	Yuan et al.	375/354
6792496	Prefetching data for peripheral component interconnect devices	September, 2004	Aboulenein et al.	710/306
6795899	Memory system with burst length shorter than prefetch length	September, 2004	Dodd et al.	711/137
6799246	Memory interface for reading/writing data from/to a memory	September, 2004	Wise et al.	711/117
6799268	Branch ordering buffer	September, 2004	Boggs et al.	712/228
6804760	Method for determining a type of memory present in a system	October, 2004	Wiliams	711/170
6804764	Write clock and data window tuning based on rank select	October, 2004	LaBerge et al.	711/170
6807630	Method for fast reinitialization wherein a saved system image of an operating system is transferred into a primary memory from a secondary memory	October, 2004	Lay et al.	713/2
6811320	System for connecting a fiber optic cable to an electronic device	November, 2004	Abbott	385/58
6816947	System and method for memory arbitration	November, 2004	Huffman	711/151
6820181	Method and system for controlling memory accesses to memory modules having a memory hub architecture	November, 2004	Jeddeloh et al.	711/169
6821029	High speed serial I/O technology using an optical link	November, 2004	Grung et al.	385/92
6823023	Serial bus communication system	November, 2004	Hannah	375/296
6845409	Data exchange methods for a switch which selectively forms a communication channel between a processing unit and multiple devices	January, 2005	Talagala et al.	710/20
6889304	Memory device supporting a dynamically configurable core organization	May, 2005	Perego et al.	711/170
6901494	Memory control translators	May, 2005	Zumkehr et al.	711/167
6904556	Systems and methods which utilize parity sets	June, 2005	Walton et al.	714/766
6910109	Tracking memory page state	June, 2005	Holman et al.	711/156
6912612	Shared bypass bus structure	June, 2005	Kapur et al.	710/309
6947672	High-speed optical data links	September, 2005	Jiang et al.	398/135
6980042	Delay line synchronizer apparatus and method	December, 2005	LaBerge	327/291
7046060	Method and apparatus compensating for frequency drift in a delay locked loop	May, 2006	Minzoni et al.	327/158
7120743	Arbitration system and method for memory responses in a hub-based memory system	October, 2006	Meyer et al.
7133991	Method and system for capturing and bypassing memory transactions in a hub-based memory system	November, 2006	James
7136958	Multiple processor system and method including multiple memory hub modules	November, 2006	Jeddeloh	710/317
7149874	Memory hub bypass circuit and method	December, 2006	Jeddeloh
7181584	Dynamic command and/or address mirroring system and method for memory modules	February, 2007	LaBerge	711/167
7187742	Synchronized multi-output digital clock manager	March, 2007	Logue et al.	375/376
7251714	Method and system for capturing and bypassing memory transactions in a hub-based memory system	July, 2007	James
20010038611	Apparatus and method to monitor communication system status	November, 2001	Darcie et al.	370/248
20010039612	Apparatus and method for fast booting	November, 2001	Lee	713/2
20020112119	Dual-port buffer-to-memory interface	August, 2002	Halbert et al.	711/115
20020116588	Software management systems and methods for automotive computing devices	August, 2002	Beckert et al.	711/161
20020144064	Controlling cache memory in external chipset using processor	October, 2002	Fanning	711/144
20030005223	System boot time reduction method	January, 2003	Coulson et al.	711/118
20030005344	Synchronizing data with a capture pulse and synchronizer	January, 2003	Bhamidipati et al.	713/400
20030043158	Method and apparatus for reducing inefficiencies in shared memory devices	March, 2003	Wasserman et al.	345/545
20030043426	Optical interconnect in high-speed memory systems	March, 2003	Baker et al.	359/109
20030093630	Techniques for processing out-of -order requests in a processor-based system	May, 2003	Richard et al.	711/154
20030149809	Method and apparatus for timing and event processing in wireless systems	August, 2003	Jensen et al.	710/22
20030156581	Method and apparatus for hublink read return streaming	August, 2003	Osborne	370/389
20030163649	Shared bypass bus structure	August, 2003	Kapur et al.	711/146
20030177320	Memory read/write reordering	September, 2003	Sah et al.	711/158
20030193927	Random access memory architecture and serial interface with continuous packet handling capability	October, 2003	Hronik	370/351
20030217223	Combined command set	November, 2003	Nino, Jr. et al.	711/105
20030227798	REDUCED POWER REGISTERED MEMORY MODULE AND METHOD	December, 2003	Pax	365/189.12
20030229762	Apparatus, method, and system for synchronizing information prefetch between processors and memory controllers	December, 2003	Maiyuran et al.	711/137
20030229770	Memory hub with internal cache and/or memory access prediction	December, 2003	Jeddeloh	711/213
20040022094	Cache usage for concurrent multiple streams	February, 2004	Radhakrishnan et al.	365/200
20040024948	Response reordering mechanism	February, 2004	Winkler et al.	710/311
20040044833	System and method for optimizing interconnections of memory devices in a multichip module	March, 2004	Ryan	711/5
20040047169	Wavelength division multiplexed memory module, memory system and method	March, 2004	Lee et al.	365/63
20040107306	Ordering rule controlled command storage	June, 2004	Barth et al.	710/310
20040126115	System having multiple agents on optical and electrical bus	July, 2004	Levy et al.	398/116
20040128449	Method and system to improve prefetching operations	July, 2004	Osborne et al.	711/137
20040144994	Apparatus and methods for optically-coupled memory systems	July, 2004	Lee et al.	257/200
20040160206	Servo motor control system	August, 2004	Komaki et al.	318/569
20040193821	Providing an arrangement of memory devices to enable high-speed data access	September, 2004	Ruhovets et al.	711/167
20040225847	Systems and methods for scheduling memory requests utilizing multi-level arbitration	November, 2004	Wastlick et al.	711/158
20040236885	Arrangement and method for system of locally deployed module units, and contact unit for connection of such a module unit	November, 2004	Fredriksson et al.	710/100
20050015426	Communicating data over a communication link	January, 2005	Woodruff et al.	709/200
20050044327	Asynchronous, independent and multiple process shared memory system in an adaptive computing architecture	February, 2005	Howard et al.	711/147
20050071542	Prefetch mechanism for use in a system including a host connected to a plurality of memory modules via a serial memory interconnect	March, 2005	Weber et al.	711/105
20050086441	Arbitration system and method for memory responses in a hub-based memory system	April, 2005	Meyer et al.	711/158
20050105350	Memory channel test fixture and method	May, 2005	Zimmerman	365/201
20050132159	Memory hub bypass circuit and method	June, 2005	Jeddeloh	711/167
20050149603	Queuing of conflicted remotely received transactions	July, 2005	DeSota et al.	709/200
20050166006	System including a host connected serially in a chain to one or more memory modules that include a cache	July, 2005	Talbot et al.	711/105
20050177677	Arbitration system having a packet memory and method for memory responses in a hub-based memory system	August, 2005	Jeddeloh	711/100
20050177695	Apparatus and method for data bypass for a bi-directional data bus in a hub-based memory sub-system	August, 2005	Larson et al.	711/167
20050213611	Method and system for synchronizing communications links in a hub-based memory system	September, 2005	James	370/503
20050268060	Method and system for terminating write commands in a hub-based memory system	December, 2005	Cronin et al.	711/167
20060022724	Method and apparatus for fail-safe resynchronization with minimum latency	February, 2006	Zerbe et al.	327/141
20060066375	Delay line synchronizer apparatus and method	March, 2006	LaBerge	327/291
20060136683	Arbitration system and method for memory responses in a hub-based memory system	June, 2006	Meyer et al.	711/154
20060174070	Memory hub bypass circuit and method	August, 2006	Jeddeloh	711/150
20060218318	Method and system for synchronizing communications links in a hub-based memory system	September, 2006	James	710/58
20060271746	Arbitration system and method for memory responses in a hub-based memory system	November, 2006	Meyer et al.	711/148
20070033317	Multiple processor system and method including multiple memory hub modules	February, 2007	Jeddeloh	710/317

EP0709786	May, 1996			Semiconductor memory with a timing controlled for receiving data at a semiconductor memory module to be accessed
EP0849685	June, 1998			Communication bus system between processors and memory modules
JP2001265539	September, 2001			ARRAY TYPE STORAGE DEVICE AND INFORMATION PROCESSING SYSTEM
WO/1993/019422	September, 1993			FIBER OPTIC MEMORY COUPLING SYSTEM
WO/2002/027499	April, 2002			SHARED TRANSLATION ADDRESS CACHING

“Free On-Line Dictionary of Computing” entry Flash Erasable Programmable Read-Only Memory, online May 17, 2004 [http://foldoc.doc.ic.ac.uk/foldoc/foldoc.cgi?flash+memory].
Intel, “Flash Memory PCI Add-In Card for Embedded Systems”, Application Note AP-758, Sep. 1997, pp. i-13.
Intel, “Intel 840 Chipset: 82840 Memory Controller Hub (MCH)”, Datasheet, www.intel.com/design/chipsets/datashts/298020.htm, Oct. 1999, pp. 1-178.
Micron Technology, Inc., “Synchronous DRAM Module 512MB/1GB (x72, ECC) 168-PIN Registered FBGA SDRAM DIMM”, Micron Technology, Inc., 2002, pp. 1-23.
Rambus, Inc., “Direct Rambus™ Technology Disclosure”, Oct. 1997. pp. 1-16.
Shanley, T. et al., “PCI System Architecture”, Third Edition, Mindshare, Inc., 1995, pp. 24-25.

Bragdon, Reginald G.

Dorsey & Whitney LLP

CROSS-REFERENCE TO RELATED APPLICATION

This application is a continuation of pending U.S. patent application Ser. No. 10/809,839, filed Mar. 24, 2004.

What is claimed is:

1. A memory hub coupled to at least one memory device, the memory hub comprising: remote and local input nodes; an output node; a configurable data path coupled to the remote and local input nodes and further coupled to the output node, the configurable data path operable to couple at least one read response received by the remote and local input nodes to the output node; and an arbitration control circuit coupled to the configurable data path, the output node, and the remote and local input nodes, the arbitration control circuit operable to generate an arbitration packet that includes data indicative of a data path configuration for a local read response received by the local input node and operable to provide the arbitration packet to the output node prior to providing the associated read response to the output node, the arbitration control circuit further operable to configure the configurable data path in accordance with data included in a downstream arbitration packet received by the remote input node in preparation of coupling an associated downstream read response to the output node.

2. The memory hub of claim 1 wherein the configurable data path comprises: a multiplexer having an output coupled to the output node and a control node coupled to the arbitration control circuit; a bypass data path coupled to the remote input node and a first input of the multiplexer; a local queue having an input coupled to the local input node and further having an output coupled to a second input of the multiplexer; and a remote queue having an input coupled to the remote input node and further having an output coupled to a third input of the multiplexer, the arbitration control circuit operable to generate a control signal for the multiplexer to selectively couple the bypass data path, local queue, or remote queue to the output node.

3. The memory hub of claim 2 wherein the arbitration control circuit is operable to store the local read response received by the local input node in the local queue and the downstream read response in the remote queue until the output node is ready to receive the respective read response.

4. The memory hub of claim 1 wherein the arbitration control circuit is operable to determine whether a local data path of the memory hub coupled to the local input node is idle, and in the event that the local data path is idle, operable to generate the arbitration packet for the local read response received by the local input node.

5. The memory hub of claim 4 wherein the arbitration packet and the local read response of the local data path is selected for transmission to the output node responsive to a predetermined arbitration scheme.

6. The memory hub of claim 1 wherein the arbitration control circuit is further operable to generate data for the arbitration packet that is used to distinguish the arbitration packet from a read response.

7. The memory hub of claim 6 wherein the arbitration packet includes a plurality of 8-bit bytes of information, wherein the plurality of 8-bit bytes of information includes one byte of data used to distinguish the arbitration packet from the read response.

8. A memory hub, comprising: a bypass data path coupled between an input node and an output node on which read responses are applied in response to being enabled; and an arbitration control circuit coupled to the bypass data path operable to receive an arbitration packet from a downstream memory hub and enable the bypass data path to receive a read response from the downstream memory hub responsive to the received arbitration packet, the arbitration packet including a data path field having activation data to enable the bypass data path of an upstream memory hub, the arbitration control circuit further operable to query an upstream memory hub to enable a bypass data path of the upstream memory hub to receive the read response from the downstream memory hub when the upstream memory hub is not busy.

9. The memory hub of claim 8, further comprising: a multiplexer having an output coupled to the output node and a control node coupled to the arbitration control circuit, the multiplexer further having a first input coupled to the bypass data path; a local queue having an input coupled to a local input node and further having an output coupled to a second input of the multiplexer; and a remote queue having an input coupled to the input node and further having an output coupled to a third input of the multiplexer, the arbitration control circuit operable to generate a control signal for the multiplexer to selectively couple the bypass data path, local queue, or remote queue to the output node.

10. The memory hub of claim 9 wherein the arbitration control circuit is operable to store the read response received from the downstream memory hub in the remote queue when the upstream memory hub is busy.

11. The memory hub of claim 10 wherein the arbitration control circuit is operable to store read data from a memory device coupled to the memory hub in the local queue, and generate an arbitration packet in response to the received read data when the upstream memory hub is not busy.

12. The memory hub of claim 8, wherein the arbitration packet includes a plurality of 8-bit bytes of data, wherein the plurality of 8-bit bytes includes one byte of data used to distinguish the arbitration packet from the read response.

13. A memory module, comprising: a plurality of memory devices; and a memory hub coupled to the memory devices through a memory device bus to access the memory devices, the memory hub comprising: remote and local input nodes, the local input node coupled to the memory device bus; an output node; a configurable data path coupled to the remote and local input nodes and further coupled to the output node, the configurable data path operable to couple at least one read response received by the remote and local input nodes to the output node; and an arbitration control circuit coupled to the configurable data path, the output node, and the remote and local input nodes, the arbitration control circuit operable to generate an arbitration packet that includes data indicative of a data path configuration for a local read response received by the local input node and operable to provide the arbitration packet to the output node prior to providing the read response to the output node, the arbitration control circuit further operable to configure the configurable data path in accordance with data included in a downstream arbitration packet received by the remote input node in preparation of coupling an associated downstream read response to the output node.

14. The memory module of claim 13 wherein the configurable data path of the memory hub comprises: a multiplexer having an output coupled to the output node and a control node coupled to the arbitration control circuit; a bypass data path coupled to the remote input node and a first input of the multiplexer; a local queue having an input coupled to the local input node and further having an output coupled to a second input of the multiplexer; and a remote queue having an input coupled to the remote input node and further having an output coupled to a third input of the multiplexer, the arbitration control circuit operable to generate a control signal for the multiplexer to selectively couple the bypass data path, local queue, or remote queue to the output node.

15. The memory module of claim 14 wherein the arbitration control circuit is operable to store the local read response received by the local input node in the local queue and the downstream read response in the remote queue until the output node is ready to receive the respective read response.

16. The memory module of claim 13 wherein the arbitration control circuit is operable to determine whether a local data path of the memory hub coupled to the local input node is idle, and in the event that the local data path is idle, operable to generate the arbitration packet for the local read response received by the local input node.

17. The memory module of claim 13 wherein the arbitration packet includes a plurality of 8-bit bytes of information, wherein the plurality of 8-bit bytes of information includes one byte of data used to distinguish the arbitration packet from the read response.

18. A memory module, comprising: a plurality of memory devices; and a memory hub coupled to the memory devices through a memory device bus to access the memory devices, the memory hub comprising: a bypass data path coupled between an input node and an output node on which read responses are applied in response to being enabled; and an arbitration control circuit coupled to the bypass data path operable to receive an arbitration packet from a downstream memory hub and enable the bypass data path to receive a read response from the downstream memory hub responsive to the received arbitration packet, the arbitration packet including a data path field having activation data to enable the bypass data path of an upstream memory hub, the arbitration control circuit further operable to query an upstream memory hub to enable a bypass data path of the upstream memory hub to receive the read response from the downstream memory hub when the upstream memory hub is not busy.

19. The memory module of claim 18 wherein the memory hub further comprises: a multiplexer having an output coupled to the output node and a control node coupled to the arbitration control circuit, the multiplexer further having a first input coupled to the bypass data path; a local queue having an input coupled to a local input node and further having an output coupled to a second input of the multiplexer; and a remote queue having an input coupled to the input node and further having an output coupled to a third input of the multiplexer, the arbitration control circuit operable to generate a control signal for the multiplexer to selectively couple the bypass data path, local queue, or remote queue to the output node.

20. The memory module of claim 19 wherein the arbitration control circuit is operable to store the memory response received from the downstream memory hub in the remote queue when the upstream memory hub is busy.

21. The memory module of claim 20 wherein the arbitration control circuit is operable to store read data from a memory device coupled to the memory hub in the local queue, and generate an arbitration packet in response to the received read data when the upstream memory hub is not busy.

22. The memory module of claim 18, wherein the arbitration packet includes a plurality of 8-bit bytes of data, wherein the plurality of 8-bit bytes includes one byte of data used to distinguish the arbitration packet from the read response.

23. A memory system having a plurality of memory modules, each memory module including a memory hub, the memory system comprising: a memory bus; a first memory hub having a first input terminal and a first output terminal coupled to the memory bus, the first memory hub including a first arbitration control circuit operable to generate a first arbitration packet including information to configure a data path responsive to retrieving read data from a memory device coupled to the first memory hub and provide the first arbitration packet to the memory bus through the first output terminal prior to providing the read data; and a second memory hub having a second input terminal and a second output terminal coupled to the memory bus, the second memory hub including a second arbitration control circuit configured to receive the first arbitration packet, the second arbitration control circuit operable to configure the data path in accordance with the information in the first arbitration packet, the second arbitration control circuit further operable to generate a second arbitration packet indicative of either the information of the first arbitration packet or read data retrieved from a memory device coupled to the second memory hub, and provide the second arbitration packet to the output terminal prior to providing the corresponding read data, each of the arbitration control circuits of the first and second memory hubs operable to store the read data and the read response when the first and second output terminals are busy.

24. The memory system of claim 23 wherein each of the arbitration packets comprises a data structure having a command code field that identifies the data structure as an arbitration packet that is distinguishable from a read response, and an address field that includes data to identify the particular hub to which the arbitration packet or the read response is directed.

25. The memory system of claim 23 wherein each of the arbitration packets includes a plurality of 8-bit bytes of information, wherein the plurality of 8-bit bytes of information includes one byte of data used to distinguish the arbitration packet from the read response.

26. A memory system, comprising: a plurality of memory modules, each having a memory hub configured to be in communication with each other, each of the memory hubs operable to propagate memory requests downstream and read responses upstream from one memory hub to another memory hub towards a memory controller; a responding memory module having a responding memory hub, the responding memory hub comprising: a local input node configured to receive read data from a memory device coupled to the responding memory hub by a local data path to generate a read response that includes the read data; a remote input node configured to receive a downstream arbitration packet and associated read response from a downstream memory hub on a memory bus; and an arbitration control circuit coupled to the local input node and the remote input node, the arbitration control circuit operable to determine whether the local data path of the responding memory hub is idle, and in the event that the local data path is idle, operable to encode a data path configuration in an arbitration packet to transmit the read response received by the local input node to transmit towards the memory controller, the arbitration control circuit further operable to decode the downstream arbitration packet received by the remote input node to generate an upstream arbitration packet encoding a data path to transmit the downstream read response to the memory controller.

27. The memory system of claim 26 wherein each of the arbitration packets comprises a command code field that identifies its data structure as an arbitration packet that is distinguishable from the read response, and an address field that includes data to identify the particular hub to which the arbitration packet or the read response is directed.

28. The memory system of claim 26 wherein each of the arbitration packets is transmitted prior to transmitting the associated read response.

29. A memory hub coupled to at least one memory device, the memory hub comprising: remote and local input nodes; an output node; a configurable data path coupled to the remote and local input nodes and further coupled to the output node, the configurable data path operable to couple at least one of a read response coupled through the remote and local input nodes to the output node; and an arbitration control circuit coupled to the configurable data path, the output node, and the remote input node, the arbitration control circuit operable to generate an arbitration packet for an associated read response coupled through the local input node and further operable to generate data for the arbitration packet that is used to distinguish the arbitration packet from the associated read response, the arbitration packet including data indicative of a data path configuration for the associated read response, the arbitration control circuit further operable to configure the configurable data path in accordance with the data included with an arbitration packet coupled thorough the remote input node in preparation of coupling an associated read response coupled through the remote input node to the output node.

30. The memory hub of claim 29 wherein the configurable data path comprises: a multiplexer having an output coupled to the output node and a control node coupled to the arbitration control circuit; a bypass data path coupled to the remote input node and a first input of the multiplexer; a local queue having an input coupled to the local input node and further having an output coupled to a second input of the multiplexer; and a remote queue having an input coupled to the remote input node and further having an output coupled to a third input of the multiplexer, the arbitration control circuit operable to generate a control signal for the multiplexer to selectively couple the bypass data path, local queue, or remote queue to the output node.

31. A memory hub, comprising: a bypass data path coupled between an input node and an output node on which read responses are coupled therebetween in response to being enabled; an arbitration control circuit coupled to the bypass data path operable to generate an arbitration packet in response to retrieving read data from a memory device coupled to the memory hub, the arbitration packet having a data path field including activation data to enable a bypass data path of an upstream memory hub, the arbitration control circuit further operable to receive an arbitration packet from a downstream memory hub and enable the bypass data path to couple a read response received therefrom from the input node to the output node; a multiplexer having an output coupled to the output node and a control node coupled to the arbitration control circuit, the multiplexer further having a first input coupled to the bypass data path; a local queue having an input coupled to a local input node and further having an output coupled to a second input of the multiplexer; and a remote queue having an input coupled to the input node and further having an output coupled to a third input of the multiplexer, the arbitration control circuit operable to generate a control signal for the multiplexer to selectively couple the bypass data path, local queue, or remote queue to the output node.

32. A memory hub coupled to at least one memory device, the memory hub comprising: remote and local input nodes; an output node; a configurable data path coupled to the remote and local input nodes and further coupled to the output node, the configurable data path operable to couple at least one read response received by the remote and local input nodes to the output node; and an arbitration control circuit coupled to the configurable data path, the output node, and the remote and local input nodes, the arbitration control circuit operable to generate an arbitration packet that includes data indicative of a data path configuration for a local read response received by the local input node and operable to determine whether a local data path of the memory hub coupled to the local input node is idle, and in the event that the local data path is idle, operable to generate the arbitration packet for the local read response received by the local input node, the arbitration control circuit further operable to configure the configurable data path in accordance with data included in a downstream arbitration packet received by the remote input node in preparation of coupling an associated downstream read response to the output node.

TECHNICAL FIELD

This present invention is related generally to a memory system for a processor-based computing system, and more particularly, to a hub-based memory system having an arbitration system and method for managing memory responses therein.

BACKGROUND OF THE INVENTION

Computer systems use memory devices, such as dynamic random access memory (“DRAM”) devices, to store data that are accessed by a processor. These memory devices are normally used as system memory in a computer system. In a typical computer system, the processor communicates with the system memory through a processor bus and a memory controller. The memory devices of the system memory, typically arranged in memory modules having multiple memory devices, are coupled through a memory bus to the memory controller. The processor issues a memory request, which includes a memory command, such as a read command, and an address designating the location from which data or instructions are to be read. The memory controller uses the command and address to generate appropriate command signals as well as row and column addresses, which are applied to the system memory through the memory bus. In response to the commands and addresses, data are transferred between the system memory and the processor. The memory controller is often part of a system controller, which also includes bus bridge circuitry for coupling the processor bus to an expansion bus, such as a PCI bus.

In memory systems, high data bandwidth is desirable. Generally, bandwidth limitations are not related to the memory controllers since the memory controllers sequence data to and from the system memory as fast as the memory devices allow. One approach that has been taken to increase bandwidth is to increase the speed of the memory data bus coupling the memory controller to the memory devices. Thus, the same amount of information can be moved over the memory data bus in less time. However, despite increasing memory data bus speeds, a corresponding increase in bandwidth does not result. One reason for the non-linear relationship between data bus speed and bandwidth is the hardware limitations within the memory devices themselves. That is, the memory controller has to schedule all memory commands to the memory devices such that the hardware limitations are honored. Although these hardware limitations can be reduced to some degree through the design of the memory device, a compromise must be made because reducing the hardware limitations typically adds cost, power, and/or size to the memory devices, all of which are undesirable alternatives. Thus, given these constraints, although it is easy for memory devices to move “well-behaved” traffic at ever increasing rates, for example, sequel traffic to the same page of a memory device, it is much more difficult for the memory devices to resolve “badly-behaved traffic,” such as bouncing between different pages or banks of the memory device. As a result, the increase in memory data bus bandwidth does not yield a corresponding increase in information bandwidth.

In addition to the limited bandwidth between processors and memory devices, the performance of computer systems is also limited by latency problems that increase the time required to read data from system memory devices. More specifically, when a memory device read command is coupled to a system memory device, such as a synchronous DRAM (“SDRAM”) device, the read data are output from the SDRAM device only after a delay of several clock periods. Therefore, although SDRAM devices can synchronously output burst data at a high data rate, the delay in initially providing the data can significantly slow the operating speed of a computer system using such SDRAM devices. Increasing the memory data bus speed can be used to help alleviate the latency issue. However, as with bandwidth, the increase in memory data bus speeds do not yield a linear reduction of latency, for essentially the same reasons previously discussed.

Although increasing memory data bus speed has, to some degree, been successful in increasing bandwidth and reducing latency, other issues are raised by this approach. For example, as the speed of the memory data bus increases, loading on the memory bus needs to be decreased in order to maintain signal integrity since traditionally, there has only been wire between the memory controller and the memory slots into which the memory modules are plugged. Several approaches have been taken to accommodate the increase in memory data bus speed. For example, reducing the number of memory slots, adding buffer circuits on a memory module in order to provide sufficient fanout of control signals to the memory devices on the memory module, and providing multiple memory device interfaces on the memory module since there are too few memory module connectors on a single memory device interface. The effectiveness of these conventional approaches are, however, limited. A reason why these techniques were used in the past is that it was cost-effective to do so. However, when only one memory module can be plugged in per interface, it becomes too costly to add a separate memory interface for each required memory slot. In other words, it pushes the system controllers package out of the commodity range and into the boutique range, thereby, greatly adding cost.

One recent approach that allows for increased memory data bus speed in a cost effective manner is the use of multiple memory devices coupled to the processor through a memory hub. In a memory hub architecture, or a hub-based memory sub-system, a system controller or memory controller is coupled over a high speed bi-directional or unidirectional memory controller/hub interface to several memory modules. Typically, the memory modules are coupled in a point-to-point or daisy chain architecture such that the memory modules are connected one to another in series. Thus, the memory controller is coupled to a first memory module, with the first memory module connected to a second memory module, and the second memory module coupled to a third memory module, and so on in a daisy chain fashion.

Each memory module includes a memory hub that is coupled to the memory controller/hub interface and a number of memory devices on the module, with the memory hubs efficiently routing memory requests and responses between the controller and the memory devices over the memory controller/hub interface. Computer systems employing this architecture can use a high-speed memory data bus since signal integrity can be maintained on the memory data bus. Moreover, this architecture also provides for easy expansion of the system memory without concern for degradation in signal quality as more memory modules are added, such as occurs in conventional memory bus architectures.

Although computer systems using memory hubs can provide superior performance, various factors may affect the performance of the memory system. For example, the manner in which the flow of read data upstream (i.e., back to the memory hub controller in the computer system) from one memory hub to another is managed will affect read latency. The management of the flow of read data by a memory hub may be generally referred to as arbitration, with each memory hub arbitrating between local memory read responses and upstream memory read responses. That is, each memory hub determines whether to send local memory read responses first or to forward memory read responses from downstream (i.e., further away from the memory hub controller) memory hubs first. Although the determination of which memory read response has lower priority will only affect the latency of that specific memory read response, the additive effect of the memory read responses having increased latency will affect the overall latency of the memory system. Consequently, the arbitration technique employed by a memory hub directly affects the performance of the overall memory system. Additionally, the implementation of the arbitration scheme will affect the overall read latency as well, since inefficient implementation will negatively impact system memory performance despite utilizing a desirable arbitration scheme. Therefore, there is a need for a system and method for implementing an arbitration scheme for managing memory responses in a system memory having a memory hub architecture.

SUMMARY OF THE INVENTION

A method according to one aspect of the invention includes transmitting a read response on a data path of a memory hub interposed between a transmitting memory hub and a receiving memory hub. The method includes receiving at the memory hub an arbitration packet including data indicative of a data path configuration for an associated read response. The arbitration packet is decoded, and the data path is configured in accordance with the data of the arbitration packet. The associated read response is received at the memory hub and the associated read response is coupled to the configured data path for transmitting the same to the receiving memory hub.

In another aspect of the invention, a memory hub coupled to at least one memory device is provided. The memory hub includes remote and local input nodes, an output node, and a configurable data path coupled to the remote and local input nodes and further coupled to the output node. The memory hub further includes an arbitration control circuit coupled to the configurable data path, the output node, and the remote input node. The arbitration control circuit generates an arbitration packet for an associated read response coupled through the local input node that includes data indicative of a data path configuration for the associated read response. The arbitration control circuit can further configure the configurable data path in accordance with the data included with an arbitration packet coupled thorough the remote input node in preparation of coupling an associated read response coupled through the remote input node to the output node.

In another aspect of the invention, a memory hub is provided having a bypass data path coupled between an input node and an output node on which read responses are coupled in response to being enabled, and further includes an arbitration control circuit. The arbitration control circuit is coupled to the bypass data path and generates an arbitration packet in response to retrieving read data from a memory device coupled to the memory hub. The arbitration packet has a data path field including activation data to enable a bypass data path of an upstream memory hub. The arbitration control circuit also receives an arbitration packet from a downstream memory hub and enables the bypass data path to couple a read response also received from the downstream memory hub from the input node to the output node.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a partial block diagram of a computer system having a memory hub based system memory in which embodiments of the present invention can be implemented.

FIG. 2 is a functional block diagram of a arbitration control component according to an embodiment of the present invention that can be utilized in the memory hubs of FIG. 1.

FIG. 3 is a data structure diagram of a arbitration packet and memory response according to an embodiment of the present invention.

FIG. 4 is a flow diagram of the operation of the arbitration control component of FIG. 3 according to an embodiment of the present invention

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

FIG. 1 illustrates a computer system 100 having a memory hub architecture in which embodiments of the present invention can be utilized. The computer system 100 includes a processor 104 for performing various computing functions, such as executing specific software to perform specific calculations or tasks. The processor 104 includes a processor bus 106 that normally includes an address bus, a control bus, and a data bus. The processor bus 106 is typically coupled to cache memory 108 , which, is typically static random access memory (“SRAM”). The processor bus 106 is further coupled to a system controller 110 , which is also referred to as a bus bridge.

The system controller 110 also serves as a communications path to the processor 104 for a variety of other components. More specifically, the system controller 110 includes a graphics port that is typically coupled to a graphics controller 112 , which is, in turn, coupled to a video terminal 114 . The system controller 110 is also coupled to one or more input devices 118 , such as a keyboard or a mouse, to allow an operator to interface with the computer system 100 . Typically, the computer system 100 also includes one or more output devices 120 , such as a printer, coupled to the processor 104 through the system controller 110 . One or more data storage devices 124 are also typically coupled to the processor 104 through the system controller 110 to allow the processor 104 to store data or retrieve data from internal or external storage media (not shown). Examples of typical storage devices 124 include hard and floppy disks, tape cassettes, and compact disk read-only memories (CD-ROMs).

The system controller 110 contains a memory hub controller 128 coupled to several memory modules 130 a - n through a bus system 154 , 156 . Each of the memory modules 130 a - n includes a memory hub 140 coupled to several memory devices 148 through command, address and data buses, collectively shown as bus 150 . The memory hub 140 efficiently routes memory requests and responses between the controller 128 and the memory devices 148 . Each of the memory hubs 140 includes write buffers and read data buffers. Computer systems employing this architecture allow for the processor 104 to access one memory module 130 a - n while another memory module 130 a - n is responding to a prior memory request. For example, the processor 104 can output write data to one of the memory modules 130 a - n in the system while another memory module 130 a - n in the system is preparing to provide read data to the processor 104 . Additionally, a memory hub architecture can also provide greatly increased memory capacity in computer systems.

FIG. 2 is a functional block diagram illustrating an arbitration control component 200 according to one embodiment of the present invention. The arbitration control component 200 can be included in the memory hubs 140 of FIG. 1. As shown in FIG. 2, the arbitration control component 200 includes two queues for storing associated memory responses. A local response queue 202 receives and stores local memory responses LMR from the memory devices 148 on the associated memory module 130 . A remote response queue 206 receives and stores downstream memory responses which cannot be immediately forwarded upstream through a bypass path 204 . An arbitration control circuit 210 is coupled to the queues 202 , 206 through a control/status bus 136 , which allows the arbitration control circuit 210 to monitor the contents of each of the queues 202 , 206 , and utilizes this information in controlling a multiplexer 208 to thereby control the overall arbitration process executed by the memory hub 140 . The control/status bus 136 also allows “handshaking” signals to be coupled from the queues 202 , 206 to the arbitration control circuit 210 to coordinate the transfer of control signals from the arbitration control circuit 210 to the queues 202 , 206 .

The arbitration control circuit 210 is further coupled to the high-speed link 134 to receive arbitration packets from downstream memory hubs. As will be explained in more detail below, arbitration packets are provided in advance of an associated memory response, and provide the arbitration control circuit 210 of an upstream memory hub with information to enable the appropriate path through the receiving memory hub in anticipation of receiving the associated memory response. Additionally, the arbitration control circuit 210 generates an arbitration packet to be provided prior to an associated LMR to serve as an early indication of the associated memory response when data is read from the memory devices 148 (FIG. 1) in response to a read request. As previously discussed, the arbitration packet will provide upstream memory hubs with appropriate information and give the respective arbitration control circuits 210 time to make decisions regarding enablement of the appropriate data paths before the memory response arrives. The arbitration control circuit 210 prepares the arbitration packet while read data for the memory response is being retrieved from memory devices 148 . The arbitration packet is provided through a switch 212 to either the multiplexer 208 or the local response queue 202 , depending on whether if the upstream memory hub is idle or busy. The multiplexer 208 , under the control of the arbitration control circuit, couples the high-speed link 134 to receive memory responses from the remote response queue 206 or the bypass path 204 , arbitration packets from the arbitration control circuit 210 , or arbitration packets and memory responses from the local response queue 202 . In an alternative embodiment of the present invention, the arbitration packets are generated in an arbitration packet circuit, rather than in the arbitration control circuit 210 , as shown in FIG. 2. Additionally, although shown in FIG. 2 as providing the arbitration packet to the multiplexer 208 to be injected into the stream of data, the arbitration packet can alternatively be provided to the local response queue 202 and placed before the associated read response packet to be injected into the data stream. It will be appreciated by those ordinarily skilled in the art that modifications to the embodiments of the present invention, such as the location at which the arbitration packet is generated or the manner in which the arbitration packet is placed into the data stream prior to the associated read packet, can be made without departing from the scope of the present invention.

FIG. 3 illustrates a data structure 300 for arbitration packets and memory responses according to an embodiment of the present invention. The data structure 300 is divided into 8-bit bytes of information, with each byte of information corresponding to a sequential bit-time. Each bit-time represents an increment of time in which new data can be provided. A response header field 302 includes two bytes of data that indicate the response is either an arbitration packet or a memory response. An address field 304 includes data that is used to identify the particular hub to which the arbitration packet or memory response is directed. A command code field 306 will have a value to identify the data structure 300 as an arbitration packet, and not as a memory response. Arbitration packets and memory responses are similar, except that the data payload of data fields 308 are “don't cares” for arbitration packets. In the data structure 300 , all 16 bits of size fields 310 carry the same value to indicate the size of the data payload carried by the memory response. For example, a “0” indicates that 32 bytes of data are included, and a “1” indicates that 64 bytes of data are included. It will be appreciated by one ordinarily skilled in the art that the embodiment of the data structure 300 shown in FIG. 3 has been provided by way of example, and that modifications to the data structure 300 can be made without deviating from the scope of the present invention. For example. the number and type of data fields of the data structure 300 can be changed or the number of bits for each bit time can be changed and still remain within the scope of the present invention.

Operation of the arbitration control component 200 (FIG. 2) will be described with reference to the flow diagram of FIG. 4. Following the receipt of a read data command, at a step 402 the memory hub initiates a read operation to retrieve the requested read data from the memory devices 148 (FIG. 1) for the memory response that will be provided to the requesting target. At a step 404 , the arbitration control circuit 210 of the memory hub determines whether the local data path is idle by checking the status of the local response queue 202 . If the local data path is idle, an arbitration packet is generated by the arbitrations control circuit 210 during the retrieval of the read data from the memory devices 148 at a step 406 . When the arbitration packet and the memory response have been prepared, and are ready for transmission, at a step 408 an upstream memory hub is queried to determine if it is busy. Where the upstream memory hub is idle, the arbitration packet is sent to the upstream memory hub, followed by the memory response at steps 410 , 412 . However, if the upstream memory hub is busy, the arbitration packet is discarded at a step 414 and the memory response is stored in a local response queue 202 at a step 416 . Similarly, in the event that at the step 404 it was determined that the local data path is busy, the memory response is also stored in the local response queue at the step 416 . At a step 418 the memory response is stored in the local response queue 202 until it is selected for transmission to the upstream memory hub in accordance with an arbitration scheme implemented by the memory hub. At a step 420 , the memory response is transmitted through each upstream memory hub in accordance with the arbitration scheme until the memory response reaches the target destination. Suitable arbitration schemes are well known in the art, and will not be described in detail herein. An example of an arbitration scheme that is also suitable for use is described in more detail in commonly assigned, co-pending U.S. patent application Ser. No. 10/690,810, entitled ARBITRATION SYSTEM AND METHOD FOR MEMORY RESPONSES IN A HUB-BASED MEMORY SYSTEM to James W. Meyer and Cory Kanski, filed on Oct. 20, 2003, which is incorporated herein by reference.

As described therein, the local and remote response queues 202 , 206 and the bypass path 204 are utilized to implement various response arbitration schemes. For example, in one embodiment, the arbitration control circuit executes an arbitration scheme that gives downstream responses, or remote responses, priority over local responses. Alternatively, in another embodiment described, the arbitration control circuit executes an arbitration scheme that gives priority to local responses over downstream responses. In another embodiment, the arbitration control circuit alternates between a predetermined number of responses from local and downstream memory, for example, local and remote responses can be alternately forwarded, or two local responses are forwarded followed by two remote responses, and so on. Another embodiment described therein utilizes an oldest first algorithm in arbitrating between local and downstream memory responses. That is, in operation, the arbitration control circuit 210 monitors response identifier portions of the memory responses stored in the local response queue and the remote response queue and selects the oldest response contained in either of these queues as the next response to be forwarded upstream. Thus, independent of the response queue in which a memory response is stored, the arbitration control circuit forwards the oldest responses first.

It will be appreciated by those ordinarily skilled in the art that other arbitration methods and schemes can be utilized without departing from the scope of the present invention.

Returning to the steps 410 , 412 where the arbitration packet is first transmitted to an upstream memory hub and then followed by the memory response, the arbitration control circuit 210 of the upstream memory hub receives the arbitration packet at a step 422 . The arbitration packet is decoded, and the appropriate data path is enabled by the arbitration control circuit 210 based on the information decoded at steps 424 , 426 . By the time the memory response is received at a step 430 , the appropriate data path is enabled by the arbitration control circuit 210 . At a step 428 , the next upstream memory hub is queried to determine if it is busy. If not, the arbitration packet and then the memory response are transmitted to the next upstream memory hub in a bypass fashion at a step 432 . The transmission of the arbitration packet and the memory response in the bypass fashion is facilitated by enabling the appropriate data path through the memory hub based on the decoded information of the arbitration packet that is sent at the step 410 before the associated memory response is sent at the step 412 .

Returning to the step 428 , if it is determined that the next upstream memory hub is busy, the arbitration packet is discarded at the step 440 , and the memory response is stored in the remote response queue 206 until the memory response is selected for transmission to the next upstream memory hub according to the arbitration scheme employed at a step 442 . At the step 420 , the memory response will make its way upstream through the memory hubs in accordance with the arbitration scheme until reaching its target destination.

From the foregoing it will be appreciated that, although specific embodiments of the invention have been described herein for purposes of illustration, various modifications may be made without deviating from the spirit and scope of the invention. For example, embodiments of the present invention have been described herein with respect to a memory hub-based system memory used in a computer system. However, it will be appreciated that embodiments of the present invention can be used in memory systems other than hub-based memory systems, where appropriate. Moreover, embodiments of the present invention can also be used in memory hub-based systems that are utilized in processor based systems, as known in the art, other than computer systems. Accordingly, the invention is not limited except as by the appended claims.