Rigg, Sidney B. (Meridian, ID, US)
Watkins, Charles M. (Eagle, ID, US)
Kirby, Kyle K. (Eagle, ID, US)
Benson, Peter A. (Boise, ID, US)
Akram, Salman (Boise, ID, US)

Plaque It! Sponsored by: Flash of Genius

11/494982

08/19/2008

07/28/2006

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Micron Technology, Inc. (Boise, ID, US)

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Weiss, Howard

Perkins Coie LLP

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a continuation of U.S. patent application Ser. No. 10/713,878 filed Nov. 13, 2003, now U.S. Pat. No. 7,091,124, which is incorporated herein by reference in its entirety. This application is related to U.S. patent application Ser. No. 11/430,735 filed May 9, 2006, which is incorporated herein by reference in its entirety. This application is also related to U.S. patent application Ser. No. 10/73 3,226 entitled MICROELECTRONIC DEVICES AND METHODS FOR FILLING VIAS IN MICROELECTRONIC DEVICES, filed Dec. 10, 2003.

We claim:

1. A method of manufacturing a microelectronic device having a die with an integrated circuit, the method comprising: forming a redistribution layer on the die, the redistribution layer including a conductive line having a first end portion spaced apart from a second end portion; forming a passage through the die and the first end portion of the conductive line; and depositing an electrically conductive material into at least a portion of the passage, wherein the electrically conductive material extends through the first end portion of the conductive line and is electrically connected to the first end portion of the conductive line, and wherein the electrically conductive material contacts the first end portion of the conductive line.

2. The method of claim 1, further comprising applying a passivation layer to at least a portion of the passage before depositing an electrically conductive material into at least a portion of the passage.

3. The method of claim 1, further comprising: cleaning the passage after forming the passage through the die and the first end portion of the redistribution layer; and applying a passivation layer to at least a portion of the passage before depositing an electrically conductive material into at least a portion of the passage.

4. The method of claim 1, further comprising applying a TiCL₄ TiN layer to at least a portion of the passage before depositing an electrically conductive material into at least a portion of the passage.

5. The method of claim 1, further comprising applying a wetting agent to at least a portion of the passage before depositing an electrically conductive material into at least a portion of the passage.

6. The method of claim 1, further comprising applying a Ni layer to at least a portion of the passage before depositing an electrically conductive material into at least a portion of the passage.

7. The method of claim 1, further comprising: applying a TiCL₄ TiN layer to at least a portion of the passage; and applying a Ni layer over at least a portion of the TiCL₄ TiN layer before depositing an electrically conductive material into at least a portion of the passage.

8. The method of claim 1, further comprising: applying a passivation layer to at least a portion of the passage; applying a TiCL₄ TiN layer over at least a portion of the passivation layer; and applying a Ni layer over at least a portion of the TiCL₄ TiN layer before depositing an electrically conductive material into at least a portion of the passage.

9. The method of claim 1 wherein forming the passage includes laser-cutting a through-hole completely through the die.

10. The method of claim 1, further comprising forming a hole in the first end portion of the conductive line before forming the passage through the die and the first end portion of the conductive line.

11. The method of claim 1, further comprising: forming a hole through the first end portion of the conductive line; and filling the hole with a passivation material, wherein forming the passage through the die and the first end portion of the conductive line includes cutting a through-hole completely through the die and the passivation material.

12. The method of claim 1, further comprising: forming a hole through the first end portion of the conductive line; and filling the hole with a passivation material, wherein forming the passage through the die and the first end portion of the conductive line includes laser-cutting a through-hole completely through the die and the passivation material.

13. The method of claim 1, further comprising: forming a hole in the first end portion of the conductive line before forming the passage through the die and the first end portion of the conductive line; and at least generally filling the first hole with a dielectric material, wherein forming the passage through the die and the first end portion of the conductive line includes forming the passage through the dielectric material.

14. A method of manufacturing a microelectronic device having a die with an integrated circuit, the method comprising: forming a redistribution layer on the die, the redistribution layer including a conductive line having a first end portion spaced apart from a second end portion; forming a passage through the die and the first end portion of the conductive line; depositing an electrically conductive material into at least a portion of the passage, wherein the electrically conductive material extends through the first end portion of the conductive line; forming a ball-pad on the second end portion of the conductive line; and depositing a solder ball on the ball-pad.

15. The method of claim 14 wherein depositing electrically conductive material into at least a portion of the passage includes depositing electrically conductive material into the passage that is electrically connected to the first end portion of the conductive line.

16. The method of claim 14 wherein depositing electrically conductive material into at least a portion of the passage includes depositing electrically conductive material into the passage that contacts the first end portion of the conductive line.

17. A method of manufacturing a microelectronic device having a die with an integrated circuit, the method comprising: forming a redistribution layer on the die, the redistribution layer including a conductive line having a first end portion spaced apart from a second end portion; etching a hole through the first end portion of the conductive line; filling the hole with a passivation material; forming a passage completely through the die and the first end portion of the conductive line, wherein forming the passage through the die and the first end portion of the conductive line includes laser-cutting a through-hole through the die and the passivation material; and depositing an electrically conductive material into at least a portion of the passage, wherein the electrically conductive material contacts the first end portion of the conductive line.

18. The method of claim 17 wherein the die includes a first surface and a second surface opposite to the first surface, wherein forming a redistribution layer on the die includes forming a redistribution layer at least proximate to the second surface, and wherein forming a passage through the die and the first end portion of the conductive line includes applying a laser from the first surface of the die toward the second surface of the die to laser-cut a through-hole through the die.

19. The method of claim 17, further comprising applying a passivation layer to at least a portion of the passage before depositing an electrically conductive material into at least a portion of the passage.

20. The method of claim 17, further comprising applying a TiCL₄ TiN layer to at least a portion of the passage before depositing an electrically conductive material into at least a portion of the passage.

21. The method of claim 17, further comprising: applying a TiCL₄ TiN layer to at least a portion of the passage; and applying a Ni layer over at least a portion of the TiCL₄ TiN layer before depositing an electrically conductive material into at least a portion of the passage.

22. A method of forming a conductive interconnect in a microfeature workpiece having a die, the die having an integrated circuit, the method comprising: forming a conductive line on a surface portion of the die, wherein the conductive line is electrically coupled to the integrated circuit; forming a hole in a portion of the conductive line; forming a via completely through the die in alignment with the hole in the conductive line, wherein the via and the hole define a passage extending completely through the die and the portion of the conductive line; and depositing an electrically conductive material into at least a portion of the passage, wherein the electrically conductive material contacts at least a portion of the conductive line proximate the hole in the conductive line.

23. The method of claim 22, further comprising insulating the die from the electrically conductive material in the passage.

24. The method of claim 22, further comprising applying an insulating layer to the die proximate to the passage to insulate the die from the electrically conductive material in the passage.

25. The method of claim 22, further comprising filling the hole in the conductive line with a material, wherein forming a via completely through the die includes forming a passage through the die and the material filling the hole in the conductive line.

26. The method of claim 22, further comprising filling the hole in the conductive line with a passivation material, wherein forming a via completely through the die includes forming a passage through the die and the passivation material filling the hole in the conductive line.

27. The method of claim 22 wherein forming a hole in a portion of the conductive line includes forming a first hole having a first diameter, and wherein forming a via includes laser-cutting a through-hole having a second diameter, the second diameter being less than the first diameter.

TECHNICAL FIELD

The following disclosure relates generally to microelectronic devices and methods for packaging microelectronic devices and, more particularly, to methods for forming vias in microelectronic workpieces.

BACKGROUND

Conventional die-level packaged microelectronic devices can include a microelectronic die, an interposer substrate or lead frame attached to the die, and a moulded casing around the die. The die generally includes an integrated circuit and a plurality of bond-pads coupled to the integrated circuit. The bond-pads are typically coupled to terminals on the interposer substrate or lead frame and serve as external electrical contacts on the die through which supply voltage, signals, etc., are transmitted to and from the integrated circuit. In addition to the terminals, the interposer substrate can also include ball-pads coupled to the terminals by conductive traces supported in a dielectric material. Solder balls can be attached to the ball-pads in one-to-one correspondence to define a “ball-grid array.” Packaged microelectronic devices with ball-grid arrays are generally higher grade packages having lower profiles and higher pin counts than conventional packages using lead frames.

One process for packaging a die with a ball-grid array at the die level includes (a) forming a plurality of dies on a semiconductor wafer, (b) cutting the wafer to separate or singulate the dies, (c) attaching individual dies to an interposer substrate, (d) wire-bonding the bond-pads of the dies to the terminals of the interposer substrate, and (e) encapsulating the dies with a suitable moulding compound. Mounting individual dies to interposer substrates or lead frames in the foregoing manner can be a time-consuming and expensive process. In addition, forming robust wire-bonds that can withstand the forces involved in moulding processes becomes more difficult as the demand for higher pin counts and smaller packages increases. Moreover, the process of attaching individual dies to interposer substrates or lead frames may damage the bare dies. These difficulties have made the packaging process a significant factor in the production of microelectronic devices.

Another process for packaging microelectronic devices is wafer-level packaging. In this process, a plurality of microelectronic dies are formed on a wafer, and then a redistribution layer is formed over the dies. The redistribution layer can include a dielectric layer and a plurality of exposed ball-pads forming arrays on the dielectric layer. Each ball-pad array is typically arranged over a corresponding die, and the ball-pads in each array are coupled to corresponding bond-pads of the die by conductive traces extending through the dielectric layer. After forming the redistribution layer on the wafer, discrete masses of solder paste are deposited onto the individual ball-pads. The solder paste is then reflowed to form small solder balls or “solder bumps” on the ball-pads. After forming the solder balls, the wafer is singulated to separate the individual microelectronic devices from each other.

Wafer-level packaging is a promising development for increasing efficiency and reducing the cost of microelectronic devices. By “pre-packaging” individual dies with a redistribution layer before cutting the wafers to singulate the dies, sophisticated semiconductor processing techniques can be used to form smaller arrays of solder balls. Additionally, wafer-level packaging is an efficient process that simultaneously packages a plurality of dies, thereby reducing costs and increasing throughput.

Packaged microelectronic devices such as those described above are used in cellphones, pagers, personal digital assistants, computers, and many other electronic products. To meet the demand for smaller electronic products, there is a continuing drive to increase the performance of packaged microelectronic devices, while at the same time reducing the height and the surface area or “footprint” of such devices on printed circuit boards. Reducing the size of microelectronic devices, however, becomes more difficult as the performance increases because higher performance typically means more integrated circuitry and bond-pads. This results in larger ball-grid arrays and thus larger footprints. One technique for increasing the component density of microelectronic devices within a given footprint is to stack one device on top of another.

FIG. 1 schematically illustrates a first microelectronic device 10 attached to a second microelectronic device 20 in a wire-bonded, stacked-die arrangement. The first microelectronic device 10 includes a die 12 having an integrated circuit 14 electrically coupled to a series of bond-pads 16 . A redistribution layer 18 electrically couples a plurality of first solder balls 11 to corresponding bond-pads 16 . The second microelectronic device 20 similarly includes a die 22 having an integrated circuit 24 electrically coupled to a series of bond-pads 26 . A redistribution layer 28 electrically couples a plurality of second solder balls 21 to corresponding bond-pads 26 . Wire-bonds 13 extending from the first solder balls 11 to the second solder balls 21 electrically couple the first microelectronic device 10 to the second microelectronic device 20 .

The second solder balls 21 on the second microelectronic device 20 are positioned outboard of the first microelectronic device 10 to facilitate installation of the wire-bonds 13 . As mentioned above, such installation can be a complex and/or expensive process. Forming the wire-bonds 13 , for example, is not only difficult because it requires individual wires between each pair of solder balls, but it may not be feasible to form wire-bonds for the high-density, fine-pitch arrays of some high performance devices. In addition, positioning the second solder balls 21 outboard of the first microelectronic device 10 to accommodate the wire-bonds 13 undesirably increases the footprint of the stacked-die arrangement.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 schematically illustrates a first microelectronic device attached to a second microelectronic device in a stacked-die arrangement in accordance with the prior art.

FIG. 2 is a cut-away isometric view of a microfeature workpiece configured in accordance with an embodiment of the invention.

FIGS. 3A-3G are schematic cross-sectional views illustrating various stages in a method of forming a conductive interconnect in a microelectronic device in accordance with an embodiment of the invention.

FIG. 4 is a schematic cross-sectional view illustrating a stage in a method of forming a conductive interconnect in a microelectronic device in accordance with another embodiment of the invention.

FIGS. 5A-5C are schematic cross-sectional views illustrating various stages in a method of forming a conductive interconnect in a microelectronic device in accordance with a further embodiment of the invention.

FIG. 6 is a schematic side cross-sectional view of a microelectronic device set configured in accordance with an embodiment of the invention.

FIG. 7 is a schematic side cross-sectional view of a microelectronic device set configured in accordance with another embodiment of the invention.

DETAILED DESCRIPTION

A. Overview

The following disclosure describes several embodiments of microelectronic devices, methods for packaging microelectronic devices, and methods for forming vias in dies and other substrates. One aspect of the invention is directed toward a method of manufacturing a microelectronic device having a die with an integrated circuit. In one embodiment, the method includes forming a bond-pad on the die electrically coupled to the integrated circuit, and forming a redistribution layer on the die. The redistribution layer can include a conductive line having a first end portion attached to the bond-pad and a second end portion spaced apart from the bond-pad. The method can further include forming a via or passage through the die, the bond-pad, and the first end portion of the conductive line. An electrically conductive material can then be deposited into at least a portion of the passage to provide a conductive interconnect extending through the die that is electrically coupled to the bond-pad and the conductive line.

In one aspect of this embodiment, the method can further include cleaning the passage and applying a passivation layer to at least a portion of the passage before depositing the electrically conductive material into the passage. In one embodiment, the passivation layer can at least generally insulate the die from the electrically conductive material filling the passage. In another aspect of this embodiment, the method can further include applying a TiCL ₄ TiN layer to at least a portion of the passage, and applying a Ni layer over at least a portion of the TiCL ₄ TiN layer before depositing the electrically conductive material into the passage.

Another aspect of the invention is directed toward a set of microelectronic devices. In one embodiment, the microelectronic device set includes a first microelectronic device stacked on a second microelectronic device in a stacked-die arrangement. The first microelectronic device can include a first die with a first integrated circuit, a first bond-pad electrically coupled to the first integrated circuit, and a passage through the first die and the first bond-pad. The first die also includes a metal interconnect in the passage and coupled to the first bond-pad to form a conductive link extending at least partially through the first microelectronic device. The second microelectronic device can include a second die with a second integrated circuit and a second bond-pad electrically coupled to the second integrated circuit. The second bond-pad can be electrically coupled to the conductive link of the first microelectronic device.

Many specific details of the present invention are described below with reference to semiconductor devices. The term “microfeature workpiece,” however, as used throughout this disclosure includes substrates upon which and/or in which microelectronic devices, micromechanical devices, data storage elements, read/write components, and other features are fabricated. For example, such microelectronic workpieces can include semiconductor wafers (e.g., silicon or gallium arsenide wafers), glass substrates, insulated substrates, and many other types of substrates. The feature signs in microfeature workpieces can include very small features of 0.11 μm or less, but larger features are also included on microfeature workpieces.

Specific details of several embodiments of the invention are described below with reference to microelectronic dies and other microelectronic devices in order to provide a thorough understanding of such embodiments. Other details describing well-known structures often associated with microelectronic devices are not set forth in the following description to avoid unnecessarily obscuring the description of the various embodiments. Persons of ordinary skill in the art will understand, however, that the invention may have other embodiments with additional elements or without several of the elements shown and described below with reference to FIGS. 2-7.

In the Figures, identical reference numbers identify identical or at least generally similar elements. To facilitate the discussion of any particular element, the most significant digit or digits of any reference number refer to the Figure in which that element is first introduced. For example, element 210 is first introduced and discussed with reference to FIG. 2.

B. Embodiments of Microfeature Workpieces

FIG. 2 is a cut-away isometric view of a wafer or microfeature workpiece 200 in accordance with an embodiment of the invention. In one aspect of this embodiment, the microfeature workpiece 200 includes a front side 201 , a back side 202 , and a plurality of microelectronic devices 210 (identified individually as microelectronic devices 210 a - f ). Each microelectronic device 210 can include a microelectronic die 212 and a redistribution layer 218 (RDL 218 ) formed on the die 212 . Each die 212 can include an integrated circuit 214 (shown schematically), a first surface 241 , a second surface 242 , and a plurality of metallic and/or conductive bond-pads 216 electrically coupled to the integrated circuit 214 . The RDL 218 can include a plurality of metallic and/or conductive lines 230 that each have a first end portion 231 electrically coupled to a corresponding bond-pad 216 , a second end portion 232 spaced outwardly from the first end portion 231 , and a trace between the first and second end portions 231 and 232 . As described in greater detail below, the second end portions 232 in one embodiment can have ball-pads configured to receive solder balls for electrically connecting the microelectronic devices 210 to other devices.

In the embodiment illustrated in FIG. 2, the processing of the microelectronic devices 210 has not been completed. As described below with reference to FIGS. 3A-6, additional processing can be carried out on the microfeature workpiece 200 to configure or package the individual microelectronic devices 210 for use in an electronic device or product. After this additional processing is complete, the microfeature workpiece 200 is cut along lines A ₁ -A ₁ to singulate the microelectronic devices 210 .

FIGS. 3A-3G illustrate various stages in a method of forming a conductive interconnect in the microelectronic device 210 b in accordance with an embodiment of the invention. FIG. 3A, more specifically, is a schematic side cross-sectional view of the microfeature workpiece 200 taken substantially along line 3 A- 3 A in FIG. 2. In one aspect of this embodiment, the RDL 218 includes a first passivation layer 350 applied to the second surface 242 of the die 212 , and a first dielectric layer 351 applied over the first passivation layer 350 . The first dielectric layer 351 can be removed around the bond-pad 216 by etching or another known process to expose the bond-pad 216 . Exposing the bond-pad 216 in this manner allows the fist end portion 231 of the conductive line 230 to contact the bond-pad 216 when the conductive line 230 is formed over the first dielectric layer 351 .

After forming the conductive line 230 , a first hole 360 is formed through the first end portion 231 of the conductive line 230 and the bond-pad 216 . In one embodiment, the first hole 360 can be formed by an etching process. In other embodiments, the first hole 360 can be formed using other suitable methods. Additionally, a second dielectric layer 352 is applied over the microfeature workpiece 200 to cover the conductive line 230 and fill the first hole 360 .

In one embodiment, the first and second dielectric layers 351 , 352 include a polyimide material. In other embodiments, the first and second dielectric layers 351 , 352 include other nonconductive and/or insulative materials. The first passivation layer 350 and/or one or more subsequent passivation layers can include a low temperature chemical vapor deposition (low temperature CVD) material, such as tetraethylorthosilicate (TEOS). In other embodiments, one or more of the passivation layers on the microfeature workpiece 200 can include parylene and/or other suitable materials, such as silicon oxide (SiO _x ) or silicon nitride (Si ₃ N ₄ ). The foregoing list of passivation and dielectric material options is not exhaustive. Accordingly, in other embodiments, it is expected that other suitable materials and processes can be used to form one or more of the layers discussed herein. In addition, it is further expected that, in yet other embodiments, one or more of the layers described above with reference to FIG. 3A, or described below with reference to subsequent Figures, may be omitted.

FIG. 3A illustrates one method for providing an RDL on a die in accordance with the present invention. In other embodiments, other methods resulting in other RDL/die configurations can be used. Accordingly, as those of ordinary skill in the art will recognize, the methods described in detail below for forming vias in microelectronic devices are not limited to the particular RDL/die configuration illustrated in FIG. 3A.

FIGS. 3B-3G are schematic side cross-sectional views similar to FIG. 3A showing the microfeature workpiece 200 in subsequent stages of forming the interconnect. FIG. 3B, for example, is a schematic side cross-sectional view of the microfeature workpiece 200 after a second hole 361 and a third hole 362 have been formed through the second dielectric layer 352 . In one aspect of this embodiment, forming the second hole 361 includes removing the second dielectric layer 352 from the first hole 360 , thereby exposing the bond-pad 216 and the first end portion 231 of the conductive line 230 . The third hole 362 is formed through the second dielectric layer 352 to expose part of the second end portion 232 of the conductive line 230 . In one aspect of this embodiment, the second and third holes 361 , 362 can be formed by dry-etching or by other suitable methods known to those of skill in the semiconductor processing art.

FIG. 3C illustrates the microfeature workpiece 200 of FIG. 3B after application of a second passivation layer 354 and a third passivation layer 356 . The second passivation layer 354 is applied over the second dielectric layer 352 such that it is deposited into the first hole 360 , the second hole 361 , and the third hole 362 . The third passivation layer 356 is applied to the first surface 241 of the die 212 . In one aspect of this embodiment, the second and third passivation layers 354 , 356 can include parylene. In other embodiments, the second passivation layer 354 can include other materials, such as an oxide.

Referring next to FIG. 3D, after application of the second and third passivation layers 354 , 356 , a laser 363 (shown schematically) cuts a passage or through-hole 364 through the microelectronic device 210 b. In one aspect of this embodiment, the through-hole 364 extends at least through the die 212 , the bond-pad 216 , and the first end portion 231 of the conductive line 230 . For example, in the illustrated embodiment, the through-hole 364 extends entirely through the third passivation layer 356 , the die 212 , and the second passivation layer 354 . The laser 363 generally cuts from the back side 202 of the microfeature workpiece 200 toward the front side 201 , but it can conceivably cut from the front side 201 toward the back side 202 . Further, the laser 363 can be aligned with respect to the bond-pad 216 using a pattern recognition system or other known alignment system. In other embodiments, the through-hole 364 can be formed using other suitable methods known to those of skill in the art. For example, in another embodiment, it is expected that the through-hole 364 can be formed by a suitable etching or drilling process.

After forming the through-hole 364 , it is cleaned to remove ablation (i.e., slag) and/or other undesirable byproducts resulting from the laser cut. In one embodiment, the through-hole 364 is cleaned using a wet-etch process. In this embodiment, the portion of the second passivation layer 354 remaining in the first hole 360 protects the bond-pad 216 and the first end portion 231 of the conductive line 230 from the wet-etch chemistry used to clean the slag from the die area of through-hole 364 . This feature allows a single cleaning process/chemistry to clean the slag from the via for the interconnect without having to use a second cleaning process to clean residue on the bond-pad 216 and first end portion 231 . In other embodiments, the through-hole 364 can be cleaned using other methods. For example, in some embodiments (one of which is described in greater detail below), cleaning agents that do not attack the metal of the bond-pad 216 can be used to clean the through-hole 364 so that the second passivation layer 354 is not needed to protect the bond-pad 216 . One such cleaning agent may include 6% TMAH: propylene glycol for removing laser ablation. Alternatively, in certain other embodiments, the through-hole 364 can remain uncleaned after formation.

Referring to FIG. 3E, after cleaning the through-hole 364 , a fourth passivation layer 358 is applied t