Langdo, Thomas A. (Cambridge, MA, US)
Currie, Matthew T. (Brookline, MA, US)
Hammond, Richard (Harriseahead, GB)
Lochtefeld, Anthony J. (Somerville, MA, US)
Fitzgerald, Eugene A. (Windham, NH, US)

Plaque It!

11/126550

08/19/2008

05/11/2005

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AmberWave Systems Corporation (Salem, NH, US)

257/E29.295

257/18

H01L31/0392

257/E29.297, 257/192, 257/E29.295, 257/190, 257/18, 257/E29.298, 257/E29.2

4010045	Process for production of III-V compound crystals	March, 1977	Ruehrwein
4282543	Semiconductor substrate and method for the preparation of the same	August, 1981	Ihara et al.	428/428
4329706	Doped polysilicon silicide semiconductor integrated circuit interconnections	May, 1982	Crowder et al.
4370510	Gallium arsenide single crystal solar cell structure and method of making	January, 1983	Stirn
4570328	Method of producing titanium nitride MOS device gate electrode	February, 1986	Price et al.	438/586
4704302	Process for producing an insulating layer buried in a semiconductor substrate by ion implantation	November, 1987	Bruel et al.
4710788	Modulation doped field effect transistor with doped Si.sub.x Ge.sub.1-x -intrinsic Si layering	December, 1987	Dämbkes et al.
4833513	MOS FET semiconductor device having a cell pattern arrangement for optimizing channel width	May, 1989	Sasaki	257/342
4969031	Semiconductor devices and method for making the same	November, 1990	Kobayashi et al.
4987462	Power MISFET	January, 1991	Kim et al.
4990979	Non-volatile memory cell	February, 1991	Otto
4997776	Complementary bipolar transistor structure and method for manufacture	March, 1991	Harame et al.
5013681	Method of producing a thin silicon-on-insulator layer	May, 1991	Godbey et al.
5089872	Selective germanium deposition on silicon and resulting structures	February, 1992	Ozturk et al.
5091767	Article comprising a lattice-mismatched semiconductor heterostructure	February, 1992	Bean et al.
5155571	Complementary field effect transistors having strained superlattice structure	October, 1992	Wang et al.
5166084	Process for fabricating a silicon on insulator field effect transistor	November, 1992	Pfiester
5177583	Heterojunction bipolar transistor	January, 1993	Endo et al.
5202284	Selective and non-selective deposition of Si.sub.1-x Ge.sub.x on a Si subsrate that is partially masked with SiO.sub.2	April, 1993	Kamins et al.
5207864	Low-temperature fusion of dissimilar semiconductors	May, 1993	Bhat et al.
5208182	Dislocation density reduction in gallium arsenide on silicon heterostructures	May, 1993	Narayan et al.
5212110	Method for forming isolation regions in a semiconductor device	May, 1993	Pfiester et al.
5221413	Method for making low defect density semiconductor heterostructure and devices made thereby	June, 1993	Brasen et al.
5240876	Method of fabricating SOI wafer with SiGe as an etchback film in a BESOI process	August, 1993	Gaul et al.
5241197	Transistor provided with strained germanium layer	August, 1993	Murakami et al.
5242847	Selective deposition of doped silion-germanium alloy on semiconductor substrate	September, 1993	Ozturk et al.
5250445	Discretionary gettering of semiconductor circuits	October, 1993	Bean et al.
5285086	Semiconductor devices with low dislocation defects	February, 1994	Fitzgerald
5291439	Semiconductor memory cell and memory array with inversion layer	March, 1994	Kauffmann et al.
5298452	Method and apparatus for low temperature, low pressure chemical vapor deposition of epitaxial silicon layers	March, 1994	Meyerson
5310451	Method of forming an ultra-uniform silicon-on-insulator layer	May, 1994	Tejwani et al.
5316958	Method of dopant enhancement in an epitaxial silicon layer by using germanium	May, 1994	Meyerson
5346848	Method of bonding silicon and III-V semiconductor materials	September, 1994	Grupen-Shemansky et al.
5374564	Process for the production of thin semiconductor material films	December, 1994	Bruel
5399522	Method of growing compound semiconductor	March, 1995	Ohori
5405802	Process of fabricating a semiconductor substrate	April, 1995	Yamagata et al.
5413679	Method of producing a silicon membrane using a silicon alloy etch stop layer	May, 1995	Godbey
5424243	Method of making a compound semiconductor crystal-on-substrate structure	June, 1995	Takasaki
5426069	Method for making silicon-germanium devices using germanium implantation	June, 1995	Selvakumar et al.
5426316	Triple heterojunction bipolar transistor	June, 1995	Mohammad
5439843	Method for preparing a semiconductor substrate using porous silicon	August, 1995	Sakaguchi et al.
5442205	Semiconductor heterostructure devices with strained semiconductor layers	August, 1995	Brasen et al.
5461243	Substrate for tensilely strained semiconductor	October, 1995	Ek et al.
5461250	SiGe thin film or SOI MOSFET and method for making the same	October, 1995	Burghartz et al.
5462883	Method of fabricating defect-free silicon on an insulating substrate	October, 1995	Dennard et al.
5476813	Method of manufacturing a bonded semiconductor substrate and a dielectric isolated bipolar transistor	December, 1995	Naruse
5479033	Complementary junction heterostructure field-effect transistor	December, 1995	Baca et al.
5484664	Hetero-epitaxially grown compound semiconductor substrate	January, 1996	Kitahara et al.
5523243	Method of fabricating a triple heterojunction bipolar transistor	June, 1996	Mohammad
5523592	Semiconductor optical device, manufacturing method for the same, and opto-electronic integrated circuit using the same	June, 1996	Nakagawa et al.
5534713	Complementary metal-oxide semiconductor transistor logic using strained SI/SIGE heterostructure layers	July, 1996	Ismail et al.
5536361	Process for preparing semiconductor substrate by bonding to a metallic surface	July, 1996	Kondo et al.
5540785	Fabrication of defect free silicon on an insulating substrate	July, 1996	Dennard et al.
5548128	Direct-gap germanium-tin multiple-quantum-well electro-optical devices on silicon or germanium substrates	August, 1996	Soref et al.
5572043	Schottky junction device having a Schottky junction of a semiconductor and a metal	November, 1996	Shimizu et al.
5596527	Electrically alterable n-bit per cell non-volatile memory with reference cells	January, 1997	Tomioka et al.
5607876	Fabrication of quantum confinement semiconductor light-emitting devices	March, 1997	Biegelsen et al.
5617351	Three-dimensional direct-write EEPROM arrays and fabrication methods	April, 1997	Bertin et al.
5630905	Method of fabricating quantum bridges by selective etching of superlattice structures	May, 1997	Lynch et al.
5659187	Low defect density/arbitrary lattice constant heteroepitaxial layers	August, 1997	Legoues et al.
5683934	Enhanced mobility MOSFET device and method	November, 1997	Candelaria
5698869	Insulated-gate transistor having narrow-bandgap-source	December, 1997	Yoshimi et al.
5705421	A SOI substrate fabricating method	January, 1998	Matsushita et al.
5714777	Si/SiGe vertical junction field effect transistor	February, 1998	Ismail et al.
5728623	Method of bonding a III-V group compound semiconductor layer on a silicon substrate	March, 1998	Mori
5739567	Highly compact memory device with nonvolatile vertical transistor memory cell	April, 1998	Wong
5759898	Production of substrate for tensilely strained semiconductor	June, 1998	Ek et al.
5777347	Vertical CMOS digital multi-valued restoring logic device	July, 1998	Bartelink
5786612	Semiconductor device comprising trench EEPROM	July, 1998	Otani et al.
5786614	Separated floating gate for EEPROM application	July, 1998	Chuang et al.
5792679	Method for forming silicon-germanium/Si/silicon dioxide heterostructure using germanium implant	August, 1998	Nakato
5808344	Single-transistor logic and CMOS inverters	September, 1998	Ismail et al.
5821577	Graded channel field effect transistor	October, 1998	Crabbé et al.
5847419	Si-SiGe semiconductor device and method of fabricating the same	December, 1998	Imai et al.
5855693	Wafer of semiconductor material for fabricating integrated devices, and process for its fabrication	January, 1999	Murari et al.	148/33.3
5863830	Process for the production of a structure having a thin semiconductor film on a substrate	January, 1999	Bruel et al.
5877070	Method for the transfer of thin layers of monocrystalline material to a desirable substrate	March, 1999	Goesele et al.
5882987	Smart-cut process for the production of thin semiconductor material films	March, 1999	Srikrishnan
5891769	Method for forming a semiconductor device having a heteroepitaxial layer	April, 1999	Liaw et al.
5906708	Silicon-germanium-carbon compositions in selective etch processes	May, 1999	Robinson et al.
5906951	Strained Si/SiGe layers on insulator	May, 1999	Chu et al.
5912479	Heterojunction bipolar semiconductor device	June, 1999	Mori et al.
5923046	Quantum dot memory cell	July, 1999	Tezuka et al.
5930632	Process of fabricating a semiconductor device having cobalt niobate gate electrode structure	July, 1999	Gardner et al.	438/287
5943560	Method to fabricate the thin film transistor	August, 1999	Chang et al.
5951757	Method for making silicon germanium alloy and electric device structures	September, 1999	Dubbelday et al.	117/102
5963817	Bulk and strained silicon on insulator using local selective oxidation	October, 1999	Chu et al.
5966622	Process for bonding crystalline substrates with different crystal lattices	October, 1999	Levine et al.
5993677	Process for transferring a thin film from an initial substrate onto a final substrate	November, 1999	Biasse et al.
5998807	Integrated CMOS circuit arrangement and method for the manufacture thereof	December, 1999	Lustig et al.
6013134	Advance integrated chemical vapor deposition (AICVD) for semiconductor devices	January, 2000	Chu et al.
6013553	Zirconium and/or hafnium oxynitride gate dielectric	January, 2000	Wallace et al.
6013563	Controlled cleaning process	January, 2000	Henley et al.
6020252	Method of producing a thin layer of semiconductor material	February, 2000	Aspar et al.
6033974	Method for controlled cleaving process	March, 2000	Henley et al.
6033995	Inverted layer epitaxial liftoff process	March, 2000	Muller
6058044	Shielded bit line sensing scheme for nonvolatile semiconductor memory	May, 2000	Sugiura et al.
6059895	Strained Si/SiGe layers on insulator	May, 2000	Chu et al.
6074919	Method of forming an ultrathin gate dielectric	June, 2000	Gardner et al.
6096590	Scalable MOS field effect transistor	August, 2000	Chan et al.
6103559	Method of making disposable channel masking for both source/drain and LDD implant and subsequent gate fabrication	August, 2000	Gardner et al.
6103597	Method of obtaining a thin film of semiconductor material	August, 2000	Aspar et al.
6103599	Planarizing technique for multilayered substrates	August, 2000	Henley et al.
6107653	Controlling threading dislocation densities in Ge on Si using graded GeSi layers and planarization	August, 2000	Fitzgerald
6111267	CMOS integrated circuit including forming doped wells, a layer of intrinsic silicon, a stressed silicon germanium layer where germanium is between 25 and 50%, and another intrinsic silicon layer	August, 2000	Fischer et al.
6117750	Process for obtaining a layer of single-crystal germanium or silicon on a substrate of single-crystal silicon or germanium, respectively	September, 2000	Bensahel et al.
6130453	Flash memory structure with floating gate in vertical trench	October, 2000	Mei et al.
6133799	Voltage controlled oscillator utilizing threshold voltage control of silicon on insulator MOSFETS	October, 2000	Favors, Jr. et al.
6140687	High frequency ring gate MOSFET	October, 2000	Shimomura et al.
6143636	High density flash memory	November, 2000	Forbes et al.
6153495	Advanced methods for making semiconductor devices by low temperature direct bonding	November, 2000	Kub et al.
6154475	Silicon-based strain-symmetrized GE-SI quantum lasers	November, 2000	Soref et al.
6160303	Monolithic inductor with guard rings	December, 2000	Fattaruso
6162688	Method of fabricating a transistor with a dielectric underlayer and device incorporating same	December, 2000	Gardner et al.
6162705	Controlled cleavage process and resulting device using beta annealing	December, 2000	Henley et al.
6166411	Heat removal from SOI devices by using metal substrates	December, 2000	Buynoski
6184111	Pre-semiconductor process implant and post-process film separation	February, 2001	Henley et al.
6190998	Method for achieving a thin film of solid material and applications of this method	February, 2001	Bruel et al.
6191007	Method for manufacturing a semiconductor substrate	February, 2001	Matsui et al.
6191432	Semiconductor device and memory device	February, 2001	Sugiyama et al.
6194722	Method of fabrication of an infrared radiation detector and infrared detector device	February, 2001	Fiorini et al.
6204529	8 bit per cell non-volatile semiconductor memory structure utilizing trench technology and dielectric floating gate	March, 2001	Lung et al.
6207977	Vertical MISFET devices	March, 2001	Augusto
6210988	Polycrystalline silicon germanium films for forming micro-electromechanical systems	April, 2001	Howe et al.
6218677	III-V nitride resonant tunneling	April, 2001	Broekaert
6225192	Method of producing a thin layer of semiconductor material	May, 2001	Aspar et al.
6228694	Method of increasing the mobility of MOS transistors by use of localized stress regions	May, 2001	Doyle et al.
6232138	Relaxed InxGa(1-x)as buffers	May, 2001	Fitzgerald et al.
6235567	Silicon-germanium bicmos on soi	May, 2001	Huang
6235568	Semiconductor device having deposited silicon regions and a method of fabrication	May, 2001	Murthy et al.
6242324	Method for fabricating singe crystal materials over CMOS devices	June, 2001	Kub et al.
6249022	Trench flash memory with nitride spacers for electron trapping	June, 2001	Lin et al.
6251751	Bulk and strained silicon on insulator using local selective oxidation	June, 2001	Chu et al.
6251755	High resolution dopant/impurity incorporation in semiconductors via a scanned atomic force probe	June, 2001	Furukawa et al.
6261929	Methods of forming a plurality of semiconductor layers using spaced trench arrays	July, 2001	Gehrke et al.
6266278	Dual floating gate EEPROM cell array with steering gates shared adjacent cells	July, 2001	Harari et al.
6271551	Si-Ge CMOS semiconductor device	August, 2001	Schmitz et al.
6271726	Wideband, variable gain amplifier	August, 2001	Fransis et al.
6281532	Technique to obtain increased channel mobilities in NMOS transistors by gate electrode engineering	August, 2001	Doyle et al.
6290804	Controlled cleavage process using patterning	September, 2001	Henley et al.
6291321	Controlling threading dislocation densities in Ge on Si using graded GeSi layers and planarization	September, 2001	Fitzgerald
6303468	Method for making a thin film of solid material	October, 2001	Aspar et al.
6313016	Method for producing epitaxial silicon germanium layers	November, 2001	Kibbel et al.
6316301	Method for sizing PMOS pull-up devices	November, 2001	Kant
6323108	Fabrication ultra-thin bonded semiconductor layers	November, 2001	Kub et al.
6326664	Transistor with ultra shallow tip and method of fabrication	December, 2001	Chau et al.
6326667	Semiconductor devices and methods for producing semiconductor devices	December, 2001	Sugiyama et al.
6329063	Method for producing high quality heteroepitaxial growth using stress engineering and innovative substrates	December, 2001	Lo et al.
6335546	Nitride semiconductor structure, method for producing a nitride semiconductor structure, and light emitting device	January, 2002	Tsuda et al.
6339232	Semiconductor device	January, 2002	Takagi
6344417	Method for micro-mechanical structures	February, 2002	Usenko
6346459	Process for lift off and transfer of semiconductor devices onto an alien substrate	February, 2002	Usenko et al.
6350311	Method for forming an epitaxial silicon-germanium layer	February, 2002	Chin et al.
6350993	High speed composite p-channel Si/SiGe heterostructure for field effect devices	February, 2002	Chu et al.
6352909	Process for lift-off of a layer from a substrate	March, 2002	Usenko
6355493	Method for forming IC's comprising a highly-resistive or semi-insulating semiconductor substrate having a thin, low resistance active semiconductor layer thereon	March, 2002	Usenko
6368733	ELO semiconductor substrate	April, 2002	Nishinaga
6368938	Process for manufacturing a silicon-on-insulator substrate and semiconductor devices on said substrate	April, 2002	Usenko
6369438	Semiconductor device and method for manufacturing the same	April, 2002	Sugiyama et al.
6372356	Compliant substrates for growing lattice mismatched films	April, 2002	Thornton et al.
6372593	Method of manufacturing SOI substrate and semiconductor device	April, 2002	Hattori et al.
6372609	Method of Fabricating SOI wafer by hydrogen ION delamination method and SOI wafer fabricated by the method	April, 2002	Aga et al.
6387829	Separation process for silicon-on-insulator wafer fabrication	May, 2002	Usenko et al.
6391740	Generic layer transfer methodology by controlled cleavage process	May, 2002	Cheung et al.
6399970	FET having a Si/SiGeC heterojunction channel	June, 2002	Kubo et al.
6403975	Semiconductor components, in particular photodetectors, light emitting diodes, optical modulators and waveguides with multilayer structures grown on silicon substrates	June, 2002	Brunner et al.
6407406	Semiconductor device and method of manufacturing the same	June, 2002	Tezuka
6410371	Method of fabrication of semiconductor-on-insulator (SOI) wafer having a Si/SiGe/Si active layer	June, 2002	Yu et al.	438/151
6420937	Voltage controlled oscillator with power amplifier	July, 2002	Akatsuka et al.
6425951	Advance integrated chemical vapor deposition (AICVD) for semiconductor	July, 2002	Chu et al.
6429061	Method to fabricate a strained Si CMOS structure using selective epitaxial deposition of Si after device isolation formation	August, 2002	Rim
6429098	Process for obtaining a layer of single-crystal germanium or silicon on a substrate of single-crystal silicon or germanium, respectively, and multilayer products obtained	August, 2002	Bensahel et al.
6445016	Silicon-on-insulator (SOI) transistor having partial hetero source/drain junctions fabricated with high energy germanium implantation	September, 2002	An et al.
6448152	Method and system for generating a plurality of donor wafers and handle wafers prior to an order being placed by a customer	September, 2002	Henley et al.
6455397	Method of producing strained microelectronic and/or optical integrated and discrete devices	September, 2002	Belford
6458672	Controlled cleavage process and resulting device using beta annealing	October, 2002	Henley et al.
6475072	Method of wafer smoothing for bonding using chemo-mechanical polishing (CMP)	November, 2002	Canaperi et al.
6489639	High electron mobility transistor	December, 2002	Hoke et al.
6500694	Three dimensional device integration method and integrated device	December, 2002	Enquist
6514836	Methods of producing strained microelectronic and/or optical integrated and discrete devices	February, 2003	Belford
6515335	Method for fabrication of relaxed SiGe buffer layers on silicon-on-insulators and structures containing the same	February, 2003	Christiansen et al.
6521041	Etch stop layer system	February, 2003	Wu et al.
6524935	Preparation of strained Si/SiGe on insulator by hydrogen induced layer transfer technique	February, 2003	Canaperi et al.
6534380	Semiconductor substrate and method of manufacturing the same	March, 2003	Yamauchi et al.
6534381	Method for fabricating multi-layered substrates	March, 2003	Cheung et al.
6537370	Process for obtaining a layer of single-crystal germanium on a substrate of single-crystal silicon, and products obtained	March, 2003	Hernandez et al.
6555839	Buried channel strained silicon FET using a supply layer created through ion implantation	April, 2003	Fitzgerald et al.
6563152	Technique to obtain high mobility channels in MOS transistors by forming a strain layer on an underside of a channel	May, 2003	Roberds et al.
6573126	Process for producing semiconductor article using graded epitaxial growth	June, 2003	Cheng et al.
6583015	Gate technology for strained surface channel and strained buried channel MOSFET devices	June, 2003	Fitzgerald et al.
6583437	Semiconductor device and method of manufacturing the same	June, 2003	Mizuno et al.
6591321	Multiprocessor system bus protocol with group addresses, responses, and priorities	July, 2003	Arimilli et al.
6593191	Buried channel strained silicon FET using a supply layer created through ion implantation	July, 2003	Fitzgerald
6593625	Relaxed SiGe layers on Si or silicon-on-insulator substrates by ion implantation and thermal annealing	July, 2003	Christiansen et al.
6596610	Method for reclaiming delaminated wafer and reclaimed delaminated wafer	July, 2003	Kuwabara et al.
6597016	Semiconductor device and method for fabricating the same	July, 2003	Yuki et al.
6602613	Heterointegration of materials using deposition and bonding	August, 2003	Fitzgerald
6605498	Semiconductor transistor having a backfilled channel material	August, 2003	Murthy et al.
6607948	Method of manufacturing a substrate using an SiGe layer	August, 2003	Sugiyama et al.
6621131	Semiconductor transistor having a stressed channel	September, 2003	Murthy et al.
6624047	Substrate and method of manufacturing the same	September, 2003	Sakaguchi et al.
6624478	High mobility transistors in SOI and method for forming	September, 2003	Anderson et al.
6632724	Controlled cleaving process	October, 2003	Henley et al.
6635909	Strained fin FETs structure and method	October, 2003	Clark et al.
6645831	Thermally stable crystalline defect-free germanium bonded to silicon and silicon dioxide	November, 2003	Shaheen et al.
6646322	Relaxed silicon germanium platform for high speed CMOS electronics and high speed analog circuits	November, 2003	Fitzgerald
6649480	Method of fabricating CMOS inverter and integrated circuits utilizing strained silicon surface channel MOSFETs	November, 2003	Fitzgerald et al.
6649492	Strained Si based layer made by UHV-CVD, and devices therein	November, 2003	Chu et al.
6656271	Method of manufacturing semiconductor wafer method of using and utilizing the same	December, 2003	Yonchara et al.
6657223	Strained silicon MOSFET having silicon source/drain regions and method for its fabrication	December, 2003	Wang et al.
6664169	Process for producing semiconductor member, process for producing solar cell, and anodizing apparatus	December, 2003	Iwasaki et al.
6674150	Heterojunction bipolar transistor and method for fabricating the same	January, 2004	Takagi et al.
6677183	Method of separation of semiconductor device	January, 2004	Sakaguchi et al.
6677192	Method of fabricating a relaxed silicon germanium platform having planarizing for high speed CMOS electronics and high speed analog circuits	January, 2004	Fitzgerald
6680240	Silicon-on-insulator device with strained device film and method for making the same with partial replacement of isolation oxide	January, 2004	Maszara
6680260	Method of producing a bonded wafer and the bonded wafer	January, 2004	Akiyama et al.
6689211	Etch stop layer system	February, 2004	Wu et al.
6690043	Semiconductor device and method of manufacturing the same	February, 2004	Usuda et al.
6703144	Heterointegration of materials using deposition and bonding	March, 2004	Fitzgerald
6703648	Strained silicon PMOS having silicon germanium source/drain extensions and method for its fabrication	March, 2004	Xiang et al.
6703688	Relaxed silicon germanium platform for high speed CMOS electronics and high speed analog circuits	March, 2004	Fitzgerald
6706614	Silicon-on-insulator (SOI) transistor having partial hetero source/drain junctions fabricated with high energy germanium implantation.	March, 2004	An et al.
6706618	Substrate processing apparatus, substrate support apparatus, substrate processing method, and substrate fabrication method	March, 2004	Takisawa et al.
6707106	Semiconductor device with tensile strain silicon introduced by compressive material in a buried oxide layer	March, 2004	Wristers et al.
6709903	Relaxed SiGe layers on Si or silicon-on-insulator substrates by ion implantation and thermal annealing	March, 2004	Christiansen et al.
6709909	Semiconductor device and method of manufacturing the same	March, 2004	Mizuno et al.
6713326	Process for producing semiconductor article using graded epitaxial growth	March, 2004	Cheng et al.
6723661	Relaxed silicon germanium platform for high speed CMOS electronics and high speed analog circuits	April, 2004	Fitzgerald
6724008	Relaxed silicon germanium platform for high speed CMOS electronics and high speed analog circuits	April, 2004	Fitzgerald
6730551	Formation of planar strained layers	May, 2004	Lee et al.
6737670	Semiconductor substrate structure	May, 2004	Cheng et al.
6743684	Method to produce localized halo for MOS transistor	June, 2004	Liu
6750130	Heterointegration of materials using deposition and bonding	June, 2004	Fitzgerald
6790747	Method and device for controlled cleaving process	September, 2004	Henley et al.
6828214	Semiconductor member manufacturing method and semiconductor device manufacturing method	December, 2004	Notsu et al.
6830976	Relaxed silicon germanium platform for high speed CMOS electronics and high speed analog circuits	December, 2004	Fitzgerald
6876010	Controlling threading dislocation densities in Ge on Si using graded GeSi layers and planarization	April, 2005	Fitzgerald
6881632	Method of fabricating CMOS inverter and integrated circuits utilizing strained surface channel MOSFETS	April, 2005	Fitzgerald et al.
6890835	Layer transfer of low defect SiGe using an etch-back process	May, 2005	Chu et al.
6921914	Process for producing semiconductor article using graded epitaxial growth	July, 2005	Cheng et al.
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20020096717	Transferable device-containing layer for silicon-on-insulator applications	July, 2002	Chu et al.
20020100942	CMOS inverter and integrated circuits utilizing strained silicon surface channel MOSFETs	August, 2002	Fitzgerald et al.
20020123167	Relaxed silicon germanium platform for high speed CMOS electronics and high speed analog circuits	September, 2002	Fitzgerald et al.
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20020125471	CMOS inverter circuits utilizing strained silicon surface channel MOSFETS	September, 2002	Fitzgerald et al.
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20020167048	Enhanced mobility NMOS and PMOS transistors using strained Si/SiGe layers on silicon-on-insulator substrates	November, 2002	Tweet et al.
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20030127646	Method for fabrication of relaxed SiGe buffer layers on silicon-on-insulators and structures containing the same	July, 2003	Christiansen et al.
20030139000	Method of creating high-quality relaxed SiGe-on-insulator for strained Si CMOS applications	July, 2003	Bedell et al.
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Dickey, Thomas L.

Goodwin Procter LLP

RELATED APPLICATIONS

This application is a continuation application of U.S. Ser. No. 10/456,103, filed Jun. 6, 2003, which claims the benefit of U.S. Provisional Application 60/386,968 filed Jun. 7, 2002, U.S. Provisional Application 60/404,058 filed Aug. 15, 2002, and U.S. Provisional Application 60/416,000 filed Oct. 4, 2002; the entire disclosures of this nonprovisional utility patent application and these three provisional applications are hereby incorporated by reference

What is claimed is:

1. A structure comprising: a substrate having a dielectric layer disposed thereon; and a strained semiconductor layer disposed in contact with the dielectric layer, wherein the strained semiconductor layer comprises approximately 100% germanium and the dielectric layer consists essentially of silicon dioxide.

2. The structure of claim 1, further comprising: a transistor including: a gate disposed above the strained semiconductor layer, the gate comprising a material selected from the group consisting of a doped semiconductor, a metal, and a metallic compound.

3. The structure of claim 2, further comprising: a gate dielectric layer disposed between the strained semiconductor layer and the gate.

4. The structure of claim 3, wherein the gate dielectric layer comprises silicon dioxide.

5. The structure of claim 3, wherein the gate dielectric layer comprises a high-k material with a dielectric constant higher than that of silicon dioxide.

6. The structure of claim 2, wherein the gate comprises a doped semiconductor, and the doped semiconductor comprises a material selected from the group consisting of polycrystalline silicon and polycrystalline silicon-germanium.

7. The structure of claim 2, wherein the gate comprises a metal, and the metal comprises a material selected from the group consisting of titanium, tungsten, molybdenum, tantalum, nickel, and iridium.

8. The structure of claim 2, wherein the gate consists essentially of a metal compound, and the metal compound comprises a material selected from the group consisting of titanium nitride, titanium silicon nitride, tungsten nitride, tantalum nitride, tantalum silicide, nickel silicide, and iridium oxide.

9. The structure of claim 2, further comprising: an overlayer disposed above the strained semiconductor layer, wherein the overlayer induces at least a portion of the strain in the strained semiconductor layer.

10. The structure of claim 9, wherein the overlayer comprises silicon nitride.

11. The structure of claim 1, wherein the strained semiconductor layer is compressively strained.

12. The structure of claim 1, wherein a composition of the strained semiconductor layer is substantially uniform throughout a thickness thereof.

13. A structure comprising: a substrate having a dielectric layer disposed thereon; and a strained semiconductor layer disposed in contact with the dielectric layer, wherein the strained semiconductor layer is tensilely strained and comprises approximately 100% germanium and the dielectric layer comprises silicon dioxide.

FIELD OF THE INVENTION

This invention relates to devices and structures comprising strained semiconductor layers and insulator layers.

BACKGROUND

Strained silicon-on-insulator structures for semiconductor devices combine the benefits of two advanced approaches to performance enhancement: silicon-on-insulator (SOI) technology and strained silicon (Si) technology. The strained silicon-on-insulator configuration offers various advantages associated with the insulating substrate, such as reduced parasitic capacitances and improved isolation. Strained Si provides improved carrier mobilities. Devices such as strained Si metal-oxide-semiconductor field-effect transistors (MOSFETs) combine enhanced carrier mobilities with the advantages of insulating substrates.

Strained-silicon-on-insulator substrates are typically fabricated as follows. First, a relaxed silicon-germanium (SiGe) layer is formed on an insulator by one of several techniques such as separation by implantation of oxygen (SIMOX), wafer bonding and etch back; wafer bonding and hydrogen exfoliation layer transfer; or recrystallization of amorphous material. Then, a strained Si layer is epitaxially grown to form a strained-silicon-on-insulator structure, with strained Si disposed over SiGe. The relaxed-SiGe-on-insulator layer serves as the template for inducing strain in the Si layer. This induced strain is typically greater than 10 ⁻³ .

This structure has limitations. It is not conducive to the production of fully-depleted strained-semiconductor-on-insulator devices in which the layer over the insulating material must be thin enough [<300 angstroms (Å)] to allow for full depletion of the layer during device operation. Fully depleted transistors may be the favored version of SOI for MOSFET technologies beyond the 90 nm technology node. The relaxed SiGe layer adds to the total thickness of this layer and thus makes it difficult to achieve the thicknesses required for fully depleted silicon-on-insulator device fabrication. The relaxed SiGe layer is not required if a strained Si layer can be produced directly on the insulating material. Thus, there is a need for a method to produce strained silicon—or other semiconductor—layers directly on insulating substrates.

SUMMARY

The present invention includes a strained-semiconductor-on-insulator (SSOI) substrate structure and methods for fabricating the substrate structure. MOSFETs fabricated on this substrate will have the benefits of SOI MOSFETs as well as the benefits of strained Si mobility enhancement. By eliminating the SiGe relaxed layer traditionally found beneath the strained Si layer, the use of SSOI technology is simplified. For example, issues such as the diffusion of Ge into the strained Si layer during high temperature processes are avoided.

This approach enables the fabrication of well-controlled, epitaxially-defined, thin strained semiconductor layers directly on an insulator layer. Tensile strain levels of ˜10 ⁻³ or greater are possible in these structures, and are not diminished after thermal anneal cycles. In some embodiments, the strain-inducing relaxed layer is not present in the final structure, eliminating some of the key problems inherent to current strained Si-on-insulator solutions. This fabrication process is suitable for the production of enhanced-mobility substrates applicable to partially or fully depleted SSOI technology.

In an aspect, the invention features a structure including a substrate having a dielectric layer disposed thereon; and a first strained semiconductor layer disposed in contact with the dielectric layer, the semiconductor layer including approximately 100% germanium.

One or more of the following features may be included. The strained semiconductor layer may be compressively strained. The strained semiconductor layer may include a thin layer and the thin layer is disposed in contact with the dielectric layer. The thin layer may include silicon.

In another aspect, the invention features a substrate having a dielectric layer disposed thereon, a strained semiconductor layer disposed in contact with the dielectric layer, and a transistor. The transistor includes a source region and a drain region disposed in a portion of the strained semiconductor layer, and a gate disposed above the strained semiconductor layer and between the source and drain regions, the gate including a material selected from the group consisting of a doped semiconductor, a metal, and a metallic compound.

One or more of the following features may be included. The doped semiconductor may include polycrystalline silicon and/or polycrystalline silicon-germanium. The metal may include titanium, tungsten, molybdenum, tantalum, nickel, and/or iridium. The metal compound may include titanium nitride, titanium silicon nitride, tungsten nitride, tantalum nitride, tantalum silicide, nickel silicide, and/or iridium oxide. A contact layer may be disposed over at least a portion of the strained semiconductor layer, with a bottommost boundary of the contact layer being disposed above a bottommost boundary of the strained semiconductor layer. The contact layer may share an interface with the semiconductor layer.

In another aspect, the invention features a structure including a substrate having a dielectric layer disposed thereon, the dielectric layer having a melting point greater than about 1700° C., and a strained semiconductor layer disposed in contact with the dielectric layer.

The following features may be included. The dielectric layer may include aluminum oxide, magnesium oxide, and/or silicon nitride.

In another aspect, the invention features a structure including a substrate having a dielectric layer disposed thereon; and a strained semiconductor layer disposed in contact with the dielectric layer. The strained semiconductor layer includes approximately 100% silicon and has a misfit dislocation density of less than about 10 ⁵ cm/cm ² . In another aspect, the invention features a structure including a substrate having a dielectric layer disposed thereon, and a strained semiconductor layer disposed in contact with the dielectric layer. The strained semiconductor layer includes approximately 100% silicon and has a threading dislocation density selected from the range of about 10 dislocations/cm ² to about 10 ⁷ dislocations/cm ² .

In another aspect, the invention features a structure including a substrate having a dielectric layer disposed thereon and a strained semiconductor layer disposed in contact with the dielectric layer. The semiconductor layer includes approximately 100% silicon and has a surface roughness selected from the range of approximately 0.01 nm to approximately 1 nm.

In another aspect, the invention features a substrate having a dielectric layer disposed thereon, and a strained semiconductor layer disposed in contact with the dielectric layer. The strained semiconductor layer includes approximately 100% silicon and has a thickness uniformity across the substrate of better than approximately ±10%.

In another aspect, the invention features a structure including a substrate having a dielectric layer disposed thereon, and a strained semiconductor layer disposed in contact with the dielectric layer. The strained semiconductor layer includes approximately 100% silicon and has a thickness of less than approximately 200 Å.

In another aspect, the invention features a structure including a substrate having a dielectric layer disposed thereon, and a strained semiconductor layer disposed in contact with the dielectric layer. The semiconductor layer includes approximately 100% silicon and has a surface germanium concentration of less than approximately 1×10 ¹² atoms/cm ² .

In another aspect, the invention features a structure including a substrate having a dielectric layer disposed thereon, and a strained semiconductor layer disposed in contact with the dielectric layer. An interface between the strained semiconductor layer and the dielectric layer has a density of bonding voids of less than 0.3 voids/cm ² .

In another aspect, the invention features a method for forming a structure, the method including providing a first substrate comprising a porous layer defining a cleave plane and having a first strained semiconductor layer formed thereon. The first strained semiconductor layer is bonded to an insulator layer disposed on a second substrate, and removing the first substrate from the first strained semiconductor layer by cleaving at the cleave plane, the strained semiconductor layer remaining bonded to the insulator layer.

In another aspect, the invention features a method for forming a structure, the method including forming a first relaxed layer over a first substrate, the first relaxed layer including a porous layer defining a cleave plane. A strained semiconductor layer is formed over the first relaxed layer. The first strained semiconductor layer is bonded to an insulator layer disposed on a second substrate. The first substrate is removed from the strained semiconductor layer by cleaving at the cleave plane, the strained semiconductor layer remaining bonded to the insulator layer

One or more of the following features may be included. The porous layer may be disposed at a top portion of the first relaxed layer. A second relaxed layer may be formed over the first relaxed layer, with the strained semiconductor layer being formed over the second relaxed layer. The first relaxed layer may be planarized, e.g., by chemical-mechanical polishing, prior to forming the second relaxed layer. At least a portion of the porous layer may remain disposed on the first strained semiconductor layer after cleaving. The portion of the porous layer may be removed from the strained semiconductor layer after cleaving. The portion of the porous layer may be removed by cleaning with a wet chemical solution that may include, e.g., hydrogen peroxide and/or hydrofluoric acid. Removing the portion of the porous layer may include oxidation.

BRIEF DESCRIPTION OF DRAWINGS

FIGS. 1A, 1 B, 2 A, 2 B, and 3 - 6 are schematic cross-sectional views of substrates illustrating a method for fabricating an SSOI substrate;

FIG. 7 is a schematic cross-sectional view illustrating an alternative method for fabricating the SSOI substrate illustrated in FIG. 6;

FIG. 8 is a schematic cross-sectional view of a transistor formed on the SSOI substrate illustrated in FIG. 6;

FIGS. 9-10 are schematic cross-sectional views of substrate(s) illustrating a method for fabricating an alternative SSOI substrate;

FIG. 11 is a schematic cross-sectional view of a substrate having several layers formed thereon;

FIGS. 12-13 are schematic cross-sectional views of substrates illustrating a method for fabricating an alternative strained semiconductor substrate;

FIG. 14 is a schematic cross-sectional view of the SSOI substrate illustrated in FIG. 6 after additional processing; and

FIGS. 15A-16D are schematic cross-sectional views of substrates illustrating alternative methods for fabricating an SSOI substrate.

Like-referenced features represent common features in corresponding drawings.

DETAILED DESCRIPTION

An SSOI structure may be formed by wafer bonding followed by cleaving. FIGS. 1A-2B illustrate formation of a suitable strained layer on a wafer for bonding, as further described below.

Referring to FIG. 1A, an epitaxial wafer 8 has a plurality of layers 10 disposed over a substrate 12 . Substrate 12 may be formed of a semiconductor, such as Si, Ge, or SiGe. The plurality of layers 10 includes a graded buffer layer 14 , which may be formed of Si _1-y Ge