Title:

Display apparatus, and image signal processing apparatus and drive control apparatus for the same

Document Type and Number:

United States Patent 7414622

Abstract:

An image data processing circuit includes a first circuit for calculating an average picture level value of the image data, a multiplier for multiplying a coefficient by the image data, a second circuit for calculating a first coefficient for the multiplier based upon the average picture level value, and a third circuit for calculating a second coefficient for the multiplier. The second coefficient is calculated so that the result of multiplying (1) image data having a value over an input range of a circuit to which data from the multiplier is inputted, and (2) the second coefficient falls in the input range. In addition, a selection circuit selects the coefficient to be used in the multiplier from the first coefficient calculated by the second circuit and the second coefficient calculated by the third circuit.

Inventors:

Abe, Naoto (Tokyo, JP)
Inamura, Kohei (Kanagawa, JP)
Sagano, Osamu (Tokyo, JP)
Saito, Hiroshi (Kanagawa, JP)
Ikeda, Takeshi (Kanagawa, JP)

Plaque It!

BACKGROUND OF THE INVENTION

1. Field of the Invention

This invention relates to display apparatuses such as display apparatuses for televisions and computers for receiving television signals and image signals of computers etc. and displaying images, and image signal processing apparatuses and drive control apparatuses for them.

More closely, it relates to a display apparatus which compensates a decreased portion of drive voltage resulting from electric resistance that a matrix wiring of a display panel has and effectively applied to display devices, and can drive the display devices with appropriate drive voltage, and an image signal processing apparatus and a drive control apparatus for the same.

2. Description of the Related Art

One of display devices is a cold cathode device. A example of a display apparatus having cold cathode devices is disclosed in JP Patent Publication No. 8-248920 (U.S. Pat. No. 5,734,361 specification). The display apparatus described in this document has such a structure that, in order to compensate lower luminance due to voltage drop by wiring resistance of electric connection wiring to the cold cathode device, its compensation data is calculated by statistical calculation and a desired value of an electron beam and the compensation value are combined.

The structure of the display apparatus described in this document is shown in FIG. 42. The structure involved in the data compensation in the apparatus is approximately as described below.

Firstly, a totalizer 1206 totalizes luminance data of one line of a digital image signal and outputs its totalized value to a memory 1207 , and thereby, compensation data corresponding to the totalized value is read out from the memory 1207 . On the other hand, the digital image signal is serial-to-parallel converted at a shift register 1204 and held for a predetermined time in a latch circuit 1205 , and thereafter, inputted at a predetermined timing to a multiplier 1208 provided with respect to each column wiring. The multiplier 1208 multiplies the luminance data and the compensation data read out from the memory 1207 with respect to each column wiring to generate data after compensation, and transfers this data after compensation to a modulating signal generator 1209 . The modulating signal generator 1209 generates a modulating signal corresponding to the data after compensation. Based upon this modulating signal, an image is displayed on a display panel. Here, like totalization processing of the luminance data of an 1 line portion of the digital image signal in the totalizer 1206 , statistical calculation processing such as calculating summation and average to the digital image signal is carried out, and based upon this value, compensation is carried out.

However, in case of the conventional compensation for voltage drop, the processing for limitation of electric power which is generally called ABL (Automatic Brightness Limiter) is not carried out.

And, in case of the conventional compensation for voltage drop, signal processing in order to calculate a current of a high voltage power supply (an anode current which is flowing through an anode electrode) precisely is not carried out either.

SUMMARY OF THE INVENTION

One purpose of the present invention is to be able to carry out ABL in case of a compensation for voltage drop as well as to compensate for voltage drop precisely.

Another purpose of the present invention is to provide a display apparatus which is able to calculate a current of a high voltage power supply (an anode current) and to carry out ABL precisely, and an image signal processing apparatus and a drive control apparatus for realizing the same.

A feature of the invention is characterized in that, a display apparatus comprises a display panel having display devices which are arranged in a matrix layout and driven through a plurality of row wirings and column wirings, a scanning unit adapted to scan the row wirings, a modulation unit adapted to supply a modulation signal to the column wiring based upon image data, a compensation unit adapted to apply compensation processing for compensating at least fluctuation of display luminance due to influence of voltage drop which is caused by a resistance of the row wiring to the image data, and a luminance control unit adapted to control display luminance of the display panel, based upon luminance information of the image data.

It is suitable that, in the display apparatus, the luminance control unit changes a drive voltage which is applied to the display panel in accordance with the luminance information.

Also, it is suitable that, in the display apparatus, the luminance control unit changes a drive voltage which is applied to the display panel in accordance with the luminance information, and changes a parameter of the compensation processing in the compensation unit.

Also, it is suitable that, in the display apparatus, the luminance control unit changes luminance level of the image data before the compensation processing or after the compensation processing in accordance with the luminance information.

Also, it is suitable that the display apparatus has a coefficient calculation unit adapted to determine a coefficient for maintaining width of the image data after the compensation processing within a predetermined range, and the luminance control unit changes display luminance of the display panel in accordance with the coefficient and the luminance information.

Also, it is suitable that the display apparatus has a coefficient calculation unit adapted to determine a coefficient for maintaining width of the image data after the compensation processing within a predetermined range, and the luminance control unit compares a value which is obtained from the coefficient and the luminance information with a predetermined luminance limitation reference value, and based upon its comparison result, changes luminance level of the image data after the compensation processing.

Also, it is suitable that, the display panel is a display panel having a common anode electrode, and the display apparatus has a coefficient calculation unit adapted to determine a coefficient for maintaining width of the image data after the compensation processing within a predetermined range, and, from an integration value of the image data and the coefficient, a value corresponding to a current value flowing through the anode electrode is calculated, and the value calculated is compared with a predetermined luminance limitation reference value, and based upon its comparison result, display luminance of the display panel is changed.

Also, it is suitable that, in the display apparatus, the luminance control unit changes display luminance of the display panel in accordance with the luminance information and a luminance limitation reference value which was set, and the luminance limitation reference value can be changed by at least one of power consumption of the display apparatus, a user interface unit or an external environment detection unit.

Another feature of the invention is characterized in that, an image signal processing apparatus for processing image data to be inputted to a display apparatus having a display panel having display devices which are arranged in a matrix layout and driven through a plurality of row wirings and column wirings, a scanning unit adapted to scan the row wirings, and a modulation unit adapted to supply a modulation signal to the column wiring based upon input image data, comprises a compensation unit adapted to apply compensation processing for compensating at least fluctuation of display luminance due to influence of voltage drop which is caused by a resistance of the row wiring to the image data, and a luminance control unit adapted to change luminance level of the image data to control display luminance of the display panel, based upon luminance information of the image data.

Still another feature of the invention is characterized in that, a drive control apparatus for controlling a drive of a display apparatus having a display panel having display devices which are arranged in a matrix layout and driven through a plurality of row wirings and column wirings, a scanning unit adapted to scan the row wirings, and a modulation unit adapted to supply a modulation signal to the column wiring based upon input image data, comprises a compensation unit adapted to apply compensation processing for compensating at least fluctuation of display luminance due to influence of voltage drop which is caused by a resistance of the row wiring to the image data, and a luminance control unit adapted to change a drive voltage of the display panel to control display luminance of the display panel, based upon luminance information of the image data.

It is suitable that, in the drive control apparatus, a parameter of the compensation processing is changed in accordance with change of the drive voltage.

Then, yet another feature of the invention is characterized in that, an image signal processing method for processing image data to be inputted to a display apparatus having a display panel having display devices which are arranged in a matrix layout and driven through a plurality of row wirings and column wirings, a scanning unit adapted to scan the row wirings, and a modulation unit adapted to supply a modulation signal to the column wiring based upon input image data, comprises a compensation step of applying compensation processing for compensating at least fluctuation of display luminance due to influence of voltage drop which is caused by a resistance of the row wiring to the image data, and a luminance control step of changing luminance level of the image data to control display luminance of the display panel, based upon luminance information of the image data.

Still yet another feature of the invention is characterized in that, a drive control method for controlling a drive of a display apparatus having a display panel having display devices which are arranged in a matrix layout and driven through a plurality of row wirings and row wirings, a scanning unit adapted to scan the column wirings, and a modulation unit adapted to supply a modulation signal to the column wiring based upon input image data, comprises a compensation step of applying compensation processing for compensating at least fluctuation of display luminance due to influence of voltage drop which is caused by a resistance portion of the row wiring to the image data, and a luminance control step of changing a drive voltage of the display panel to control display luminance of the display panel, based upon luminance information of the image data.

It is suitable that, in the drive control method, a parameter of the compensation processing is changed in accordance with change of the drive voltage.

BRIEF DESCRIPTION OF THE DRAWINGS

In the accompanying drawings:

FIG. 1 is a block diagram of a display apparatus according to a preferred embodiment of the invention;

FIG. 2 is a diagram showing an overview of a display panel;

FIG. 3 is a diagram showing electrical connections of the display panel;

FIG. 4 is a diagram showing one example of a characteristic of a surface conduction electron-emitting device;

FIG. 5 is a diagram showing one example of a driving method of the display panel;

FIG. 6 is a diagram for explaining an influence of voltage drop;

FIG. 7 is a diagram for explaining a degeneracy model;

FIG. 8 is a graph showing voltage drop amount calculated in a discrete manner;

FIG. 9 is a graph showing change amount of emission current calculated in a discrete manner;

FIG. 10 is a diagram showing a calculation example of compensation data in case of a value of image data is 64;

FIG. 11 is a diagram showing a calculation example of compensation data in case of a value of image data is 128;

FIG. 12 is a diagram showing a calculation example of compensation data in case of a value of image data is 192;

FIG. 13 is a diagram for explaining an interpolation method of the compensation data;

FIG. 14 is a block diagram showing structures of signal processing series and drive series of the display apparatus according to a first embodiment of the invention;

FIG. 15 is a block diagram showing a structure of a scanning circuit;

FIG. 16 is a block diagram showing a structure of an inverse γ processing part;

FIG. 17 is a block diagram showing a structure of a data arrangement conversion part;

FIG. 18 is a diagram for explaining a structure of a modulation unit and its operation;

FIG. 19 is a timing chart for explaining operations of the modulation unit;

FIG. 20 is a diagram for explaining a drive voltage calculation part;

FIG. 21 is a diagram for explaining a compensation data calculation unit;

FIG. 22 is a block diagram showing a structure of a discrete compensation data calculation part;

FIG. 23 is a block diagram showing a structure of a compensation data interpolation part;

FIG. 24 is a block diagram showing a structure of a linear approximation unit;

FIG. 25 is a timing chart for explaining operations of a display apparatus according to a preferred embodiment of the invention;

FIG. 26 is a block diagram showing a structure of a display device according to a second embodiment of the invention;

FIG. 27 is a block diagram showing a structure of a scanning circuit;

FIG. 28 is a diagram showing an example of an image of successive 4 frames;

FIG. 29 is a graph showing values of image data in the successive 4 frames;

FIG. 30 is a graph showing an appearance of change of a gain in successive frames;

FIG. 31 is a block diagram showing a structure of a variation of the display apparatus according to the second embodiment of the invention;

FIG. 32 is a timing chart for explaining operations of the modulation unit;

FIG. 33 is a block diagram showing a structure of a compensation data calculation unit;

FIG. 34 is a block diagram showing a structure of a discrete compensation data calculation part;

FIG. 35 is a block diagram showing a structure of a display apparatus according to a third embodiment of the invention;

FIG. 36 is a block diagram showing a structure of a variation of the display apparatus according to the third embodiment of the invention;

FIG. 37 is a block diagram showing a structure of a display apparatus according to a fourth embodiment of the invention;

FIG. 38 is a diagram showing a conversion characteristic of a conversion unit;

FIG. 39 is a diagram showing a characteristic of a selection voltage generation unit;

FIG. 40 is a block diagram showing a structure of a display apparatus according to a fifth embodiment of the invention;

FIG. 41 is a block diagram showing a structure of a display apparatus according to a sixth embodiment of the invention; and

FIG. 42 is a block diagram showing a structure of a conventional display apparatus.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

FIG. 1 is a block diagram for explaining a display apparatus according to several preferred embodiments of the invention.

In FIG. 1A, 301 designates a display panel, 302 designates a scanning circuit, 303 designates a modulation circuit, 304 designates a compensation circuit as a compensation unit adapted to carry out compensation for voltage drop, 305 designates a detection circuit for detecting luminance information of input image data, and 306 A is a control circuit for carrying out a drive control in accordance with the detected luminance information.

To incoming image data, the compensation circuit 304 applies, for example, voltage drop compensation processing to be hereinafter described, and the data is supplied to the modulation circuit 303 as a drive unit of the display panel 301 .

On the other hand, the detection circuit 305 detects, from the input image data, for example, luminance information in 1 frame image. The detected luminance information is inputted to the control circuit 306 A, and the control circuit 306 A carries out processing for changing a drive voltage which is applied to the display panel 301 by the drive unit.

According to this embodiment, it is possible to carry out the voltage drop compensation successfully, over carrying out display brightness (luminance) control of the display panel like ABL (automatic brightness limiter).

The display apparatus of FIG. 1B is a conformation in which detail of the display apparatus shown in FIG. 1A was changed, and the control circuit 306 B carries out not only processing for changing the drive voltage in the same manner as in the control circuit 306 A but also drive control and signal processing control such as changing parameters for voltage drop compensation processing in conformity to the drive voltage after the change and adjusting compensation amount by substantially voltage drop compensation processing.

According to the embodiment, over carrying out display brightness (luminance) control of the display panel like ABL, the voltage drop compensation can be carried out more successfully with good precision.

The display apparatus of FIG. 1C is a conformation in which detail of the display apparatus shown in FIG. 1B was changed, and the control circuit 306 C carries out signal processing control such as changing parameters for the voltage drop compensation processing and adjusting substantially compensation amount by the voltage drop compensation processing in accordance with the detected luminance information. The control circuit 306 C is a circuit which fixes, for example, a coefficient (gain) for changing and adjusting the luminance level of the image data. The fixed gain may be used for gain adjustment of the image data before the voltage drop compensation processing, and may be used for gain adjustment of the image data after the voltage drop compensation processing.

According to the embodiment, over carrying out the display brightness (luminance) control of the display panel like ABL, it can carry out the voltage drop compensation more successfully with good precision and it can carry out the brightness (luminance) control and the voltage drop compensation only by the processing of the image data. Accordingly, it is amore suitable conformation, in case that the detection circuit 305 , the compensation circuit 304 and the control circuit are realized in one chip semiconductor integrated circuit, and in case that those functions are realized by a software.

As described above, the control circuits 306 A, 306 B and 306 C work as a luminance control unit adapted to control the display luminance of the display panel 301 .

The change of the drive voltage can be easily realized for example, by selecting a reference voltage applied to the display device by a switch of the drive unit. The reference voltage is a multilevel voltage determining a selection electric potential and a non-selection electric potential of the scanning signal, display electric potential and non-display electric potential of the modulation signal etc. Or, the reference voltage may be anode voltage for determining the electric potential of the anode in the display panel with an electron emitting device used as a display device. Here, an adjustment is carried out such as changing at least one electric potential among these electric potentials.

The luminance information is APL (average picture level) in a broad sense, i.e., average luminance level of all pixels in 1 frame, an integrated value of image data of all pixels in 1 frame, or the average luminance level of a large number of pixels selected appropriately out of all pixels in 1 frame or the integrated value of pixel data of a large number of pixels and so on. The luminance information like APL is suitable for carrying out ABL control.

Among others, in case that the integrated value is used as the luminance information, since it becomes clear that an electric current value corresponding to the display luminance of actual 1 frame portion of the display panel can be obtained from the integrated value and the coefficient which are used for changing the luminance level of the image data, on the basis of this coefficient and the integrated value, good control can be carried out. The detail of this will be described later.

Also, in the foregoing description, it was explained under such assumption that the detection circuit 305 detects the luminance information from the input image data, but information such as a display mode and an input source of the image data etc. may be treated as the luminance information to be detected. Herewith, in accordance with the display mode and the input source, the luminance control with an effect of the voltage drop compensation can be carried out.

Further, it is desirable to provide a gain calculation unit adapted to determine a gain for accommodating width of the image data after the compensation processing within a predetermined range, and to provide, according to need, a limiter for limiting maximum width of the image data.

Then, a value obtained from its gain and the luminance information is compared with a predetermined luminance limitation reference value, and on the basis of its comparison result, display luminance level of the display panel may be changed.

The voltage drop compensation is processing for compensating a difference between a drive voltage which should be applied to a selected display device and an applied voltage actually applied thereto due to the voltage drop resulting from electric resistance of wiring connected to the display device and current flowing therein. As its processing, a method for compensating the image data before being modulated by the modulation circuit is desirably used. For example, in case that, as to a drive voltage “+5” for displaying the image data of a certain luminance level (e.g., “+5”), an actual applied voltage is getting down to a voltage “+4” for displaying luminance level “+4” due to the voltage drop, a compensation for changing the image data of luminance level “+5” to the image data of luminance level “+6” is carried out. When this is done, since the actual applied voltage due to the voltage drop is not “+6” but becomes “+5”, the luminance level “+5” to be desired to be primarily displayed is realized. In reality, there is no need for the luminance level to coincide with “+5” and it is enough to be able to compensate to a value as close as possible to it. Also, in case of a kind of line sequential drive of a matrix display panel, the voltage drop due to resistance of the scanning wiring (row wiring) is maximized, and the voltage drop amount differs by amount of an electric current flowing through another display device on the same selected line and its spatial distribution. Further, in case that a pulse width modulation is carried out in 1 horizontal scanning period, the voltage drop amount differs also by a temporal distribution of electric current in the 1 horizontal scanning period by the same reason.

In case that such voltage drop compensation is carried out, if luminance adjustment like ABL is used at the same time, there is a fear that precision of the voltage drop compensation is fluctuated to be lowered.

The display apparatus in this embodiment and its image signal processing apparatus and drive control apparatus suppress these fluctuations and enable the voltage drop compensation with higher precision to be carried out.

In case of the conformation as shown in FIG. 1B, it is desirable that the control circuit 306 B has a compensated image data calculation unit having a function for renewing calculation parameters for calculating the compensated image data, in accordance with the drive voltage represented as a difference voltage of the selection electric potential on the occasion of sequentially selecting a row wiring by the scanning circuit 302 and the modulation electric potential (display electric potential) on the occasion of modulation by the modulation circuit 303 . Or, it may be one for changing the calculation parameter such as the gain to be multiplied with an output of the compensation circuit 304 .

Then, it is desirable that as the detection circuit 305 , an average luminance detection circuit for detecting an average luminance level of the input image data is provided, and the control circuit 306 B has a drive voltage adjustment function for setting the drive voltage based upon its average luminance level.

Or, it is desirable that the control circuit 306 B has a plurality of display modes including at least a mode for giving a priority to the luminance and a mode for giving a priority to power consumption, and has a drive voltage adjustment function for setting the drive voltage based upon the selected display mode.

Further, it is desirable that the control circuit 306 B has an image signal input terminal for television and an image signal input terminal for computer, and has a drive voltage adjustment function for setting the drive voltage based upon which terminal (image source) is supplying an image to be displayed.

It is desirable that the drive voltage adjustment function is a function for making the selection electric potential variable on the occasion of sequentially selecting a row wiring by the scanning circuit 302 , and/or a function for making the modulation electric potential which is outputted by the modulation circuit 303 variable.

It is desirable that the compensated image data calculation unit has a voltage drop amount calculation unit for predicting the voltage drop on the row wiring for the input image data, a luminance lowering amount calculation unit for predicting the lowering amount of the luminance by the voltage drop from the voltage drop amount, and a compensation amount calculation unit for calculating a compensation amount which is applied to the input image data from the luminance lowering amount.

It is desirable that the voltage drop amount calculation unit renews a device current as the calculation parameter used on the occasion of calculating the voltage drop amount on the row wiring in compliance with the drive voltage.

It is desirable that the voltage drop amount calculation unit sets a plurality of reference times in 1 horizontal scanning period in compliance with the input image data, and further, along the selected row wiring, sets a plurality of reference points, and predicts and calculates the voltage drop amount at the reference points and at a plurality of reference times.

It is desirable that the luminance lowering amount calculation unit predicts and calculates the lowering amount of the luminance corresponding to a horizontal position that the voltage drop amount calculation unit calculated the voltage drop amount and a plurality of the reference times.

It is desirable that the compensation amount calculation unit calculates the compensated image data to a plurality of preset image data values, at a plurality of discrete horizontal display positions as the reference points, from the luminance lowering amount occurring at the plurality of reference times, at the plurality of reference points calculated by the luminance lowering amount calculation unit.

It is desirable that the compensated image data calculation unit further has an interpolation circuit for interpolates the discrete compensated image data calculated by the compensation amount calculation unit, and for calculating the compensated image data corresponding to the input image data value and its horizontal display position.

It is desirable that the display device is an electron-emitting device which can emit electrons in compliance with the drive voltage to be applied, an EL (electroluminescence) device having a light-emitting object as represented by an organic EL and an inorganic EL, or a LED device.

It is desirable that the electron-emitting device is a cold cathode device.

It is desirable that the cold cathode device is a surface conduction electron-emitting device, a field emission device etc., and what used, as an electron-emission material, a nano-structure in which carbon is a major component, as represented by CNT (Carbon Nano-Tube) or GNF (Graphite Nano Fiber), is desirably used.

It is desirable to have a fluorescent substance emitting fluorescence when electrons emitted from the electron-emitting device collide one another.

It is desirable that the display panel has the display devices arranged in a matrix layout and driven through the row wiring (scanning wiring) and the column wiring (modulation wiring).

Hereinafter, preferred embodiments of this invention will be described in detail by way of illustration with reference to the drawings. However, dimensions, materials, shapes, relative configurations etc. of components described in this embodiment are not intended to limit a scope of this invention to them, as long as there is no specific description in particular.

First Embodiment

This embodiment relates to a display apparatus having a processing circuit for compensating an influence applied to a display image by voltage drop in a scanning wiring, in view of such a phenomenon that, in a display apparatus in which cold-cathode devices as the display devices are arranged in a simple matrix layout, the voltage drop occurs in electric current flowing into the scanning wiring and wiring resistance of the scanning wiring and a display image is deteriorated, and relates particularly to one which realizes it with relatively small circuit size.

The compensation circuit (voltage drop compensation circuit) for compensating the decrease of the applied voltage due to the voltage drop described here is one which calculates deterioration of the display image caused by the voltage drop in compliance with the input image data, and obtains the compensation data for compensating it, and applies the compensation to the image data.

In this embodiment, it is possible to carry out the voltage drop compensation properly, even in case of carrying out luminance limitation, by controlling the drive voltage (difference electric potential of the selection electric potential and the modulation electric potential in case of selection) to be applied to the cold cathode device depending upon the average luminance level of the input image signal, from another view point that power consumption upon display is reduced.

Hereinafter, a preferred embodiment in case that the surface conduction electron-emitting device is used as the display device will be described.

(Overview of the Image Display Device)

FIG. 2 is a perspective view of the display panel using the image display device according to this embodiment. Note that, in order to show its internal construction, the display panel is presented with a part removed. In the diagram, a rear plate 1005 , a sidewall 1006 and a face plate 1007 constitute an airtight container for maintaining the inner part of the display panel as a vacuum.

A substrate 1001 is fixed to the rear plate 1005 . On the substrate 1001 , there are formed N×M cold cathode devices 1002 . Row wirings (scanning wirings) 1003 , column wirings (modulation wirings) 1004 and cold cathode devices 1002 are connected as shown in FIG. 3. A construction wired in this fashion is referred to as a passive matrix.

Further, on a bottom surface of the face plate 1007 there is formed a fluorescent film (a fluorescent member) 1008 . Since the display apparatus according to this embodiment is a color display apparatus, phosphors of the fluorescent film 1008 portion are colored separately in three primary colors of red, green and blue. The cold cathode devices are formed in the matrix manner so as to correspond with each of the pixels (picture elements) on the rear plate 1005 . The phosphors are constructed such that the pixels are formed at positions where emitted electrons (emission current) that are emitted from the cold cathode devices will abut against the phosphors.

On a bottom surface of the fluorescent film 1008 , there is formed a metal back 1009 .

A high voltage terminal Hv is electrically connected to the metal back 1009 . By applying a high voltage to the high voltage terminal Hv, the high voltage is applied between the rear plate 1005 and the face plate 1007 .

In accordance with this embodiment, the surface conduction electron-emitting devices are made as the cold cathode devices inside the display panel described above. It is also possible to use as the cold cathode device a field emission device. Further, the present invention can also be applied in an image display device in which self light-emitting devices other than the cold cathode devices, such as EL devices.

(Characteristics of Surface Conduction Electron-Emitting Devices)

The surface conduction electron-emitting devices exhibit an emission current Ie/device drive voltage Vf characteristic, and a device current If/device drive voltage Vf characteristic, as shown in FIG. 4. Note that, the emission current Ie is much smaller than the device current If, and since it is difficult to show these currents in a diagram using the same scales, they are shown in two graphs using respectively different scales.

The emission current Ie in the surface conduction electron-emitting devices exhibit the following three characteristics.

First, when a voltage equal to or greater than a given voltage (this will be referred to as a “threshold voltage Vth”) is applied to the device, the emission current Ie increases dramatically. However, on the other hand, when a voltage that is less than the threshold voltage Vth is applied to the device, the emission current Ie is hardly detected. In other words, the surface conduction electron-emitting device is a non-linear device having a clear threshold voltage Vth with respect to the emission current Ie.

Second, since the emission current Ie varies depending upon the voltage Vf that is applied to the devices, it is possible to control the amount of the emission current Ie by making the voltage Vf variable.

And third, since the surface conduction electron-emitting devices are also cold cathode devices, they have quick responsiveness which enables the emission time of the emission current Ie to be controlled by controlling the time when the voltage Vf is applied.

By taking advantage of the above-mentioned characteristics, the surface conduction electron-emitting devices can be used for the display apparatus in a favorable fashion.

For example, in a display apparatus using the display panel shown in FIG. 2, if the first characteristic is used, it becomes possible to perform the display by progressive scanning the display screen. In other words, according to the desired luminance a voltage which is equal to or greater than the threshold voltage Vth is applied as appropriate to the devices being driven, and a voltage below the threshold voltage Vth is applied to the devices which are in a non-selected state. By sequentially changing the devices which are being driven, the display screen can be scanned sequentially to perform the display.

Further, by utilizing the second characteristic, the amplitude of the voltage Vf applied to the devices is controlled to thereby enable the luminous brightness of the phosphors to be controlled, thus enabling image displays at various brightness.

Further, by utilizing the third characteristic, the illumination time of the phosphors can be controlled with the time that the voltage Vf is applied to the devices, whereby image displays of various brightness can be performed.

In the display apparatus of this embodiment, modulation was performed on the quantity of the electron beam of the display panel by using the above-mentioned third characteristic.

(Method of Driving the Display Panel)

The method of driving the display panel will be described concretely by use of FIG. 5.

FIG. 5 shows one example of voltage applied to voltage supply terminals of the scanning wiring and the modulation wiring on the occasion of driving the display panel.

In the figure, a horizontal scanning period I shows a period for having pixels in a row “i” emitted light.

In order to have the pixels in the row i emitted light, the scanning wiring in the row i is made to be of a selection state, and a selection electric potential Vs is applied to its voltage supply terminal Dxi. Also, voltage supply terminals Dxk (k=1, 2, . . . N, but ≠i) for other scanning wiring are made to be of non-selection state, and non-selection electric potential Vns is applied thereto.

In this embodiment, the selection electric potential Vs is set to −5V which is about 30% to 50% of a V _SEL(see, FIG. 4), and the non-selection electric potential Vns is set to a ground electric potential (GND). In addition, the voltage V _SELis assumed to be a rated voltage for driving the surface conduction electron-emitting device of the embodiment.

To the voltage supply terminal of the modulation wiring, a pulse-width modulation signal of voltage amplitude Vpwm is supplied.

Conventionally, pulse width of the pulse-width modulation signal to be supplied to the j-th modulation wiring was determined according to a value of the image data at the pixel in the row i at a column j of the image to be displayed, and pulse-width modulation signals corresponding to the value of the image data at respective pixels were supplied to all of the modulation wirings.

On the other hand, in this embodiment, by determining the pulse width of the pulse-width modulation signal to be supplied to the j-th modulation wiring in compliance with the value of the image data of the pixel in the row i at the column j of the image to be displayed and its compensation amount, the lower luminance due to the influence of the voltage drop is compensated.

In this embodiment, voltage of the voltage Vpwm is set to +0.5 V _SEL.

The surface conduction electron-emitting device emits electrons when the voltage V _SELis applied to both end of the device as shown in FIG. 4, but does not emit electrons at all in case of the applied voltage which is smaller than the voltage Vth. Also, the voltage Vth, as shown in FIG. 4, is characterized to be larger than 0.5 V _SEL.

On this account, electrons are not emitted from the surface conduction electron-emitting device connected to the scanning wiring to which the non-selection electric potential Vns is applied. Also, in the same manner, since the voltage applied to the both ends of the surface conduction electron-emitting device on the selected scanning wiring is Vs during a period in which an output of a pulse-width modulation unit is of the ground electric potential (hereinafter, called as the period in which the output is “L”), electrons are not emitted.

That is, electrons are emitted from the surface conduction electron-emitting device on the scanning wiring to which the selection voltage Vs was applied, in compliance with the period in which the output of the pulse-width modulation unit is Vpwm (hereinafter called as the period in which the output is “H”). Since, when the electrons are emitted, the above-described fluorescent substance emits light in compliance with amount of emitted electron beams, it is possible to obtain the luminance in compliance with the time for emission.

(With Regard to the Voltage Drop in the Scanning Wiring)

As described above, a basic problem to be solved is that, in particular, due to the voltage drop in the scanning wiring, the electric potential on the scanning wiring is increased, and thereby, the voltage to be applied to the surface conduction electron-emitting device is reduced, and the emission current from the surface conduction electron-emitting device is reduced.

A device current for 1 device of the surface conduction electron-emitting device, although it differs also by design specifications and manufacturing methods of the surface conduction electron-emitting devices, is around several 100 μA in case that the voltage V _SELwas applied thereto.

In case that only 1 pixel on the scanning wiring selected in a certain horizontal scanning period is made to emit light and other pixels than it are made not to emit light, the device current flowing into the selected scanning wiring from the modulation wiring is simply a current for 1 pixel (i.e., the above-described several 100 μA). In this case, there is almost no case that the voltage drop occurs and light emission luminance is going down.

However, in case that, in a certain horizontal scanning period, all pixels in a selected row are made to emit light, currents for all pixels are to flow into the selected scanning wiring from all modulation wirings. The summation of these currnts become several 100 mA to several A, and it becomes difficult to neglect the voltage drop on the scanning wiring caused by the wiring resistance of the scanning wiring.

In case that the voltage drop occurs on the scanning wiring, the drive voltage applied to the both ends of the surface conduction electron-emitting device drops. On this account, the emission current for emitting light from the surface conduction electron-emitting device is going down and as a result, the light emission luminance was reduced.

Specifically, a case in which a pattern with a white cross shape on a black background is displayed as a display image as shown in FIG. 6A will be considered.

In such a case, when a line “L” is driven, the number of pixels which are lit up is small. Therefore, hardly any voltage drop occurs in the scanning wiring on this line. As a result, the desired amount of emission current is emitted from the surface conduction electron-emitting devices at each pixel, and the illumination at the desired luminance can be achieved.

On the other hand, when a line “L′” in the same diagram is driven, all the pixels light up simultaneously. Therefore, the voltage drop does occur in the scanning wiring, and the emission current emitted from the surface conduction electron-emitting devices of each pixel decreases. As a result, the luminance at line L′ decreases.

Thus, depending on differences in the image data at each of the horizontal lines, the influence suffered due to the voltage drop would change, and therefore, when displaying a cross pattern as shown in FIG. 6A, an image as in FIG. 6B would be shown.

Note that this phenomenon is not limited to cross patterns, but also occurs in some cases when displaying, for example, a window pattern or a natural image.

Further, to complicate things further, when modulation is performed by means of the pulse width modulation, there are instances where the degree of the voltage drop changes during one horizontal scanning period.

FIG. 5 shows pulse-width modulation signals having pulse widths corresponding to the value of the inputted image data, and having their rising edges synchronized with each other. In a case where such pulse-width modulation signals are outputted to each column, differences will occur depending on the inputted image data, but, generally speaking, in one horizontal scanning period, the number of illuminated pixels is greatest immediately after the rising of the pulse. After the rising edge, the pixels go out in sequence starting with the least bright pixels. Accordingly, the number of illuminated pixels during one horizontal scanning period decreases as time passes. Therefore, the amount of the voltage drop occurring in the scanning wiring also has a tendency to be greatest at the start of one horizontal scanning period, and then gradually diminish. The output of the pulse-width modulation signals changes with each unit of time that corresponds to a single gradation in the modulation. Therefore, the chronological change in the voltage drops also occurs with each unit of time corresponding to a single gradation of the pulse width modulation signal.

(Method of Calculating the Voltage Drop)

In order to find the compensation amount for reducing the influence of the voltage drop, firstly, as its first stage, there may be hardware for predicting size of the voltage drop and its temporal change in real time.

However, it is general that the display panel of the display apparatus has several thousand modulation wirings, and it is very difficult to calculate the voltage drops at points where all of the modulation wirings intersect with the selected scanning wiring, and it is not realistic to manufacture hardware to calculate these in real time.

On the other hand, as a result for the inventors to study the voltage drop, it turned out that there are the following features.

i) At a certain point of time in 1 horizontal scanning period, the amount of voltage drop occurring on the scanning wiring is a specially continuous on the scanning wiring and a very smooth curve.

ii) The amount of the voltage drop differs also depending upon the display image, and also varies with respect to each time corresponding to 1 gradation of the pulse-width modulation, but overall, the amount of the voltage drop is larger near the raising edge of the pulse, and getting smaller or maintained as time passes. That is, there is no case that the size of the voltage drop increases during 1 horizontal scanning period when the drive method as shown in FIG. 5 is used.

Then, the calculation will be carried out in simplified manner by use of an approximate model as described below.

Firstly, in the light of the feature i), on the occasion of calculating the amount of the voltage drop at a certain point of time, the calculation is carried out in a approximate simplified manner by use of a degeneracy model in which several thousand modulation wirings are concentrated into several to several tens of wirings to carry out calculation (This will be described in detail in the following calculation of the voltage drop by use of the degeneracy model.).

Next, in light of the characteristic described at “ii)”, a plurality of different points of time are established within one horizontal scanning period, and the voltage drops at each of these times are calculated, whereby an overall prediction of the chronological changes in the voltage drop is made.

Specifically, by using a degeneracy model described below to calculate the voltage drops at a plurality of points of time, an overall prediction of the chronological change of the voltage drop is made.

(Calculation of the Voltage Drop Using the Degeneracy Model)

FIG. 7A is a diagram for explaining blocks and nodes used when performing degeneration. In order to abbreviate the diagram, only the selected scanning wiring, the modulation wirings and the surface conduction electron-emitting devices connected to their intersecting portions are shown in FIGS. 7A to 7C.

Now, the diagram shows a point of time during one horizontal scanning period, and it is assumed that the illumination state of each pixel on the selected scanning wiring (i.e., whether the output from the modulation means is “H” or “L”) has already been determined. In the illumination state, the device current flowing from each of the modulation wirings to the selected scanning wiring is defined as Ifi (where i=1, 2, . . . N, and i denotes a column number).

Further, as shown in the same diagram, n modulation wirings, a portion where the selected scanning wiring intersects with the n modulation wirings and the surface conduction electron-emitting device arranged at the intersection, are assumed to constitute one group that is defined as 1 block. In accordance with the present embodiment, the blocks are divided into 4 blocks.

Further, a position referred to as a “node” is established at the boundary positions of each block. The “node” refers to a horizontal position (reference point) for discretely calculating the amount of the voltage drop that will occur in the scanning wiring in the degeneracy model.

In accordance with the present embodiment, 5 nodes from a node 0 to a node 4 are established at the boundary positions of the blocks.

FIG. 7B is a diagram for explaining the degeneracy model.

In the degeneracy model, n modulation wirings included in 1 block in FIG. 7A are degenerated to 1 modulation wiring and this single degenerated modulation wiring is connected such that it is located in the center of the block on the scanning wiring.

Further, electric current sources are connected to the modulation wirings of each of the blocks which have been degenerated, and it is assumed that electric current total sums IF 0 to IF 3 in each of the blocks are flowing from the power sources.

Namely, Ifj (j=0, 1, 2, 3) is the electric current expressed as:

$\begin{matrix} IFj = \sum_{i = j \times n + 1}^{(j + 1) \times n} IFi & (Equation 1) \end{matrix}$

Further the potential at both ends of the scanning wiring is Vs in FIG. 7A, but it is the ground potential in FIG. 7B. It is because, according to the degeneracy model, the electric current flowing from the modulation wiring to the selected scanning wiring is modeled according to the above-mentioned electric current source, whereby the voltage drop amount at each portion on the scanning wiring can be calculated by treating the electricity supply portion as a reference (ground) potential to calculate the voltages at each part.

Further, the reason why the surface conduction electron-emitting device is abbreviated is because from the perspective of the selected scanning wiring if an equivalent electric current flows in from the column wirings, the generated voltage drop itself will not change at all due to whether or not the surface conduction electron-emitting devices are provided. Therefore, the electric current value that flows in from electric current source of each block is set to the total electric current value (Equation 1) of the device currents in each block, whereby the surface conduction electron-emitting device can be abbreviated.

Further, the wiring resistance in the scanning wirings in each block is n-times the wiring resistance r of the scanning wiring in one section. (Here, a “section” refers an area from the intersection between the scanning wiring and a certain column wiring to the intersection with the next column wiring. Also, in the present example, the wiring resistances of the scanning wirings in one section are assumed to be equal to each other.)

In the above-mentioned degeneracy model, the voltage drop amounts DV 0 to DV 4 occurring at each node on the scanning wiring can be calculated in a simple fashion by using the following equation with product sum format:
DV0= a 00×IF0+ a 01×IF1+ a 02×IF2+ a 03×IF3
DV1= a 10×IF0+ a 11×IF1+ a 12×IF2+ a 13×IF3
DV2= a 20×IF0+ a 21×IF1+ a 22×IF2+ a 23×IF3
DV3= a 30×IF0+ a 31×IF1+ a 32×IF2+ a 33×IF3
DV4= a 40×IF0+ a 41×IF1+ a 42×IF2+ a 43×IF3

In other words, the voltage drop amounts DVi (i=0, 1, 2, 3, 4) are expressed as:

$\begin{matrix} DVi = \sum_{j = 0}^{3} aij \times IFj (i = 0, 1, 2, 3, 4) & (Equation 2) \end{matrix}$

However, in the degeneracy model, the “aij” refers to the voltage generated at the i-th node when the unit potential is applied only to j-th block. (Hereinafter, the foregoing will serve as the definition of “aij”.)

The above-mentioned aij can be derived in a simple fashion according to Kirchhoff's Law as follows.

Namely, in FIG. 7B, if the wiring resistance up to the supply terminal on the left side of the scanning wiring as viewed from the electric current source in block i is defined as rli (i=0, 1, 2, 3), and the wiring resistance up to the supply terminal on the right side is rri (i=0, 1, 2, 3), and the wiring resistance between the block 0 and the left supply terminal and the wiring resistance between the block 4 and the right supply terminal are both defined as rt, then the following is established:
rl 0= rt +0.5 ×n×r
rr 0= rt+ 3.5 ×n×r
rl 1= rt+ 1.5 ×n×r
rr 1= rt+ 2.5 ×n×r
rl 2= rt +2.5 ×n×r
rr 2= rt+ 1.5 ×n×r
rl 3= rt+ 3.5 ×n×r
rr 3= rt+ 0.5 ×n×r

Further, the following is supposedly set:
a=rl 0// rr 0= rl 0 ×rr 0/( rl 0× rr 0)
b=rl 1// rr 1= rl 1× rr 1/( rl 1× rr 1)
c=rl 2// rr 2= rl 2× rr 2/( rl 2× rr 2)
d=rl 3// rr 3= rl 3× rr 3/( rl 3× rr 3)

Therefore, aij can be derived in a simple fashion as in (Equation 3). However, in (Equation 3), A//B is a symbol expressing a resistance value parallel to resistance A and resistance B, where A//B=A×B/(A+B).
a 00= a×rt/rl 0
a 10= a ×( rt +3 ×n×r )/ rr 0
a 20= a ×( rt+ 2 ×n×r )/ rr 0
a 30= a ×( rt+ 1× n×r )/ rr 0
a 40= a×rt/rr 0
a 01= b×rt/rl 1
a 11= b ×( rt+n×r )/ rl 1
a 21= b ×( rt+ 2 ×n×r )/ rr 1
a 31= b ×( rt+n×r )/ rr 1
a 41= b×rt/rr 1
a 02= c×rt/rl 2
a 12= c ×( rt+n×r )/ rl 2
a 22= c ×( rt+ 2 ×n×r )/ rl 2
a 32= c ×( rt+n×r )/ rr 2
a 42= c×rt/rr 2
a 03= d×rt/rl 3
a 13= d ×( rt+n×r )/ rl 3
a 23= d ×( rt+ 2 ×n×r )/ rl 3
a 33= d ×( rt+ 3 ×n×r )/ rl 3
a 43= d×rt/rr 3 (Equation 3)

Even if the number of blocks is not 4, the definition of aij enables the calculation by using (Equation 2) in a simple fashion using Kirchhoff's Law. Further, even in a case where the electricity supply terminals are not supplied to both sides of the scanning wiring as in the present embodiment, but are supplied to only one side thereof, the computation can be performed in a simple fashion by performing the calculation in accordance with the aij definition.

Note that, the parameter aij defined in (Equation 3) does not need to be recalculated each time the calculation is performed. Rather, it may be calculated once and then stored as a table.

Further, the total sum electric currents IF 0 to IF 3 for each block as determined with (Equation 1) are approximated as follows:

$\begin{matrix} IFj = \sum_{i = j \times n + 1}^{(j + 1) \times n} IFi = IFS \times \sum_{i = j \times n + 1}^{(j + 1) \times n} Counti & (Equation 4) \end{matrix}$

However, in (Equation 4), Counti is a variable that will take a value of “1” when the “i”-th pixel on the selected scanning wiring is in the illuminated state, and will take a value of “0” when the pixel is in the turned-off state.

IFS denotes an amount produced when the device current IF flowing when the voltage V _SELis applied to both ends of one device of the surface conduction electron-emitting devices is multiplied by a coefficient a taking a value between 0 and 1. In other words, it is defined as follows:
IFS=αIF (Equation 5)

According to (Equation 4), the device current proportionate to the number of pixels illuminated within a given block flows from column wirings of each block to the selected scanning wiring. Device current IF of one device which is multiplied by the coefficient α is set as the device current IFS of one device considering that the voltage in the scanning wiring increases due the voltage drop, thus reducing the amount of the device current.

In addition, if the drive voltage to be applied to the both ends of the surface conduction electron-emitting device is assumed to be V _DRV, in case that the drive voltage V _DRVvaries, a value of the device current IF used in (Equation 5) may be renewed in accordance with the value of the voltage V _DRVto carry out the calculation.

FIG. 7C shows one example of calculation results of the voltage drop amounts DV 0 to DV 4 at respective nodes in a certain illuminated state by use of the degeneracy model.

Since the voltage drop exhibits an extremely smooth curve, the voltage drops between nodes are presumed to take values indicated approximately by a dotted line in the diagram.

Thus, when the present degeneracy model is used, it is possible to calculate the voltage drop with respect to the inputted image data at the position of the node at desired points of time.

As described above, the voltage drop amount in a given illuminated state can be calculated in a simple fashion by using the degeneracy model.

Further the voltage drop that will occur on the selected scanning wiring changes chronologically within one horizontal scanning period. However, as described above, these changes are predicted by obtaining the illuminated states of several points of time within one horizontal scanning period, and using the degeneracy model to calculate the voltage drops exhibited in those illuminated states. Note that, the number of illuminations within each block at a given point of time within one horizontal scanning period can be obtained in a simple fashion by referencing the image data at each block.

Now, as an example, it will be assumed that the number of bits of the data inputted into the pulse width modulation circuit is 8 bits, and the pulse width modulation circuit outputs a linear pulse width with respect to the value of the input data. In other words, the input data value is 0, the output is “L”; when the input data value is 255, “H” is outputted during one horizontal scanning period; and when the input data is 128, “H” is outputted for the first half of one horizontal scanning period, and “L” is outputted for the last half thereof.

In a case as described above, the number of illuminations at the time when the pulse-width modulation signal is started (i.e., at the time of the rising edge in the modulation signal of the present example) can easily be detected by performing counting on the input data to the pulse-width modulation circuit are greater than 0. Similarly, the number of illuminations at the central point of time in one horizontal scanning period can be detected easily by counting the number of input data to the pulse width modulation circuit that are greater than 128. By comparing the image data with respect to a given threshold as described above, the number of illuminations in an arbitrary period of time can be counted easily by counting the number of outputs from the comparator that are positive.

Here, in order to simplify the following explanation, an amount of time referred to as a time slot will be defined.

Namely, a time slot is defined as an amount of time since a rising edge of the pulse-width modulation signal within one horizontal scanning period, and “time slot=0” indicates a point of time immediately following the start of the pulse-width modulation signal. “Time slot=64” is defined as indicating a point of time where time corresponding to 64 gradations has elapsed since the start of the pulse-width modulation signal. Similarly, “time slot=128” is defined as indicating a point of time where time corresponding to 128 gradations has elapsed since the start of the pulse-width modulation signal.

Note that, in accordance with the present embodiment, an example was given in which the pulse width modulation uses the rising-edge time as a reference, and the pulse width after that point of time is modulated. However, in a case where the falling-edge time of pulse is used as the reference to modulate the pulse width, the direction in which the time axis moves and the direction in which the time slot progresses will be opposite directions, but it goes without saying that the present invention may be applied nevertheless.

(Calculation of Compensation Data Based on the Voltage Drop Amount)

As described above, the degeneracy model is used to repeatedly perform calculations to approximately and discretely calculate the chronological changes exhibited by the voltage drops within one horizontal scanning period.

FIG. 8 illustrates an example in which the voltage drops are repeatedly calculated with respect to given image data to calculate the chronological changes of the voltage drops in the scanning wiring. The voltage drops and their chronological changes shown here are one example given with respect to given image data, and it is natural that the voltage drops with respect to different image data will exhibit different changes.

In FIG. 8, the degeneracy model is applied for calculation with respect to 4 points of time at which time slot is 0, 64, 128 and 192, respectively, and the voltage drop at each of those times is discretely calculated.

In accordance with FIG. 8, the voltage drop amounts at each node are connected by a dotted line. However, the dotted line is drawn only to make the diagram easier to look at. The voltage drops calculated using the present degeneracy model are each calculated discretely at each of the node positions which are indicated by the white squares, the white circles, the black circles and the white triangles.

FIG. 9 is a graph estimating the emission current that is emitted from a given surface conduction electron-emitting device in the illuminated state when the voltage drop shown in FIG. 8 occurs in the selected scanning wiring.

The vertical axis indicates the emission current amount as percentages at each time and at each location where the degree of the emission current that is emitted when there is not voltage drop is 100%. The horizontal axis indicates the horizontal positions.

As shown in FIG. 9, at the horizontal position (the reference point) at node 2 , the following is established: the emission current when time slot=0 is Ie 0 ; the emission current when time slot=64 is Ie 1 ; the emission current when time slot=128 is Ie 2 ; and the emission current when time slot=192 is Ie 3 .

Note that, the emission current Ie shown in FIG. 9 is calculated from the graphs showing the voltage drop amounts in FIG. 8 and the “drive voltage/emission current” shown in FIG. 4. Specifically, the value of the emission current produced when the voltage calculated by subtracting the voltage drop amount from the voltage V _DRVis applied, is simply plotted out mechanically.

Therefore, FIG. 8 primarily indicates the electric current that is emitted from the surface conduction electron-emitting device when it is in the illuminated state. The surface conduction electron-emitting devices in the turned-off state do not emit electric currents.

FIGS. 10A, 10 B and 10 C are diagrams for explaining a method for calculating the voltage drop amount compensation data based on the changes with a time in the emission current. These diagrams illustrate an example of calculating compensation data for compensating an image data having an inputted data size of 64.

The luminous amount of the luminance is equal to the emission charge amount in which the emission current from the emission current pulse is integrated with a time. Therefore, when fluctuation in the luminance caused by the voltage drop is considered hereinafter, explanations will be made based on the emission charge amount.

Now, in the case where there is no influence from the voltage drop, the emission current is “IE”. Further, if the amount of time corresponding to 1 gradation in the pulse width modulation is assumed to be Δt, then the emission charge amount Q 0 which should be emitted by the emission current pulse when the image data value is 64 is expressed as follows. The emission current pulse's amplitude IE times the pulse width (i.e., 64×Δt), which can be expressed as:
Q 0=IE×64×Δ t (Equation 6)

However, in actuality, the voltage drop in the scanning wiring causes the electric current amount that is emitted from the device to drop.

In the following way, the amount of the emission charge amount produced by the emission current pulse can be approximately calculated in a way which takes the influence of the voltage drop into consideration: i.e., the emission currents of the time slots 0 and 64 at node 2 are established as Ie 0 and Ie 1 , respectively, and if the emission current from 0 to 64 is approximated as a value changing in a linear fashion between Ie 0 and Ie 1 , then the emission charge amount Q 1 during this period will exhibit a trapezoidal area shown in FIG. 10B. In other words, the foregoing can be calculated as:
Q 1=(Ie0+Ie1)×64×Δ t× 0.5 (Equation 7)

Next, as shown in FIG. 10C, in order to compensate the amount of the emission current that is caused by the voltage drop, the influence from the voltage drop can be removed by extending the pulse width by an amount equal to DC 1 . Further, in the case where the compensation for the voltage drop is made and the pulse width is extended, it is considered that the emission current amounts at each of the time slots will change. However, here, for the sake of simplicity, as shown in FIG. 10C, when the time slot=0, the emission current is Ie 0 , and when the time slot=(64+DC 1 ), the emission current is Ie 1 . Further, the emission current between the time slot 0 and the time slot (64+DC 1 ) is approximated as a value along a straight line connecting the emission currents at these 2 points.

Therefore, the emission charge amount Q 2 produced by the emission current pulse after the compensation can be calculated as:
Q 2=(Ie0+Ie1)×(64+DC1)×Δ t× 0.5 (Equation 8)

If this is equal to the above-mentioned Q 0 , then
IE×64×Δ t =(Ie0+Ie1)×(64+DC1)×Δ t× 0.5

When this is calculated with respect to DC 1 ,
DC1=((2×IE−Ie0−Ie1)/(Ie0+Ie1))×64 (Equation 9)

Thus, the compensation data when the size of the image data is 64 is calculated as described above.

In other words, in the case of the image data with the value of 64 at the node 2 position, the compensation amount CData may be added until DC 1 as described in the (Equation 9).

FIGS. 11A to 11C are examples of calculation of the compensation data for image data having a value of 128, based on the calculated voltage drop amount.

In the case where there is no influence from the voltage drop, the emission charge amount Q 3 that should be produced by the emission current pulse when the image data value is 128 is:
Q 3=IE×128 ×Δt= 2× Q 0 (Equation 10)

On the other hand, the emission charge amount produced by the actual emission current pulse having been influenced by the voltage drop can be approximately calculated in the following way. Namely, the emission current amounts at the time slots 0, 64 and 128 at node 2 are set to be Ie 0 , Ie 1 and Ie 2 , respectively. Further, the emission current during the period from time slot 0 to 64 alters a value on a straight line connecting Ie 0 and Ie 1 , and if the emission current during the period from time slot 64 to 128 is approximated as its value changing along the straight line between Ie 1 and Ie 2 , then the emission charge amount Q 4 between the time slot 1 to 128 will be the sum of the two trapezoidal areas in FIG. 11B. That is, it can be calculated as:
Q 4=(Ie0+Ie1)×64 ×Δt× 0.5+(Ie1+Ie2)×64×Δ t× 0.5 (Equation 11)

On the other hand, the voltage drop compensation amount was calculated as follows. The interval corresponding to the time slots 0 to 64 is defined as an interval 1 , and the interval corresponding to the time slots 64 to 128 is defined as an interval 2 . When the compensation has been carried out, the interval 1 portion is extended by an amount equivalent to DC 1 , thus being extended to an interval 1 ′, and the interval 2 part is extended by an amount equivalent to DC 2 , thus being extended to an interval 2 ′. At this time, by compensating each of the intervals, the emission charge amount becomes the same as Q 0 described above.

Further, it goes without saying that the emission currents at the beginning and end of each interval are altered by performing the compensation. However, in order to simplify the calculations, it is assumed that these emission currents do not change. In other words, the emission current at the beginning of the interval 1 ′ is Ie 0 , and the emission current at the end of the interval 1 ′ is Ie 1 . The emission current at the beginning of the interval 2 ′ is Ie 1 , and the emission current at the end of the interval 2 ′ is Ie 2 .

As such, DC 1 can be calculated in a fashion similar to (Equation 9).

DC 2 can also be calculated based on a similar approach:
DC2=((2×IE×Ie1−Ie2)/(Ie1+Ie2))×64 (Equation 12)

As a result, for the image data having the size of 128 at the node 2 position, it is sufficient to add the compensation amount CData that is equivalent to:
CData=DC1+DC2 (Equation 13)

FIGS. 12A to 12C are examples of calculating compensation data for image data having a value of 192 , based on the calculated voltage drop amount.

Now, the emission charge amount Q 5 that will be produced by an emission current pulse anticipated when the image data value is 192 is:
Q 5=IE×192×Δ t= 3 ×QO

On the other hand, the emission charge amount produced by the actual emission current pulse having received the influence by the voltage drop can be approximately calculated as follows. Namely, during the time slots 0, 64, 128 and 192 for node 2 , the emission current amounts at each of these time slots is Ie 0 , Ie 1 , Ie 2 and Ie 3 , respectively. Further, if the emission current during the period from the time slot 0 to 64 is approximated as its value changing along a straight line connecting Ie 0 and Ie 1 , and if the emission current during the period from the time slot 64 to 128 is approximated as its value changing along a straight line connecting Ie 1 and Ie 2 , and if the emission current during the period from the time slot 128 to 192 is approximated as its value changing along a straight line connecting Ie 2 and Ie 3 , then an emission charge amount Q 6 during a period from the time slot 0 to 192 will be as represented by the 3 trapezoidal areas in FIG. 12C. In other words, the emission charge amount Q 6 can be calculated as:

$\begin{matrix} \begin{matrix} Q 6 = (Ie 0 + Ie 1) \times 64 \times Δ t \times 0.5 + \\ (Ie 1 + Ie 2) \times 64 \times Δ t \times 0.5 + \\ (Ie 2 + Ie 3) \times 64 \times Δ t \times 0.5 \end{matrix} & (Equation 14) \end{matrix}$

The interval corresponding to the time slot 0 to 64 is defined as an interval 1 , the interval corresponding to the time slot 64 to 128 is defined as an interval 2 , and the interval corresponding to the time slot 128 to 192 is defined as an interval 3 . In the same manner as is described above, after the compensation has been carried out, the interval 1 part is extended by an amount equivalent to DC 1 , thus being extended to an interval 1 ′, the interval 2 part is extended by an amount equivalent to DC 2 , thus being extended to an interval 2 ′, and the interval 3 part is extended by an amount equivalent to DC 3 , thus being extended to an interval 3 ′. At this time, by compensating each of the intervals, the emission current amount becomes the same as Q 0 described above.

Further, it has been temporarily assumed that the emission currents at the beginning and the end of each interval remain unchanged before and after the compensation. That is, the emission current at the beginning of the interval 1 ′ is Ie 0 , and the emission current at the end of the interval 1 ′ is Ie 1 . The emission current at the beginning of the interval 2 ′ is Ie 1 , and the emission current at the end of the interval 2 ′ is Ie 2 . The emission current at the beginning of the interval 3 ′ is Ie 2 , and the emission current at the end of the interval 3 ′ is Ie 3 .

Therefore, DC 1 and DC 2 can each be calculated in the same ways as shown in (Equation 9) and (Equation 12).

Further, DC 3 can be calculated as:
DC3=((2×IE−Ie2−Ie3)/(Ie2+Ie3))×64 (Equation 15)

As a result, the compensation data CData to be added to the image data having the value of 192 at the node 2 position can be calculated as:
CData=DC1+DC2+DC3 (Equation 16)

The foregoing explains the calculation of the compensation data CData for the image data having the sizes of 64, 128 and 192 with respect to the node 2 position.

Further, when the pulse width is 0, it is obvious that the voltage drop has no influence on the emission current. Therefore, the compensation data is 0, and the compensation data CData to be added to the image data is also 0.

Note that, the reason why the compensation data is calculated in this scattered fashion for image data 0, 64, 128 and 192 is to reduce the volume of the calculations. In other words, if the same calculation were to be performed on all the image data, the volume of the calculations would become extremely large, and the amount of hardware for performing the calculations would become extremely great. On the other hand, there is a tendency that the greater the image data at a given node position, the greater the compensation data will be. Therefore, when the compensation data for an arbitrary image data is to be calculated, the calculation volume can be significantly decreased by using a linear approximation to interpolate between points in the vicinity of the image data for which the compensation data has already been calculated. Note that the interpolation will be explained in detail when discrete compensated data interpolating means is explained.

Further, if the same approach is applied to all the node positions, the compensation data for the 0, 64, 128 and 192 image data at all the node positions can be calculated.

In this embodiment, by applying the degeneracy model to 4 points of the time slots 0, 64, 128, and 192, the voltage drop amounts at respective times were calculated, and thereby, it became possible to calculate the compensation data corresponding to 4 image data reference values of 0, 64, 128, and 192.

However, optimally, by making a time interval for calculating the voltage drop in fines by use of the degeneracy model and increasing the number of the reference values of the image data, it is possible to treat the temporal variation of the voltage drop more precisely and to reduce errors of the approximate calculation.

For example, in this embodiment, the calculation was carried out at only the 4 points of the time slots 0, 64, 128, and 192, but in case that the calculation was carried out at intervals of 16 time slots among the time slots 0 to 255 (i.e., the reference values of the image data are set every 16 in the value of the image data), more preferable result was obtained.

In addition, on that occasion, based upon similar way of thinking, (Equation 6) to (Equation 16) may be modified to carry out the calculation.

An example, obtained by this method, of discrete compensation data to certain input image data is shown in FIG. 13A. In this figure, a horizontal axis corresponds to the horizontal display position, and positions of respective nodes are described. Also, a vertical axis corresponds to the value of the compensation data.

The discrete compensation data is calculated at each of the node positions and the values of the image data Data (image data reference values=0, 64, 128, 192) which are indicated by the white squares, the white circles, the black circles and the white triangles.

(Method of Interpolating the Discrete Compensation Data)

The compensation data calculated discretely is discrete one to positions of respective nodes, and is not one providing compensation data in an arbitrary horizontal position (column wiring number). Also, at the same time to it, it is compensation data to the image data having the size of the reference values of several predetermined image data at respective node positions, but is not one providing compensation data in accordance with size of actual image data value.

Consequently, compensation data fit in with the size of the input image data value in respective column wirings is calculated by interpolating the compensation data calculated discretely.

FIG. 13B is a diagram showing a method for calculating compensation data corresponding to image data “Data” at a position×located between a node n and a node n+1.

Note that it is presumed that the compensation data has already been discretely calculated for positions Xn and Xn+1 at the node n and at the node n+1. Further, the inputted image data Data has a value between image data reference values Dk and Dk+1 for which discrete compensation data have already been calculated.

If the discrete compensation data for the reference value for the “k”-th image data at the node n is written as CData[k] [n], then the compensation data CA for the pulse width Dk at the position x can be calculated in the following way according to the linear approximation using the values of CData[k] [n] and CData[k] [n+1].

$\begin{matrix} CA = \frac{\begin{matrix} (X_{n + 1} - x) \times CData [k] [n] + \\ (x - X_{n}) \times CData [k] [n + 1] \end{matrix}}{X_{n + 1} - X_{n}} & (Equation 17) \end{matrix}$

Further, compensation data CB for image data Dk+1 at the position x can be calculated as follows.

$\begin{matrix} CB = \frac{\begin{matrix} (X_{n + 1} - x) \times CData [k + 1] [n] + \\ (x - X_{n}) \times CData [k + 1] [n + 1] \end{matrix}}{X_{n + 1} - X_{n}} & (Equation 18) \end{matrix}$

By linearly approximating the compensation data CA and CB, the compensation data CD for the image data Data at the position x can be calculated as follows.

$\begin{matrix} CD = \frac{CA \times (D_{k + 1} - Data) + CB \times (Data - D_{k})}{D_{k + 1} - D_{k}} & (Equation 19) \end{matrix}$

As described above, in order to calculate the compensation data from the discrete compensation data such that the compensation data is appropriate for the actual position and the actual image data size, the calculations can be performed easily by using the methods written in (Equation 17) to (Equation 19).

The compensation data calculated herewith is added to the image data to compensate the image data and the pulse-width modulation is carried out in compliance with the image data after the compensation, and thereby, deterioration of the image quality due to the voltage drop can be reduced and the image quality can be improved.

Since calculated amount can be reduced by adopting the approximation such as the degeneracy etc., with respect to hardware for compensation, it can be configured by very small-sized hardware.

(Explanation of Functions of Overall System and Respective Parts)

Then, hardware of the display apparatus with a built-in compensation data calculation unit will be described.

FIG. 14 is a block diagram showing an outline of its circuit structure. In the figure, 1 designates the display panel of FIG. 2, Dx 1 to DxM and Dx 1 ′ to DxM′ designate voltage supply terminals for the scanning wirings of the display panel, Dy 1 to DyN designate voltage supply terminals for the modulation wirings of the display panel, Hv designates a high-voltage supply terminal for applying acceleration voltage between a face plate and a rear plate, Va designates a high-voltage power supply, 2 designates a scanning circuit (scanning unit), 3 designates a synchronization signal separation circuit, 4 designates a timing generation circuit, 7 designates a RGB conversion part for converting YPbPr signals separated by the synchronizing signal separation circuit 3 into RGB signals, 17 designates an inverse γ processing part, 5 designates a shift register for 1 line of the image data, 6 designates a latch circuit for 1 line of the image data, 8 designates a pulse-width modulation unit (modulation unit) outputting modulation signals to the modulation wirings of the display panel, 12 designates an adder (calculation processing unit, addition processing unit), 14 designates a compensation data calculation unit, 221 designates an average luminance level calculation unit (average luminance detection circuit), and 222 designates a drive voltage calculation part.

Also, in the same figure, R, G, and B designate parallel input image data, Ra, Ga, and Ba designate RGB-parallel image data to which inverse γ conversion processing described later is applied, Data is image data which was parallel/serial-converted by a data array conversion part 9 , CD designates compensation data which was calculated by the compensation data calculation unit 14 , and Dout designates image data which was compensated (compensated image data) by adding the compensation data to the image data by the adder 12 .

(Synchronization Signal Separation Circuit, Timing Generation Circuit)

The display apparatus of this embodiment can display NTSC, PAL, SECAM, HDTV and other such television signals, and also computer outputs such as VGA and the like.

In FIG. 14, only the HDTV format is shown in order to simplify the diagram.

From an image signal of HDTV system, firstly, synchronization signals Vsync, Hsync are separated by a synchronization signal separation circuit 3 , and supplied to a timing generation circuit 4 . The image signal from which the synchronization signals were separated are supplied to a RGB conversion part 7 . Inside of the RGB conversion part 7 , besides a conversion circuit from YPbPr to RGB, not-shown low pass filter and A/D converter etc. are disposed. The RGB conversion part 7 converts YPbPr which is filtered with the low pass filter to digital RGB signals by the A/D converter, and supplies the same to the inverse γ processing part 17 .

(Timing Generation Circuit)

The timing generation circuit 4 has a built-in PLL circuit, and it generates timing signals synchronized to synchronization signals from various image sources and generates operation timing signals for each part.

Examples of timing signals generated by the timing generation circuit 4 include a TSFT for controlling operating timing of the shift resistor 5 ; a control signal Dataload for latching data from the shift resistor 5 to the latch circuit 6 ; a pulse width modulation start signal Pwmstart for the modulation circuit 8 ; a clock Pwmclk for the pulse width modulation; and a timing signal Tscan for controlling the operation of the scanning circuit 2 .

(Scanning Circuit)

The scanning circuits 2 and 2 ′ in FIG. 14 are circuits for outputting the selection electric potential Vs or the non-selection electric potential Vns to the connection terminals Dx 1 to DxM to sequentially scan the display panel 1 in steps of 1 line during 1 horizontal scanning period.

The scanning circuit 2 and 2 ′, as shown in FIG. 15, has a variable power supply for setting the selection electric potential Vs on the basis of a selection electric potential instruction value SVs which is supplied from a drive voltage calculation part to be described later. In this embodiment, by changing the selection electric potential Vs, it is possible to change the drive voltage of the cold cathode device disposed on the display panel 1 .

The scanning circuits 2 and 2 ′ are circuits which sequentially change the scanning wiring that is being selected with respect to each horizontal period, in synchronous with a timing signal Tscan from the timing generation circuit 4 to carry out the scanning.

In addition, Tscan designates a group of timing signals generated of vertical synchronization signals and horizontal synchronization signals etc.

The scanning circuits 2 and 2 ′, as shown in FIG. 15, are composed of M number of switches and shift registers etc. It is desirable that these switches are composed of transistors and FETs.

In addition, in order to reduce the voltage drop in the scanning wiring, it is effective that, as shown in FIG. 14, the scanning circuits are connected to both ends of the scanning wiring of the display panel to drive from the both ends. However, the method in this embodiment is applicable to a case that the scanning circuits are not connected to the both ends of the scanning wiring. In that case, the above-described (Equation 3) may be modified.

In FIG. 15, a panel drive power supply which provides the selection electric potential Vs and the non-selection electric potential Vns is disposed in the scanning circuits, but it is desirable that such panel drive power supply is formed as an independent power supply circuit separated from the scanning circuits.

(Inverse γ Processing Part)

CRTs have a luminous characteristic of the approximately 2.2 power to their inputs (hereinafter referred to as inverse γ characteristic). Input image signals, taking such characteristic of CRTs into consideration, are converted generally in compliance with the γ characteristic of the 0.45 power to realize a linear luminous characteristic on the occasion of displaying on CRT.

On the other hand, the display panel 1 of the display apparatus in this embodiment, in case that the modulation is carried out by adjusting duration of time that the drive voltage is applied, has a substantially linear luminous characteristic with respect to length of time that the drive voltage is applied. Accordingly, the input image signal may be converted on the basis of the inverse γ characteristic (hereinafter, referred to as inverse γ conversion).

FIG. 16 shows the detail of a inverse γ processing part 17 . This inverse γ processing part 17 is a block for carrying out the inverse γ conversion of the input image signal.

The inverse γ processing part 17 in this embodiment realizes the inverse γ conversion processing by use of a memory. The number of bits of the image signals R, G, and B are set to 8 bits, and the number of bits of the image signals Ra, Ga, and Ba as outputs from the inverse γ processing part 17 are also set to 8 bits, and the inverse γ processing part 17 is configured by using a memory having 8 bit addresses and 8 bit data with respect to each color.

(Data Array Conversion Part)

A data array conversion part 9 in FIG. 14 is a circuit for performing a parallel/serial conversion on the RGB parallel image signals Rb, Gb and Bb, to make them appropriate for pixel array of the display panel. As shown in FIG. 17, the data array conversion part 9 is composed of FIFO (a First In First Out) memories 2021 R, 2021 G and 2021 B for each of the RGB colors, and a selector 2022 .

Although they are not shown in the diagram, the FIFO memory has two memories capable of holding number of words equal to the number of horizontal pixels, where one of the memories is for odd-number lines, and the other memory is for even-number lines. When image data from an odd-number line is inputted, this data is inputted into the FIFO for the odd-number line while image data stored in the immediately previous horizontal scanning period is read out from the FIFO memory for the even-number line. When the image data from the even-number line is inputted, the data is written into FIFO for the even-number line while the image data stored in the immediately previous horizontal scanning period is read out from the FIFO for the odd-number line.

The data read out from the FIFO memory undergoes the parallel/serial conversion by the selector in accordance with the pixel array of the display panel, and is then outputted as serial image data SData for the RGB. The data array conversion part 9 operates based on the timing control signals from the timing generation circuit 4 .

(Adder)

The adder 12 in FIG. 14 is a unit for adding the compensation data CD from the compensation data calculation unit 14 and the image data Data. By carrying out the addition, the image data Data is compensated and is, as image data Dout, transferred to the shift register 5 .

In addition, on the occasion of adding the image data Data and the compensation data CD, there is a possibility that overflow occurs in the adder 12 . In contrast to this, in this embodiment, as a structure for preventing the overflow, depending upon maximum value on the occasion of adding the image data Data and the compensation data CD, bid width of the adder 12 and bit width of the modulation unit 8 after that were determined.

More concretely, in case of the display apparatus of this embodiment, since the compensation data became maximum 120 on the occasion of a screen in which all the image data values are 255, the maximum value of the output of the adder 12 becomes 255+120=375. Then, supposing that the number of output bits of the adder is of 9 bits, and the number of bits of the modulation unit is of 9 bits, the number of bits in respective parts was determined.

Also, as another structure for preventing the overflow, the maximum value of the compensation data to be added is estimated in advance, and, in order to prevent the overflow from occurring when its maximum value was added, a range of a value that the image data can take may be lessen in advance.

In order to lessen range of the value that the image data can take, for example, the input image data may be limited on the occasion of carrying out A/D conversion, and a multiplier may be provided so that a gain of more than 0 and less than 1 is multiplied with the input image data to limit its range.

(Delay Circuit)

The image data SData which has been reordered by the data array conversion part 9 is inputted into the compensation data calculation unit 14 and into the delay circuit 19 . A compensation data interpolating part of the compensation data calculation unit 14 described below cross-references horizontal position information x from the timing control circuit and the value of the image data SData to calculate the compensation data CD which will be suitable for each horizontal position and for each image data value.

The delay circuit 19 is provided to absorb the time required for the calculation of the compensation data. When the adder 12 adds the compensation data to the image data, the delay circuit 19 performs the delay so that the compensation data corresponding to the image data is added accurately. The delay circuit 19 is constituted by using a flip-flop circuit.

(Shift Resistor, Latch Circuit)

The image data Dout as outputs from the adder 12 undergoes the serial/parallel conversion by the shift resistor 5 , whereby the image data Dout changes from its serial data format into parallel image data ID 1 to IDN per modulation wiring and then it is outputted to the latch circuit 6 . The latch circuit 6 latches the data from the shift resistor 5 immediately before one horizontal interval is started, based on the timing signal Dataload. The outputs from the latch circuit 6 are delivered to the modulation unit 8 as parallel image data D 1 to DN.

Note that, in accordance with this embodiment, the image data ID 1 to IDN and D 1 to DN are each composed of 8 bits. Their operation timing is based on the timing control signals TSFT and Dataload from the timing generation circuit 4 .

(Details of the Modulation Circuit)

The parallel image data D 1 to DN outputted from the latch circuit 6 is provided to the modulation unit 8 .

As shown in FIG. 18A, the modulation unit 8 is a pulse width modulation circuit (PWM circuit) including a PWM counter, and a comparator and a switch (a FET in FIG. 18A) for each modulation wiring.

As shown in FIG. 18B, the relationship between the image data D 1 to DN and the output pulse width from the modulation unit 8 is a linear relationship.

FIG. 18C shows 3 examples of an output waveform from the modulation unit 8 . In FIG. 18C, the waveform depicted at the top is a waveform when the input data to the modulation unit 8 is 0. The waveform depicted in the middle is a waveform when the input data to the modulation unit 8 is 256. The waveform depicted on the bottom is the waveform when the input data to the modulation unit 8 is 511.

In addition, in this embodiment, the number of bits of the input data D 1 to DN to the modulation unit 8 is, as described above, on the ground that the overflow does not occur, set to 9 bits (in addition, in the above-stated description, there are places describing that, when the input data of the modulation unit 8 is 511, the modulation signal of pulse width corresponding to 1 horizontal scanning period is outputted, but in detail, as shown in FIG. 18C, although it is very short tim

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