Harrison, Ronnie M. (Boise, ID, US)

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11/182965

08/19/2008

07/15/2005

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Micron Technology, Inc. (Boise, ID, US)

327/158

703/19

G06F17/50; H03L7/06

716/6, 327/158, 703/19, 703/13

3633174	MEMORY SYSTEM HAVING SELF-ADJUSTING STROBE TIMING	January, 1972	Griffin	340/172.5
4004100	Group frame synchronization system	January, 1977	Takimoto	179/15BS
4077016	Apparatus and method for inhibiting false locking of a phase-locked loop	February, 1978	Sanders et al.	331/4
4096402	MOSFET buffer for TTL logic input and method of operation	June, 1978	Schroeder et al.	307/362
4404474	Active load pulse generating circuit	September, 1983	Dingwall	307/260
4481625	High speed data bus system	November, 1984	Roberts et al.	370/85
4508983	MOS Analog switch driven by complementary, minimally skewed clock signals	April, 1985	Allgood et al.	307/577
4511846	Deskewing time-critical signals in automatic test equipment	April, 1985	Nagy et al.	328/164
4514647	Chipset synchronization arrangement	April, 1985	Shoji	307/269
4524448	Variable delay unit for data synchronizer using phase-sensitive counter to vary the delay	June, 1985	Hullwegen	375/118
4573017	Unitary phase and frequency adjust network for a multiple frequency digital phase locked loop	February, 1986	Levine	327/114
4600895	Precision phase synchronization of free-running oscillator output signal to reference signal	July, 1986	Landsman	331/1A
4603320	Connector interface	July, 1986	Farago	341/89
4638187	CMOS output buffer providing high drive current with minimum output signal distortion	January, 1987	Boler et al.	307/451
4638451	Microprocessor system with programmable interface	January, 1987	Hester et al.
4687951	Fuse link for varying chip operating parameters	August, 1987	McElroy	307/269
4697167	Sync pattern encoding system for data sectors written on a storage medium	September, 1987	O'Keeffe et al.	340/347
4727541	Hierarchical data transmission system	February, 1988	Mori et al.	370/112
4740962	Synchronizer for time division multiplexed data	April, 1988	Kish, III	370/102
4746996	Skew error correction circuit for video signal reproducing apparatus	May, 1988	Furuhata et al.	360/36.2
4773085	Phase and frequency detector circuits	September, 1988	Cordell	375/120
4789796	Output buffer having sequentially-switched output	December, 1988	Foss	307/443
4791622	Optical data format employing resynchronizable data sectors	December, 1988	Clay et al.	369/59
4818995	Parallel transmission system	April, 1989	Takahashi et al.	341/94
4893087	Low voltage and low power frequency synthesizer	January, 1990	Davis	328/14
4902986	Phased locked loop to provide precise frequency and phase tracking of two signals	February, 1990	Lesmeister	331/25
4924516	Method and system for a synchronized pseudo-random privacy modem	May, 1990	Bremer et al.	380/46
4953128	Variable delay circuit for delaying input data	August, 1990	Kawai et al.	365/194
4958088	Low power three-stage CMOS input buffer with controlled switching	September, 1990	Farah-Bakhsh et al.	307/443
4972470	Programmable connector	November, 1990	Farago	380/3
4979185	High speed serial data link	December, 1990	Bryans et al.	375/20
4984204	High speed sensor system using a level shift circuit	January, 1991	Sato et al.	365/189.11
4984255	Edge transition insensitive delay line system and method	January, 1991	Davis et al.	375/106
5020023	Automatic vernier synchronization of skewed data streams	May, 1991	Smith
5038115	Method and apparatus for frequency independent phase tracking of input signals in receiving systems and the like	August, 1991	Myers et al.	331/2
5062082	Semiconductor memory device with delay in address predecoder circuit independent from ATD	October, 1991	Choi	365/230.06
5075569	Output device circuit and method to minimize impedance fluctuations during crossover	December, 1991	Branson	307/270
5086500	Synchronized system by adjusting independently clock signals arriving at a plurality of integrated circuits	February, 1992	Greub	395/550
5087828	Timing circuit for single line serial data	February, 1992	Sato et al.	307/269
5113519	Maintenance of file attributes in a distributed data processing system	May, 1992	Johnson et al.	395/600
5120990	Apparatus for generating multiple phase clock signals and phase detector therefor	June, 1992	Koker	307/269
5122690	Interface circuits including driver circuits with switching noise reduction	June, 1992	Bianchi	307/475
5128560	Boosted supply output driver circuit for driving an all N-channel output stage	July, 1992	Chern et al.	307/475
5128563	CMOS bootstrapped output driver method and circuit	July, 1992	Hush et al.	307/482
5130565	Self calibrating PWM utilizing feedback loop for adjusting duty cycles of output signal	July, 1992	Girmay	307/265
5134311	Self-adjusting impedance matching driver	July, 1992	Biber et al.	307/270
5150186	CMOS output pull-up driver	September, 1992	Pinney et al.	357/42
5165046	High speed CMOS driver circuit	November, 1992	Hesson	307/270
5168199	Horizontal linearity correction circuitry for cathode ray tube display	December, 1992	Huffman et al.	315/370
5179298	CMOS buffer circuit which is not influenced by bounce noise	January, 1993	Hirano et al.	307/443
5182524	Method and apparatus for stabilizing pulsed microwave amplifiers	January, 1993	Hopkins	330/149
5194765	Digitally controlled element sizing	March, 1993	Dunlop et al.	307/443
5212601	Disk drive data synchronizer with window shift synthesis	May, 1993	Wilson	360/51
5220208	Circuitry and method for controlling current in an electronic circuit	June, 1993	Schenck	307/443
5223755	Extended frequency range variable delay locked loop for clock synchronization	June, 1993	Richley	307/603
5229929	Output peak current correction for PWM invertors	July, 1993	Shimizu et al.	363/98
5233314	Integrated charge-pump phase-locked loop circuit	August, 1993	McDermott et al.	331/17
5233564	Multiport memory with test signal generating circuit controlling data transfer from RAM port to SAM port	August, 1993	Ohshima et al.	365/230.05
5239206	Synchronous circuit with clock skew compensating function and circuits utilizing same	August, 1993	Yanai	307/272.2
5243703	Apparatus for synchronously generating clock signals in a data processing system	September, 1993	Farmwald et al.
5254883	Electrical current source circuitry for a bus	October, 1993	Horowitz et al.	307/443
5256989	Lock detection for a phase lock loop	October, 1993	Parker et al.	331/1A
5257294	Phase-locked loop circuit and method	October, 1993	Pinto et al.	375/120
5268639	Testing timing parameters of high speed integrated circuit devices	December, 1993	Gasbarro et al.	324/158R
5272729	Clock signal latency elimination network	December, 1993	Bechade et al.	375/118
5274276	Output driver circuit comprising a programmable circuit for determining the potential at the output node and the method of implementing the circuit	December, 1993	Casper et al.	307/443
5276642	Method for performing a split read/write operation in a dynamic random access memory	January, 1994	Lee	365/189.04
5278460	Voltage compensating CMOS input buffer	January, 1994	Casper	307/296.5
5281865	Flip-flop circuit	January, 1994	Yamashita et al.	307/279
5283631	Programmable capacitance delay element having inverters controlled by adjustable voltage to offset temperature and voltage supply variations	February, 1994	Koerner et al.	307/451
5289580	Programmable multiple I/O interface controller	February, 1994	Latif et al.
5295164	Apparatus for providing a system clock locked to an external clock over a wide range of frequencies	March, 1994	Yamamura	375/120
5304952	Lock sensor circuit and method for phase lock loop circuits	April, 1994	Quiet et al.	331/1A
5311481	Wordline driver circuit having a directly gated pull-down device	May, 1994	Casper et al.	365/230.06
5311483	Synchronous type semiconductor memory	May, 1994	Takasugi	365/233
5313431	Multiport semiconductor memory device	May, 1994	Uruma et al.	365/230.05
5315269	Phase-locked loop	May, 1994	Fujii	331/1A
5315388	Multiple serial access memory for use in feedback systems such as motion compensated television	May, 1994	Shen et al.	348/718
5321368	Synchronized, digital sequential circuit	June, 1994	Hoelzle	328/63
5337285	Method and apparatus for power control in devices	August, 1994	Ware et al.	365/227
5341405	Data recovery apparatus and methods	August, 1994	Mallard, Jr.	375/120
5347177	System for interconnecting VLSI circuits with transmission line characteristics	September, 1994	Lipp	307/443
5347179	Inverting output driver circuit for reducing electron injection into the substrate	September, 1994	Casper et al.	307/451
5355391	High speed bus system	October, 1994	Horowitz et al.	375/36
5361002	Voltage compensating CMOS input buffer	November, 1994	Casper	327/530
5367649	Programmable controller	November, 1994	Cedar	395/375
5379299	High speed propagation delay compensation network	January, 1995	Schwartz	370/108
5390308	Method and apparatus for address mapping of dynamic random access memory	February, 1995	Ware et al.	395/400
5400283	RAM row decode circuitry that utilizes a precharge circuit that is deactivated by a feedback from an activated word line driver	March, 1995	Raad	365/203
5402389	Synchronous memory having parallel output data paths	March, 1995	Flannagan et al.	365/233
5408640	Phase delay compensator using gating signal generated by a synchronizer for loading and shifting of bit pattern to produce clock phases corresponding to frequency changes	April, 1995	MacIntyre et al.	395/550
5410263	Delay line loop for on-chip clock synthesis with zero skew and 50% duty cycle	April, 1995	Waizman	327/141
5416436	Method for time delaying a signal and corresponding delay circuit	May, 1995	Rainard	327/270
5416909	Input/output controller circuit using a single transceiver to serve multiple input/output ports and method therefor	May, 1995	Long et al.	395/275
5420544	Semiconductor integrated circuit, method of designing the same and method of manufacturing the same	May, 1995	Ishibashi	331/11
5424687	PLL frequency synthesizer and PLL frequency synthesizing method capable of obtaining high-speed lock-up and highly-reliable oscillation	June, 1995	Fukuda	331/11
5428311	Fuse circuitry to control the propagation delay of an IC	June, 1995	McClure	327/276
5428317	Phase locked loop with low power feedback path and method of operation	June, 1995	Sanchez et al.	331/1A
5430408	Transmission gate circuit	July, 1995	Ovens et al.	327/407
5430676	Dynamic random access memory system	July, 1995	Ware et al.	365/189.02
5432823	Method and circuitry for minimizing clock-data skew in a bus system	July, 1995	Gasbarro et al.	375/356
5438545	Data output buffer of semiconductor memory device for preventing noises	August, 1995	Sim	365/189.05
5440260	Variable delay circuit	August, 1995	Hayashi et al.	327/278
5440514	Write control for a memory using a delay locked loop	August, 1995	Flannagan et al.	365/194
5444667	Semiconductor synchronous memory device having input circuit for producing constant main control signal operative to allow timing generator to latch command signals	August, 1995	Obara	365/233
5446696	Method and apparatus for implementing refresh in a synchronous DRAM system	August, 1995	Ware et al.	365/222
5448193	Normalization of apparent propagation delay	September, 1995	Baumert et al.	327/156
5451898	Bias circuit and differential amplifier having stabilized output swing	September, 1995	Johnson	327/563
5457407	Binary weighted reference circuit for a variable impedance output buffer	October, 1995	Shu et al.	326/30
5463337	Delay locked loop based clock synthesizer using a dynamically adjustable number of delay elements therein	October, 1995	Leonowich	327/158
5465076	Programmable delay line programmable delay circuit and digital controlled oscillator	November, 1995	Yamauchi et al.	331/179
5473274	Local clock generator	December, 1995	Reilly et al.	327/159
5473575	Integrated circuit I/O using a high performance bus interface	December, 1995	Farmwald et al.	365/230.06
5473639	Clock recovery apparatus with means for sensing an out of lock condition	December, 1995	Lee et al.	375/376
5485490	Method and circuitry for clock synchronization	January, 1996	Leung et al.	375/371
5488321	Static high speed comparator	January, 1996	Johnson	327/66
5489864	Delay interpolation circuitry	February, 1996	Ashuri	327/161
5497127	Wide frequency range CMOS relaxation oscillator with variable hysteresis	March, 1996	Sauer	331/17
5497355	Synchronous address latching for memory arrays	March, 1996	Mills et al.	365/230.08
5498990	Reduced CMOS-swing clamping circuit for bus lines	March, 1996	Leung et al.	327/323
5500808	Apparatus and method for estimating time delays using unmapped combinational logic networks	March, 1996	Wang	364/578
5502672	Data output buffer control circuit	March, 1996	Kwon	365/189.05
5506814	Video random access memory device and method implementing independent two WE nibble control	April, 1996	Hush et al.	365/230.03
5508638	Low current redundancy fuse assembly	April, 1996	Cowles et al.	326/38
5513327	Integrated circuit I/O using a high performance bus interface	April, 1996	Farmwald et al.
5515403	Apparatus and method for clock alignment and switching	May, 1996	Sloan et al.	375/371
5532714	Method and apparatus for combining video images on a pixel basis	July, 1996	Knapp et al.	345/114
5539345	Phase detector apparatus	July, 1996	Hawkins	327/150
5544124	Optimization circuitry and control for a synchronous memory device with programmable latency period	August, 1996	Zagar et al.	365/230.08
5544203	Fine resolution digital delay line with coarse and fine adjustment stages	August, 1996	Casasanta et al.	375/376
5550515	Multiphase clock synthesizer having a plurality of phase shifted inputs to a plurality of phase comparators in a phase locked loop	August, 1996	Liang et al.	331/11
5550549	Transponder system and method	August, 1996	Procter, Jr. et al.	342/47
5550783	Phase shift correction circuit for monolithic random access memory	August, 1996	Stephens, Jr. et al.	365/233
5552727	Digital phase locked loop circuit	September, 1996	Nakao	327/159
5555429	Multiport RAM based multiprocessor	September, 1996	Parkinson et al.
5557224	Apparatus and method for generating a phase-controlled clock signal	September, 1996	Wright et al.	327/115
5557781	Combination asynchronous cache system and automatic clock tuning device and method therefor	September, 1996	Stones et al.
5563546	Selector circuit selecting and outputting voltage applied to one of first and second terminal in response to voltage level applied to first terminal	October, 1996	Tsukada	327/408
5568075	Timing signal generator	October, 1996	Curran et al.	327/172
5568077	Latch circuit	October, 1996	Sato et al.	327/199
5572557	Semiconductor integrated circuit device including PLL circuit	November, 1996	Aoki	375/376
5572722	Time skewing arrangement for operating random access memory in synchronism with a data processor	November, 1996	Vogley	395/555
5574698	Ram row decode circuitry that utilizes a precharge circuit that is deactivated by a feedback from an activated word line driver	November, 1996	Raad	365/230.06
5576645	Sample and hold flip-flop for CMOS logic	November, 1996	Farwell	327/94
5577079	Phase comparing circuit and PLL circuit	November, 1996	Zenno et al.	375/373
5577236	Memory controller for reading data from synchronous RAM	November, 1996	Johnson et al.
5578940	Modular bus with single or double parallel termination	November, 1996	Dillon et al.	326/30
5578941	Voltage compensating CMOS input buffer circuit	November, 1996	Sher et al.	326/34
5579326	Method and apparatus for programming signal timing	November, 1996	McClure	371/61
5581197	Method of programming a desired source resistance for a driver stage	December, 1996	Motley et al.	326/30
5589788	Timing adjustment circuit	December, 1996	Goto	327/276
5590073	Random access memory having flash memory	December, 1996	Arakawa et al.	365/185.08
5594690	Integrated circuit memory having high speed and low power by selectively coupling compensation components to a pulse generator	January, 1997	Rothenberger et al.	365/189.01
5610558	Controlled tracking of oscillators in a circuit with multiple frequency sensitive elements	March, 1997	Mittel et al.	331/2
5614855	Delay-locked loop	March, 1997	Lee et al.	327/158
5619473	Semiconductor memory device with dual address memory read amplifiers	April, 1997	Hotta	365/238.5
5621340	Differential comparator for amplifying small swing signals to a full swing output	April, 1997	Lee et al.	327/65
5621690	Nonvolatile memory blocking architecture and redundancy	April, 1997	Jungroth et al.	365/200
5621739	Method and apparatus for buffer self-test and characterization	April, 1997	Sine et al.	371/22.1
5623523	Method and apparatus for increasing voltage in a charge pump used in a phase locked loop	April, 1997	Gehrke	375/376
5627780	Testing a non-volatile memory	May, 1997	Malhi	365/185.09
5627791	Multiple bank memory with auto refresh to specified bank	May, 1997	Wright et al.	365/222
5631872	Low power consumption semiconductor dynamic random access memory device by reusing residual electric charge on bit line pairs	May, 1997	Naritake et al.	365/227
5636163	Random access memory with a plurality amplifier groups for reading and writing in normal and test modes	June, 1997	Furutani et al.	365/233
5636173	Auto-precharge during bank selection	June, 1997	Schaefer	365/230.03
5636174	Fast cycle time-low latency dynamic random access memories and systems and methods using the same	June, 1997	Rao	365/230.03
5638335	Semiconductor device	June, 1997	Akiyama et al.	365/230.03
5644743	Hybrid analog-digital phase error detector	July, 1997	Barrett, Jr. et al.	375/375
5646904	Semicoductor memory with a timing controlled for receiving data at a semiconductor memory module to be accessed	July, 1997	Ohno et al.	365/233
5652530	Method and apparatus for reducing clock-data skew by clock shifting	July, 1997	Ashuri	326/93
5657289	Expandable data width SAM for a multiport RAM	August, 1997	Hush et al.	365/230.05
5657481	Memory device with a phase locked loop circuitry	August, 1997	Farmwald et al.
5663921	Internal timing method and circuit for programmable memories	September, 1997	Pascucci et al.	365/233
5666313	Semiconductor memory device with complete inhibition of boosting of word line drive signal and method thereof	September, 1997	Ichiguchi	365/195
5666322	Phase-locked loop timing controller in an integrated circuit memory	September, 1997	Conkle	365/233
5668763	Semiconductor memory for increasing the number of half good memories by selecting and using good memory blocks	September, 1997	Fujioka et al.	365/200
5668774	Dynamic semiconductor memory device having fast operation mode and operating with low current consumption	September, 1997	Furutani	365/233
5673005	Time standard circuit with delay line oscillator	September, 1997	Pricer	331/1R
5675274	Semiconductor clock signal generation circuit	October, 1997	Kobayashi et al.	327/158
5675588	Testing apparatus for transmission system	October, 1997	Maruyama et al.	371/20.4
5692165	Memory controller with low skew control signal	November, 1997	Jeddeloh et al.
5694065	Switching control circuitry for low noise CMOS inverter	December, 1997	Hamasaki et al.	327/108
5708611	Synchronous semiconductor memory device	January, 1998	Iwamoto et al.	365/233X
5712580	Linear phase detector for half-speed quadrature clocking architecture	January, 1998	Baumgartner et al.	327/12
5712883	Clock signal distribution system	January, 1998	Miller et al.	375/371
5719508	Loss of lock detector for master timing generator	February, 1998	Daly	327/12
5737342	Method for in-chip testing of digital circuits of a synchronously sampled data detection channel	April, 1998	Ziperovich	371/25.1
5740123	Semiconductor integrated circuit for changing pulse width according to frequency of external signal	April, 1998	Uchida	365/233
5751665	Clock distributing circuit	May, 1998	Tanoi	368/120
5764092	Delay clock generator for generating a plurality of delay clocks delaying the basic clock	June, 1998	Wada et al.	327/271
5767715	Method and apparatus for generating timing pulses accurately skewed relative to clock	June, 1998	Marquis et al.	327/159
5768177	Controlled delay circuit for use in synchronized semiconductor memory	June, 1998	Sakuragi	365/194
5774699	System controller for controlling switching operations of various operation clocks for CPU, DRAM, and the like	June, 1998	Nagae
5778214	Bit-phase aligning circuit	July, 1998	Taya et al.
5781499	Semiconductor memory device	July, 1998	Koshikawa	365/233
5784422	Apparatus and method for accurate synchronization with inbound data packets at relatively low sampling rates	July, 1998	Heermann	375/355
5789947	Phase comparator	August, 1998	Sato	327/3
5790612	System and method to reduce jitter in digital delay-locked loops	August, 1998	Chengson et al.	375/373
5794020	Data transfer apparatus fetching reception data at maximum margin of timing	August, 1998	Tanaka et al.
5805931	Programmable bandwidth I/O port and a communication interface using the same port having a plurality of serial access memories capable of being configured for a variety of protocols	September, 1998	Morzano et al.
5812619	Digital phase lock loop and system for digital clock recovery	September, 1998	Runaldue	375/376
5822314	Communications system and method of operation	October, 1998	Chater-Lea	370/337
5831545	Method and apparatus for adjusting a communication strategy in a radio communication system using location	November, 1998	Murray et al.	340/825.49
5831929	Memory device with staggered data paths	November, 1998	Manning	365/233
5841707	Apparatus and method for a programmable interval timing generator in a semiconductor memory	November, 1998	Cline et al.	365/194
5852378	Low-skew differential signal converter	December, 1998	Keeth	327/171
5872959	Method and apparatus for parallel high speed data transfer	February, 1999	Nguyen et al.
5889828	Clock reproduction circuit and elements used in the same	March, 1999	Miyashita et al.	375/374
5889829	Phase locked loop with improved lock time and stability	March, 1999	Chiao et al.	375/376
5898242	Self-calibrating clock circuit employing a continuously variable delay module in a feedback loop	April, 1999	Peterson	327/278
5898674	System and method for performing non-disruptive diagnostics through a frame relay circuit	April, 1999	Mawhinney et al.	370/247
5909130	Digital lock detector for phase-locked loop	June, 1999	Martin et al.	327/12
5917760	De-skewing data signals in a memory system	June, 1999	Millar	365/194
5920518	Synchronous clock generator including delay-locked loop	July, 1999	Harrison et al.	365/233
5926047	Synchronous clock generator including a delay-locked loop signal loss detector	July, 1999	Harrison	327/159
5926436	Semiconductor memory device	July, 1999	Toda et al.	365/236
5940608	Method and apparatus for generating an internal clock signal that is synchronized to an external clock signal	August, 1999	Manning
5940609	Synchronous clock generator including a false lock detector	August, 1999	Harrison
5945855	High speed phase lock loop having high precision charge pump with error cancellation	August, 1999	Momtaz	327/157
5946244	Delay-locked loop with binary-coupled capacitor	August, 1999	Manning	365/194
5953284	Method and apparatus for adaptively adjusting the timing of a clock signal used to latch digital signals, and memory device using same	September, 1999	Baker et al.	365/233
5953386	High speed clock recovery circuit using complimentary dividers	September, 1999	Anderson	375/376
5964884	Self-timed pulse control circuit	October, 1999	Partovi et al.	713/503
5990719	Adaptive filtering scheme for sampling phase relations of clock networks	November, 1999	Dai et al.	327/244
6005694	Method and system for detecting optical faults within the optical domain of a fiber communication network	December, 1999	Liu	359/110
6005823	Memory device with pipelined column address path	December, 1999	Martin et al.	365/230.08
6011732	Synchronous clock generator including a compound delay-locked loop	January, 2000	Harrison et al.	365/194
6011822	Differential charge pump based phase locked loop or delay locked loop	January, 2000	Dreyer	375/376
6016282	Clock vernier adjustment	January, 2000	Keeth	365/233
6023489	Method and apparatus for code synchronization in a global positioning system receiver	February, 2000	Hatch	375/208
6026050	Method and apparatus for adaptively adjusting the timing of a clock signal used to latch digital signals, and memory device using same	February, 2000	Baker et al.	635/233
6026134	Phase locked loop (PLL) with linear parallel sampling phase detector	February, 2000	Duffy et al.	375/376
6029250	Method and apparatus for adaptively adjusting the timing offset between a clock signal and digital signals transmitted coincident with that clock signal, and memory device and system using same	February, 2000	Keeth	713/400
6038219	User-configurable frame relay network	March, 2000	Mawhinney et al.	370/242
6067592	System having a synchronous memory device	May, 2000	Farmwald et al.	710/104
6072802	Initial synchronization method in code division multiple access reception system	June, 2000	Uhm et al.	370/441
6087857	Clock signal phase comparator	July, 2000	Wang	327/5
6101152	Method of operating a synchronous memory device	August, 2000	Farmwald et al.	365/233
6101197	Method and apparatus for adjusting the timing of signals over fine and coarse ranges	August, 2000	Keeth et al.	370/517
6105157	Salphasic timing calibration system for an integrated circuit tester	August, 2000	Miller	714/744
6115318	Clock vernier adjustment	September, 2000	Keeth	365/233
6119242	Synchronous clock generator including a false lock detector	September, 2000	Harrison	713/503
6125157	Delay-locked loop circuitry for clock delay adjustment	September, 2000	Donnelly et al.	375/371
6147905	Non-volatile semiconductor memory device	November, 2000	Seino	365/185.11
6147916	Semiconductor memory device with precharge voltage correction circuit	November, 2000	Ogura	365/203
6160423	High speed source synchronous signaling for interfacing VLSI CMOS circuits to transmission lines	December, 2000	Haq	327/41
6173432	Method and apparatus for generating a sequence of clock signals	January, 2001	Harrison	716/1
6253360	Timing generator	June, 2001	Yoshiba	716/6
6262921	Delay-locked loop with binary-coupled capacitor	July, 2001	Manning	365/194
6269451	Method and apparatus for adjusting data timing by delaying clock signal	July, 2001	Mullarkey	713/401
6285726	10/100 mb clock recovery architecture for switches, repeaters and multi-physical layer ports	September, 2001	Gaudet	375/376
6295328	Frequency multiplier using delayed lock loop (DLL)	September, 2001	Kim et al.	375/376
6298450	Detecting states of signals	October, 2001	Liu et al.	713/502
6327196	Synchronous memory device having an adjustable data clocking circuit	December, 2001	Mullarkey	365/194
6338127	Method and apparatus for resynchronizing a plurality of clock signals used to latch respective digital signals, and memory device using same	January, 2002	Manning	711/167
6378079	Computer system having memory device with adjustable data clocking	April, 2002	Mullarkey	713/401
6438043	Adjustable I/O timing from externally applied voltage	August, 2002	Gans et al.	365/194
6442644	Memory system having synchronous-link DRAM (SLDRAM) devices and controller	August, 2002	Gustavson et al.	711/105
6484244	Method and system for storing and processing multiple memory commands	November, 2002	Manning	711/154
6499111	Apparatus for adjusting delay of a clock signal relative to a data signal	December, 2002	Mullarkey	713/401
6580531	Method and apparatus for in circuit biasing and testing of a modulated laser and optical receiver in a wavelength division multiplexing optical transceiver board	June, 2003	Swanson et al.	359/110
6665222	Synchronous dynamic random access memory device	December, 2003	Wright et al.	365/203
6694496	Flexible preamble processing for detecting a code sequence	February, 2004	Goslin et al.	716/4

EP0171720	February, 1986			Data delay/memory circuit
EP0295515	December, 1988			Signal generating apparatus.
EP0406786	January, 1991			Device for transforming a type "D" flip-flop into a flip-flop called type "B" able to sample data both on leading and trailing edges of the clock signal.
EP0450871	October, 1991			Interfaces for transmission lines.
EP0476585	March, 1992			Reference delay generator and electronic device using the same.
EP0655741	May, 1995			Memory device and serial-parallel data transform circuit.
EP0655834	May, 1995			Delay circuit using capacitor and transistor
EP0680049	November, 1995			Synchronizer
EP0703663	March, 1996			Programmable digital delay unit
EP0704848	April, 1996			Semiconductor pipeline memory device eliminating time loss due to difference between pipeline stages from data access
EP0704975	April, 1996			Digital phase locked loop having coarse and fine stepsize variable delay lines
EP0767538	April, 1997			Method and device for generating a signal
JP61237512	October, 1986			SEMICONDUCTOR INTEGRATED CIRCUIT
JP2112317	April, 1990
JP4135311	May, 1992
JP5136664	June, 1993
JP5282868	October, 1993
JP07319577	December, 1995			AUTOMATIC CLOCK PHASE ADJUSTING SYSTEM AND DUPLEX DATA PROCESSOR WITH AUTOMATIC CLOCK PHASE ADJUSTING FUNCTION
WO/1994/029871	December, 1994			METHOD AND APPARATUS FOR WRITING TO MEMORY COMPONENTS
WO/1995/022200	August, 1995			VOLTAGE CONTROLLED PHASE SHIFTER WITH UNLIMITED RANGE
WO/1995/022206	August, 1995			DELAY-LOCKED LOOP
WO/1996/010866	April, 1996			CMOS DYNAMIC LATCHING INPUT BUFFER CIRCUIT
WO/1997/014289	April, 1997			PROTOCOL FOR COMMUNICATION WITH DYNAMIC MEMORY
WO/1997/042557	November, 1997			ASYNCHRONOUS REQUEST/SYNCHRONOUS DATA DYNAMIC RANDOM ACCESS MEMORY

Alvarez, J. et al. “A Wide-Bandwidth Low Voltage PLL for PowerPC™ Microprocessors” IEEE IEICE Trans. Electron., vol. E-78. No. 6, Jun. 1995, pp. 631-639.
Anonymous, “Draft Standard for a High-Speed Memory Interface (SyncLink)”, Microprocessor and Microcomputer Standards Subcommittee of the IEEE Computer Society, Copyright 1996 by the Institute of Electrical and Electronics Engineers, Inc., New York, NY, pp. 1-56.
Anonymous, “Programmable Pulse Generator”, IBM Technical Disclosure Bulletin, vol. 17, No. 12, May 1975, pp. 3553-3554.
Arai, Y. et al., “A Time Digitizer CMOS Gate-Array with a 250 ps Time Resolution”, XP 000597207, IEEE Journal of Solid-State Circuits, vol. 31, No. 2, Feb. 1996, pp. 212-220.
Anonymous, “Pulse Combining Network”, IBM Technical Disclosure Bulletin, vol. 32, No. 12, May 1990, pp. 149-151.
Anonymous, “Variable Delay Digital Circuit”, IBM Technical Disclosure Bulletin, vol. 35, No. 4A, Sep. 1992, pp. 365-366.
Arai, Y. et al., “A CMOS Four Channel x 1K Time Memory LSI with 1-ns/b Resolution”, IEEE Journal of Solid-State Circuits, vol. 27, No. 3, M, 8107 Mar. 1992, No. 3, New York, US, pp. 59-364 and pp. 528-531.
Aviram, A. et al., “Obtaining High Speed Printing on Thermal Sensitive Special Paper With a Resistive Ribbon Print Head”, IBM Technical Disclosure Bulletin, vol. 27, No. 5, Oct. 1984, pp. 3059-3060.
Bazes, M., “Two Novel Fully Complementary Self-Biased CMOS Differential Amplifiers”, IEEE Journal of Solid-State Circuits, vol. 26, No. 2, Feb. 1991, pp. 165-168.
Chapman, J. et al., “A Low-Cost High-Performance CMOS Timing Vernier for ATE”, IEEE International Test Conference, Paper 21.2, 1995, pp. 459-468.
Christiansen, J., “An Integrated High Resolution CMOS Timing Generator Based on an Array of Delay Locked Loops”, IEEE Journal of Solid-State Circuits, vol. 31, No. 7, Jul. 1996, pp. 952-957.
Combes, M. et al., “A Portable Clock Multiplier Generator Using Digital CMOS Standard Cells”, IEEE Journal of Solid-State Circuits, vol. 31, No. 7, Jul. 1996, pp. 958-965.
Donnelly, K. et al., “A 660 MB/s Interface Megacell Portable Circuit in 0.3 μm-0.7 μm CMOS ASIC”, IEEE Journal of Solid-State Circuits, vol. 31, No. 12, Dec. 1996, pp. 1995-2001.
Goto, J. et al., “A PLL-Based Programmable Clock Generator with 50- to 350-MHz Oscillating Range for Video Signal Processors”, IEICE Trans. Electron., vol. E77-C, No. 12, Dec. 1994, pp. 1951-1956.
Gustavsion, David B., et al., “IEEE Standard for Scalable Coherent Interface (SCI),” IEEE Computer Society, IEEE Std. 1596-1992, Aug. 2, 1993.
Hamamoto, T., “400-MHz Random Column Operating SDRAM Techniques with Self-Skew Compensation”, IEEE Journal of Solid-State Circuits, vol. 33, No. 5, May 1998, pp. 770-778.
Kikuchi, S. et al., “A Gate-Array-Based 666Mhz VLSI Test System”, IEEE International Test Conference, Paper 21.1, 1995, pp. 451-458.
Ko, U. et al., “A 30-ps Jitter, 3.6-μs Locking, 3.3-Volt Digital PLL for CMOS Gate Arrays”, IEEE Custom Integrated Circuits Conference, 1993, pp. 23.3.1-23.3.4.
Lee, T. et al., “A 2.5V Delay-Locked Loop for an 18Mb 500MB/s DRAM”, IEEE International Solid-State Circuits Conference Digest of Technical Papers, Paper No. FA 18.6, 1994, pp. 300-301.
Lesmeister, G., “A Densely Integrated High Performance CMOS Tester”, International Test Conference, Paper 16.2, 1991, pp. 426-429.
Ljuslin, C. et al., “An Integrated 16-channel CMOS Time to Digital Converter”, IEEE Nuclear Science Symposium & Medical Imaging Conference Record, vol. 1, 1993, pp. 625-629.
Maneatis, J., “Low-Jitter Process-Independent DLL and PLL Based on Self-Biased Techniques”, IEEE Journal of Solid-State Circuits, vol. 31, No. 11, Nov. 1996, pp. 1723-1732.
Nakamura, M. et al., “A 156 Mbps CMOS Clock Recovery Circuit for Burst-mode Transmission”, Symposium on VLSI Circuits Digest of Technical Papers, 1996, pp. 122-123.
Novof, I. et al., “Fully Integrated CMOS Phase-Locked Loop with 15 to 240 MHz Locking Range and ±50 ps Jitter”, IEEE Journal of Solid-State Circuits, vol. 30, No. 11, Nov. 1995, pp. 1259-1266.
Park, D. et al., “Fast Acquistion Frequency Synthesizer with the Multiple Phase Detectors”, IEEE Pacific Rim Conference on Communications, Computers and Signal Processing, vol. 2, May 1991. pp. 665-668.
Saeki, T. et al., “A 2.5-ns Clock Access, 250-MHz, 256-Mb SDRAM with Synchronous Mirror Delay”, IEEE Journal of Solid-State Circuits, vol. 31, No. 11, Nov. 1996, pp. 1656-1665.
Santos, D. et al., “A CMOS Delay Locked Loop and Sub-Nanosecond Time-to-Digital Converter Chip”, IEEE Nuclear Science Symposium and Medical Imaging Conference Record, vol. 1, Oct. 1995, pp. 289-291.
Shirotori, T. et al., “PLL-based, Impedance Controlled Output Buffer”, 1991 Symposium on VLSI Circuits Digest of Technical Papers, pp. 49-50.
Sidiropoulos, S. et al., “A CMOS 500 Mbps/pin synchronous point to point link interface”, IEEE Symposium on VLSI Circuits Digest of Technical Papers, 1994, pp. 43-44.
Sidiropoulos, S. et al., “A Semi-Digital DLL with Unlimited Phase Shift Capability and 0.08-400MHz Operating Range,” IEEE International Solid State Circuits Conference, Feb. 8, 1997, pp. 332-333.
Soyuer, M. et al., “A Fully Monolithic 1.25GHz CMOS Frequency Synthesizer”, IEEE Symposium on VLSI Circuits Digest of Technical Papers, 1994, pp. 127-128.
Taguchi, M. et al., “A 40-ns 64-Mb DRAM with 64-b Parallel Data Bus Architecture”, IEEE Journal of Solid-State Circuits, vol. 26, No. 11, Nov. 1991, pp. 1493-1497.
Tanoi, S. et al., “A 250-622 MHz Deskew and Jitter-Suppressed Clock Buffer Using a Frequency- and Delay-Locked Two-Loop Architecture”, 1995 Symposium on VLSI Circuits Digest of Technical Papers, vol. 11, No. 2, pp. 85-86.
Tanoi, S. et. al., “A 250-622 MHz Deskew and Jitter-Suppressed Clock Buffer Using Two-Loop Architecture”, IEEE IEICE Trans. Electron., vol. E-79-C. No. 7, Jul. 1996, pp. 898-904.
von Kaenel, V. et al., “A 320 MHz, 1.5 mW @ 1.35 V CMOS PLL for Microprocessor Clock Generation”, IEEE Journal of Solid-State Circuits, vol. 31, No. 11, Nov. 1996, pp. 1715-1722.
Watson, R. et al., “Clock Buffer Chip with Absolute Delay Regulation Over Process and Environmental Variations”, IEEE Custom Integrated Circuits Conference, 1992, pp. 25.2.1-25.2.5.
Yoshimura, T. et al. “A 622-Mb/s Bit/Frame Synchronizer for High-Speed Backplane Data Communication”, IEEE Journal of Solid-State Circuits, vol. 31, No. 7, Jul. 1996, pp. 1063-1066.
Anonymous, “400Mhz SLDRAM, 4M x 16 SLDRAM Pipelined, Eight Bank, 2.5 V Operation,” SLDRAM Consortium Advance Sheet, published throughout the United States, Jan. 1997, pp. 1-22.
Kim, B. et al., “A 30MHz High-Speed Analog/Digital PLL in 2μm CMOS”, ISSCC, Feb. 1990, Two Pages.
Nielson, E., “Inverting latches make simple VCO”, EDN, Jun. 19, 1997, Five Pages.
Ishibashi, A. et al., “High-Speed Clock Distribution Architecture Employing PLL for 0.6μm CMOS SOG”, IEEE Custom Integrated Circuits Conference, 1992, pp. 27.6.1-27.6.4.
Sidiropoulos, S. et al., “A 700-Mb/s/pin CMOS Signaling Interface Using Current Integrating Receivers”, IEEE Journal of Solid-State Circuits, vol. 32, No. 5, May 1997, pp. 681-690.

Jones, Hugh

Dorsey & Whitney LLP

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a continuation of U.S. patent application Ser. No. 09/758,970, filed Jan. 9, 2001, now U.S. Pat. No. 6,954,097 which is a continuation of U.S. patent application Ser. No. 08/879,847, filed Jun. 20, 1997, issued Jan. 9, 2001 as U.S. Pat. No. 6,173,432 B1.

The invention claimed is:

1. A clock circuit for generating a sequence of clock signals, comprising: a first delay locked loop having a multi-tap adjustable delay circuit and a phase detector, the multi-tap adjustable delay circuit having an input clock node to receive a reference clock signal and a control node to receive a control signal and configured to generate the sequence of clock signals which are increasingly delayed from a first clock signal to a last clock signal by delaying the reference clock signal by respective delays that are a function of the control signal, the phase detector configured to compare the phase of the first and last clock signals and generate the control signal as a function of a phase relationship therebetween, the phase detector including a charge pump and configured to generate a first signal in response to a first-type of clock edge of the last clock signal lagging a second-type of clock edge of the first clock signal and generate a second signal in response to the first-type of clock edge of the last clock signal leading the second-type of clock edge of the first clock signal, the phase detector further configured to generate as the control signal a voltage that increases toward one polarity responsive to the first signal and toward the opposite polarity responsive to the second signal, the first delay locked loop configured to delay the last clock signal to have a first phase relative to the first clock signal; and a second delay locked loop configured to synchronize the first clock signal to a master clock signal whereby the clock signals in the sequence have different respective phases with respect to the master clock signal.

2. The clock circuit of claim 1 wherein the first delay locked loop is configured to delay the last clock signal to have be 180 degrees out of phase with the first clock signal.

3. The clock circuit of claim 1 wherein the multi-tap adjustable delay circuit is configured to increasingly delay the clock signals in the sequence in equal increments from the first clock signal to the last clock signal to provide adjacent clock signals in the sequence having respective phases that are equally spaced from each other.

4. The clock circuit of claim 1, further comprising a multiplexer configured to select one of the clock signals and provide the same a clock output terminal.

5. The clock circuit of claim 1 wherein the second delay locked loop comprises: a phase detector to compare the phase of the master clock signal to the phase of the last clock signal and generate a control signal as a function of a phase relationship therebetween; an adjustable delay coupled to the phase detector and having an input clock node to receive the master clock signal and further having a control node to receive the control signal, the adjustable delay configured to provide the reference clock signal having a delay relative to the master clock signal that is a function of a control signal.

6. The clock circuit of claim 5 wherein the phase detector includes a charge pump and the phase detector is configured to generate a first signal in response to a first-type of clock edge of the last clock signal lagging a second-type of clock edge of the master clock signal and generate a second signal in response to the first-type of clock edge of the last clock signal leading the second-type of clock edge of the master clock signal, the phase detector further configured to generate as the control signal a voltage that increases toward one polarity responsive to the first signal and toward the opposite polarity responsive to the second signal.

7. A clock circuit for providing a plurality of clock signals that have predetermined phases relative to a master clock signal, the clock circuit comprising: a first adjustable delay configured to provide a reference clock signal having a delay relative to the master clock signal, the first adjustable delay adjusted in accordance with a first control signal; a second adjustable delay configured to provide a plurality of clock signals having different respective delays relative to the reference clock signal, the second adjustable delay adjusted in accordance with a second control signal; a first phase detector coupled to the first adjustable delay and configured to compare the master clock signal and a first one of the plurality of clock signals and generate an enable signal in response to a variance from a first phase relationship due to a greater delay than needed to provide the first phase relationship, the first phase detector further configured to generate as the first control signal a voltage that increases toward one polarity responsive to the enable signal and toward the opposite polarity responsive to the absence of the enable signal; and a second phase detector coupled to the second adjustable delay and configured to compare the first one of the plurality of clock signals and a second one of the plurality of clock signals and generate the second control signal based on a variance from a second phase relationship.

8. The clock circuit of claim 7 wherein the first and second phase relationships are the same.

9. The clock circuit of claim 8 wherein the first and second phase relationships are 180 degrees out of phase.

10. The clock circuit of claim 7 wherein the first and second phase relationships provide that the second one of the plurality of clock signals and the master clock signal are in phase.

11. The clock circuit of claim 7 wherein the reference clock signal having a phase relative to the master clock signal is one of the plurality of clock signals produced.

12. The clock circuit of claim 7 wherein the second phase detector is configured to generate an enable signal in response to the variance from the second phase relationship due to a greater delay than needed to provided the second phase relationship and further configured to generate as the second control signal a voltage that increases toward one polarity responsive to the enable signal and toward the opposite polarity responsive to the absence of the enable signal.

13. The clock circuit of claim 7 wherein the second adjustable delay is configured to provide N clock signals, the phase of each of the clock signals relative to the phase of the master clock signal is [M/N]*180 degrees, where M=0, 1, . . . N.

14. The clock circuit of claim 7, further comprising a multiplexer configured to select one of the plurality of clock signals and couple the selected clock signal to a clock output terminal.

15. A clock circuit for providing a plurality of clock signals that have predetermined phases relative to a master clock signal, the clock circuit comprising: a first adjustable delay configured to provide a reference clock signal having a delay relative to the master clock signal, the first adjustable delay adjusted in accordance with a first control signal; a second adjustable delay configured to provide a plurality of clock signals having different respective delays relative to the reference clock signal, the second adjustable delay adjusted in accordance with a second control signal; a first phase detector coupled to the first adjustable delay and configured to compare the master clock signal and a first one of the plurality of clock signals and generate a variance from a first phase relationship; and a second phase detector coupled to the second adjustable delay and configured to compare the first one of the plurality of clock signals and a second one of the plurality of clock signals and generate an enable signal in response to the variance from the second phase relationship due to a greater delay than needed to provided the second phase relationship, the second phase detector further configured to generate as the second control signal a voltage that increases toward one polarity responsive to the enable signal and toward the opposite polarity responsive to the absence of the enable signal.

16. The clock circuit of claim 15 wherein the first and second phase relationships are the same.

17. The clock circuit of claim 16 wherein the first and second phase relationships are 180 degrees out of phase.

18. The clock circuit of claim 15 wherein the first and second phase relationships provide that the second one of the plurality of clock signals and the master clock signal are in phase.

19. The clock circuit of claim 15 wherein the reference clock signal having a phase relative to the master clock signal is one of the plurality of clock signals produced.

20. The clock circuit of claim 15 wherein the second adjustable delay is configured to provide N clock signals, the phase of each of the clock signals relative to the phase of the master clock signal is [M/N]*180 degrees, where M=0, 1, . . . N.

21. The clock circuit of claim 15, further comprising a multiplexer configured to select one of the plurality of clock signals and couple the selected clock signal to a clock output terminal.

TECHNICAL FIELD

This invention relates to generating a sequence of accurately phased clock signals, and more particularly, to using delay and phase locked loops to provide a sequence of clock signals that are accurately phased relative to a master clock signal.

BACKGROUND OF THE INVENTION

Clock signals are used by a wide variety of digital circuits to control the timing of various events occurring during the operation of the digital circuits. For example, clock signals are used to designate when commands and other signals used in computer systems are valid and can thus be used to control the operation of the computer system. A clock signal can then be used to latch the command or other signals so that they can be used after the command or other signals are no longer valid.

The problem of accurately controlling the timing of clock signals for high speed digital circuits is exemplified by clock signals used in high speed dynamic random access memories (“DRAMs”) although the problem is, of course, also applicable to other digital circuits. Initially, DRAMs were asynchronous and thus did not operate at the speed of an external clock. However, since asynchronous DRAMs often operated significantly slower than the clock frequency of processors that interfaced with the DRAM, “wait states” were often required to halt the processor until the DRAM had completed a memory transfer. The operating speed of asynchronous DRAMs was successfully increased through such innovations as burst and page mode DRAMs which did not require that an address be provided to the DRAM for each memory access. More recently, synchronous dynamic random access memories (“SDRAMs”) have been developed to allow the pipelined transfer of data at the clock speed of the motherboard. However, even SDRAMs are incapable of operating at the clock speed of currently available processors. Thus, SDRAMs cannot be connected directly to the processor bus, but instead must interface with the processor bus through a memory controller, bus bridge, or similar device. The disparity between the operating speed of the processor and the operating speed of SDRAMs continues to limit the speed at which processors may complete operations requiring access to system memory.

A solution to this operating speed disparity has been proposed in the form of a computer architecture known as “SyncLink.” In the SyncLink architecture, the system memory is coupled to the processor directly through the processor bus. Rather than requiring that separate address and control signals be provided to the system memory, SyncLink memory devices receive command packets that include both control and address information. The SyncLink memory device then outputs or receives data on a data bus that is coupled directly to the data bus portion of the processor bus.

An example of a packetized memory device using the SyncLink architecture is shown in FIG. 1. The SyncLink memory device 10 includes a clock divider and delay circuit 40 that receives a master or command clock signal on line 42 and generates a large number of other clock and timing signals to control the timing of various operations in the memory device 10. The memory device 10 also includes a command buffer 46 and an address capture circuit 48 which receive an internal clock signal ICLK, a command packet CA0-CA9 on a command bus 50, and a FLAG signal on line 52. As explained above, the command packet contains control and address data for each memory transfer, and the FLAG signal identifies the start of a command packet which may include more than one 10-bit packet word. In fact, a command packet is generally in the form of a sequence of 10-bit packet words on the 10-bit command bus 50. The command buffer 46 receives the command packet from the bus 50, and compares at least a portion of the command packet to identifying data from an ID register 56 to determine if the command packet is directed to the memory device 10 or some other memory device 10 in a computer system. If the command buffer determines that the command is directed to the memory device 10, it then provides a command word to a command decoder and sequencer 60. The command decoder and sequencer 60 generates a large number of internal control signals to control the operation of the memory device 10 during a memory transfer.

The address capture circuit 48 also receives the command words from the command bus 50 and outputs a 20-bit address corresponding to the address data in the command. The address is provided to an address sequencer 64 which generates a corresponding 3-bit bank address on bus 66, a 10-bit row address on bus 68, and a 7-bit column address on bus 70.

One of the problems of conventional DRAMs is their relatively low speed resulting from the time required to precharge and equilibrate circuitry in the DRAM array. The packetized memory device 10 shown in FIG. 1 largely avoids this problem by using a plurality of memory banks 80, in this case eight memory banks 80a-h. After a memory read from one bank 80a, the bank 80a can be precharged while the remaining banks 80b-h are being accessed. Each of the memory banks 80a-h receive a row address from a respective row latch/decoder/driver 82a-h. All of the row latch/decoder/drivers 82a-h receive the same row address from a predecoder 84 which, in turn, receives a row address from either a row address register 86 or a refresh counter 88 as determined by a multiplexer 90. However, only one of the row latch/decoder/drivers 82a-h is active at any one time as determined by bank control logic 94 as a function of bank data from a bank address register 96.

The column address on bus 70 is applied to a column latch/decoder 100 which, in turn, supplies I/O gating signals to an I/O gating circuit 102. The I/O gating circuit 102 interfaces with columns of the memory banks 80a-h through sense amplifiers 104. Data is coupled to or from the memory banks 80a-h through the sense amplifiers 104 and I/O gating circuit 102 to a data path subsystem 108 which includes a read data path 110 and a write data path 112. The read data path 110 includes a read latch 120 receiving and storing data from the I/O gating circuit 102. In the memory device 10 shown in FIG. 1, 64 bits of data are applied to and stored in the read latch 120. The read latch then provides four 16-bit data words to a multiplexer 122. The multiplexer 122 sequentially applies each of the 16-bit data words to a read FIFO buffer 124. Successive 16-bit data words are clocked through the FIFO buffer 124 by a clock signal generated from an internal clock by a programmable delay circuit 126. The FIFO buffer 124 sequentially applies the 16-bit words and two clock signals (a clock signal and a quadrature clock signal) to a driver circuit 128 which, in turn, applies the 16-bit data words to a data bus 130. The driver circuit 128 also applies the clock signals to a clock bus 132 so that a device, such as a processor, reading the data on the data bus 130 can be synchronized with the data.

The write data path 112 includes a receiver buffer 140 coupled to the data bus 130. The receiver buffer 140 sequentially applies 16-bit words from the data bus 130 to four input registers 142, each of which is selectively enabled by a signal from a clock generator circuit 144. Thus, the input registers 142 sequentially store four 16-bit data words and combine them into one 64-bit data word applied to a write FIFO buffer 148. The write FIFO buffer 148 is clocked by a signal from the clock generator 144 and an internal write clock WCLK to sequentially apply 64-bit write data to a write latch and driver 150. The write latch and driver 150 applies the 64-bit write data to one of the memory banks 80a-h through the I/O gating circuit 102 and the sense amplifier 104.

As mentioned above, an important goal of the SyncLink architecture is to allow data transfer between a processor and a memory device to occur at a significantly faster rate. However, the operating rate of a packetized DRAM, including the packetized memory device 10 shown in FIG. 1, is limited by the time required to receive and process command packets applied to the memory device 10. More specifically, not only must the command packets be received and stored, but they must also be decoded and used to generate a wide variety of signals. However, in order for the memory device 10 to operate at a very high speed, the command packets must be applied to the memory device 10 at a correspondingly high speed. As the operating speed of the memory device 10 increases, the command packets are provided to the memory device 10 at a rate that can exceed the rate at which the command buffer 46 can process or even store the command packets.

One of the limiting factors in the speed at which the command buffer 46 can store and process the command packets is control of the relative timing between the command packets and the clock signal ICLK. Both the command data signals and the ICLK signal are delayed relative to receipt of the command packet on the command bus 50 and the master clock signal on line 42. Furthermore, the amount of the delay is highly variable, and it is difficult to control. If the delay of the internal clock signal ICLK cannot be precisely controlled, it may cause the latch in the command buffer 48 to latch invalid command data signals. Thus, the speed at which command packets can be applied to the memory device 10 is limited by the delays in the memory device 10. Similar problems exist for other control signals in the memory device 10 which control the operation of the memory device 10 during each clock cycle.

Although the foregoing discussion is directed to the need for faster command buffers in packetized DRAMs, similar problems exist in other memory devices, such as asynchronous DRAMs and synchronous DRAMs, which must process control and other signals at a high rate of speed. Thus, for the reasons explained above, the limited operating speed of conventional command buffers threatens to severely limit the maximum operating speed of memory devices, particularly packetized DRAMs. Therefore, there is a need to precisely control the timing of clock signals relative to other signals, such as command packets applied to a command buffer in a packetized DRAM.

SUMMARY OF THE INVENTION

In one aspect of the invention, a clock circuit having first and second delay locked loops generates a sequence of clock signals. The first delay locked loop is configured to delay a reference clock signal to have a first phase relationship relative to a master clock signal and the second delay locked loop is configured to delay a plurality of clock signals relative to the reference clock signal. The plurality of clock signals have different respective phases relative to the phase of the reference clock signal.

In another aspect of the invention a clock circuit having first and second delay locked loops generates a sequence of clock signals. The first delay locked loop has a multi-tap adjustable delay circuit configured to generate the sequence of clock signals which are increasingly delayed from a first clock signal to a last clock signal. The first delay locked loop is configured to delay the last clock signal to have a first phase relative to the first clock signal. The second delay locked loop is configured to synchronize the first clock signal to a master clock signal whereby the clock signals in the sequence have different respective phases with respect to the master clock signal.

In another aspect of the invention a clock circuit provides a plurality of clock signals that have predetermined phases relative to a master clock signal. The clock circuit includes first and second adjustable delays and first and second phase detectors. The first adjustable delay, which is adjusted in accordance with a first control signal, is configured to provide a reference clock signal having a delay relative to the master clock signal. The second adjustable delay, which is adjusted in accordance with a second control signal, is configured to provide a plurality of clock signals having different respective delays relative to the reference clock signal. The first phase detector is coupled to the first adjustable delay and is configured to compare the master clock signal and a first one of the plurality of clock signals and generate the first control signal based on a variance from a first phase relationship. The second phase detector is coupled to the second adjustable delay and is configured to compare the first one of the plurality of clock signals and a second one of the plurality of clock signals and generate the second control signal based on a variance from a second phase relationship.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram of a conventional packetized dynamic random access memory (“DRAM”) that may use a clock generator in accordance with an embodiment of the present invention.

FIG. 2 is a block diagram illustrating the manner in which an embodiment of clock generator in accordance with present invention may be used in a command latch in the packetized DRAM of FIG. 1.

FIG. 3 is a more detailed block diagram and logic diagram of the command latch of FIG. 2 using an embodiment of a clock generator in accordance with present invention.

FIG. 4 is a timing diagram showing many of the waveforms present in the command latch of FIG. 3.

FIG. 5 is a block diagram of a computer system using a plurality of DRAMs, each of which include the command latch of FIG. 3.

DETAILED DESCRIPTION OF THE INVENTION

One embodiment of a command latch 200 using an embodiment of a clock generator 210 in accordance with present invention is illustrated in FIG. 2. The command latch 200 also includes a latch circuit 212 receiving a command data bit CMD DATA from a command packet on a line of the command bus 50. The clock generator 210 receives a master or command clock signal CMD CLK on line 42 and generates the internal clock signal ICLK which is applied to the clock input of the latch circuit 212. The output of the latch circuit 212 is coupled to a variety of circuits in the memory device 10, including a select circuit 214. As explained below, the clock generator 210 produces a sequence of clock signals each having an increased delay relative to the leading edge of the master clock. One of the clock signals in the sequence is selected for use as the internal clock signal ICLK for clocking the latch circuit 212. The clock signal in the sequence for use as ICLK is selected by a multi-bit select word SELECT generated by the select circuit 214. Basically, the select circuit 214 determines which of the clock signals in the sequence has the proper timing to match the delay of the command data from the command bus 50 to the input of the latch circuit 212. The select circuit 214 then applies an appropriate SELECT word to the clock generator 210 to use the selected clock signal in the sequence as the internal clock signal ICLK.

A variety of designs may be used for the select circuit 214, as will be apparent to one skilled in the art. For example, a plurality of very short logic “1” pulses may be applied to the command bus line 50 in synchronism with the command clock signal CMD CLK. The select circuit 214 can then select each of the clock signals in the sequence and determine which clock signal(s) are able to capture the logic “1” pulses. If several clock signals are successful in capturing the logic “1” pulses, then the clock signal occurring midway between the successful clock signals can be used as the internal clock signal ICLK.

The command latch 200, including one embodiment of a clock generator 210 in accordance with the present invention, is shown in greater detail in FIG. 3. The latch 212 is illustrated in FIG. 3 as consisting of a receiver buffer 240 receiving a respective one of 10 bits of the command data CMD DATA. The output of the receiver buffer 240 is applied to the data input D of a latch circuit 242. The latch circuit 242 latches or stores the logic level applied to its D input whenever a clock signal applied to its clock C input goes high. The stored logic level is then continuously applied to the output of the latch circuit 242. Although a single receiver buffer 240 and latch circuit 242 are shown in FIG. 3, it will be understood that there are actually 10 receiver buffers 240 and latch circuits 242 to store the 10 bits of the command data on the command bus 50.

As explained above, it is very difficult to clock the latch circuit 242 at the proper time at the maximum speed of the command latch 200 because delays of the CMD DATA from the command bus 50 to the latch circuit 242 may not be equal to delays of the CMD CLK from the line 42 to the clock input of the latch circuit 242. Also, of course, unequal delays external to an integrated circuit containing the command latch 200 may cause the CMD CLK and the CMD DATA to be applied to the integrated circuit at different times. The function of the clock generator 210 is to provide an internal clock signal ICLK to the clock input of the latch circuit 242 that is capable of storing a command data bit at even the fastest operating speed of the command latch 200 despite any unequal internal or external delays that would cause the command bit and ICLK to be coupled to the latch circuit 242 at different times. However, it will be understood that the clock generator 210 may be used for other purposes both in dynamic random access memories and in other circuits.

The master or command clock CMD CLK is coupled from line 42 through a receiver buffer 250 substantially identical to the receiver buffer 240 coupling a command data bit to the latch circuit 242. The output of the receiver buffer 250 is applied to a conventional voltage controlled delay circuit 252 and to one input of a phase detector 254. The voltage controlled delay circuit 252 couples the output of the receiver buffer 250 to an output line 256 with a delay that is a function of a control signal applied to the delay circuit 252 on line 258. Although the control signal on line 258 is an analog voltage, it will be understood that other types of control signals, including digital words, may alternatively be used. The output of the voltage controlled delay circuit 252 is applied to a multi-tap voltage controlled delay line 260.

The multi-tap voltage controlled delay line 260 couples the clock signal applied to its input on line 256 to a plurality of output lines 264a-264n. The incoming clock signal is coupled to the output lines 264 with an increasing delay from the first line 264a to the last line 264n. In the embodiment illustrated in FIG. 3, there are 17 output lines 264, but the delay line 260 may have a greater or lesser number of output lines 264. When a delay locked loop that includes the delay line 260 is locked as explained below, the signals at the first output line 264a and the last or 17th output line 264n are the inverse of each other, i.e., phased 180 degrees from each other. Thus, the signals on the 17 lines are delayed by 11.25 degrees more than the signal coupled to the previous line 264. Thus, the first line 264a has a relative phase of zero degrees, the 16th line 264n-1 has a phase of 168.75 degrees and the last line 264n has a phase of 180 degrees. More specifically, a control voltage applied to the delay line 260 through line 270 is adjusted so that the phase of the signal on the last line 264n relative to the phase on the first line 264a is 180 degrees. This is accomplished by applying the first line 264a and the last line 264n to respective inputs of a phase detector 272.

As mentioned above, the delay line 260 and phase detector 272 implement a first delay locked loop. When the first delay locked loop is locked, the signal on line 264n will have a phase relative to the phase of the signal on line 264a of 180 degrees. Therefore, as mentioned above, the signal on each of the output lines 264a-264n will sequentially increase from zero degrees to 180 degrees. Although the signals on lines 264a-n are equally phased apart from each other, it will be understood that equal phasing is not required.

The clock generator 210 also includes a second delay locked loop formed by the phase detector 254, the voltage controlled delay circuit 252 and the voltage controlled delay line 260. More particularly, the last output line 264n of the delay line 260 is applied through a simulated multiplexer circuit 290 and a clock driver 292 to one input of the phase detector 254. It will be recalled that the other input of the phase detector 254 receives the output of the receiver buffer 250. Like the phase detector 272, when the second delay locked loop is locked, the signals applied to the phase detector 254 are the inverse of each other. Thus, when the second loop is locked, the phase of the signal at the output of the clock driver 292 is 540 degrees (effectively 180 degrees) relative to the phase of the signal at the output of the receiver buffer 250.

The remaining output lines 264a-264n-1 of the delay line 260 are coupled to a multiplexer 310 having a plurality of output lines coupled to respective clock drivers 312a-n. The multiplexer 310 couples the input of each of the clock drivers 312a-n to any one of the output lines 264a-264n-1 as determined by respective select words SELECT. The clock driver 312a is used to generate the internal clock signal ICLK which is coupled to the clock input of the latch circuit 242. The other clock drivers 312b-n are used to couple various clock outputs from the delay line to other circuits in the memory device (not shown).

The phase detectors 254, 272 are each implemented using to a phase detector circuit 330, a charge pump 332 and a capacitor 334. However, other varieties of phase detectors may alternatively be used.

The phase detector circuit 330 applies either an increase signal on line 336 or a decrease signal on line 338 to respective inputs of the charge pump 332. The phase detector circuit 330 generates the increase signal on line 336 whenever the phase of a first signal on one of its inputs relative to a second signal on the other of its inputs is less than 180 degrees. As explained below, the increase signal on line 336 causes the charge pump 332 to adjust the control voltage to increase the delay of the first signal so that the phase of the first signal relative to the phase of the second signal approaches 180 degrees. The phase detector circuit 330 generates the decrease signal on line 338, in the opposite condition, i.e., when the phase of the second signal relative to the first signal is greater than 180 degrees. The decrease signal on line 338 causes the charge pump 332 to adjust the control voltage to reduce the delay of second signal toward 180 degrees.

Although the phase detector circuit 330 may be implemented in a variety of ways, it may simply use two set-reset flip-flops (not shown) for generating the increase and decrease signals, respectively. The increase flip-flop is set by the rising edge of the first signal on one of the inputs and reset by the falling edge of the second signal on the other input. Thus, the duration that the flip-flop is set, and hence the duration of the increase signal on line 336, corresponds to the period of time that the second signal must be further delayed to have a phase of 180 degrees relative to the phase of the first signal. Similarly, the flip-flop producing the decrease signal on line 338 is set by the falling edge of the second signal and reset by the rising edge of the first signal so that the duration of the decrease signal on line 338 corresponds to the time that the second signal is delayed beyond the time that it would have a phase of 180 degrees relative to the phase of the first signal.

There are also a variety of approaches for implementing the charge pump 332. However, the charge pump 332 can be implemented by simply applying a constant current to the capacitor 334 for the duration of each increase signal on line 336 and removing a constant current from the capacitor 334 for the duration of each decrease signal on line 338. Appropriate circuitry could also be included in either the phase detector circuit 330 or the charge pump 332 to provide hysteresis in a band when the first and second signals have relative phases of approximately 180 degrees from each other as will be apparent to one skilled in the art. The operation of the command latch 200 of FIG. 3 can best be explained with reference to the timing diagram of FIG. 4. As illustrated in FIG. 4, the command clock signal CMD CLK on line 42 is delayed by approximately 70 degrees in passing through the receiver buffer 250 to node A (FIG. 3). Assuming that both of the delay-lock loops are locked, the signal at the output of the receiver buffer 250 is delayed by 120 degrees in passing through the voltage controlled delay circuit 252 to node B. The signal on node B is then coupled to node C with a delay of another 120 degrees and to node D with a delay of 300 degrees so that the signals at nodes C and D are phased 180 degrees apart from each other. Since the signals at nodes C and D are compared to each other by the phase detector 272, the phase detector 272 adjusts the control voltage on line 270 to ensure that the signals at nodes C and D are phased 180 degrees from each other. The other outputs from the delay line 260 have phases relative to the phase of the signal at node C that increase 11.25 degrees for each output in sequence from the first line 264a to the last line 264n.

As mentioned above, one of the first 16 output lines 264a-264n-1 of the delay lines 260 is coupled through the multiplexer 310 and the clock driver 312a to provide the internal clock signal ICLK at node E. In passing through the multiplexer 310 and the clock driver 312a, the selected output from the delay line is delayed by another 120 degrees. Thus, the signal Eo coupled from the first output line of the delay line 260 is delayed by 120 degrees, the signal E4 from the fifth output is delayed by 165 degrees, the signal E8 from the ninth output is delayed by 210 degrees, the signal E12 from the 13th output is delayed by 255 degrees, and the signal E15 from the 16th output is delayed by 288.75 degrees. Although the output signals are coupled from the delay line 260 through the multiplexer 310 and clock driver 312a with a delay, that delay is matched by the coupling of the signal from line 264n through the simulated multiplexer 290 and clock driver 292 since the same circuit is used for the simulated multiplexer 290 as the multiplexer 310 and the clock driver 292 is identical to the clock driver 312a. For this reason, and because the phase of the signal on line 264n is 180 degrees relative to the phase of the signal on line 264a, the signal at the output of the clock driver 292 at node G has a phase relative to the phase of the signal Eo at the output of the clock 312a of 180 degrees. Since the signals applied to the inputs of the phase detector 254 are the inverse of each other when the delay-locked loop is locked, the signal Eo has substantially the same phase as the signal at the output of the receiver buffer 250. Furthermore, the delay of the voltage controlled delay circuit 252 will be adjusted so that the signal Eo always has the same phase as the command clock coupled to the output of the receiver buffer 250 at A. Assuming the CMD DATA is valid on the rising edge of the CMD CLK signal, the command data bit coupled to the latch circuit 242 is valid on the rising edge of ICLK since ICLK is properly phased to the signal at node A and the delay through the receiver buffer 250 is substantially the same as the delay through the receiver buffer 240.

In operation, the multiplexer 310 selects one of the outputs from the delay line 260 as determined by the SELECT signal so that the optimum clock signal between Eo and E15 (FIG. 4) will be used as the internal clock ICLK.

In summary, the “inner” delay locked loop formed by the phase detector 272 and the voltage controlled delay circuit 260 generates a sequence of signals that have increasing phases from zero to 180 degrees. The “outer” delay locked loop formed by the phase detector 254, the voltage controlled delay circuit 252 and the delay line 260 align one of the clock signals in the sequence to the command clock. As a result, all of the clock signals at the output of the delay line 260 have respective predetermined phases relative to the phase of the command clock at node A.

Although the embodiment of the clock generator 210 illustrated in FIG. 3 uses delay-locked loops, it will be understood that other locked loop circuits, such as phase-locked loop circuits, may also be used. Other modifications will also be apparent to one skilled in the art.

A computer system using the command latch 200 of FIGS. 2 and 3 in each of a plurality of packetized DRAMs 10 of FIG. 1 is shown in FIG. 5. With reference to FIG. 5 the computer system 400 includes a processor 402 having a processor bus 404 coupled to three packetized dynamic random access memory or SyncLink DRAMs (“SLDRAM”) 10a-c. The computer system 400 also includes one or more input devices 4100, such as a keypad or a mouse, coupled to the processor 402 through a bus bridge 412 and an expansion bus 414, such as an industry standard architecture (“ISA”) bus or a Peripheral component interconnect (“PCI”) bus. The input devices 410 allow an operator or an electronic device to input data to the computer system 400. One or more output devices 420 are coupled to the processor 402 to display or otherwise output data generated by the processor 402. The output devices 420 are coupled to the processor 402 through the expansion bus 414, bus bridge 412 and processor bus 404. Examples of output devices 420 include printers and video display units. One or more data storage devices 422 are coupled to the processor 402 through the processor bus 404, bus bridge 412, and expansion bus 414 to store data in or retrieve data from storage media (not shown). Examples of storage devices 422 and storage media include fixed disk drives floppy disk drives, tape cassettes and compact-disk read-only memory drives.

In operation, the processor 402 communicates with the memory devices 10a-c via the processor bus 404 by sending the memory devices 10a-c command packets that contain both control and address information. Data is coupled between the processor 402 and the memory devices 10a-c, through a data bus portion of the processor bus 404. Although all the memory devices 10a-c are coupled to the same conductors of the processor bus 404, only one memory device 10a-c at a time reads or writes data, thus avoiding bus contention on the processor bus 404. Bus contention is avoided by each of the memory devices 10a-c and the bus bridge 412 having a unique identifier, and the command packet contains an identifying code that selects only one of these components.

The computer system 400 also includes a number of other components and signal lines which have been omitted from FIG. 5 in the interests of brevity. For example, as explained above, the memory devices 10a-c also receive a command or master clock signal to provide internal timing signals, a data clock signal clocking data into and out of the memory device 16, and a FLAG signal signifying the start of a command packet.

From the foregoing it will be appreciated that, although specific embodiments of the invention have been described herein for purposes of illustration, various modifications may be made without deviating from the spirit and scope of the invention. Accordingly, the invention is not limited except as by the appended claims.