Title:

Semiconductor component having thinned die with conductive vias configured as conductive pin terminal contacts

Document Type and Number:

United States Patent 7417325

Abstract:

A semiconductor component includes a thinned semiconductor die having protective polymer layers on up to six surfaces. The component also includes contact bumps on the die embedded in a circuit side polymer layer, and terminal contacts on the contact bumps in a dense area array. A method for fabricating the component includes the steps of providing a substrate containing multiple dice, forming trenches on the substrate proximate to peripheral edges of the dice, and depositing a polymer material into the trenches. In addition, the method includes the steps of planarizing the back side of the substrate to contact the polymer filled trenches, and cutting through the polymer trenches to singulate the components from the substrate. Prior to the singulating step the components can be tested and burned-in while they remain on the substrate.

Inventors:

Farnworth, Warren M. (Nampa, ID, US)
Wood, Alan G. (Boise, ID, US)
Doan, Trung Tri (Boise, ID, US)

Plaque It!

CROSS REFERENCE TO RELATED APPLICATIONS

This application is a division of Ser. No. 10/646,897, filed Aug. 22, 2003, which is a division of Ser. No. 10/094,161, filed Mar. 6, 2002, U.S. Pat. No. 6,908,784.

This application is related to Ser. No. 10/719,876, filed Nov. 21, 2003, U.S. Pat. No. 6,964,915, to Ser. No. 10/719,907, filed Nov. 21, 2003, U.S. Pat. No. 7,029,949, to Ser. No. 11/052,378, filed Feb. 7, 2005, U.S. Pat. No. 7,221,059, to Ser. No. 11/050,857, filed Feb. 7, 2005, to Ser. No. 11/146,397, filed Jun. 7, 2005, U.S. Pat. No. 7,157,353, to Ser. No. 11/204,264, filed Aug. 15, 2005, to Ser. No. 11/390,321, filed Mar. 27, 2006, and to Ser. No. 11/496,180, filed Jul. 31, 2006.

Claims:

What is claimed is:

1. A semiconductor component comprising: a thinned semiconductor die comprising a substrate having a plurality of integrated circuits, a circuit side, a back side and a plurality of die contacts on the circuit side in electrical communication with the integrated circuits having openings therein; a polymer layer covering the circuit side having continuous edge polymer layers covering the edges; a plurality of contact bumps in the openings and on the die contacts encapsulated in the polymer layer; a plurality of conductive vias comprising vias in the substrate and conductive members filling the vias in electrical contact with the contact bumps and the die contacts; and a plurality of terminal contacts comprising exposed portions of the conductive members configured as conductive pins projecting from the back side of the die in an area array having a pitch matching that of the die contacts.

2. The semiconductor component of claim 1 wherein the area array comprises a dense grid array.

3. The semiconductor component of claim 1 wherein the conductive pins are arranged in a micro pin grid array on the back side of the die, and the component comprises a chip scale package.

4. The semiconductor component of claim 1 wherein each conductive via comprises a reverse junction bias in the substrate.

5. The semiconductor component of claim 1 further comprising a second polymer layer covering the back side, the second polymer layer and the edge polymer layers encapsulating the die on six surfaces with a chip scale outline.

6. The semiconductor component of claim 1 wherein the component has a chip scale outline and the terminal contacts are arranged in a micro pin grid array having a pitch of about 2 μm.

7. The semiconductor component of claim 1 further comprising non oxidizing layers on the tips of the conductive pins.

8. The semiconductor component of claim 1 wherein the edge polymer layers comprise portions of polymer filled trenches.

9. The semiconductor component of claim 1 further comprising electrically insulating layers in the openings configured to insulate the conductive members from the substrate.

Description:

FIELD OF THE INVENTION

This invention relates generally to semiconductor manufacture and packaging. More particularly, this invention relates to encapsulated semiconductor components, to methods for fabricating the components, and to systems incorporating the components.

BACKGROUND OF THE INVENTION

In semiconductor manufacture, different types of components have been developed recently, that are smaller and have a higher input/output capability than conventional plastic or ceramic packages. For example, one type of semiconductor component is referred to as a chip scale package (CSP) because it has an outline, or “footprint”, that is about the same as the outline of the die contained in the package.

Typically, a chip scale package includes a dense area array of solder bumps, such as a standardized grid array as disclosed in U.S. Pat. No. 6,169,329 to Farnworth et al. The solder bumps permit the package to be flip chip mounted to a substrate, such as a package substrate, a module substrate or a circuit board. Another type of component, referred to as a bumped die, can also include solder bumps in a dense area array. Bumped dice are sometimes considered as the simplest form of a chip scale package. Another type of component, referred to as a BGA device, is also sometimes considered a chip scale package. Yet another type of component as disclosed in U.S. Pat. No. 6,150,717 to Wood et al. is referred to as a direct die contact (DDC) package.

The quality, reliability and cost of these types of components is often dependent on the fabrication method. Preferably a fabrication method is performed on a substrate, such as a semiconductor wafer, containing multiple components, in a manner similar to the wafer level fabrication of semiconductor dice. A wafer level fabrication method permits volume manufacture with low costs, such that the components are commercially viable.

In addition to providing volume manufacture, the fabrication method preferably produces components that are as free of defects as possible. In this regard, semiconductor dice include relatively fragile semiconductor substrates that are susceptible to cracking and chipping. It is preferable for a fabrication method to protect the dice, and prevent damage to the fragile semiconductor substrates of the dice. Similarly, it is preferable for the completed components to have structures which provide as much protection as possible for the dice.

The present invention is directed to a novel wafer level fabrication method for fabricating semiconductor components, such as chip scale packages, BGA devices and DDC devices, in large volumes, at low costs, and with minimal defects. In addition, the fabrication method produces components with increased reliability, and with a chip scale outline, but with the dice protected on six surfaces by polymer layers.

SUMMARY OF THE INVENTION

In accordance with the present invention, encapsulated semiconductor components, methods for fabricating the components, and systems incorporating the components are provided.

In a first embodiment, the component comprises a semiconductor package in a chip scale configuration, and containing a single die having a circuit side, a back side and four edges. The die includes a semiconductor substrate thinned from the back side, and integrated circuits in a required configuration on the circuit side. In addition, the die includes die contacts on the circuit side in electrical communication with the integrated circuits.

In addition to the die, the component includes planarized contact bumps on the die contacts, and terminal contacts on the planarized contact bumps. The terminal contacts can comprise conductive bumps or balls, in a dense area array, such as a grid array, or alternately planar pads configured as an edge connector. The component also includes a circuit side polymer layer on the circuit side of the die encapsulating the planarized contact bumps, a back side polymer layer on the thinned back side of the die, and edge polymer layers on the edges of the die.

For fabricating the component, a substrate is provided which contains a plurality of semiconductor dice having the die contacts formed thereon. For example, the substrate can comprise a semiconductor wafer, or portion thereof, which contains dice separated by streets. Initially, conductive bumps are formed on the die contacts using a suitable process, such as bonding pre-formed balls, electroless deposition, electrolytic deposition, or stenciling and reflowing of conductive bumps. Trenches are then formed in the substrate between the dice to a depth that is less than a thickness of the substrate. The trenches can be formed by scribing, etching or lasering the substrate.

The circuit side polymer layer is then formed on the bumps and in the trenches, and both the circuit side polymer layer and the bumps can be planarized. The circuit side polymer layer can be formed using a nozzle deposition process, a transfer molding process, an injection molding process, a screen printing process, a stenciling process, a spin resist process, a dry film process, a stereo lithographic process, or any other suitable deposition process. The circuit side polymer layer protects the dice during the fabrication process, and also protects the dice in the completed components. Following formation of the circuit side polymer layer, the substrate is thinned from the back side, such that the polymer filled trenches are exposed. The thinning step can be performed by mechanically planarizing the substrate or by etching the substrate.

Next, the back side polymer layer is formed on the thinned back side of the substrate and can also be planarized. The back side polymer layer can be formed as described above for the circuit side polymer layer. The back side polymer layer protects the dice during the fabrication process, and also protects the dice in the completed components.

Next, the terminal contacts are formed on the contact bumps using a suitable deposition or bonding process. Finally, grooves are formed through the polymer filled trenches to singulate the completed components from one another. The grooves have a width that is less than the width of the polymer filled trenches, such that the edge polymer layers which comprise portions of the polymer filled trenches, remain on the four edges of the dice. The singulated component is encapsulated on six sides (i.e., circuit side, back side, four edges) by the circuit side polymer layer, the back side polymer layer and by edge polymer layers on the four edges. Prior to the singulation step, the components can be tested and burned-in while they remain on the substrate. In addition, the components are electrically isolated on the substrate, which is a particular advantage for burn-in testing.

A second embodiment component includes conductive vias in the thinned substrate, which electrically connect the die contacts to terminal contacts formed on the back side polymer layer. The terminal contacts can comprise conductive bumps or balls, or alternately planar pads configured as an edge connector. In addition, the conductive vias can be used to electrically connect terminal contacts on both sides of the component for stacking multiple components, and for facilitating testing of the components.

A third embodiment component is singulated by etching the substrate. The component includes a circuit side polymer layer, contact bumps embedded in the polymer layer, and terminal contacts on the contact bumps. In addition, the component includes a thin sealing coat, such as vapor deposited parylene, on five surfaces.

A fourth embodiment component includes a circuit side polymer layer, contact bumps embedded in the polymer layer, and terminal contacts on the contact bumps. In addition, the component includes a thinned semiconductor substrate having a back side coat tape for protecting and laser marking the substrate. Alternately, a heat sink can be attached directly to the back side of the thinned semiconductor substrate.

A fifth embodiment component includes a circuit side polymer layer, which comprises two separate polymer materials, including an imageable polymer material (e.g., a photopolymer), and a second polymer material having tailored electrical characteristics. The imageable polymer material also covers the edges of the component, and is formed into dams having a criss-cross pattern configured to retain the tailored polymer material. Depending on the material, the imageable polymer material can be blanket deposited, exposed, and then developed, using a conventional UV photolithography system, or alternately a laser stereo lithography system.

A sixth embodiment pin grid array component includes conductive vias in a thinned die having conductive members in electrical communication with die contacts. In addition, a semiconductor substrate of the thinned die has been planarized and etched to expose portions of the conductive members which form terminal contact pins for the component.

A seventh embodiment component includes a thinned die having conductive vias formed by laser machining and etching openings in a thinned semiconductor substrate. In addition, the thinned substrate can include doped contacts, having a different conductivity type than the bulk of the substrate. The thinned substrate can be etched very thin, such that a very thin component is provided.

An eighth embodiment ball grid array component includes conductive vias in a thinned die having conductive members in electrical communication with die contacts. In addition, a semiconductor substrate of the thinned die has been planarized and etched to expose portions of the conductive members which are used to form a pattern of redistribution conductors. Further, balls are bonded to the redistribution conductors to form terminal contacts in a ball grid array.

In each embodiment, the components can be used to construct systems such as MCM packages, multi chip modules and circuit boards. In addition, prior to assembling the systems, the components can be tested at the wafer level, such that each of the components can be certified as a known good component (KGC) prior to incorporation into the system.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1A is a schematic cross sectional view taken along section line 1 A- 1 A of FIG. 2A illustrating a step in a first embodiment fabrication method;

FIG. 1B is a schematic cross sectional view taken along section line 1 B- 1 B of FIG. 2B illustrating a step in the first embodiment fabrication method;

FIG. 1C is a schematic cross sectional view taken along section line 1 C- 1 C of FIG. 2C illustrating a step in the first embodiment fabrication method;

FIG. 1D is a schematic cross sectional view taken along section line 1 D- 1 D of FIG. 2D illustrating a step in the first embodiment fabrication method;

FIG. 1E is a schematic cross sectional view taken along section line 1 E- 1 E of FIG. 2E illustrating a step in the first embodiment fabrication method;

FIG. 1F is a schematic cross sectional view taken along section line 1 F- 1 F of FIG. 2F illustrating a step in the first embodiment fabrication method;

FIG. 1G is a schematic cross sectional view taken along section line 1 G- 1 G of FIG. 2G illustrating a step in the first embodiment fabrication method;

FIG. 1H is a schematic cross sectional view taken along section line 1 H- 1 H of FIG. 2H illustrating a step in the first embodiment fabrication method;

FIG. 1I is a schematic cross sectional view taken along section line 1 I- 1 I of FIG. 2I illustrating a step in the first embodiment fabrication method;

FIG. 1J is a schematic cross sectional view taken along section line 1 J- 1 J of FIG. 2J illustrating a step in the first embodiment fabrication method;

FIG. 1K is a schematic cross sectional view illustrating a step in the first embodiment fabrication method;

FIGS. 1L-1N are schematic cross sectional views of an alternate embodiment of the first embodiment fabrication method shown in FIGS. 1A-1K;

FIG. 1O is a schematic cross sectional view of an alternate embodiment of the first embodiment fabrication method shown in FIGS. 1A-1K;

FIGS. 1P-1R are schematic cross sectional views of an alternate embodiment of the first embodiment fabrication method shown in FIGS. 1A-1K;

FIG. 2A is a cross sectional view taken along section line 2 A- 2 A of FIG. 1A illustrating die contacts on a wafer containing a plurality of semiconductor dice;

FIG. 2B is a cross sectional view taken along section line 2 B- 2 B of FIG. 1B illustrating bumps on the die contacts;

FIG. 2C is a cross sectional view taken along section line 2 C- 2 C of FIG. 1C illustrating trenches formed in the streets between the dice on the wafer;

FIG. 2D is a cross sectional view taken along section line 2 D- 2 D of FIG. 1D illustrating a good die dam on the wafer;

FIG. 2E is a cross sectional view taken along section line 2 E- 2 E of FIG. 1E illustrating a support dam on the wafer;

FIG. 2F is a cross sectional view taken along section lien 2 F- 2 F of FIG. 1F illustrating deposition of the circuit side polymer layer on the wafer;

FIG. 2G is a cross sectional view taken along section line 2 G- 2 G of FIG. 1G illustrating the circuit side polymer layer and the bumps following planarization;

FIG. 2H is a cross sectional view taken along section line 2 H- 2 H of FIG. 1H illustrating the polymer filled trenches on the back side of the wafer following back side thinning of the wafer;

FIG. 2I is a cross sectional view taken along section line 2 I- 2 I of FIG. 1I illustrating the back side polymer layer on the wafer following planarization;

FIG. 2J is a cross sectional view taken along section line 2 J- 2 J of FIG. 1J illustrating the terminal contacts on the circuit side polymer layer;

FIG. 2K is a cross sectional view taken along section line 2 K- 2 K of FIG. 1K illustrating the singulated first embodiment components and the edge polymer layers on the components;

FIG. 3A is an enlarged portion of FIG. 2A, taken along section line 3 A, illustrating a die contact;

FIG. 3B an enlarged portion of FIG. 2B, taken along section line 3 B, illustrating a metal bump;

FIG. 3C is an enlarged portion of FIG. 2C, taken along section line 3 C, illustrating the trenches in the streets of the wafer;

FIG. 3D is an enlarged cross sectional view taken along section line 3 D- 3 D of FIG. 2D illustrating a metal bump, a trench and the good die dam;

FIG. 3E is an enlarged cross sectional view taken along section line 3 E- 3 E of FIG. 2E illustrating the support dam, the good die dam, a trench and two metal bumps;

FIG. 3F is an enlarged cross sectional view taken along section line 3 F- 3 F of FIG. 2F illustrating the circuit side polymer layer in the trenches and on the bumps;

FIG. 3G is an enlarged cross sectional view taken along section line 3 G- 3 G of FIG. 2G illustrating the circuit side polymer layer and the bumps following a planarization step;

FIG. 3H is an enlarged portion of FIG. 2H illustrating the polymer filled trenches following a back side thinning step;

FIG. 3I is a cross sectional view taken along section line 3 I- 3 I of FIG. 2I illustrating the back side polymer layer on the wafer following a planarization step;

FIG. 3J is a cross sectional view taken along section line 3 J- 3 J of FIG. 2J illustrating the terminal contacts on the bumps and the circuit side polymer layer;

FIG. 4A is a plan view of a first embodiment semiconductor component;

FIG. 4B is a side elevation view of FIG. 4A;

FIG. 4C is an enlarged cross sectional view of the component taken along section line 4 C- 4 C of FIG. 4A;

FIG. 5A is an enlarged cross sectional view equivalent to FIG. 4C of an alternate embodiment of the first embodiment component having planar terminal contacts configured as an edge connector;

FIG. 5B is a view taken along line 5 B- 5 B of FIG. 5A illustrating the edge connector;

FIG. 6A is an enlarged cross sectional view equivalent to FIG. 4C of an alternate embodiment of the first embodiment component having encapsulation on five surfaces;

FIG. 6B is an enlarged cross sectional view equivalent to FIG. 4C of an alternate embodiment of the first embodiment component having a heat sink;

FIG. 7 is a block diagram illustrating steps in the first embodiment fabrication method;

FIGS. 8A-8F are schematic cross sectional views illustrating steps in a second embodiment fabrication method;

FIGS. 8G-8I are schematic cross sectional views illustrating steps in an alternate embodiment of the second embodiment fabrication method;

FIG. 9A is an enlarged view taken along line 9 A- 9 A of FIG. 8A illustrating a conductive via;

FIG. 9B is an enlarged cross sectional view taken along section line 9 B- 9 B of FIG. 8A illustrating the conductive via;

FIG. 9C is an enlarged cross sectional view equivalent to FIG. 9B but illustrating an alternate embodiment conductive via;

FIG. 9D is an enlarged cross sectional view taken along section line 9 D- 9 D of FIG. 8B illustrating a contact bump on the conductive via;

FIG. 9E is an enlarged cross sectional view taken along section line 9 E- 9 E of FIG. 8C illustrating the conductive via, the contact bump, and a circuit side polymer layer prior to planarization;

FIG. 9F is an enlarged cross sectional view taken along section line 9 F- 9 F of FIG. 8D illustrating the conductive via, the contact bump, and the circuit side polymer layer following planarization;

FIG. 9G is an enlarged cross sectional view taken along section line 9 G- 9 G of FIG. 8E illustrating the conductive via, the contact bump, the circuit side polymer layer, a back side polymer layer, and a terminal contact in electrical communication with the conductive via;

FIG. 9H is an enlarged cross sectional view taken along section line 9 H- 9 H of FIG. 8H illustrating the conductive via, planarized contact bump and terminal contact formed using the fabrication method of FIGS. 8G-8I;

FIG. 10A is an enlarged partial cross sectional view illustrating a second embodiment component fabricated using the fabrication method of FIGS. 8A-8F;

FIG. 10B is an enlarged partial cross sectional view illustrating two second embodiment components in a stacked assembly;

FIG. 11A is an enlarged partial cross sectional view equivalent to FIG. 10A of an alternate embodiment of the second embodiment component having terminal contacts only on the back side polymer layer;

FIG. 11B is an enlarged partial cross sectional view equivalent to FIG. 10A of another alternate embodiment of the second embodiment component having offset terminal contacts;

FIG. 11C is an enlarged partial cross sectional view equivalent to FIG. 10A of another alternate embodiment of the second embodiment component having edge connector terminal contacts on the back side polymer layer;

FIG. 11D is an enlarged partial cross sectional view equivalent to FIG. 10A of another alternate embodiment of the second embodiment component having edge connector terminal contacts on both the back side polymer layer and the circuit side polymer layer;

FIG. 11E is an enlarged partial cross sectional view equivalent to FIG. 10A of another alternate embodiment of the second embodiment component having terminal contacts on the circuit side polymer layer;

FIG. 11F is an enlarged partial cross sectional view equivalent to FIG. 10A of another alternate embodiment of the second embodiment component having terminal contacts on both the circuit side polymer layer and the back side polymer layer;

FIG. 12A is an enlarged partial cross sectional view equivalent to FIG. 10A of another alternate embodiment of the second embodiment component configured as an interconnect;

FIG. 12B is an enlarged partial cross sectional view of a stacked system constructed using the interconnect component of FIG. 12A;

FIG. 12C is an enlarged partial cross sectional view of a module system constructed using an alternate embodiment of the interconnect component of FIG. 12A;

FIGS. 13A-13F are schematic cross sectional views illustrating steps in a method for fabricating a third embodiment semiconductor component using an etching step for singulating the component;

FIG. 13G is an enlarged cross sectional view taken along section line 13 G- 13 G of FIG. 13F illustrating a hermetic seal layer on the third embodiment component;

FIG. 14A is a cross sectional view taken along section line 14 A- 14 A of FIG. 13B illustrating an etch mask;

FIG. 14B is a cross sectional view taken along section line 14 B- 14 B of FIG. 13C illustrating a circuit side polymer layer;

FIGS. 15A-15F are schematic cross sectional views illustrating steps in a method for fabricating a fourth embodiment semiconductor component encapsulated on a single side;

FIG. 15G is an enlarged view taken along line 15 G- 15 G of FIG. 15E illustrating a laser marking;

FIG. 16 is a schematic cross sectional view of an alternate embodiment of the fourth embodiment semiconductor component having a heat sink;

FIGS. 17A-17I are schematic cross sectional views illustrating steps in a method for fabricating a fifth embodiment semiconductor component;

FIG. 17J is an enlarged portion of FIG. 17I, taken along section line 17 J, illustrating the fifth component;

FIG. 18A is a schematic cross sectional view of a system in a package (SIP) fabricated using components constructed in accordance with the invention;

FIG. 18B is a plan view of a multi chip module system fabricated using components constructed in accordance with the invention;

FIG. 18C is a cross sectional view taken along section line 18 C- 18 C of FIG. 18B;

FIGS. 19A-19F are schematic cross sectional views illustrating steps in a method for fabricating a sixth embodiment semiconductor component;

FIG. 19G is an enlarged portion of FIG. 19F illustrating the completed sixth embodiment semiconductor component;

FIG. 20A is a cross sectional view taken along section line 20 A- 20 A of FIG. 19A;

FIG. 20B is a cross sectional view taken along section line 20 B- 20 B of FIG. 19B;

FIG. 20C is a cross sectional view taken along section line 20 C- 20 C of FIG. 19C;

FIG. 20D is a cross sectional view taken along section line 20 D- 20 D of FIG. 19D;

FIG. 20E is a cross sectional view taken along section line 20 E- 20 E of FIG. 19E;

FIG. 20F is a view taken along line 20 F- 20 F of FIG. 19F;

FIGS. 21A-21E are schematic cross sectional views illustrating steps in a method for fabricating a seventh embodiment semiconductor component;

FIG. 21F is an enlarged portion of FIG. 21E illustrating the completed seventh embodiment semiconductor component;

FIG. 21G is an enlarged schematic cross section equivalent to FIG. 21F of an alternate embodiment of the seventh embodiment semiconductor component;

FIG. 21H is an enlarged schematic cross section equivalent to FIG. 21F of an alternate embodiment of the seventh embodiment semiconductor component;

FIG. 21I is an enlarged schematic cross section equivalent to FIG. 21F of an alternate embodiment of the seventh embodiment semiconductor component;

FIGS. 22A-22E are schematic cross sectional views illustrating steps in a method for fabricating an eighth embodiment semiconductor component; and

FIG. 22F is an enlarged portion of FIG. 22E illustrating the completed eighth embodiment semiconductor component.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

As used herein, the term “semiconductor component” refers to an electronic element that includes a semiconductor die. Exemplary semiconductor components include semiconductor packages, semiconductor dice, BGA devices, and DDC devices.

Referring to FIGS. 1A-1K, 2 A- 2 K and 3 A- 3 J, steps in the method for fabricating a first embodiment semiconductor component 16 (FIG. 1K) in accordance with the invention are illustrated. As will be further explained, each completed component 16 (FIG. 1K) contains a single die encapsulated by polymer layers on six surfaces. The component 16 is thus referred to as a “6× component”.

Initially, as shown in FIGS. 1A, 2 A and 3 A, a plurality of semiconductor dice 10 are provided, for fabricating a plurality of semiconductor components 16 (FIG. 1K). The dice 10 can comprise conventional semiconductor dice having a desired configuration. For example, each die 10 can comprise a dynamic random access memory (DRAM), a static random access memory (SRAM), a flash memory, a microprocessor, a digital signal processor (DSP) or an application specific integrated circuit (ASIC). The dice 10 and the components 16 can have any polygonal shape. In the illustrative embodiment, the dice 10 and the components 16 are rectangular in shape, but other polygonal shapes, such as square or hexagonal can also be utilized.

As shown in FIG. 2A, the dice 10 can be contained on a semiconductor wafer 12 . Although in the illustrative embodiment, the method is performed on an entire semiconductor wafer 12 , it is to be understood that the method can be performed on a portion of a wafer, on a panel, or on any other substrate that contains multiple semiconductor dice.

In the illustrative embodiment, the dice 10 are formed on the wafer 12 with integrated circuits and semiconductor devices using techniques that are well known in the art. As also shown in FIG. 2A, the dice 10 are separated by streets 13 on the wafer 12 .

As shown in FIG. 1A, the wafer 12 and each die 10 includes a semiconductor substrate 14 wherein the integrated circuits are formed. In addition, the wafer 12 and each die 10 include a circuit side 20 (first side) wherein the integrated circuits are located, and a back side 22 (second side). Although the processes to follow are described as being formed on the circuit side 20 or on the back side 22 , it is to be understood that any operation performed on the circuit side 20 can also be formed on the back side 22 , and any operation performed on the back side 22 can be performed on the circuit side 20 .

Each die 10 also includes a pattern of die contacts 18 formed on the circuit side 20 , in a dense area array, in electrical communication with the integrated circuits thereon. As shown in FIG. 3A, the die contacts 18 are generally circular shaped metal pads having a desired size and spacing. In addition, the die contacts 18 can comprise a solderable metal such as nickel, copper, gold, silver, platinum, palladium, tin, zinc and alloys of these metals. In the illustrative embodiment, the die contacts 18 comprise Ni/Au pads having a diameter of about 330 μm.

The die contacts 18 can be formed on the circuit side 20 of the wafer 12 using known techniques, such as deposition and patterning of one or more redistribution layers in electrical communication with the bond pads (not shown) for the dice 10 . One such technique is described in U.S. Pat. No. 5,851,911 to Farnworth, which is incorporated herein by reference. Alternately, the die contacts 18 can comprise the bond pads of the dice 10 . In addition, the die contacts 18 can be electrically insulated from the semiconductor substrate 14 by insulating layers (not shown), formed of suitable materials such as BPSG, SiO ₂or polyimide.

Next, as shown in FIGS. 1B, 2 B and 3 B, a bump formation step is performed in which contact bumps 24 are formed on the die contacts 18 . The contact bumps 24 can comprise metal bumps deposited on the die contacts 18 using a suitable deposition process, such as stenciling and reflow of a solder alloy onto the die contacts 18 . The contact bumps 24 can comprise solder, another metal, or a conductive polymer material. As will become more apparent as the description proceeds, the contact bumps 24 function as interconnects between the die contacts 18 and terminal contacts 42 (FIG. 1K) which will be formed on the completed components 16 . As shown in FIG. 1B, a dicing tape 26 can be attached to the back side 22 of the wafer 12 for performing a scribing step to follow. Suitable dicing tapes 26 are manufactured by Furikawa or Nitto Denko.

Next, as shown in FIGS. 1C, 2 C and 3 C, a scribing step is performed, during which trenches 28 are formed in the streets 13 of the wafer 12 between the dice 10 . Although the scribing step is illustrated after the bump formation step, it is to be understood that the scribing step can be performed prior to the bump formation step. The scribing step can be performed using a dicing saw having saw blades set to penetrate only part way through the wafer 12 . The scribing step can also be performed by etching the trenches 28 using a wet etching process, a dry etching process or a plasma etching process. With an etching process, the dicing tape 26 does not need to be employed. However, an etch mask (not shown) can be formed on the circuit side 20 of the wafer 12 having openings that define the pattern of the trenches 28 . In addition, the depth of the trenches 28 can be controlled using suitable end pointing techniques.

As another alternative, the trenches 28 can be formed in the substrate 14 by laser machining the wafer 12 using a laser machining system. A suitable laser system for laser machining the trenches 28 is manufactured by Electro Scientific, Inc., of Portland, Oreg. and is designated a Model No. 2700.

The trenches 28 can have a criss-cross pattern as shown, similar to a tic tac toe board, such that each trench is parallel to some trenches and perpendicular to other trenches. As such, the trenches 28 substantially surround each die 10 , defining the four edges 30 of each die 10 , and the rectangular polygonal peripheral shape of each die 10 as well.

As shown in FIG. 1C, the trenches 28 do not extend through the full thickness Tw of the wafer 12 and the semiconductor substrate 14 . Rather, the trenches 28 have a depth d measured from the surface of the circuit side 20 of the wafer 12 , that is less than the thickness Tw of the wafer 12 . The depth d can have any value provided it is less than the value of the full thickness Tw. By way of example, the depth d can be from about 0.1 to 0.9 of the thickness Tw. However, as will be more fully explained, the depth d must be greater than a depth Ts (FIG. 3I) of the thinned substrate 14 T (FIG. 3I).

In the illustrative embodiment, the wafer 12 has a thickness Tw of about 28 mils (725 μm), and the trenches 28 have a depth d of about 10 mils (254 μm). In addition to the depth d, the trenches 28 have a width W, which in the illustrative embodiment is about 4 mils (101.6 μm). The scribing step can be performed using a dicing saw having saw blades with the width W, which are configured to penetrate the circuit side 20 of the wafer 12 to the depth d. Alternately, with an etching process for forming the trenches 28 , openings in an etch mask determine the width W, and control of the etch process end points the trenches 28 with the depth d.

Next, as shown in FIGS. 1D, 2 D and 3 D, a good die dam 32 is formed on the circuit side 20 of the wafer 12 . As shown in FIG. 2D, the good die dam 32 encircles only the complete, or “good” dice on the wafer. The incomplete or “bad” dice are not encircled by the good die dam 32 . As shown in FIG. 3D, the good die dam 32 has a height H measured from the surface of the circuit side 20 of the wafer 12 that can be greater than, or alternately less than, a height Hb of the contact bumps 24 . In the illustrative embodiment, the height Hb of the contact bumps 24 is about 13.78 mils (350 μm), and the height H of the good die dam 32 is slightly greater.

The good die dam 32 can comprise a polymer material deposited on the wafer 12 using a suitable deposition process such as deposition through a nozzle, screen printing, stenciling or stereographic lithography. In the illustrative embodiment, the good die dam 32 is deposited on the wafer 12 using a nozzle deposition apparatus. The nozzle deposition apparatus is under computer control, and is configured to move in x and y directions across the wafer 12 , and in z directions towards and away from the wafer 12 . One suitable nozzle deposition apparatus, also known as a material dispensing system, is manufactured by Asymtek of Carlsbad, Calif.

The good die dam 32 can comprise a curable polymer material having a relatively high viscosity, such that the polymer material sticks to the wafer 12 , and stays in a desired location. Suitable curable polymers for the good die dam 32 include silicones, polyimides and epoxies. In addition, these polymer materials can include fillers such as silicates configured to reduce the coefficient of thermal expansion (CTE) and adjust the viscosity of the polymer material. One suitable curable polymer is manufactured by Dexter Electronic Materials of Rocky Hill, Conn. under the trademark “HYSOL” FP4451. The good die dam 32 can also comprise a polymer such as parylene, deposited using a vapor deposition process to be hereinafter described.

Next, as shown in FIGS. 1E, 2 E and 3 E, a support dam 34 is formed on the wafer 12 . In the illustrative embodiment, the support dam 34 comprises a serpentine-shaped ribbon of polymer material formed outside of the good die dam 32 proximate to the peripheral edges of the wafer 12 . The support dam 34 is configured to support peripheral areas of the wafer 12 during the planarization steps to follow. Specifically, these peripheral areas are subject to cracking without the support dam 34 . The support dam 34 can comprise a curable polymer material deposited using a suitable deposition process such as deposition through a nozzle, screen printing or stenciling.

In the illustrative embodiment, the support dam 34 comprises a same material as the good die dam 32 , and is deposited using the previously described nozzle deposition apparatus. Alternately, the support dam 34 can comprise one or more pre-formed polymer elements attached to the wafer 12 . In this case, the support dam 32 can have a serpentine-shape, a donut shape, or can merely be a segment or ribbon of material, that supports a particular area on the wafer 12 .

Following deposition, both the good die dam 32 and the support dam 34 can be cured to harden the polymer material. For example, curing can be performed by placing the wafer 12 in an oven at a temperature of about 90° to 165° C. for about 30 to 60 minutes.

Next, as shown in FIGS. 1F, 2 F and 3 F, a circuit side polymer layer 36 is deposited on the circuit side 20 of the wafer 12 within the good die dam 32 . The circuit side polymer layer 36 can comprise a relatively low viscosity, curable material configured to spread over a relatively large area. The circuit side polymer layer 36 can be deposited using a suitable deposition process such as deposition through a nozzle, spatuling, screen printing or stenciling. In the illustrative embodiment the circuit side polymer layer 36 is deposited in a spiral pattern 46 (FIG. 2F) to completely fill the area enclosed by the good die dam 32 , using the previously described nozzle deposition apparatus.

As shown in FIG. 3F, the circuit side polymer layer 36 is contained by the good die dam 32 . In addition, the circuit side polymer layer 36 encapsulates the contact bumps 24 and covers the surfaces of the dice 10 . As also shown in FIG. 3F, the circuit side polymer layer 36 fills the trenches 28 , forming polymer filled trenches 28 P between the dice 10 .

The circuit side polymer layer 36 can comprise a curable polymer such as a silicone, a polyimide or an epoxy. In addition, these materials can include fillers, such as silicates, configured to reduce the coefficient of thermal expansion (CTE) and adjust the viscosity of the polymer material. One suitable curable polymer material is manufactured by Dexter Electronic Materials of Rocky Hill, Conn. under the trademark “HYSOL” FP4450.

Following deposition, the circuit side polymer layer 36 can be cured to harden the polymer material. For example, curing can be performed by placement of the wafer 12 in an oven at a temperature of about 90° to 165° C. for about 30 to 60 minutes.

Next, as shown in FIGS. 1G, 2 G and 3 G, a circuit side planarization step is performed, in which the circuit side polymer layer 36 is planarized to form a planarized circuit side polymer layer 36 P. This planarization step also planarizes the contact bumps 24 to form planarized contact bumps 24 P. In addition, this planarization step planarizes the good die dam 32 to form a planarized good die dam 32 P, and planarizes the support dam 34 to form a planarized support dam 34 P.

The circuit side planarization step can be performed using a mechanical planarization apparatus (e.g., a grinder). One suitable mechanical planarization apparatus is manufactured by Okamoto, and is designated a model no. VG502. The circuit side planarization step can also be performed using a chemical mechanical planarization (CMP) apparatus. A suitable CMP apparatus is commercially available from a manufacturer such as Westech, SEZ, Plasma Polishing Systems, or TRUSI. The circuit side planarization step can also be performed using an etch back process, such as a wet etch process, a dry etch process or a plasma etching process.

In the illustrative embodiment, the circuit side planarization step can be performed such that the thickness of the circuit side polymer layer 36 is reduced by an amount sufficient to expose and planarize the surfaces of the contact bumps 24 . In the illustrative embodiment, the planarized circuit side polymer layer 36 P has a thickness Tcs of about 12 mils (304.8 μm). As another alternative the circuit side planarization step need not also planarize the contact bumps 24 . For example, the contact bumps 24 can remain generally concave in shape, and can protrude past the surface of the planarized circuit side polymer layer 36 P.

Rather than the above nozzle deposition and planarizing process, the circuit side polymer layer 36 can be formed by another suitable deposition process, such as an injection molding process, a transfer molding process, a stenciling process, a screen printing process, a spin resist process, a dry film process, or a stereographic lithographic process. As another alternative, the circuit side polymer layer 36 can comprise a polymer such as parylene, deposited using a vapor deposition process to be hereinafter described. As yet another alternative, the circuit side polymer layer 36 can comprise a wafer level underfill material to be hereinafter described.

Next, as shown in FIGS. 1H, 2 H and 3 H, a back side thinning step is performed using the above described mechanical planarization apparatus. The back side thinning step removes semiconductor material from the semiconductor substrate 14 to form a thinned semiconductor substrate 14 T and thinned dice 10 T. In addition, enough of the semiconductor material is removed to expose the polymer filled trenches 28 P. As such, the back side thinning step would singulate the thinned dice 10 T, but the polymer filled trenches 28 P hold the thinned dice 10 T and the wafer 12 together. Following the back side thinning step, all of the thinned dice 10 T are electrically isolated by the polymer filled trenches 28 P.

The amount of semiconductor material removed by the back side thinning step is dependent on the thickness Tw of the wafer 12 , and on the depth d of the trenches 28 . For example, if the thickness Tw of the wafer 12 is about 28 mils (725 μm), and the depth d of the trenches is about 10 mils (25.4 μm), then at least 18 mils (457.2 μm) of semiconductor material must be removed to expose the polymer filled trenches 28 P. In the illustrative embodiment about 22 mils (558.8 μm) of semiconductor material is removed, such that the thickness Ts (FIG. 3I) of the thinned substrate 14 T is about 6 mils (152.4 μm). However, the thickness Ts of the thinned substrate 14 T can vary from about 10 μm to 720 μm.

The thickness Ts of the thinned substrate 14 T can be related to the original thickness Tw of the wafer 12 by the formula Ts=Tw−y, where y represents the amount of material removed by the back side thinning step.

Optionally, a chemical polishing step (CMP) can be performed to remove grind damage to the thinned semiconductor substrate 14 T. Polishing can be performed using a commercial CMP apparatus from a manufacturer such as Westech, SEZ, Plasma Polishing Systems or TRUSI. As another option an etching step can be performed using an etchant such as TMAH, to remove grind damage to the thinned semiconductor substrate 14 T.

Next, as shown in FIGS. 1I, 2 I and 3 I, a planarized back side polymer layer 38 P is formed on the thinned back side 22 T of the thinned wafer 12 T. The planarized back side polymer layer 38 P can be formed by depositing a polymer material on the thinned back side 22 T, curing the polymer material, and then mechanically planarizing the cured polymer material. All of these steps can be performed substantially as previously described for the planarized circuit side polymer layer 36 P.

Alternately, the planarized back side polymer layer 38 P can be formed by attaching or laminating a polymer film, such as a polyimide or epoxy tape, having an adhesive surface and a desired thickness to the thinned back side 22 T. In this case the back side planarizing step can be eliminated. One suitable polymer film is a polymer tape manufactured by Lintec, and designated #LE 5950. As another alternative, the back side polymer layer 38 P can be formed by an injection molding process, a transfer molding process, a spin resist process, a dry film process, a stereo lithographic process, or any other suitable process.

As shown in FIG. 3I, a thickness T of the component 16 is equal to a thickness Tp of the planarized back side polymer layer 38 P, plus the thickness Ts of the thinned substrate 14 T. In the illustrative embodiment the polymer material is initially deposited to a thickness of about 12 mils, and the thickness Tp of the planarized back side polymer layer 38 P is about 10.5 mils (266.7 μm). Accordingly, the thickness T of the component 16 is about 28.5 mils (723.9 μm).

Following forming of the planarized back side polymer layer 38 P, pin one indicators (not shown) can be laser printed on the back side polymer layer 38 P, and also on the circuit side polymer layer 36 P, as required. This printing step can be performed using a conventional laser printing apparatus. Preferably the planarized back side polymer layer 38 P is opaque to the wavelength of the laser being employed during the printing step.

Next, as shown in FIGS. 1J, 2 J and 3 J, a terminal contact forming step is performed for forming the terminal contacts 42 . This step is performed by bonding, or depositing, the terminal contacts 42 on the planarized surface of the planarized contact bumps 24 P. As with the contact bumps 24 , the terminal contacts 42 can comprise metal bumps deposited on the planarized contact bumps 24 P using a suitable deposition process, such as stenciling and reflow of a solder alloy. If desired, the same stencil mask that was used to form the contact bumps 24 P can be used to form the terminal contacts 42 . Also, rather than being formed of solder, the terminal contacts 42 can comprise another metal, or a conductive polymer material.

The terminal contacts 42 (and the contact bumps 24 as well) can also be formed by electrolytic deposition, by electroless deposition, or by bonding pre-fabricated balls to the planarized contact bumps 24 P. A ball bumper can also be employed to bond pre-fabricated balls. A suitable ball bumper is manufactured by Pac Tech Packaging Technologies of Falkensee, Germany. The terminal contacts 42 can also be formed using a conventional wire bonder apparatus adapted to form a ball bond, and then to sever the attached wire.

Because the terminal contacts 42 are in effect “stacked” on the planarized contact bumps 24 P, a relatively large spacing distance is provided for flip chip mounting, and the reliability of the component 16 is increased. In addition, the offset, or spacing, provided by the planarized contact bumps 24 P and the terminal contacts 42 , may allow the component 16 to be flip chip mounted without requiring an underfill for some applications.

Optionally, the terminal contacts 42 can be rigidified with a polymer support layer as described in U.S. Pat. No. 6,180,504 B1 to Farnworth et al., which is incorporated herein by reference. As another option, the terminal contacts 42 can be formed in a standardized grid array as described in U.S. Pat. No. 6,169,329 to Farnworth et al., which is incorporated herein by reference. As yet another option, the terminal contacts 42 can be formed as described in U.S. Pat. No. 6,281,131 B1 to Gilton et al., which is incorporated herein by reference.

In addition, the number, the diameter D (FIG. 4A) and the pitch P (FIG. 4B) of the terminal contacts 42 (and of the contact bumps 24 as well) can be selected as required. A representative diameter D can be from about 0.005-in (0.127 mm) to about 0.016-in (0.400 mm) or larger. A representative pitch P can be from about 0.004-in (0.100 mm) to about 0.039-in (1.0) mm or more.

As shown in FIG. 1J, following formation of the terminal contacts 42 , the dicing tape 26 can be applied to the planarized back side polymer layer 38 P.

Next, as shown in FIGS. 1K and 2K, a singulating step is performed to singulate the components 16 from the wafer 12 and from one another. During the singulating step, grooves 44 are sawn, or otherwise formed, in the polymer filled trenches 28 P. The grooves 44 extend through the planarized circuit side polymer layer 36 P, through the polymer filled trenches 28 P, through the planarized back side polymer layer 38 P, and into the dicing tape 26 . However, the grooves 44 have a width Wg that is less than the width W of the trenches 28 . Accordingly, edge polymer layers 40 remain on the four edges 30 of the thinned die 10 T. Specifically, the edge polymer layers 40 comprise portions of the polymer material in the polymer filled trenches 28 P. Further, the edge polymer layers 40 provide rigidity for the edges of the component 16 , and for the terminal contacts 42 proximate to the edges of the component 16 .

The singulating step can be performed using a dicing saw having saw blades with the width Wg. Alternately the singulating step can be performed using another singulation method, such as cutting with a laser or a water jet or be etching the substrate 14 T with a suitable wet or dry etchant. By way of example, if the width of the trenches 28 is about 4 mils (101.6 μm), and the width Wg of the grooves 44 is about 2 mils (50.8 μm), the edge polymer layers 40 will have a thickness of about 1 mil (25.4 μm).

Prior to the singulating step, the components 16 on the wafer 12 can be tested and burned-in using a wafer level test process. Suitable wafer level burn-in test procedures are described in U.S. Pat. No. 6,233,185 B1 to Beffa et al., which is incorporated herein by reference. In addition, a wafer level burn-in apparatus is described in U.S. Pat. No. 6,087,845 to Wood et al., which is incorporated herein by reference.

Because the components 16 on the wafer 12 are electrically isolated by the polymer filled trenches 28 P and the back side planarization step, burn-in testing is improved, as defective components 16 remain electrically isolated, and do not adversely affect the burn-in test procedure. In addition, the active circuitry on the thinned semiconductor die 10 T is protected from damage during test and burn-in. Further, the components 16 have a physical robustness that facilitates testing and handling of the components 16 by the manufacturer and the end user.

Referring to FIGS. 4A-4C, a singulated component 16 is illustrated. As shown in FIG. 4C, the component 16 includes the thinned die 10 T, the thinned substrate 14 T and the die contacts 18 in electrical communication with the integrated circuits thereon. The component 16 also includes the planarized contact bumps 24 P on the die contacts 18 .

In addition, the component 16 includes the planarized circuit side polymer layer 36 P which covers the circuit side 20 of the thinned die 14 T, and encapsulates the planarized contact bumps 24 P. The planarized contact bumps 24 P are thus supported and rigidified by the planarized circuit side polymer layer 36 P. In addition, the planarized contact bumps 24 P function as interconnects between the die contacts 18 and the terminal contacts 42 . Still further, the planarized circuit side polymer layer 36 P has been mechanically planarized to a precise thickness with a planar surface.

The component 16 also includes the terminal contacts 42 bonded to the planarized contact bumps 24 P. In addition, the terminal contacts 42 are arranged in a dense area array such as a ball grid array (BGA), such that a high input/output capability is provided for the component 16 .

The component 16 also includes the planarized back side polymer layer 38 P which covers the thinned back side 22 T of the thinned die 10 T. Again, the planarized back side polymer layer 38 P has been mechanically planarized to a precise thickness with a planar surface.

In addition, the component 16 includes four edge polymer layers 40 which cover and rigidify the four edges 30 of the thinned die 10 T. The component 16 is thus protected on six sides by polymer layers 36 P, 38 P and 40 . In the illustrative embodiment the planarized circuit side polymer layer 36 P and the edge polymer layers 40 are a continuous layer of material, and the planarized back side polymer layer 38 P is a separate layer of material. In addition, the edge polymer layers 40 are formed by portions of the polymer filled trenches 28 P (FIG. 3F).

Referring to FIGS. 5A and 5B, an alternate embodiment component 16 EC is substantially similar to the previously described component 16 (FIGS. 4A-4C) but includes terminal contacts 42 EC configured as an edge connector 43 (FIG. 5B). The edge connector 43 (FIG. 5B) can be configured as described in U.S. Pat. No. 5,138,434 to Wood et al., which is incorporated herein by reference.

The terminal contacts 42 EC can comprise planar, polygonal pads formed of a relatively hard metal such as copper or nickel. In addition, conductors 45 on the circuit side 20 establish electrical paths between the terminal contacts 42 EC and the die contacts 18 . The component 16 EC can be fabricated substantially as shown in FIG. 1A-1K, but with the conductors 45 and the terminal contacts 42 EC fabricated in place of the contact bumps 24 . The conductors 45 and the terminal contacts 42 EC can be fabricated by deposition and patterning of one or more metal layers. Alternately electroless plating can provide robustness and lower electrical resistance.

Referring to FIG. 6A, an alternate embodiment component 16 - 5 X is substantially similar to the previously described component 16 (FIG. 4A-4C) but is encapsulated on five surfaces rather than on six surfaces. As such, the component 16 - 5 X does not include a polymer layer on the thinned backside 22 T of the thinned semiconductor substrate 14 T. The thinned backside 22 T is thus exposed, and can be used to mount a heat sink to the thinned semiconductor substrate 14 T. The component 16 - 5 X can be fabricated essentially as shown in FIGS. 1A-1K, but without forming the planarized back side polymer layer 38 P of FIG. 1I.

Referring to FIG. 6B, an alternate embodiment component 16 HS is substantially similar to the previously described component 16 - 5 X (FIG. 4F), but includes a heat sink 65 attached to the thinned back side 22 T of the thinned semiconductor substrate 14 T. In addition, a thermally conductive adhesive layer 63 , such as a nitride filled epoxy, attaches the heat sink 65 to the thinned back side 22 T. Heat transfer between the thinned semiconductor substrate 14 T and the heat sink 65 is facilitated because the thinned back side 22 T exposes the semiconductor material. The heat sink 65 can comprise a flat metal plate formed of copper or other metal having a high thermal conductivity. In addition, the heat sink 65 can include ribs or fins (not shown) configured to provide an increased surface area for heat transfer.

FIG. 7 summarizes the steps illustrated in FIGS. 1A-1K for fabricating the first embodiment component 16 .

Referring to FIGS. 1L-1N, an alternate embodiment of the first embodiment fabrication method illustrated in FIGS. 1A-1K is illustrated. In this method the same steps are utilized as previously shown in FIGS. 1A-1G and described in the related portions of the specification. However, the thinning step is performed as shown in FIG. 1L, by mechanical planarization in combination with etching to remove damage caused by the mechanical planarization. This forms a thinned wafer 12 T-E having thinned dice 10 T-E with thinned substrates 14 T-E, and a planarized circuit side polymer layer 36 P-E, substantially as previously described. However, in this case the polymer filled trenches 28 P-E extend past the thinned back side 22 T-E because they are not affected by the etching process. Stated differently, the thinned semiconductor substrates 14 T-E are recessed with respect to the back side edges of the polymer filled trenches 28 P-E. The etching process can be performed using a wet etchant, such as KOH or TMAH, that selectively etches the semiconductor substrate 14 . Alternately, the etching process can be performed using a dry etching process or a plasma etching process. As another alternative the polymer filled trenches 28 P-E can be polished back to the level of the thinned back side 22 T-E.

Next, as shown in FIG. 1M, planarized back side polymer layers 38 P-E are formed on the thinned substrates 14 T-E, substantially as previously described for planarized back side polymer layer 38 P. The planarized back side polymer layers 38 P-E fit into the recesses formed by the polymer filled trenches 28 P-E.

Next, as shown in FIG. 1N, the thinned wafer 12 T-E is singulated substantially as previously described, by forming grooves 44 -E through the polymer filled trenches 28 P-E. Each singulated component 16 -E includes a thinned die 10 T-E that has been etched back from the back side. In addition, each component 16 -E includes the planarized back side polymer layer 38 P-E, and edge polymer layers 40 E which comprise portions of the polymer filled trenches 28 P-E.

Referring to FIG. 10, another alternate embodiment of the first embodiment fabrication method is illustrated. FIG. 10 corresponds to FIG. 1N which shows the singulating step. All of the previous fabrication steps as shown in FIGS. 1A-1J are the same. However, in this embodiment the singulating step is performed as shown in FIG. 10, such that singulated components 16 -BE have beveled edges 51 . The beveled edges 51 can be formed using saw blades configured to make beveled cuts.

Referring to FIGS. 1P-1R, an alternate embodiment of the first embodiment fabrication method illustrated in FIGS. 1A-1K is illustrated. In this method the same steps are utilized as previously shown in FIGS. 1A-1G and described in the related portions of the specification. However, in this embodiment both a circuit side polymer layer 36 UF, and a back side polymer layer 38 UF comprise a polymer film having specific characteristics.

Specifically, the polymer film comprises a thermoset polymer film having a Young's modulus of about 4 G Pascal, and a coefficient of thermal expansion (CTE) of about 33 parts per million per ° C. In addition, the polymer film preferably cures and planarizes at a temperature and in a time period that are similar to the temperature and time period for a solder reflow process for bonding solder bumps to semiconductor components (e.g., about 200-250° C. for about several minutes). Further, the polymer film preferably has low alpha emission characteristics.

One suitable thermoset polymer film is a wafer level underfill film manufactured by 3M corporation. In addition, this polymer film is self planarizing, such that a mechanical planarization step as previously described is not necessary.

As shown in FIG. 1P, the wafer 12 UF has a back side 22 UF, and includes semiconductor dice 10 UF on a semiconductor substrate 14 UF. In addition, contact bumps 24 UF have been formed on die contacts 18 UF substantially as previously described for contact bumps 24 (FIG. 1B) and die contacts 18 (FIG. 1A).

As also shown in FIG. 1P, a circuit side polymer layer 36 UF is formed by depositing and curing the above described thermoset polymer film on the circuit side 20 UF of the wafer 12 UF. In particular, a piece of the polymer film having a desired thickness, and about the same peripheral shape as the wafer 12 UF, is placed on the circuit side 20 UF and on the contact bumps 24 UF. The polymer film is then heated to a temperature of about 200-250° C. for several minutes, such that softening and then curing occurs. Following the curing step, each contact bump 24 UF is surrounded by a portion of the circuit side polymer layer 36 UF, but with a tip portion of each contact bumps 24 UF exposed. As such, the circuit side polymer layer 36 UF has a thickness Tuf on the circuit side 20 UF that is less than a height Hcb of the contact bumps 24 UF. In the illustrative embodiment the thickness Tuf is about half the height Hcb. However, the thickness Tuf can be from about 0.1 to 0.9 of the height Hcb.

Polymer filled trenches 28 UF are also formed during formation of the circuit side polymer layer 36 UF, substantially as previously described for polymer filled trenches 28 P (FIG. 1F). In this case, during the curing step the above described polymer film softens and flows into the trenches 28 (FIG. 1C).

Next, as shown in FIG. 1Q, a thinning step is performed substantially as previously described, to form a thinned wafer 12 T-UF having thinned dice 10 T-UF and a thinned substrate 14 T-UF with a thinned back side 22 T-UF. In addition, a back side polymer layer 38 UF is formed on the thinned back side 22 T-UF by depositing and curing the above described polymer film. Alternately, the back side polymer layer 38 UF can be formed using the previously described deposition and planarization steps.

Next, as shown in FIG. 1R, the thinned wafer 12 T-UF and the components 16 UF are singulated, substantially as previously described, by forming grooves 44 UF through the polymer filled trenches 28 UF. Each singulated component 16 UF includes a thinned die 10 T-UF. In addition, each singulated component 16 UF includes a portion of the circuit side polymer layer 36 UF, a portion of the back side polymer layer 38 UF, and edge polymer layers 40 UF which comprise portions of the polymer filled trenches 28 UF. In addition, each component 16 UF includes exposed contact bumps 24 UF, which function as the terminal contacts for the component 16 UF. Further, the contact bumps 24 UF are rigidified by the circuit side polymer layer 36 UF. Alternately, terminal contacts can be bonded to the exposed contact bumps 24 UF, as previously described for terminal contacts 42 (FIG. 1K).

Referring to FIGS. 8A-8F, steps in a method for fabricating a second embodiment component 16 A (FIG. 8F) are illustrated. As with the first embodiment component 16 , each completed component 16 A (FIG. 8F) includes a single semiconductor die encapsulated on six surfaces (6×). In addition, each die includes conductive vias 68 A formed in a semiconducting substrate thereof.

Initially, as shown in FIG. 8A, a plurality of semiconductor dice 10 A are provided on a semiconductor wafer 12 A substantially as previously described. Each die 10 A includes a semiconductor substrate 14 A containing integrated circuits. In addition, the wafer 12 A and each die 10 A includes a circuit side 20 A (first side) wherein the integrated circuits are located, and a back side 22 A (second side). Each die 10 A also includes a pattern of die contacts 18 A in the form of bond pads on the circuit side 20 A, in electrical communication with the integrated circuits thereon. The die contacts 18 A are embedded in an insulating layer 64 A having openings 80 A aligned with the die contacts 18 A. The insulating layer 64 A can comprise a glass such as BPSG, an oxide such as silicon dioxide, or a polymer layer such as polyimide. In addition, a dielectric layer 71 A electrically insulates the die contacts 18 A from the bulk of the substrate 14 A, and from the integrated circuits on the substrate 14 A. The dielectric layer 71 A can comprise an electrically insulating material such as silicon dioxide, or polyimide, formed during fabrication of the wafer 12 A. In addition, the dielectric layer 71 A rather than being blanket deposited, can be located or can have a shape (e.g., donut shape) that insulates only selected portions of the substrate 14 A.

As shown in FIG. 8A, conductive vias 68 A are formed through the die contacts 18 A, and through the semiconductor substrate 14 A, and extend from the circuit side 20 A to the back side 22 A of the dice 10 A. As shown in FIGS. 9A and 9B, each conductive via 68 A includes a via 74 A formed in the substrate 14 A, a conductive member 76 A in the via 74 A, and an insulating layer 78 A which electrically insulates the conductive member 76 A from the bulk of the substrate 14 A.

One method for forming the vias 74 A for the conductive vias 68 A combines laser machining and etching processes. Initially, openings 82 A are formed in the die contacts 18 A using an etch mask (not shown) and an etching process. Depending on the material of the die contacts 18 A, a wet etchant can be used to etch the die contacts 18 A. For example, for die contacts 18 A made of aluminum, one suitable wet etchant is H ₃PO ₄. The openings 82 A in the die contacts 18 A are generally circular, and are smaller in diameter than the width of the die contacts 18 A. The die contacts 18 A thus have metal around their peripheries, but no metal in the center. In the illustrative embodiment, the openings 82 A have a diameter that is about one half the width of the die contacts 18 A. In addition, the openings 82 A surround a portion of the substrate 14 A, such that the die contacts 18 A and the openings 82 A form targets, or bullseyes, for a subsequent laser drilling step in which a laser beam is directed at the openings 82 A and through the substrate 14 A. The laser beam initially pierces the substrate 14 A on the portions of the substrate 14 A surrounded by the openings 82 A.

The laser drilling step forms lasered openings through the substrate 14 A, which do not touch the metal of the die contacts 18 A, as they are located in the middle of the openings 82 A in the die contacts 18 A. For example, the lasered openings can have diameters that are about one half the diameter of the openings 82 A. The laser beam thus initially contacts and pierces the substrate 14 A without having to contact and pierce the metal that forms the die contacts 18 A. This helps to prevent shorting between the conductive via and the die contacts 18 A.

Following the laser drilling step, a cleaning step can be performed in which the lasered openings are cleaned using a suitable wet or dry etchant to form the vias 74 A for the conductive vias 68 A. One suitable wet etchant for cleaning the lasered openings with the substrate 14 A comprising silicon is tetramethylammoniumhydroxide (TMAH). By way of example, the diameters of the vias 74 A can be from 10 μm to 2 mils or greater.

A suitable laser system for performing the laser drilling step is manufactured by Electro Scientific, Inc., of Portland, Oreg. and is designated a Model No. 2700. A representative laser fluence for forming the vias 74 A through a silicon substrate having a thickness of about 28 mils, is from 2 to 10 watts/per opening at a pulse duration of 20-25 ns, and at a repetition rate of up to several thousand per second. The wavelength of the laser beam can be a standard UV wavelength (e.g., 355 nm).

Still referring to FIGS. 9A and 9B, following the laser drilling and cleaning steps, the insulating layers 78 A can be formed on the inside surfaces of the vias 74 A. The insulating layers 78 A can be a grown or a deposited material. With the substrate 14 A comprising silicon, the insulating layers 78 A can be an oxide, such as SiO ₂, formed by a growth process by exposure of the substrate 14 A to an O ₂atmosphere at an elevated temperature (e.g., 950° C.). In this case the insulating layers 78 A do not completely close the vias 74 A, but form only on the sidewalls of the vias 74 A.

Alternately, the insulating layers 78 A can comprise an electrically insulating material, such as an oxide or a nitride, deposited using a deposition process such as CVD, or a polymer material deposited using a suitable deposition process such as screen printing. In this case, if the insulating material completely fills the vias 74 A, a subsequent laser drilling step, substantially as previously described, may be required to re-open the vias 74 A.

Following formation of the insulating layers 78 A, the conductive members 76 A can be formed within the vias 74 A. The conductive members 76 A can be plugs that completely fill the vias 74 A, or alternately, can be layers that cover just the inside surfaces or sidewalls of the vias 74 A. The conductive members 76 A can comprise a highly conductive metal, such as aluminum, titanium, nickel, iridium, copper, gold, tungsten, silver, platinum, palladium, tantalum, molybdenum, tin, zinc and alloys of these metals. The above metals can be deposited within the openings 76 A using a deposition process, such as electroless deposition, CVD, or electrolytic deposition. Alternately a solder metal can be screen printed in the vias 74 A and drawn into the vias 74 A with capillary action. A solder metal can also be drawn into the vias 74 A using a vacuum system and a hot solder wave.

Rather than being a metal, the conductive members 76 A can comprise a conductive polymer, such as a metal filled silicone, or an isotropic epoxy. Suitable conductive polymers are available from A.I. Technology, Trenton, N.J.; Sheldahl, Northfield, Minn.; and 3M, St. Paul, Minn. A conductive polymer can be deposited within the vias 74 A, as a viscous material, and then cured as required. A suitable deposition process, such as screen printing, or stenciling, can be used to deposit the conductive polymer into the vias 74 A.

The conductive vias 68 A can also be formed using the laser machining processes disclosed in U.S. Pat. No. 6,107,109 to Akram et al, U.S. Pat. No. 6,114,240 to Akram et al., and U.S. Pat. No. 6,294,837 B1 to Akram et al., all of which are incorporated herein by reference. Rather than a laser machining processes, the conductive vias 68 A can be formed by etching the vias 74 A using an etch mask and a suitable etchant. As another alternative, the conductive vias 68 A can be formed as described in U.S. Pat. No. 6,313,531 B1 to Geusic et al., which is incorporated herein by reference.

As shown in FIG. 9C, an alternate embodiment counter bored conductive via 68 A-CB can be formed in the substrate 14 A. In this case, the above described laser machining process can be controlled to form the counter bored conductive via 68 A-CB from the backside 22 A but only part way through the substrate 14 A. As also shown in FIG. 9C, the substrate 14 A can be a first conductivity type (e.g., P type silicon). In addition, the substrate 14 A can include a conductivity region 114 A for each counterbored via 68 A-CB having a second conductivity type (e.g., N type silicon). The conductivity region 114 A can comprise a portion of the substrate 14 doped to provide a conductivity type that is opposite to that of the substrate 14 A. For example, the conductivity region 114 A can comprise N type silicon, while the bulk of the substrate 14 A can comprise P type silicon. As such, the conductivity region 114 A can be doped with phosphorus or arsenic or any other suitable dopant, while the bulk of the substrate 14 A can be doped with boron or gallium or any other suitable dopant. This arrangement allows some latitude in locating the counterbored via 68 A-CB because a reverse bias junction is formed by the conductivity region 114 A, and an additional insulating layer is not required in the area of the conductivity region 114 A. The terminal contact 42 A (FIG. 8F) can be formed directly on the conductivity region 114 A such that a tolerance equal to the height of the conductivity region 114 A is provided for locating the counterbored via 68 A-CB.

Next, as shown in FIGS. 8B and 9D, contact bumps 24 A are formed on the die contacts 18 A in electrical communication with the conductive vias 68 A. The contact bumps 24 A can comprise a solderable metal such as nickel, copper, gold, silver, platinum, palladium or alloys of these metals. These metals can be deposited using an electroless or electrolytic deposition process in a manner similar to deposition of a conventional under bump metalization layer. The contact bumps 24 A fill the openings 80 A in the insulating layer 64 A, fill the openings 82 A in the die contacts 18 A, and physically contact the conductive members 76 A. As will be further explained, the contact bumps 24 A can be used to stack multiple components 16 A and to provide contact points for testing the components 16 A. As also shown in FIG. 8B, trenches 28 A are formed part way through the substrate 14 A using a scribing, etching or lasering process, substantially as previously described.

Next, as shown in FIGS. 8C and 9E, a circuit side polymer layer 36 A can be formed on the circuit side 20 A and on the contact bumps 24 A. The circuit side polymer layer 36 A can be formed substantially as previously described for circuit side polymer layer 36 in FIG. 1F.

Next, as shown in FIGS. 8D and 9F, the circuit side polymer layer 36 A and the contact bumps 24 A, can be mechanically planarized (ground) to form a planarized circuit side polymer layer 36 AP and planarized contact bumps 24 AP. This planarization step can be performed substantially as previously described for circuit side polymer layer 36 and planarized contact bumps 24 P in FIG. 1G. During the planarization step, the metal material of the contact bumps 24 A provides a contact surface for end pointing the planarization process.

As also shown in FIGS. 8D and 9F, a backside thinning step is performed, as previously described and shown in FIG. 1H to form a thinned substrate 14 AT having a thinned back side 22 AT.

Next, as shown in FIGS. 8E and 9G, a planarized back side polymer layer 38 AP is formed on the thinned back side 22 AT of the thinned substrate 14 AT. This step can be formed by depositing a polymer material on the thinned back side 22 AT, curing the polymer material, and then mechanically planarizing the cured polymer material, substantially as previously described and shown in FIG. 1I for planarized back side polymer layer 38 P. Alternately, the planarized back side polymer layer 38 AP can be formed by attaching or laminating a polymer film, such as a polyimide or epoxy tape, having an adhesive surface and a desired thickness to the thinned back side 22 AT. In addition, the planarized back side polymer layer 38 AP can comprise a polymer film that is opaque to radiation at a selected wavelength. Such an opaque material will prevent damage to the integrated circuits on the thinned substrate 14 AT during subsequent processing, such as laser marking with a laser beam at the selected wavelength.

The planarized back side polymer layer 38 AP can also comprise a photoimageable polymer material, such as a thick film resist. One such resist comprises a negative tone resist, which is blanket deposited to a desired thickness, exposed, developed and then cured. A suitable resist formulation is sold by Shell Chemical under the trademark “EPON RESIN SU-8”. Such a resist can be deposited to a thickness of from about 0.5-20 mils and then built up using successive layers. A conventional resist coating apparatus, such as a spin coater, or a meniscus coater can be used to deposit the resist. The deposited resist can then be “prebaked” at about 95° C. for about 15 minutes and exposed in a desired pattern using a conventional UV aligner with a dose of about 165 mJ/cm ². Developing can be accomplished with a solution of PGMEA (propylenglycol-monomethylether-acetate). This can be followed by a hard bake at about 200° C. for about 30 minutes.

As shown in FIG. 9G, the planarized back side polymer layer 38 AP includes conductive vias 70 A in electrical communication with the conductive vias 68 A. The conductive vias 70 A can be formed by forming openings in the planarized back side polymer layer 38 AP, and then filling this openings with a conductive material substantially as previously described for conductive vias 68 A. For example, the openings for the conductive vias 70 A can be etched using a photopatterned etch mask and a suitable etchant. Alternately, if the planarized back side polymer layer 38 AP comprises a photoimageable material, the openings for the conductive vias 70 A can be formed by exposure and development of the photoimageable material. The conductive vias 70 A are aligned with, and have a same longitudinal axis as the conductive vias 68 A.

As also shown in FIG. 9G, pads 85 A can be formed on the conductive vias 70 A and the terminal contacts 42 A can be bonded to the pads 85 A. The pads 85 A can be formed using a suitable deposition process, such as electroless plating, electrolytic plating, CVD or stenciling. In addition the pads can be aligned with the conductive vias 70 A using an etch mask, such as a photopatterned resist layer.

As also shown in FIGS. 8E and 9G, terminal contacts 42 A are formed on the pads 85 A. The terminal contacts 42 A can be formed substantially as previously described for terminal contacts 42 in FIG. 1J. For example, the terminal contacts 42 A can comprise metal bumps deposited on the pads 85 A using a suitable deposition process, such as stenciling and reflowing of a solder alloy. As also shown in FIGS. 8E and 9G, a dicing tape 26 A can be applied to the planarized circuit side polymer layer 36 AP.

Next, as shown in FIG. 8F, a singulating step is performed to singulate the components 16 A from the wafer 12 A and from one another. The singulating step can be performed by forming grooves 44 A in the polymer filled trenches 28 AP substantially as previously described and shown in FIG. 1K. However, in this case the singulating step is performed from the back side 22 AT rather than the circuit side 20 A.

As shown in FIG. 10A, a singulated component 16 A includes the thinned die 14 AT having the die contacts 18 A in electrical communication with the integrated circuits thereon. The component 16 A also includes the planarized contact bumps 24 AP on the die contacts 18 A, and the conductive vias 68 A and 70 A in electrical communication with the planarized contact bumps 24 AP.

In addition, the component 16 A includes the planarized circuit side polymer layer 36 AP, which covers the circuit side 20 A of the thinned die 14 AT, and encapsulates the planarized contact bumps 24 AP. The component 16 A also includes the terminal contacts 42 A bonded to the pads 85 A in electrical communication with the conductive vias 68 A and 70 A. The component 16 A also includes the planarized back side polymer layer 38 AP which covers the thinned back side 22 AT of the thinned die 10 AT. In addition, the component 16 A includes four edge polymer layers 40 A which cover the four edges 30 A of the thinned die 10 AT. The component is thus encapsulated on all six surfaces (6×).

The component 16 A can be used to construct systems such as systems in a package and module systems to be hereinafter described. The component 16 A can also be used to construct the stacked system 83 shown in FIG. 10B. In this case the terminal contacts 42 A on a first component 16 A- 1 are bonded to the planarized contact bumps 24 AP on a second component 16 A- 2 . The stacked system 83 can be mounted to a supporting substrate such as a circuit board, or the module substrate 58 of FIGS. 18B and 18C, using the terminal contacts 42 A on the second component 16 A- 2 .

Referring to FIGS. 8G-8H and 9 H, an alternate embodiment of the fabrication method illustrated in FIGS. 8A-8F is illustrated. In this embodiment, the conductive vias 70 A (FIG. 8E) are replaced by planarized back side contact bumps 25 AP (FIG. 9H). The method is initially identical to the method shown in FIGS. 8A-8D. However, as shown in FIG. 8A, pads 87 A are formed directly on the thinned back side 22 AT of the thinned substrate 14 AT in electrical communication with the conductive vias 68 A. The pads 87 A can be formed of a solderable metal using a suitable deposition process such as photopatterning and etching a deposited metal layer. Back side contact bumps 25 A are then formed on the pads 87 A substantially as previously described for contact bumps 24 in FIG. 1E.

Next, as shown in FIG. 8H, the planarized back side polymer layer 38 AP, and planarized back side contact bumps 25 AP are formed, using a mechanical planarization step, (grinding) substantially as previously described for planarized front side polymer layer 36 P and planarized contact bumps 24 P in FIG. 1H. In addition, terminal contacts 42 A are bonded to the planarized back side contact bumps 25 AP substantially as previously described for terminal contacts 42 in FIG. 1J.

Next, as shown in FIG. 8I, a singulation step is performed substantially as previously described and shown in FIG. 8F. The completed component 16 A′ is identical to the previously described component 16 A (FIG. 8F), but includes planarized back side contact bumps 25 AP rather than conductive vias 70 A (FIG. 8F). The component 16 A′ can also be used to form a stacked system identical to the stacked system 83 of FIG. 10B.

Referring to FIG. 11A, an alternate embodiment component 16 A-A is illustrated. The component 16 A-A can be constructed substantially as previously described for component 16 A (FIG. 10A), with conductive vias 68 A-A, 70 A-A, in electrical communication with planarized contact bumps 24 AP-A and terminal contacts 42 A-A. However, a planarized circuit side polymer layer 36 AP-A covers and insulates the planarized contact bumps 24 AP-A.

Referring to FIG. 11B, an alternate embodiment component 16 A-B is illustrated. The component 16 A-B can be constructed substantially as previously described for component 16 A-A (FIG. 11A), with conductive vias 68 A-B, 70 A-B, in electrical communication with planarized contact bumps 24 AP-B and terminal contacts 42 A-B. In addition, a planarized circuit side polymer layer 36 AP-B covers and insulates the planarized contact bumps 24 AP-B. However, the terminal contacts 42 A-B are offset with respect to a longitudinal axis of the conductive vias 68 A-B, 70 A-B. In addition, conductors 89 A-B on the planarized back side polymer layer 38 AP-B electrically connect the terminal contacts 42 A-B to the conductive vias 68 A-B, 70 A-B. The conductors 89 A-B can have a fan out configuration, and the pitch of the terminal contacts 42 A-B can be different than the pitch of the conductive vias 68 A-B, 70 A-B and the planarized contact bumps 24 AP-B.

Referring to FIG. 11C, an alternate embodiment component 16 A-C is illustrated. The component 16 A-C can be constructed substantially as previously described for component 16 A-B (FIG. 11B), with conductive vias 68 A-C, 70 A-C, in electrical communication with planarized contact bumps 24 AP-C and conductors 89 A-C. However, planar terminal contacts 42 A-C are formed on the planarized back side polymer layer 38 AP-C in an edge connector configuration, substantially as previously described for terminal contacts 42 EC of FIG. 5A.

Referring to FIG. 11D, an alternate embodiment component 16 A-D is illustrated. The component 16 A-D can be constructed substantially as previously described for component 16 A-C (FIG. 11C) with planar terminal contacts 42 A-D formed on the planarized back side polymer layer 38 AP-D in an edge connector configuration. In addition, the planarized contact bumps 24 AP-D are in electrical communication with planar terminal contacts 42 A-D on the planarized circuit side polymer layer 36 AP-D in an edge connector configuration.

Referring to FIG. 11E, an alternate embodiment component 16 A-E is illustrated. The component 16 A-E can be constructed substantially as previously described for component 16 A-A (FIG. 11A), with conductive vias 68 A-E, 70 A-E, in electrical communication with contact bumps 24 AP-E and terminal contacts 42 A-E. In addition, a planarized circuit side polymer layer 36 AP-E covers and insulates the planarized contact bumps 24 AP-E. However, the terminal contacts 42 A-E are offset with respect to a longitudinal axis of the conductive vias 68 A-E, 70 A-E. In addition, conductors 87 E electrically connect the terminal contacts 42 A-E to the conductive vias 68 A-E, 70 A-E. The conductors 87 E are electrically insulated by the planarized circuit side polymer layer 36 AP-E. The conductors 87 E can have a fan out configuration, and the pitch of the terminal contacts 42 A-E can be different than the pitch of the conductive vias 68 A-E, 70 A-E and the planarized contact bumps 24 AP-E. In addition, the terminal contacts 42 A-E are bonded to under bump metallization layers 47 E on the conductors 89 A-E. In this case singulation can be from the circuit side as this surface is more planar than the terminal contacts 42 A-E.

Referring to FIG. 11F, an alternate embodiment component 16 A-F is illustrated. The component 16 A-F can be constructed substantially as previously described for component 16 A-A (FIG. 11A), with conductive vias 68 A-F, 70 A-F, in electrical communication with planarized contact bumps 24 AP-F. In addition, a planarized circuit side polymer layer 36 AP-F covers and insulates the planarized contact bumps 24 AP-F. The component 16 A-F also includes terminal contacts 42 A-F on opposing sides thereof, including terminal contacts 42 A-F on the circuit side polymer layer 36 AP-F and terminal contacts 42 A-F on the back side polymer layer 38 AP-F. Conductors 87 F on the opposing side of the component 16 A-F electrically connect the terminal contacts 42 A-F to the conductive vias 68 A-F, 70 A-F. In addition, the terminal contacts 42 A-F are bonded to under bump metallization layers 47 F on the conductors 89 A-F. Further an additional insulating layer 49 E electrically insulates the conductors 87 F on the back side polymer layer 38 AP-F.

Referring to FIG. 12A, an alternate embodiment component 16 I is illustrated. The component 16 I is configured as an interconnect for constructing systems such as multi chip modules, and does not contain active semiconductor devices. However, the component 16 I can include capacitors, inductors and other electrical devices. The component 16 I includes a thinned substrate 14 IT, which can comprise a semiconductor material but without active circuitry. In addition, the component 16 I includes conductive vias 68 I and planarized contact bumps 24 IP on opposing side. The thinned substrate 14 IT is encapsulated on six surfaces by a planarized circuit side polymer layer 36 IP, a pl

5071792	Process for forming extremely thin integrated circuit dice	December, 1991	VanVonno et al.
5138434	Packaging for semiconductor logic devices	August, 1992	Wood et al.
5229647	High density data storage using stacked wafers	July, 1993	Gnadinger
5266912	Inherently impedance matched multiple integrated circuit module	November, 1993	Kledzik
5436203	Shielded liquid encapsulated semiconductor device and method for making the same	July, 1995	Lin
5485039	Semiconductor substrate having wiring conductors at a first main surface electrically connected to plural pins at a second main surface	January, 1996	Fujita et al.
5496775	Semiconductor device having ball-bonded pads	March, 1996	Brooks
5607875	Method of separating a semiconductor wafer with dielectrics	March, 1997	Nishizawa et al.
5618752	Method of fabrication of surface mountable integrated circuits	April, 1997	Gaul
5686317	Method for forming an interconnect having a penetration limited contact structure for establishing a temporary electrical connection with a semiconductor die	November, 1997	Akram et al.
5789307	Method of separating electronic devices contained in a carrier	August, 1998	Igel et al.
5851911	Mask repattern process	December, 1998	Farnworth
5863813	Method of processing semiconductive material wafers and method of forming flip chips and semiconductor chips	January, 1999	Dando
5888883	Method of dividing a wafer and method of manufacturing a semiconductor device	March, 1999	Sasaki et al.
5893725	C4 substrate contact pad which has a layer of NI-B plating	April, 1999	Bhansali
5897337	Process for adhesively bonding a semiconductor chip to a carrier film	April, 1999	Kata et al.
5904546	Method and apparatus for dicing semiconductor wafers	May, 1999	Wood et al.
5925936	Semiconductor device for face down bonding to a mounting substrate and a method of manufacturing the same	July, 1999	Yamaji
5933713	Method of forming overmolded chip scale package and resulting product	August, 1999	Farnworth
5952716	Pin attach structure for an electronic package	September, 1999	Dibble et al.	257/697
6013534	Method of thinning integrated circuits received in die form	January, 2000	Mountain
6013948	Stackable chip scale semiconductor package with mating contacts on opposed surfaces	January, 2000	Akram et al.
6020217	Semiconductor devices with CSP packages and method for making them	February, 2000	Kuisi et al.
6051875	Semiconductor chip	April, 2000	Dando
6054772	Chip sized package	April, 2000	Mostafazadeh et al.
6060373	Method for manufacturing a flip chip semiconductor device	May, 2000	Saitoh
6074896	Method of processing semiconductor material wafers and method of forming flip chips and semiconductor chips	June, 2000	Dando
6080602	Method of producing a semiconductor device using a reduced mounting area	June, 2000	Tani et al.
6087845	Universal wafer carrier for wafer level die burn-in	July, 2000	Wood et al.
6097087	Semiconductor package including flex circuit, interconnects and dense array external contacts	August, 2000	Farnworth et al.
6107109	Method for fabricating a semiconductor interconnect with laser machined electrical paths through substrate	August, 2000	Akram et al.
6107164	Using grooves as alignment marks when dicing an encapsulated semiconductor wafer	August, 2000	Ohuchi
6114240	Method for fabricating semiconductor components using focused laser beam	September, 2000	Akram et al.
6130111	Packaged semiconductor device and method of manufacturing the same	October, 2000	Ikuina et al.
6136137	System and method for dicing semiconductor components	October, 2000	Farnworth et al.
6150717	Direct die contact (DDC) semiconductor package	November, 2000	Wood et al.
6153448	Semiconductor device manufacturing method	November, 2000	Takahashi et al.
6169329	Semiconductor devices having interconnections using standardized bonding locations and methods of designing	January, 2001	Farnworth et al.
6177295	Method of manufacturing semiconductor devices with "chip size package"	January, 2001	De Samber et al.
6180504	Method for fabricating a semiconductor component with external polymer support layer	January, 2001	Farnworth
6221751	Wafer fabrication of die-bottom contacts for electronic devices	April, 2001	Chen et al.
6228678	Flip chip with integrated mask and underfill	May, 2001	Gilleo et al.
6233185	Wafer level burn-in of memory integrated circuits	May, 2001	Beffa et al.
6281131	Methods of forming electrical contacts	August, 2001	Gilton et al.
6294837	Semiconductor interconnect having laser machined contacts	September, 2001	Akram et al.
6313531	Coaxial integrated circuitry interconnect lines, and integrated circuitry	November, 2001	Geisic et al.
6313651	Carrier and system for testing bumped semiconductor components	November, 2001	Hembree et al.
6326698	Semiconductor devices having protective layers thereon through which contact pads are exposed and stereolithographic methods of fabricating such semiconductor devices	December, 2001	Akram
6338980	Method for manufacturing chip-scale package and manufacturing IC chip	January, 2002	Satoh
6350664	Semiconductor device and method of manufacturing the same	February, 2002	Haji et al.
6353267	Semiconductor device having first and second sealing resins	March, 2002	Ohuchi et al.
6379999	Semiconductor device and method of manufacturing the same	April, 2002	Tanabe
6432752	Stereolithographic methods for fabricating hermetic semiconductor device packages and semiconductor devices including stereolithographically fabricated hermetic packages	August, 2002	Farnworth et al.
6451624	Stackable semiconductor package having conductive layer and insulating layers and method of fabrication	September, 2002	Farnworth et al.
6515371	Semiconductor device with elastic structure and wiring	February, 2003	Akiyama et al.
6524890	Method for manufacturing semiconductor device having element isolation structure	February, 2003	Ueda et al.
6534387	Semiconductor device and method of manufacturing the same	March, 2003	Shinogi et al.
6534854	Pin grid array package with controlled impedance pins	March, 2003	Fazelpour et al.	257/697
6544821	Stereolithographic methods of fabricating semiconductor devices having protective layers thereon through which contact pads are exposed	April, 2003	Akram
6544902	Energy beam patterning of protective layers for semiconductor devices	April, 2003	Farnworth
6549821	Stereolithographic method and apparatus for packaging electronic components and resulting structures	April, 2003	Farnworth
6573156	Low defect method for die singulation and for structural support for handling thin film devices	June, 2003	Wang et al.
6579748	Fabrication method of an electronic component	June, 2003	Okuno et al.
6589855	Methods of processing semiconductor wafer and producing IC card, and carrier	July, 2003	Miyamoto et al.
6607970	Semiconductor device and method of manufacturing the same	August, 2003	Wakabayashi
6620731	Method for fabricating semiconductor components and interconnects with contacts on opposing sides	September, 2003	Farnworth et al.
6649445	Wafer coating and singulation method	November, 2003	Qi et al.
6717245	Chip scale packages performed by wafer level processing	April, 2004	Kinsman et al.
6774659	Method of testing a semiconductor package device	August, 2004	Chiang
6803303	Method of fabricating semiconductor component having encapsulated, bonded, interconnect contacts	October, 2004	Hiatt et al.
6809421	Multichip semiconductor device, chip therefor and method of formation thereof	October, 2004	Hayasaka et al.
6828175	Semiconductor component with backside contacts and method of fabrication	December, 2004	Wood et al.
6833613	Stacked semiconductor package having laser machined contacts	December, 2004	Akram et al.
6841413	Thinned die integrated circuit package	January, 2005	Liu
6903442	Semiconductor component having backside pin contacts	June, 2005	Wood et al.
6903443	Semiconductor component and interconnect having conductive members and contacts on opposing sides	June, 2005	Wood et al.
6906418	Semiconductor component having encapsulated, bonded, interconnect contacts	June, 2005	Hiatt et al.
6908784	Method for fabricating encapsulated semiconductor components	June, 2005	Farnworth
6911355	Semiconductor package having flex circuit with external contacts	June, 2005	Farnworth et al.
6964915	Method of fabricating encapsulated semiconductor components by etching	November, 2005	Farnworth et al.
7029949	Method for fabricating encapsulated semiconductor components having conductive vias	April, 2006	Farnworth et al.
7081665	Semiconductor component having thinned substrate, backside pin contacts and circuit side contacts	July, 2006	Wood et al.
7132731	Semiconductor component and assembly having female conductive members	November, 2006	Wood et al.
7157353	Method for fabricating encapsulated semiconductor components	January, 2007	Farnworth et al.
7221059	Wafer level semiconductor component having thinned, encapsulated dice and polymer dam	May, 2007	Farnworth et al.
20010040117	COMPONENT TAPE INCLUDING A PRINTED COMPONENT COUNT	November, 2001	Easton
20020009826	Method of manufacturing a cavity-down plastic ball grid array (CD-PBGA) substrate	January, 2002	Chien
20020017710	Semiconductor device and method of manufacturing the same, circuit board, and electronic equipment	February, 2002	Kurashima et al.	257/686
20020097302	TWO-STEP TRENCH ETCH FOR A FULLY INTEGRATED THEMAL INKJET PRINTHEAD	July, 2002	Nikkel
20050168908	Electrostatic chuck	August, 2005	Maeda et al.	361/234