Kim, Tae H. (Boise, ID, US)
Ingalls, Charles L. (Meridian, ID, US)
Kirsch, Howard C. (Eagle, ID, US)
Gum, Jeremy J. (Boise, ID, US)

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11/497126

08/26/2008

08/01/2006

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Micron Technology, Inc. (Boise, ID, US)

365/185.23

365/63, 365/230.06

G11C8/00; G11C16/06; G11C5/06

365/203.06, 365/185.23, 365/63

5097441	Interdigitated and twisted word line structure for semiconductor memories	March, 1992	Cho et al.	365/230.06
5159572	DRAM architecture having distributed address decoding and timing control	October, 1992	Morton	365/230.06
5208782	Semiconductor integrated circuit device having a plurality of memory blocks and a lead on chip (LOC) arrangement	May, 1993	Sakuta et al.	365/230.03
5363338	Word line driving circuit for dynamic RAM	November, 1994	Oh	365/230.06
5461587	Row redundancy circuit and method for a semiconductor memory device with a double row decoder	October, 1995	Oh	365/200
5513142	Semiconductor memory device for maintaining level of signal line	April, 1996	Arimoto et al.	365/189.11
5574698	Ram row decode circuitry that utilizes a precharge circuit that is deactivated by a feedback from an activated word line driver	November, 1996	Raad	365/230.06
5640359	Word driver circuit and a memory circuit using the same	June, 1997	Suzuki et al.	365/230.06
5706245	Word line decoding circuit of a semiconductor memory device	January, 1998	Kim	365/230.06
5708620	Memory device having a plurality of bitlines between adjacent columns of sub-wordline drivers	January, 1998	Jeong	365/230.06
5774412	Local word line phase driver	June, 1998	Raad et al.	365/230.06
5854770	Decoding hierarchical architecture for high integration memories	December, 1998	Pascucci	365/230.06
5862098	Word line driver circuit for semiconductor memory device	January, 1999	Jeong	365/230.06
5875149	Word line driver for semiconductor memories	February, 1999	Oh et al.	365/230.06
5943289	Hierarchical word line structure	August, 1999	Ahn et al.	365/230.06
6449195	Method and apparatus for coupling noise reduction in a semiconductor device	September, 2002	Min et al.	365/189.05
6501672	Dynamic random access memory (DRAM) capable of canceling out complementary noise developed in plate electrodes of memory cell capacitors	December, 2002	Sekiguchi et al.	365/72
6549445	Semiconductor memory device including plurality of global data lines in parallel arrangement with low parasitic capacitance, and fabrication method thereof	April, 2003	Ooishi et al.	365/63
6556503	Methods and apparatus for reducing decoder area	April, 2003	Schreck	365/230.06
6816410	Method for programming a three-dimensional memory array incorporating serial chain diode stack	November, 2004	Kleveland et al.	365/185.03
6876567	Ferroelectric memory device and method of reading a ferroelectric memory	April, 2005	Chow	365/145
6879505	Word line arrangement having multi-layer word line segments for three-dimensional memory array	April, 2005	Schuerlein	365/51
6894941	RAM having dynamically switchable access modes	May, 2005	Kurjanowicz et al.	365/222
7110318	Semiconductor memory device	September, 2006	Nii	365/230.06

EP0001694	January, 1986			Process for producing high purity anhydrous ethanol.
JP0200003619	February, 2000

Phan, Trong

Yoder, Fletcher

This application is a divisional of application Ser. No. 10/928,034, filed on Aug. 27, 2004 now U.S. Pat. No. 7,110,319.

What is claimed is:

1. A method of reducing coupling noise between adjacent wordlines in a memory device comprising: selecting a first wordline; delivering an enable signal from a first row decoder to a first wordline driver, wherein the first wordline driver is configured to drive the first wordline; and delivering a disable signal from a second row decoder to a second wordline driver, wherein the second wordline driver is configured to drive a second wordline, and wherein the second wordline is immediately adjacent to the first wordline; delivering both an enable signal from the first row decoder and a phase signal from a phase driver to a third wordline driver, wherein the third wordline driver is configured to drive a third wordline, and wherein the third wordline driver is further configured to sink coupling noise on the third wordline to ground upon receiving the phase signal, the third wordline driver being immediately adjacent to a first side of the second wordline driver receiving the disable signal from the second row decoder, the third wordline being immediately adjacent to the second wordline; and wherein the first wordline driver is immediately adjacent to a second side of the second wordline driver, the first and second sides of the second wordline driver being opposite from one another.

2. The method, as set forth in claim 1, wherein the second wordline driver comprises first and second transistors, wherein each of the first and second transistors is coupled between the second wordline and ground and wherein the first transistor is larger than the second transistor, and wherein delivering the enable signal and delivering the disable signal sink coupling noise on the second wordline to ground.

3. The method, as set forth in claim 1, wherein delivering a disable signal from the second row decoder to the second wordline driver comprises not delivering an enable signal from the second row decoder to the second wordline driver.

4. The method, as set forth in claim 1, wherein delivering the enable signal and delivering the disable signal sink coupling noise on the second wordline to ground.

5. The method, as set forth in claim 1, further comprising: deselecting the first wordline; selecting the second wordline; delivering an enable signal from a second row decoder to the second wordline driver; and delivering a disable signal from the first row decoder to the first wordline driver.

6. A method of operating a memory device comprising: delivering a first enable signal from a first row decoder to a first plurality of wordline drivers, wherein each of the first plurality of wordline drivers is configured to drive a respective wordline, the first plurality of wordline drivers including a first wordline driver and a third wordline driver, and wherein the first enable signal is delivered at a first time; delivering a second enable signal from a second row decoder to a second plurality of wordline drivers, wherein each of the second plurality of wordline drivers is configured to drive a respective wordline, the second plurality of wordline drivers including a second wordline driver, and wherein the second enable signal is delivered at a second time, wherein the second time is different from the first time; and delivering a phase signal from a phase driver to the third wordline driver, wherein the third wordline driver is configured to sink coupling noise on the third wordline to ground upon receiving the phase signal, the third wordline driver being immediately adjacent to the second wordline driver receiving the disable signal from the second row decoder; and wherein the first plurality of wordline drivers is interleaved with the second plurality of wordline drivers such that each of the first plurality of wordline drivers is only immediately adjacent to at least one of the second plurality of wordline drivers.

7. The method, as set forth in claim 6, wherein the first plurality of wordline drivers are not enabled while the second plurality of wordline drivers are enabled.

8. The method, as set forth in claim 6, wherein delivering the first enable signal sinks coupling noise on the second wordline to ground, and wherein delivering the second enable signal sinks coupling noise on the first wordline to ground.

9. The method, as set forth in claim 6, wherein sinking coupling noise on the second wordline to ground comprises providing a current path to ground through a transistor in one of the second plurality of wordline drivers, and wherein sinking coupling noise on the first wordline to ground comprises providing a current path though to ground through a transistor in one of the first plurality of wordline drivers.

10. The method, as set forth in claim 6, wherein each of the first plurality of wordline drivers and each of the second plurality of wordline drivers comprises: a first transistor, wherein a first terminal of the first transistor is coupled to a phase driver and wherein a second terminal of the first transistor is coupled to the respective wordline; a second transistor, wherein a first terminal of the second transistor is coupled to the second terminal of the first transistor and a second terminal of the second transistor is coupled to ground, and wherein a gate of the first transistor is coupled to the gate of the second transistor and configured to receive a signal from one of the first and second row decoder; and a third transistor, wherein a first terminal of the third transistor is coupled to the first terminal of the second transistor and wherein a second terminal of the third transistor is coupled to ground.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention generally relates to integrated circuits and, more particularly, to memory devices configured to reduce coupling noise between adjacent wordlines in a memory array.

2. Description of the Related Art

This section is intended to introduce the reader to various aspects of art, which may be related to various aspects of the present invention, which are described and/or claimed below. This discussion is believed to be helpful in providing the reader with background information to facilitate a better understanding of the various aspects of the present invention. Accordingly, it should be understood that these statements are to be read in this light, and not as admissions of prior art.

A wide variety of integrated circuit devices are available for storing data in systems such as computer systems. One type of commonly used memory device is a Dynamic Random Access Memory (DRAM) device. A DRAM memory cell typically includes an access device, such as a transistor, coupled to a storage device, such as a capacitor. The access device allows the transfer of charge to and from the storage capacitor. The data is stored in a binary format; a logical “1” is stored as a charged a capacitor, and a logical “0” is stored as a discharged capacitor. A typical DRAM device is arranged in a plurality of addressable rows and columns which form a memory array. To access a memory cell, a particular row or “wordline” and a particular column or “bitline” may be implemented.

With the constantly increasing demand for higher data storage capacity, memory arrays are becoming more dense. Memory density is typically limited by current processing technologies used for fabrication of the memory arrays. Disadvantageously, as the density of memory arrays increase, other aspects of the memory array, such as electrical characteristics, may also be affected. For instance, coupling noise between adjacent wordlines may have a greater impact on device performance as the device density increases. Disadvantageously, the increased coupling noise between adjacent wordlines may negatively impact device performance and increase current leakage as well as the occurrence of soft errors which may alter the data storage in the memory cells.

Embodiments of the present invention may address one or more of the problems set forth above.

BRIEF DESCRIPTION OF THE DRAWINGS

Advantages of the invention may become apparent upon reading the following detailed description and upon reference to the drawings in which:

FIG. 1 illustrates a block diagram of a portion of a memory device that may be fabricated in accordance with embodiments of the present invention;

FIG. 2 illustrates a more detailed block diagram of a portion of a memory device;

FIG. 3 is a schematic drawing illustrating an exemplary Dynamic Random Access Memory (DRAM) cell;

FIG. 4 is a schematic drawing illustrating an exemplary wordline driver circuit that may be implemented in accordance with embodiments of the present invention;

FIG. 5 is a schematic drawing illustrating wordline drivers implemented in accordance with prior techniques;

FIG. 6 is a block diagram of a portion of the memory array fabricated in accordance with embodiments of the present invention; and

FIG. 7 is a schematic drawing illustrating wordline drivers implemented in accordance with embodiments of the present invention.

DETAILED DESCRIPTION OF SPECIFIC EMBODIMENTS

One or more specific embodiments of the present invention will be described below. In an effort to provide a concise description of these embodiments, not all features of an actual implementation are described in the specification. It should be appreciated that in the development of any such actual implementation, as in any engineering or design project, numerous implementation-specific decisions must be made to achieve the developers' specific goals, such as compliance with system-related and business-related constraints, which may vary from one implementation to another. Moreover, it should be appreciated that such a development effort might be complex and time consuming, but would nevertheless be a routine undertaking of design, fabrication, and manufacture for those of ordinary skill having the benefit of this disclosure.

Referring initially to FIG. 1, a block diagram of a portion of a memory device 10 is illustrated. The memory device 10 may be, for example, a Dynamic Random Access Memory (DRAM) device. The memory device 10 includes a memory array 12 having a number of memory cells arranged in a grid pattern comprising a number of rows and columns. The number of memory cells (and corresponding rows and columns) may vary depending on system requirements and device specifications.

As previously described, the columns or “bitlines” BL are implemented to read and write data to the memory array 12 . The “wordlines” WL are implemented to access a particular row of the memory array 12 . Accordingly, the memory device 10 includes a row address buffer 14 , row decoder 16 , column address buffer 18 and column decoder 20 . The row address buffer 14 controls the row decoder 16 , and the column address buffer 18 controls the column decoder 20 . The row decoder 16 and column decoder 20 selectively access memory cells in the memory array 12 in response to address signals that are provided during read, write and refresh operations. The address signals are typically provided by an external controller such as a microprocessor or other memory controller.

In one exemplary mode of operation, the memory device 10 receives an address corresponding to a particular memory cell in the memory array 12 at each of the row address buffer 14 and the column address buffer 18 . The row address buffer 14 identifies one of the wordlines WL of the particular memory cell in the memory array 12 corresponding to the requested address and passes the address to the row decoder 16 . The row decoder 16 selectively activates the particular wordline WL to activate the access device for each memory cell in the memory array 12 connected to the selected wordline WL. The column address buffer 18 identifies the bitline BL at the particular memory cell corresponding to the requested address and passes the address to the column decoder 20 . The column decoder 20 selects the bitline (or bitlines) BL of the memory cell in the memory array 12 corresponding to the requested address.

The column decoder 20 is coupled to the bitline drivers and sense amplifiers 22 . The bitline drivers and sense amplifiers 22 sense a differential voltage between bitline pairs (BL and BL ) and drive the bitlines (columns) to full power rails in response thereto. Wordline drivers 24 are provided between the row decoder 16 and the memory array 12 to activate a selected wordline in the memory array 12 according to the selected row address. The row decoder 16 , wordline drivers 24 and the general operation of the memory device 10 will be described in more detail with reference to FIG. 2 below.

Referring now to FIG. 2, a more detailed block diagram of an exemplary memory device 10 is illustrated. As previously described, the memory array 12 generally includes a number of memory cells 26 . Each of the memory cells is coupled to a respective wordline WL and a respective bitline BL or a complementary bitline BL . If the memory device 10 is a DRAM device, each memory cell 26 will include an access device and a storage device. Referring briefly to FIG. 3, an exemplary DRAM memory cell 26 is illustrated. The exemplary embodiment of the memory cell 26 includes a field effect transistor (FET) 28 which is implemented to provide access to a storage capacitor 30 . As will be appreciated, the gate of the FET 28 is coupled to a wordline WL and the drain of the FET 28 is coupled to a bitline BL (or a complementary bitline BL ). By controlling the gate via a voltage applied to the wordline WL, a charge on the bitline BL may be stored in the capacitor 30 , as previously described.

Because each memory cell 26 is dynamic, the maximum available voltage is generally implemented to write data to the memory cell 26 to minimize the frequency of memory refresh cycles. In order to write the maximum voltage into a memory cell 26 , the gate of the access transistor 28 is generally driven to a pumped voltage level, V _CCP . Returning to FIG. 2, a phase driver block 32 is generally implemented to provide the pumped voltage V _CCP to the access FET 28 in the memory cell 26 through a respective wordline driver 24 A- 24 H. The pumped voltage V _CCP is generally applied through the phase lines PH 0 -PH 7 . A single phase driver may be implemented to drive a number of phase lines PH 0 -PH 7 . In the present exemplary embodiment, the phase lines PH 0 -PH 3 are driven by one phase driver 34 A, while the phase lines PH 4 -PH 7 are driven by another phase driver 34 B. As will be appreciated, driving one of the phase lines PH 0 -PH 7 may require excessive operating current. That is, only one row at a time requires excessive the pumped voltage V _CCP . By driving only a single wordline driver 24 A- 24 H through a respective phase line PH 0 -PH 7 , operating current can be substantially reduced.

As previously described, external address lines provided to the memory device 10 are received by the row decoder 16 which decodes the address lines to identify a selected memory row address. Because the pitch of the memory array and corresponding wordlines is very small, a separate row decoder 16 cannot be provided for each row. Accordingly, each row decoder 16 is generally coupled to a group of memory rows. In the exemplary embodiment illustrated in FIG. 2, each individual row decoder 16 A and 16 B is coupled to four rows through a respective wordline driver 24 A- 24 H. An enable signal LT 0 is provided from the row decoder 16 A to the wordline drivers 24 A- 24 D, through the inverter 35 A. Similarly, an enable signal LT 1 is provided from the row decoder 16 B to the wordline drivers 24 E- 24 H, through the inverter 35 B. By implementing the phase lines PH 0 -PH 7 , one of the wordlines WL coupled to the group of wordlines can be connected to a pump supply voltage V _CCP through a respective wordline driver 24 A- 24 H.

Referring briefly to FIG. 4, an exemplary wordline driver, such as the wordline driver 24 A, is illustrated. The wordline driver 24 A includes a p-channel metal oxide silicon field effect transistor (MOSFET) 36 and two n-channel MOSFET transistors 38 and 40 . The gates of the transistors 36 and 38 are coupled together and receive an enable signal from a respective row decoder 34 , generally indicated here as LT . The gate of the transistor 36 generally receives a signal from a respective phase driver, indicated here as PH. The gate of the transistor 40 generally receives the inverse of the phase driver signal, indicated here as PH .

When the signal from the individual row decoder LT is low, the p-channel transistor 36 couples the wordline WL to an associated one of the phase lines PH. If the associated global phase line PH is connected to a pump voltage V _CCP , the wordline activates the access transistor 28 in the memory cell 26 . When LT is high, the n-channel transistor 38 couples the wordline WL to ground and the access FET 28 is not activated. The n-channel transistor 40 is generally small compared to the transistor 38 . For instance, the current capability of the n-channel transistor 38 may be at least four times greater than the current capability of the transistor 40 . The transistor 40 is generally implemented to reduce the coupling noise on the wordline WL.

Referring now to FIG. 5, a more detailed example of a portion of the wordline driver block 24 is illustrated. As previously described, each wordline WL 0 -WL 3 includes a respective wordline driver 24 A- 24 D. Each wordline driver 24 A- 24 D includes a p-channel MOS transistor 36 A- 36 D, a first n-channel MOS transistor 38 A- 38 D and a second n-channel MOS transistor 40 A- 40 D. As will be appreciated, each wordline WL 0 -WL 3 includes a parasitic capacitance 42 between adjacent wordlines. The parasitic capacitance 42 A- 42 C varies depending on the specific design of the memory device 10 . The parasitic capacitance 42 A represents coupling noise between adjacent wordlines WL 0 and WL 1 . The parasitic capacitance 42 B represents coupling noise between adjacent wordlines WL 1 and WL 2 , etc. Accordingly, when one wordline is active, an adjacent wordline may receive noise through the parasitic capacitance 42 A- 42 C. Disadvantageously, the coupling noise may cause an unselected wordline to activate if the coupling noise becomes sufficiently large. This condition is exacerbated in densely fabricated wordline structures.

To mitigate some of the effects of the parasitic capacitance 42 , the FETs 40 A- 40 D are implemented to provide a noise sinking path to ground from an active wordline to an inactive wordline. For instance, if the wordline WL 0 is selected, as indicated in FIG. 5, the corresponding condition of the inverted enable signal LT 0 from the row decoder 16 A and the boosted voltage signal PH 0 -PH 3 received from the phase driver 34 A will cause the transistors 36 A- 36 D and 40 A- 40 D to be activated, as indicated in FIG. 5. Accordingly, when the wordline WL 0 is active, coupling noise through the parasitic capacitance 42 A will result between the wordline WL 0 and the wordline WL 1 . By opening transistor 40 B, the coupling noise on the wordline WL 1 is pulled to ground through the transistor 40 B, as indicated by the current dissipation path 44 . Advantageously, the transistor 40 B reduces or eliminates the coupling noise on the wordline WL 1 . However, as device designs become more dense, the coupling noise through the parasitic capacitor 42 A may become too large for the small transistor 40 B to sufficiently eliminate. Accordingly, an improved device configured to better handle cross coupling between adjacent wordlines is described below with reference to FIGS. 6 and 7.

FIG. 6 illustrates a block diagram of a portion of the memory device 10 fabricated in accordance with embodiments of the present invention. In the present exemplary embodiment, rather than placing row drivers which are controlled through the same row decoder directly adjacent to one another, as in FIGS. 2 and 5, the placement of the row drivers 24 A- 24 H may be such that each wordline driver 24 A- 24 H is directly adjacent to a wordline driver 24 A- 24 H which receives a signal from a different row decoder.

As illustrated in FIG. 6, each of the row drivers 24 A- 24 D receives the inverted enable signal LT 0 from the row decoder 16 A. Similarly, each of the wordline drivers 24 E- 24 H receives the inverted enable signal LT 1 from the row decoder 16 B. By interleaving the wordline drivers 24 A- 24 H, as indicated in FIG. 6, the coupling noise on inactive wordlines which are located directly adjacent to an active wordline may be more effectively reduced.

Referring now to FIG. 7, a more detailed illustration of the block diagram depicted in FIG. 6 will be discussed. As discussed with reference to FIG. 6, each adjacent wordline driver receives a signal from a different row decoder. Accordingly, the wordline drivers 24 A and 24 B receive the inverted enable signal LT 0 from the row decoder 16 A. The placement of the wordline drivers 24 A and 24 B is arranged such that they are interleaved with the wordline drivers 24 E and 24 F which receive the inverted enable signal LT 1 from the row decoder 16 B.

In the present example, the wordline WL 0 is selected, as indicated in FIG. 7. Accordingly, the wordline WL 1 is not selected. However, as previously described, the parasitic capacitance 42 A between the wordline WL 0 and the wordline WL 1 provides a noise path which results in coupling noise on WL 1 . However, unlike the embodiment described with reference to FIG. 5, because the wordline driver 24 E (arranged to drive the wordline WL 1 ) is coupled to an inactive row decoder, the coupling noise may be more significantly reduced through the large transistor 38 E as indicated by the current noise path 46 . Based on the state of the transistors 36 E, 38 E and 40 E, due to the inactive signals LT 1 and PH 4 , the transitor 38 E is open and therefore, provides a stronger path to ground such that increases in the coupling noise between active and inactive wordlines can be more effectively reduced and/or eliminated.

While the invention may be susceptible to various modifications and alternative forms, specific embodiments have been shown by way of example in the drawings and have been described in detail herein. However, it should be understood that the invention is not intended to be limited to the particular forms disclosed. Rather, the invention is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the invention as defined by the following appended claims.