Harrison, Ronnie M. (Boise, ID, US)

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11/203511

08/26/2008

08/12/2005

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Micron Technology, Inc. (Boise, ID, US)

375/374

327/3, 327/157, 327/148

H03D3/24; G01R25/00; H03L7/06

327/159, 331/57, 331/1A, 375/375, 331/16, 331/34, 326/115, 327/148, 331/11, 327/162, 326/55, 375/374, 327/152, 375/373, 331/25, 331/173, 327/12, 327/157, 331/185, 327/156, 375/376

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4096402	MOSFET buffer for TTL logic input and method of operation	June, 1978	Schroeder et al.	307/362
4404474	Active load pulse generating circuit	September, 1983	Dingwall	307/260
4481625	High speed data bus system	November, 1984	Roberts et al.	370/85
4508983	MOS Analog switch driven by complementary, minimally skewed clock signals	April, 1985	Allgood et al.	307/577
4511846	Deskewing time-critical signals in automatic test equipment	April, 1985	Nagy et al.	328/164
4514647	Chipset synchronization arrangement	April, 1985	Shoji	307/269
4524448	Variable delay unit for data synchronizer using phase-sensitive counter to vary the delay	June, 1985	Hullwegen	375/118
4573017	Unitary phase and frequency adjust network for a multiple frequency digital phase locked loop	February, 1986	Levine	327/114
4600895	Precision phase synchronization of free-running oscillator output signal to reference signal	July, 1986	Landsman	331/1A
4603320	Connector interface	July, 1986	Farago	341/89
4638187	CMOS output buffer providing high drive current with minimum output signal distortion	January, 1987	Boler et al.	307/451
4638451	Microprocessor system with programmable interface	January, 1987	Hester et al.	395/889
4687951	Fuse link for varying chip operating parameters	August, 1987	McElroy	307/269
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4727541	Hierarchical data transmission system	February, 1988	Mori et al.	370/112
4740962	Synchronizer for time division multiplexed data	April, 1988	Kish, III	370/102
4746996	Skew error correction circuit for video signal reproducing apparatus	May, 1988	Furuhata et al.	360/36.2
4773085	Phase and frequency detector circuits	September, 1988	Cordell	375/120
4789796	Output buffer having sequentially-switched output	December, 1988	Foss	307/443
4791622	Optical data format employing resynchronizable data sectors	December, 1988	Clay et al.	369/59
4818995	Parallel transmission system	April, 1989	Takahashi et al.	341/94
4893087	Low voltage and low power frequency synthesizer	January, 1990	Davis	328/14
4902986	Phased locked loop to provide precise frequency and phase tracking of two signals	February, 1990	Lesmeister	331/25
4924516	Method and system for a synchronized pseudo-random privacy modem	May, 1990	Bremer et al.	380/46
4953128	Variable delay circuit for delaying input data	August, 1990	Kawai et al.	365/194
4958088	Low power three-stage CMOS input buffer with controlled switching	September, 1990	Farah-Bakhsh et al.	307/443
4972470	Programmable connector	November, 1990	Farago	380/3
4979185	High speed serial data link	December, 1990	Bryans et al.	375/20
4984204	High speed sensor system using a level shift circuit	January, 1991	Sato et al.	365/189.11
4984255	Edge transition insensitive delay line system and method	January, 1991	Davis et al.	375/106
5020023	Automatic vernier synchronization of skewed data streams	May, 1991	Smith	364/900
5038115	Method and apparatus for frequency independent phase tracking of input signals in receiving systems and the like	August, 1991	Myers et al.	331/2
5062082	Semiconductor memory device with delay in address predecoder circuit independent from ATD	October, 1991	Choi	365/230.06
5075569	Output device circuit and method to minimize impedance fluctuations during crossover	December, 1991	Branson	307/270
5086500	Synchronized system by adjusting independently clock signals arriving at a plurality of integrated circuits	February, 1992	Greub	395/550
5087828	Timing circuit for single line serial data	February, 1992	Sato et al.	307/269
5113519	Maintenance of file attributes in a distributed data processing system	May, 1992	Johnson et al.	395/600
5120990	Apparatus for generating multiple phase clock signals and phase detector therefor	June, 1992	Koker	307/269
5122690	Interface circuits including driver circuits with switching noise reduction	June, 1992	Bianchi	307/475
5128560	Boosted supply output driver circuit for driving an all N-channel output stage	July, 1992	Chern et al.	307/475
5128563	CMOS bootstrapped output driver method and circuit	July, 1992	Hush et al.	307/482
5130565	Self calibrating PWM utilizing feedback loop for adjusting duty cycles of output signal	July, 1992	Girmay	307/265
5134311	Self-adjusting impedance matching driver	July, 1992	Biber et al.	307/270
5150186	CMOS output pull-up driver	September, 1992	Pinney et al.	357/42
5165046	High speed CMOS driver circuit	November, 1992	Hesson	307/270
5168199	Horizontal linearity correction circuitry for cathode ray tube display	December, 1992	Huffman et al.	315/370
5179298	CMOS buffer circuit which is not influenced by bounce noise	January, 1993	Hirano et al.	307/443
5182524	Method and apparatus for stabilizing pulsed microwave amplifiers	January, 1993	Hopkins	330/149
5194765	Digitally controlled element sizing	March, 1993	Dunlop et al.	307/443
5212601	Disk drive data synchronizer with window shift synthesis	May, 1993	Wilson	360/51
5220208	Circuitry and method for controlling current in an electronic circuit	June, 1993	Schenck	307/443
5223755	Extended frequency range variable delay locked loop for clock synchronization	June, 1993	Richley	307/603
5229929	Output peak current correction for PWM invertors	July, 1993	Shimizu et al.	363/98
5233314	Integrated charge-pump phase-locked loop circuit	August, 1993	McDermott et al.	331/17
5233564	Multiport memory with test signal generating circuit controlling data transfer from RAM port to SAM port	August, 1993	Ohshima et al.	365/230.05
5239206	Synchronous circuit with clock skew compensating function and circuits utilizing same	August, 1993	Yanai	307/272.2
5243703	Apparatus for synchronously generating clock signals in a data processing system	September, 1993	Farmwald et al.	395/325
5254883	Electrical current source circuitry for a bus	October, 1993	Horowitz et al.	307/443
5256989	Lock detection for a phase lock loop	October, 1993	Parker et al.	331/1A
5257294	Phase-locked loop circuit and method	October, 1993	Pinto et al.	375/120
5268639	Testing timing parameters of high speed integrated circuit devices	December, 1993	Gasbarro et al.	324/158R
5272729	Clock signal latency elimination network	December, 1993	Bechade et al.	375/118
5274276	Output driver circuit comprising a programmable circuit for determining the potential at the output node and the method of implementing the circuit	December, 1993	Casper et al.	307/443
5276642	Method for performing a split read/write operation in a dynamic random access memory	January, 1994	Lee	365/189.04
5278460	Voltage compensating CMOS input buffer	January, 1994	Casper	307/296.5
5281865	Flip-flop circuit	January, 1994	Yamashita et al.	307/279
5283631	Programmable capacitance delay element having inverters controlled by adjustable voltage to offset temperature and voltage supply variations	February, 1994	Koerner et al.	307/451
5289580	Programmable multiple I/O interface controller	February, 1994	Latif et al.	395/275
5295164	Apparatus for providing a system clock locked to an external clock over a wide range of frequencies	March, 1994	Yamamura	375/120
5304952	Lock sensor circuit and method for phase lock loop circuits	April, 1994	Quiet et al.	331/1A
5311481	Wordline driver circuit having a directly gated pull-down device	May, 1994	Casper et al.	365/230.06
5311483	Synchronous type semiconductor memory	May, 1994	Takasugi	365/233
5313431	Multiport semiconductor memory device	May, 1994	Uruma et al.	365/230.05
5315269	Phase-locked loop	May, 1994	Fujii	331/1A
5315388	Multiple serial access memory for use in feedback systems such as motion compensated television	May, 1994	Shen et al.	348/718
5321368	Synchronized, digital sequential circuit	June, 1994	Hoelzle	328/63
5337285	Method and apparatus for power control in devices	August, 1994	Ware et al.	365/227
5341405	Data recovery apparatus and methods	August, 1994	Mallard, Jr.	375/120
5347177	System for interconnecting VLSI circuits with transmission line characteristics	September, 1994	Lipp	307/443
5347179	Inverting output driver circuit for reducing electron injection into the substrate	September, 1994	Casper et al.	307/451
5355391	High speed bus system	October, 1994	Horowitz et al.	375/36
5361002	Voltage compensating CMOS input buffer	November, 1994	Casper	327/530
5367649	Programmable controller	November, 1994	Cedar	395/375
5379299	High speed propagation delay compensation network	January, 1995	Schwartz	370/108
5390308	Method and apparatus for address mapping of dynamic random access memory	February, 1995	Ware et al.	395/400
5400283	RAM row decode circuitry that utilizes a precharge circuit that is deactivated by a feedback from an activated word line driver	March, 1995	Raad	365/203
5402389	Synchronous memory having parallel output data paths	March, 1995	Flannagan et al.	365/233
5408640	Phase delay compensator using gating signal generated by a synchronizer for loading and shifting of bit pattern to produce clock phases corresponding to frequency changes	April, 1995	MacIntyre et al.	395/550
5410263	Delay line loop for on-chip clock synthesis with zero skew and 50% duty cycle	April, 1995	Waizman	327/141
5416436	Method for time delaying a signal and corresponding delay circuit	May, 1995	Rainard	327/270
5416909	Input/output controller circuit using a single transceiver to serve multiple input/output ports and method therefor	May, 1995	Long et al.	395/275
5420544	Semiconductor integrated circuit, method of designing the same and method of manufacturing the same	May, 1995	Ishibashi	331/11
5424687	PLL frequency synthesizer and PLL frequency synthesizing method capable of obtaining high-speed lock-up and highly-reliable oscillation	June, 1995	Fukuda	331/11
5428311	Fuse circuitry to control the propagation delay of an IC	June, 1995	McClure	327/276
5428317	Phase locked loop with low power feedback path and method of operation	June, 1995	Sanchez et al.	331/1A
5430408	Transmission gate circuit	July, 1995	Ovens et al.	327/407
5430676	Dynamic random access memory system	July, 1995	Ware et al.	365/189.02
5432823	Method and circuitry for minimizing clock-data skew in a bus system	July, 1995	Gasbarro et al.	375/356
5438545	Data output buffer of semiconductor memory device for preventing noises	August, 1995	Sim	365/189.05
5440260	Variable delay circuit	August, 1995	Hayashi et al.	327/278
5440514	Write control for a memory using a delay locked loop	August, 1995	Flannagan et al.	365/194
5444667	Semiconductor synchronous memory device having input circuit for producing constant main control signal operative to allow timing generator to latch command signals	August, 1995	Obara	365/233
5446696	Method and apparatus for implementing refresh in a synchronous DRAM system	August, 1995	Ware et al.	365/222
5448193	Normalization of apparent propagation delay	September, 1995	Baumert et al.	327/156
5451898	Bias circuit and differential amplifier having stabilized output swing	September, 1995	Johnson	327/563
5457407	Binary weighted reference circuit for a variable impedance output buffer	October, 1995	Shu et al.	326/30
5463337	Delay locked loop based clock synthesizer using a dynamically adjustable number of delay elements therein	October, 1995	Leonowich	327/158
5465076	Programmable delay line programmable delay circuit and digital controlled oscillator	November, 1995	Yamauchi et al.	331/179
5473274	Local clock generator	December, 1995	Reilly et al.	327/159
5473575	Integrated circuit I/O using a high performance bus interface	December, 1995	Farmwald et al.	365/230.06
5473639	Clock recovery apparatus with means for sensing an out of lock condition	December, 1995	Lee et al.	375/376
5485490	Method and circuitry for clock synchronization	January, 1996	Leung et al.	375/371
5488321	Static high speed comparator	January, 1996	Johnson	327/66
5489864	Delay interpolation circuitry	February, 1996	Ashuri	327/161
5497127	Wide frequency range CMOS relaxation oscillator with variable hysteresis	March, 1996	Sauer	331/17
5497355	Synchronous address latching for memory arrays	March, 1996	Mills et al.	365/230.08
5498990	Reduced CMOS-swing clamping circuit for bus lines	March, 1996	Leung et al.	327/323
5500808	Apparatus and method for estimating time delays using unmapped combinational logic networks	March, 1996	Wang	364/578
5502672	Data output buffer control circuit	March, 1996	Kwon	365/189.05
5506814	Video random access memory device and method implementing independent two WE nibble control	April, 1996	Hush et al.	365/230.03
5508638	Low current redundancy fuse assembly	April, 1996	Cowles et al.	326/38
5513327	Integrated circuit I/O using a high performance bus interface	April, 1996	Farmwald et al.	395/309
5515403	Apparatus and method for clock alignment and switching	May, 1996	Sloan et al.	375/371
5532714	Method and apparatus for combining video images on a pixel basis	July, 1996	Knapp et al.	345/114
5539345	Phase detector apparatus	July, 1996	Hawkins	327/150
5544124	Optimization circuitry and control for a synchronous memory device with programmable latency period	August, 1996	Zagar et al.	365/230.08
5544203	Fine resolution digital delay line with coarse and fine adjustment stages	August, 1996	Casasanta et al.	375/376
5550515	Multiphase clock synthesizer having a plurality of phase shifted inputs to a plurality of phase comparators in a phase locked loop	August, 1996	Liang et al.	331/11
5550549	Transponder system and method	August, 1996	Procter et al.	342/47
5550783	Phase shift correction circuit for monolithic random access memory	August, 1996	Stephens, Jr. et al.	365/233
5552727	Digital phase locked loop circuit	September, 1996	Nakao	327/159
5555429	Multiport RAM based multiprocessor	September, 1996	Parkinson et al.	395/800
5557224	Apparatus and method for generating a phase-controlled clock signal	September, 1996	Wright et al.	327/115
5557781	Combination asynchronous cache system and automatic clock tuning device and method therefor	September, 1996	Stones et al.	395/550
5563546	Selector circuit selecting and outputting voltage applied to one of first and second terminal in response to voltage level applied to first terminal	October, 1996	Tsukada	327/408
5568075	Timing signal generator	October, 1996	Curran et al.	327/172
5568077	Latch circuit	October, 1996	Sato et al.	327/199
5572557	Semiconductor integrated circuit device including PLL circuit	November, 1996	Aoki	375/376
5572722	Time skewing arrangement for operating random access memory in synchronism with a data processor	November, 1996	Vogley	395/555
5574698	Ram row decode circuitry that utilizes a precharge circuit that is deactivated by a feedback from an activated word line driver	November, 1996	Raad	365/230.06
5576645	Sample and hold flip-flop for CMOS logic	November, 1996	Farwell	327/94
5577079	Phase comparing circuit and PLL circuit	November, 1996	Zenno et al.	375/373
5577236	Memory controller for reading data from synchronous RAM	November, 1996	Johnson et al.	395/551
5578940	Modular bus with single or double parallel termination	November, 1996	Dillon et al.	326/30
5578941	Voltage compensating CMOS input buffer circuit	November, 1996	Sher et al.	326/34
5579326	Method and apparatus for programming signal timing	November, 1996	McClure	371/61
5581197	Method of programming a desired source resistance for a driver stage	December, 1996	Motley et al.	326/30
5589788	Timing adjustment circuit	December, 1996	Goto	327/276
5590073	Random access memory having flash memory	December, 1996	Arakawa et al.	365/185.08
5594690	Integrated circuit memory having high speed and low power by selectively coupling compensation components to a pulse generator	January, 1997	Rothenberger et al.	365/189.01
5610558	Controlled tracking of oscillators in a circuit with multiple frequency sensitive elements	March, 1997	Mittel et al.	331/2
5614855	Delay-locked loop	March, 1997	Lee et al.	327/158
5619473	Semiconductor memory device with dual address memory read amplifiers	April, 1997	Hotta	365/238.5
5621340	Differential comparator for amplifying small swing signals to a full swing output	April, 1997	Lee et al.	327/65
5621690	Nonvolatile memory blocking architecture and redundancy	April, 1997	Jungroth et al.	365/200
5621739	Method and apparatus for buffer self-test and characterization	April, 1997	Sine et al.	371/22.1
5623523	Method and apparatus for increasing voltage in a charge pump used in a phase locked loop	April, 1997	Gehrke	375/376
5627780	Testing a non-volatile memory	May, 1997	Malhi	365/185.09
5627791	Multiple bank memory with auto refresh to specified bank	May, 1997	Wright et al.	365/222
5631872	Low power consumption semiconductor dynamic random access memory device by reusing residual electric charge on bit line pairs	May, 1997	Naritake et al.	365/227
5636163	Random access memory with a plurality amplifier groups for reading and writing in normal and test modes	June, 1997	Furutani et al.	365/233
5636173	Auto-precharge during bank selection	June, 1997	Schaefer	365/230.03
5636174	Fast cycle time-low latency dynamic random access memories and systems and methods using the same	June, 1997	Rao	365/230.03
5638335	Semiconductor device	June, 1997	Akiyama et al.	365/230.03
5644743	Hybrid analog-digital phase error detector	July, 1997	Barrett et al.	375/375
5646904	Semicoductor memory with a timing controlled for receiving data at a semiconductor memory module to be accessed	July, 1997	Ohno et al.	365/233
5652530	Method and apparatus for reducing clock-data skew by clock shifting	July, 1997	Ashuri	326/93
5657289	Expandable data width SAM for a multiport RAM	August, 1997	Hush et al.	365/230.05
5657481	Memory device with a phase locked loop circuitry	August, 1997	Farmwald et al.	395/551
5663921	Internal timing method and circuit for programmable memories	September, 1997	Pascucci et al.	365/233
5666313	Semiconductor memory device with complete inhibition of boosting of word line drive signal and method thereof	September, 1997	Ichiguchi	365/195
5666322	Phase-locked loop timing controller in an integrated circuit memory	September, 1997	Conkle	365/233
5668763	Semiconductor memory for increasing the number of half good memories by selecting and using good memory blocks	September, 1997	Fujioka et al.	365/200
5668774	Dynamic semiconductor memory device having fast operation mode and operating with low current consumption	September, 1997	Furatani	365/233
5673005	Time standard circuit with delay line oscillator	September, 1997	Pricer	331/1R
5675274	Semiconductor clock signal generation circuit	October, 1997	Kobayashi et al.	327/158
5675588	Testing apparatus for transmission system	October, 1997	Maruyama et al.	371/20.4
5692165	Memory controller with low skew control signal	November, 1997	Jeddeloh et al.	395/551
5694065	Switching control circuitry for low noise CMOS inverter	December, 1997	Hamasaki et al.	327/108
5708611	Synchronous semiconductor memory device	January, 1998	Iwamoto	365/233X
5712580	Linear phase detector for half-speed quadrature clocking architecture	January, 1998	Baumgartner et al.	327/12
5712883	Clock signal distribution system	January, 1998	Miller et al.	375/371
5719508	Loss of lock detector for master timing generator	February, 1998	Daly	327/12
5737342	Method for in-chip testing of digital circuits of a synchronously sampled data detection channel	April, 1998	Ziperovich	371/25.1
5740123	Semiconductor integrated circuit for changing pulse width according to frequency of external signal	April, 1998	Uchida	365/233
5751665	Clock distributing circuit	May, 1998	Tanoi	368/120
5764092	Delay clock generator for generating a plurality of delay clocks delaying the basic clock	June, 1998	Wada et al.	327/271
5767715	Method and apparatus for generating timing pulses accurately skewed relative to clock	June, 1998	Marquis et al.	327/159
5768177	Controlled delay circuit for use in synchronized semiconductor memory	June, 1998	Sakuragi	365/194
5774699	System controller for controlling switching operations of various operation clocks for CPU, DRAM, and the like	June, 1998	Nagae	395/551
5778214	Bit-phase aligning circuit	July, 1998	Taya et al.	395/551
5781499	Semiconductor memory device	July, 1998	Koshikawa	365/233
5784422	Apparatus and method for accurate synchronization with inbound data packets at relatively low sampling rates	July, 1998	Heermann	375/355
5789947	Phase comparator	August, 1998	Sato	327/3
5790612	System and method to reduce jitter in digital delay-locked loops	August, 1998	Chengson et al.	375/373
5794020	Data transfer apparatus fetching reception data at maximum margin of timing	August, 1998	Tanaka et al.	395/552
5805931	Programmable bandwidth I/O port and a communication interface using the same port having a plurality of serial access memories capable of being configured for a variety of protocols	September, 1998	Morzano et al.	395/884
5812619	Digital phase lock loop and system for digital clock recovery	September, 1998	Runaldue	375/376
5822314	Communications system and method of operation	October, 1998	Chater-Lea	370/337
5831545	Method and apparatus for adjusting a communication strategy in a radio communication system using location	November, 1998	Murray et al.	340/825.49
5831929	Memory device with staggered data paths	November, 1998	Manning	365/233
5841707	Apparatus and method for a programmable interval timing generator in a semiconductor memory	November, 1998	Cline et al.	365/194
5852378	Low-skew differential signal converter	December, 1998	Keeth	327/171
5872959	Method and apparatus for parallel high speed data transfer	February, 1999	Nguyen et al.	395/552
5889828	Clock reproduction circuit and elements used in the same	March, 1999	Miyashita et al.	375/374
5889829	Phase locked loop with improved lock time and stability	March, 1999	Chiao et al.	375/376
5898242	Self-calibrating clock circuit employing a continuously variable delay module in a feedback loop	April, 1999	Peterson	327/278
5898674	System and method for performing non-disruptive diagnostics through a frame relay circuit	April, 1999	Mawhinney et al.	370/247
5909130	Digital lock detector for phase-locked loop	June, 1999	Martin et al.	327/12
5917760	De-skewing data signals in a memory system	June, 1999	Millar	365/194
5920518	Synchronous clock generator including delay-locked loop	July, 1999	Harrison et al.	365/233
5926047	Synchronous clock generator including a delay-locked loop signal loss detector	July, 1999	Harrison	327/159
5926436	Semiconductor memory device	July, 1999	Toda et al.	365/236
5940608	Method and apparatus for generating an internal clock signal that is synchronized to an external clock signal	August, 1999	Manning	395/551
5940609	Synchronous clock generator including a false lock detector	August, 1999	Harrison	395/559
5945855	High speed phase lock loop having high precision charge pump with error cancellation	August, 1999	Momtaz	327/157
5946244	Delay-locked loop with binary-coupled capacitor	August, 1999	Manning	365/194
5953284	Method and apparatus for adaptively adjusting the timing of a clock signal used to latch digital signals, and memory device using same	September, 1999	Baker et al.	365/233
5953386	High speed clock recovery circuit using complimentary dividers	September, 1999	Anderson	375/376
5964884	Self-timed pulse control circuit	October, 1999	Partovi et al.	713/503
5990719	Adaptive filtering scheme for sampling phase relations of clock networks	November, 1999	Dai et al.	327/244
6005694	Method and system for detecting optical faults within the optical domain of a fiber communication network	December, 1999	Liu	359/110
6005823	Memory device with pipelined column address path	December, 1999	Martin et al.	365/230.08
6011732	Synchronous clock generator including a compound delay-locked loop	January, 2000	Harrison et al.	365/194
6011822	Differential charge pump based phase locked loop or delay locked loop	January, 2000	Dreyer	375/376
6014042	Phase detector using switched capacitors	January, 2000	Nguyen	327/3
6016282	Clock vernier adjustment	January, 2000	Keeth	365/233
6021268	Method and apparatus for modeling receiver bandwidth for telecommunications analysis	February, 2000	Johnson	395/500.24
6023489	Method and apparatus for code synchronization in a global positioning system receiver	February, 2000	Hatch	375/208
6026050	Method and apparatus for adaptively adjusting the timing of a clock signal used to latch digital signals, and memory device using same	February, 2000	Baker et al.	635/233
6026134	Phase locked loop (PLL) with linear parallel sampling phase detector	February, 2000	Duffy et al.	375/376
6029250	Method and apparatus for adaptively adjusting the timing offset between a clock signal and digital signals transmitted coincident with that clock signal, and memory device and system using same	February, 2000	Keeth	713/400
6038219	User-configurable frame relay network	March, 2000	Mawhinney et al.	370/242
6067592	System having a synchronous memory device	May, 2000	Farmwald et al.	710/104
6072802	Initial synchronization method in code division multiple access reception system	June, 2000	Uhm et al.	370/441
6087857	Clock signal phase comparator	July, 2000	Wang	327/5
6101152	Method of operating a synchronous memory device	August, 2000	Farmwald et al.	365/233
6101197	Method and apparatus for adjusting the timing of signals over fine and coarse ranges	August, 2000	Keeth et al.	370/517
6105157	Salphasic timing calibration system for an integrated circuit tester	August, 2000	Miller	714/744
6115318	Clock vernier adjustment	September, 2000	Keeth	365/233
6119242	Synchronous clock generator including a false lock detector	September, 2000	Harrison	713/503
6125157	Delay-locked loop circuitry for clock delay adjustment	September, 2000	Donnelly et al.	375/371
6147905	Non-volatile semiconductor memory device	November, 2000	Seino	365/185.11
6147916	Semiconductor memory device with precharge voltage correction circuit	November, 2000	Ogura	365/203
6150889	Circuit and method for minimizing recovery time	November, 2000	Gulliver et al.	331/14
6160423	High speed source synchronous signaling for interfacing VLSI CMOS circuits to transmission lines	December, 2000	Haq	327/41
6173432	Method and apparatus for generating a sequence of clock signals	January, 2001	Harrison	716/1
6194917	XOR differential phase detector with transconductance circuit as output charge pump	February, 2001	Deng	327/12
6253360	Timing generator	June, 2001	Yoshiba	716/6
6262921	Delay-locked loop with binary-coupled capacitor	July, 2001	Manning	365/194
6269451	Method and apparatus for adjusting data timing by delaying clock signal	July, 2001	Mullarkey	713/401
6285726	10/100 mb clock recovery architecture for switches, repeaters and multi-physical layer ports	September, 2001	Gaudet	375/376
6295328	Frequency multiplier using delayed lock loop (DLL)	September, 2001	Kim et al.	375/376
6298450	Detecting states of signals	October, 2001	Liu et al.	713/502
6327196	Synchronous memory device having an adjustable data clocking circuit	December, 2001	Mullarkey	365/194
6327318	Process, voltage, temperature independent switched delay compensation scheme	December, 2001	Bhullar et al.	375/374
6338127	Method and apparatus for resynchronizing a plurality of clock signals used to latch respective digital signals, and memory device using same	January, 2002	Manning	711/167
6377646	Spread spectrum at phase lock loop (PLL) feedback path	April, 2002	Sha	375/376
6378079	Computer system having memory device with adjustable data clocking	April, 2002	Mullarkey	713/401
6430696	Method and apparatus for high speed data capture utilizing bit-to-bit timing correction, and memory device using same	August, 2002	Keeth	713/503
6438043	Adjustable I/O timing from externally applied voltage	August, 2002	Gans et al.	365/194
6442644	Memory system having synchronous-link DRAM (SLDRAM) devices and controller	August, 2002	Gustavson et al.	711/105
6484244	Method and system for storing and processing multiple memory commands	November, 2002	Manning	711/154
6493320	Automatic initialization and tuning across a high speed, plesiochronous, parallel link	December, 2002	Schober et al.	370/241
6499111	Apparatus for adjusting delay of a clock signal relative to a data signal	December, 2002	Mullarkey	713/401
6526111	Method and apparatus for phase locked loop having reduced jitter and/or frequency biasing	February, 2003	Prasad	375/376
6580531	Method and apparatus for in circuit biasing and testing of a modulated laser and optical receiver in a wavelength division multiplexing optical transceiver board	June, 2003	Swanson et al.	359/110
6665222	Synchronous dynamic random access memory device	December, 2003	Wright et al.	365/203
6694496	Flexible preamble processing for detecting a code sequence	February, 2004	Goslin et al.	716/4
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Ghayour, Mohammad H.

Williams, Lawrence B.

Dorsey & Whitney LLP

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a continuation of U.S. patent application Ser. No. 10/186,471, filed Jun. 28, 2002, now U.S. Pat. No. 7,016,451 which is a continuation of U.S. patent application Ser. No. 09/260,212, filed Mar. 1, 1999, issued Oct. 22, 2002 as U.S. Pat. No. 6,470,060 B1.

The invention claimed is:

1. A phase detector, comprising: a first phase detector circuit having first and second clock signal transition detectors and a flip-flop, each clock signal transition detector having an input to receive a respective one of first and second input clock signals, the flip-flop having first and second inputs coupled to the output of a respective one of the clock signal transition detectors and further having an output corresponding to an output of the first phase detector; a second phase detector circuit having first and second inputs to receive the first and second clock signals, respectively, and further having an output; and an output circuit having first and second inputs coupled to the outputs of the first and second phase detector circuits and further having an output, the output circuit configured to provide an output current having a first polarity, an output current having a second opposite polarity, or no output current in response to output signals from the first and second phase detector circuits.

2. The phase detector of claim 1 wherein the second phase detector circuit comprises first and second clock signal transition detectors coupled to a respective input of the second phase detector circuit, and a flip flop coupled to the first and second clock signal transition detectors, the first phase detector circuit configured to generate an output signal having a duty cycle according to the phase relationship between a first clock edge of the first and second clock signals, and the second phase detector circuit configured to generate an output signal having a duty cycle according to the phase relationship between a second clock edge of the first and second clock signals.

3. The phase detector of claim 2 wherein the output circuit comprises: a first current circuit; a second current circuit; and a switching circuit configured to selectively couple and decouple the output of the output circuit from the first and second current circuits responsive to the relative duty cycles of the output signals from the first and second phase detector circuits.

4. The phase detector of claim 3 wherein the output circuit provides a positive current in response to the output signal of the first phase detector circuit having a greater duty cycle than the output signal of the second phase detector circuit and a negative current in response to the output signal of the second phase detector circuit having a greater duty cycle than the output signal of the first phase detector circuit.

5. The phase detector of claim 1, further comprising a capacitor coupled to the output of the output circuit.

6. A phase detector, comprising: a phase detector circuit having first and second input nodes to receive first and second clock signals and further having first and second output nodes, the phase detector circuit configured to produce a first output signal at the first output node having a duty cycle related to the phase relationship between a rising edge of the first and second clock signals and produce a second output signal at the second output node having a duty cycle related to the phase relationship between a falling edge of the first and second clock signals, wherein the phase detector circuit comprises first and second circuits, each circuit including first and second transition detectors and a flip-flop coupled to the first and second transition detectors, each of the transition detectors having an input to receive a respective one of the first and second clock signals and configured to produce a respective trigger pulse provided to the flip-flop in response to a transition in the respective clock signal; and an output circuit having first and second input nodes coupled to a respective output node of the phase detector circuit and further having an output, the output circuit configured to provide an output signal having an increasing magnitude, an output signal having a decreasing magnitude, or an output signal having a constant magnitude according to the relative duty cycles of the first and second output signals.

7. The phase detector of claim 6 wherein the output circuit comprises: a first current circuit; a second current circuit; a switching circuit configured to selectively couple and decouple the output of the output circuit from the first and second current circuits responsive to the relative duty cycles of the first and second output signals; and a capacitor coupled to the output of the output circuit.

8. The phase detector of claim 7 wherein the output circuit is configured to provide a positive current in response to the first output signal having a greater duty cycle than the second output signal and a negative current in response to the second output signal having a greater duty cycle than the first output signal.

9. A phase detector, comprising: a phase detector circuit configured to generate first and second phase dependent signals indicative of the phase relationship of first and second input clock signals, the phase detector circuit comprising: first phase detector circuitry having first and second inputs to receive the first and second clock signals, respectively, and further having an output to provide a first phase dependent output signal; and second phase detector circuitry having first and second inputs to receive the first and second clock signals, respectively, and further having an output to provide a second phase dependent output signal; and a current source coupled to the phase detector circuit and configured to provide an output current having a first polarity, an output current having a second opposite polarity, or provide no output current in accordance with the first and second phase dependent signals from the phase detector circuit.

10. The phase detector of claim 9 wherein the first phase detector circuitry comprises: first and second clock signal transition detectors, each clock signal transition detector having an input to receive a respective one of first and second input clock signals and configured to produce a trigger pulse at an output in response to a transition in the respective clock signal; and a flip-flop having first and second inputs coupled to the output of a respective one of the clock signal transition detectors and further having an output corresponding to an output of the first phase detector circuitry.

11. The phase detector of claim 9 wherein the first phase detector circuitry is configured to generate the first phase dependent output signal having a duty cycle related to the phase relationship between a rising edge of the first and second input clock signals and the second phase detector circuitry is configured to generate the second phase dependent output signal having a duty cycle related to the phase relationship between a falling edge of the first and second clock signals.

12. The phase detector of claim 11 wherein the current source comprises: a first current circuit; a second current circuit; and a switching circuit configured to selectively couple and decouple an output of the current source from the first and second current circuits responsive to first and second phase dependent output signals.

13. The phase detector of claim 12 wherein the current source is configured to provide a positive current in response to the first phase dependent output signal having a greater duty cycle than the second phase dependent output signal and a negative current in response to the second phase dependent output signal having a greater duty cycle than the first phase dependent output signal.

14. The phase detector of claim 13, further comprising a capacitor coupled to the output of the current source.

15. A phase detector, comprising: a phase detector circuit configured to generate first and second phase dependent signals indicative of the phase relationship of first and second input clock signals; the phase detector circuit comprising: first phase detector circuitry having first and second inputs to receive the first and second clock signals, respectively, and further having an output to provide a first phase dependent output signal; and second phase detector circuitry having first and second inputs to receive the first and second clock signals, respectively, and further having an output to provide a second phase dependent output signal; and an output circuit coupled to the phase detector circuit and configured to provide an output signal having an increasing magnitude, a decreasing magnitude, or a constant magnitude in accordance with the first and second phase dependent signals from the phase detector circuit.

16. The phase detector of claim 15 wherein the first phase detector circuitry is configured to generate the first phase dependent output signal having a duty cycle related to the phase relationship between a rising edge of the first and second input clock signals and the second phase detector circuitry is configured to generate the second phase dependent output signal having a duty cycle related to the phase relationship between a falling edge of the first and second clock signals.

17. The phase detector of claim 15 wherein the output circuit comprises: a first current circuit; a second current circuit; a switching circuit configured to selectively couple and decouple the output of the output circuit from the first and second current circuits responsive to the relative duty cycles of the first and second output signals; and a capacitor coupled to the output of the output circuit.

18. The phase detector of claim 17 wherein the output circuit is configured to provide a positive current in response to the first output signal having a greater duty cycle than the second output signal and a negative current in response to the second output signal having a greater duty cycle than the first output signal.

TECHNICAL FIELD

This invention relates to generating a control signal and, more particularly, to generating a control signal based on the phase relationship between two input clock signals, and to memory devices and computer systems using such control signal generators.

BACKGROUND OF THE INVENTION

Conventional computer systems include a processor (not shown) coupled to a variety of memory devices, including read-only memories (“ROMs”) which traditionally store instructions for the processor, and a system memory to which the processor may write data and from which the processor may read data. The processor may also communicate with an external cache memory, which is generally a static random access memory (“SRAM”). The processor also communicates with input devices, output devices, and data storage devices.

Processors generally operate at a relatively high speed. Processors such as the Pentium® and Pentium II® microprocessors are currently available that operate at clock speeds of at least 400 MHz. However, the remaining components of existing computer systems, with the exception of SRAM cache memory, are not capable of operating at the speed of the processor. For this reason, the system memory devices, as well as the input devices, output devices, and data storage devices, are not coupled directly to the processor bus. Instead, the system memory devices are generally coupled to the processor bus through a memory controller, bus bridge or similar device, and the input devices, output devices, and data storage devices are coupled to the processor bus through a bus bridge. The memory controller allows the system memory devices to operate at a clock frequency that is substantially lower than the clock frequency of the processor. Similarly, the bus bridge allows the input devices, output devices, and data storage devices to operate at a frequency that is substantially lower than the clock frequency of the processor. Currently, for example, a processor having a 300 MHz clock frequency may be mounted on a mother board having a 66 MHz clock frequency for controlling the system memory devices and other components.

Access to system memory is a frequent operation for the processor. The time required for the processor, operating, for example, at 300 MHz, to read data from or write data to a system memory device operating at, for example, 66 MHz, greatly slows the rate at which the processor is able to accomplish its operations. Thus, much effort has been devoted to increasing the operating speed of system memory devices.

System memory devices are generally dynamic random access memories (“DRAMs”). Initially, DRAMs were asynchronous and thus did not operate at even the clock speed of the motherboard. In fact, access to asynchronous DRAMs often required that wait states be generated to halt the processor until the DRAM had completed a memory transfer. However, the operating speed of asynchronous DRAMs was successfully increased through such innovations as burst and page mode DRAMs, which did not require that an address be provided to the DRAM for each memory access. More recently, synchronous dynamic random access memories (“SDRAMs”) have been developed to allow the pipelined transfer of data at the clock speed of the motherboard. However, even SDRAMs are typically incapable of operating at the clock speed of currently available processors. Thus, SDRAMs cannot be connected directly to the processor bus, but instead must interface with the processor bus through a memory controller, bus bridge, or similar device. The disparity between the operating speed of the processor and the operating speed of SDRAMs continues to limit the speed at which processors may complete operations requiring access to system memory.

A solution to this operating speed disparity has been proposed in the form of a packetized memory device known as a SLDRAM memory device. In the SLDRAM architecture, the system memory may be coupled to the processor, either directly through the processor bus or through a memory controller. Rather than requiring that separate address and control signals be provided to the system memory, SLDRAM memory devices receive command packets that include both control and address information. The SLDRAM memory device then outputs or receives data on a data bus that may be coupled directly to the data bus portion of the processor bus. A master clock signal transmitted to each memory device is used to synchronize data transfer between the processor and memory device and also serves as a basis from which to generate internal clock signals coordinating internal memory operations.

One of the factors limiting the access speed of SLDRAM memory devices is the speed at which the command buffer of each device can store and process the command packets. The processing speed of the command buffer is dependent on the control of the relative timing between transmission of the command packets from the processor and an internal clock signal ICLK of the memory device used to trigger a latch in the command buffer to capture the command signals. Both the command signals and the ICLK signal are delayed relative to receipt of the command packet on a command bus and a command clock signal CMDCLK. Furthermore, the amount of the delay is highly variable, and it is difficult to control. If the delay of the internal clock signal ICLK cannot be precisely controlled, it may cause the latch in the command buffer to latch invalid command signals. Thus, the speed at which command packets can be applied to the memory device is limited by the delays in the memory device. Similar problems exist for other control signals in the memory device that control the operation of the memory device during each clock cycle, such as latching of data in the memory device and in a memory controller.

Consequently, the operation of a SLDRAM memory architecture necessitates the generation of a sequence of clock signals having predetermined phases relative to a master clock signal. Phase-locked and delay locked loops have been employed to ensure the precise phase relationship between clock signals. In such a closed loop, there is typically a phase detector receiving two clock signals, and a voltage controlled delay circuit through which one clock signal passes. The voltage controlled delay circuit receives control signals from the phase detector that are used adjust the variable delay value in order to establish a predetermined phase relationship between the two clock signals. For example, where the desired phase relationship between two clock signals is zero degrees, the phase detector will detect any phase difference between the two clock signals and generate a control signal that is transmitted to the voltage controlled delay circuit. The delay circuit will adjust the delay value according to the control signal until the clock signal passing through the voltage controlled delay circuit is synchronized with the other clock signal. The clock control circuitry in an SLDRAM is described in greater detail in U.S. patent application Ser. Nos. 08/879,847, 08/890,055, 08/933,324, 08/994,461, 09/146,716, and 09/150,079, which are incorporated herein by reference.

A single phase detector connected to a CMOS inverter has been used as a means of providing a control signal to the above-described voltage controlled delay circuits. As shown in FIG. 1, clock signals CLK 1 and CLK 2 are applied to two pulse generating circuits 11 , 12 , each of which includes a NAND gate 16 receiving a respective clock signal directly and through three series connected inverters 18 , 20 , 22 . The output of each pulse generating circuit 11 , 12 set and reset a flip-flop 26 formed by cross-coupled NAND gates 28 , 30 . A single output of the flip-flop 26 is connected to the gates of an inverter 36 formed by a PMOS transistor 38 and an NMOS transistor 40 . A current source 44 supplies current to the source of the PMOS transistor 38 , and a current sink 46 draws current from the source of the NMOS transistor 40 . When the output from the flip-flop 26 is low, the PMOS transistor 38 is turned ON and the NMOS transistor 40 is turned OFF. In this condition, a conductive path is created for the current source 44 to couple current to a capacitor 48 . A control signal VOUT is generated by the capacitor 48 . When the current source 44 is applying current to the capacitor 48 , the voltage of the control signal VOUT increases linearly. In the alternative case where the output from the flip-flop 26 is high, the PMOS transistor 38 is switched OFF and the NMOS transistor 40 is switched ON. The current sink 46 is then coupled to the capacitor 48 to draw current from the capacitor 48 . The voltage of the control signal VOUT then decreases linearly. As a result, the control signal VOUT has a sawtooth waveform component.

The problem with using a single phase detector connected to an inverter 36 , as shown in FIG. 1, is that even after the voltage controlled delay circuit has been adjusted so the clock signals have the predetermined phase relationship, the circuit will nevertheless continue to generate a sawtooth ripple voltage at its output. The sawtooth waveform component of the control signal VOUT is transmitted to the voltage controlled delay circuit (not shown in FIG. 1), which is forced to constantly adjust the delay value, and consequently, the phase relationship between the two clock signals CLK 1 and CLK 2 . The closed loop system will oscillate around a center-point and continue to “hunt” for the optimum control voltage value.

The result is a “phase jitter” imparted to clock signals used to latch command and data signals. Although the phase jitter introduced by the sawtooth ripple voltage may be acceptable in some applications, in high speed memory applications where the clock frequencies are high and the need to control the phase relationship between clock signals is critical, the clocks signals may fail to correctly latch command and data signals.

To accommodate the problems associated with the sawtooth ripple, the memory system designer may relax the timing requirements of the memory system by slowing down the clock frequencies and reducing the operating speed of the memory device. However, this approach defeats the primary purpose of developing high speed memory systems. Therefore, there is a need for a phase detector that generates a control signal that does not vary when the input clock signals have been adjusted to a predetermined phase relationship.

SUMMARY OF THE INVENTION

In one aspect of the invention, a phase detector having a phase detector circuit and a current source is provided. The phase detector circuit is configured to generate first and second phase dependent signals indicative of the phase relationship of first and second input clock signals. The current source is coupled to the phase detector circuit and is configured to provide an output current having a first polarity, an output current having a second opposite polarity, or provide no output current in accordance with the first and second phase dependent signals from the phase detector circuit.

In another aspect of the invention, a phase detector having a phase detector circuit and an output circuit is provided. The phase detector circuit is configured to generate first and second phase dependent signals indicative of the phase relationship of first and second input clock signals and the an output circuit is configured to provide an output signal having an increasing magnitude, a decreasing magnitude, or a constant magnitude in accordance with the first and second phase dependent signals from the phase detector circuit.

In another aspect of the invention, a phase detector having a phase detector circuit and an output circuit is provided. The phase detector circuit has first and second input nodes to receive first and second clock signals and further has first and second output nodes. The phase detector circuit is configured to produce a first output signal at the first output node and produce a second output signal at the second output node. The first output signal has a duty cycle related to the phase relationship between a rising edge of the first and second clock signals and the second output node has a duty cycle related to the phase relationship between a falling edge of the first and second clock signals. The output circuit has first and second input nodes coupled to a respective output node of the phase detector circuit and further has an output. The output circuit is configured to provide an output signal having an increasing magnitude, an output signal having a decreasing magnitude, or an output signal having a constant magnitude according to the relative duty cycles of the first and second output signals.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a logic diagram of a conventional phase detector circuit and charge pump.

FIG. 2 is a block diagram illustrating a phase detector including two phase detector circuits connected to a charge pump.

FIG. 3 is a logic diagram of the phase detector circuits of FIG. 2 in accordance with an embodiment of the present invention.

FIG. 4, comprising FIGS. 4 a - 4 c , is a timing diagram showing several of the waveforms present in the phase detector circuits.

FIG. 5 is a logic diagram of the charge pump of FIG. 2 in accordance with an embodiment of the present invention.

FIG. 6 is a block diagram of a clock generator circuit using an embodiment of the phase detector of FIG. 2.

FIG. 7 is a block diagram of a computer system using a plurality of DRAMs, each of which includes the phase detector of FIG. 2.

DETAILED DESCRIPTION OF THE INVENTION

An embodiment of a phase detector 10 in accordance with the present invention is illustrated in FIG. 2. The phase detector includes two single-to-dual signal converters 102 , 104 that receive input clock signals CLK 1 , CLK 2 , respectively, and produce complementary clock signals CLK 1 *, CLK 2 * and non-complementary clock signals CLK 1 , CLK 2 based on the original input clock signals. The single-to-dual signal converters may be implemented using a variety of designs known to one skilled in the art. For example, an inverter and transfer gate having the same propagation delay connected in parallel will produce a complementary and a non-complementary signal from an input clock signal. The CLK 1 , CLK 1 *, CLK 2 , CLK 2 * signals are transmitted to two phase detector circuits 100 , 101 that produce select signals OUT 1 , OUT 1 *, OUT 2 , OUT 2 * and transmits them to a phase dependent signal source or a charge pump 200 via signal lines 106 , 107 , 108 , 109 , respectively. The charge pump 200 in turn generates an output current IOUT according to the OUT 1 , OUT 1 * signals from the phase detector circuit 100 , and the OUT 2 , OUT 2 * signals from the phase detector circuit 101 . The IOUT current may be converted into a control signal V ₀ by capacitor 20 connected to an output 280 , and the control signal V ₀ may be used to adjust the delay value of a voltage controlled delay circuit.

FIG. 3 illustrates an embodiment of the phase detector circuits 100 , 101 in greater detail. Each detector circuit 100 , 101 consists of two signal transition detectors 110 , 120 that generate a trigger pulse upon detecting a low-to-high transition of an input clock signal it receives. Each detector circuit 100 , 101 also includes a dual output flip-flop 150 that is set and reset by the trigger pulses it receives from the signal transitions detectors 110 , 120 . Each flip-flop 150 is formed by a pair of cross-coupled NAND gates 152 , 154 . The output from the phase detector circuits 100 , 101 are applied to NAND gates 165 , 166 through inverters 161 - 164 . Each NAND gate 165 , 166 also receives a respective input signal from the flip-flop 150 . The combination of inverters 161 - 164 and NAND gates 165 , 166 creates a buffer circuit that will cause the respective NAND gates 165 , 166 to immediately switch upon receiving a trigger pulse from the respective signal transition detector, as explained below.

Each phase detector circuit 100 , 101 receives a pair of active-low control signals, SETA*, RSTA*, and SETB*, RSTB*, respectively. The SETA* and RSTA* signals are applied to the phase detector circuit 100 , and the SETB* and RSTB* signals are applied to the phase detector circuit 101 . The control signals are generated by a control circuit (not shown), and are used to put each phase detector circuit 100 , 101 into a predetermined state. Signal RSTA* is provided directly to the NAND gate 152 of the flip-flop 150 and the NAND gate 113 of the signal transition detector 120 , and signal SETA* is provided directly to the NAND gate 154 of the flip-flop 150 and the NAND gate 113 of the signal transition detector 110 . The RSTB*, SETB* signals are similarly provided to the respective NAND gates of the phase detector circuit 101 .

To illustrate the operation of the control signals, consider the effect the SETA*, RSTA* signals have on phase detector circuit 100 . During normal operation of the phase detector circuit 100 , the RSTA* and SETA* signals are both high. In this situation, the NAND gates 113 of the signal transition detectors 110 , 120 behave as inverters, and the NAND gates 152 , 154 behave as simple two input NAND gates. However, when the SETA* signal goes low, the output of the NAND gates 113 a and 154 are forced high. Consequently, the NAND gate 118 a outputs a high to the NAND gate 152 , and the NAND gate 118 b outputs a low that sets the flip-flop 150 . The OUT 1 signal is then forced high and the OUT 1 * signal is forced low. In a similar manner, when the RSTA* signal goes low, the flip-flop 150 is reset so that the OUT 1 signal is forced low and the OUT 1 * signal is forced high. Control signals RSTB* and SETB* operate in the same manner for the phase detector circuit 101 by forcing the OUT 2 , OUT 2 * signals to a predetermined state when active. To simplify the explanation of the operation of the signal transition detectors 110 , 120 , it will be assumed that the SETA*, RSTA*, SETB*, and RSTB* signals are inactive (i.e., at a high signal level).

In operation, the CLK 1 , CLK 2 signals are initially low thereby applying a low signal directly to one input of the NAND gates 118 b , 118 c and causing the inverters 116 a , 116 d to apply low signals to the other input of the NAND gates 118 a , 118 d , respectively. Thus, the NAND gates 118 a - d initially output a high signal. When the respective clock signal goes high, e.g., the CLK 1 signal, the NAND gate 118 c outputs a low signal until the high signal has propagated through inverter 112 c , NAND gate 113 c , and through series inverters 114 c , 115 c , 116 c . The inverter of 116 c then applies a low signal to the NAND gate 118 c , thereby causing the output of the NAND gate 118 c to again go high. Thus, the signal transition detector 110 outputs a low-going pulse responsive to the CLK 1 signal. The low-going pulse has a width equal to the total propagation delay through inverter 112 , NAND gate 113 , and series inverters 114 , 115 , 116 . The signal transition detectors 110 , 120 in the phase detector circuit 100 , and the signal transition detector 120 in the phase detector circuit 101 , each operate in the same manner to output a low pulse responsive to the rising edge of the clock signal to which it is connected.

The low-going pulse from each of the signal transition detectors 110 , 120 sets or resets the flip-flops 150 . More specifically, each flip-flop 150 is set by each pulse from the respective signal transition detector 110 , thereby causing the NAND gate 152 to output a high signal and the NAND gate 154 to output a low signal. Each flip-flop 150 is reset by each pulse from the respective signal transition detector 120 , thereby causing the NAND gate 152 to output a low signal and NAND gate 154 to output a high signal. The output of NAND gates 152 , 154 are then inverted by NAND gates 165 , 166 , respectively, of the buffer circuit to provide the OUT 1 , OUT 1 *, OUT 2 , OUT 2 * signals to the charge pump 200 . As a result, the OUT 1 signal is high during the period between the rising edge of the CLK 2 signal and the falling edge of the CLK 1 signal (i.e., the rising edge of the CLK 1 * signal). In a similar manner, the OUT 2 signal generated by the detector circuit 101 is high during the period between the falling edge of the CLK 2 signal (i.e., the rising edge of the CLK 2 * signal) and the rising edge of the CLK 1 signal.

To illustrate the operation of the phase detector circuits 100 , 101 , consider three situations: first, where CLK 1 and CLK 2 are in phase; second, where CLK 1 is leading CLK 2 by φ; and third, where CLK 1 is lagging CLK 2 by φ.

The phase relationship when the CLK 1 and CLK 2 signals are in phase is illustrated in FIG. 4 a . As explained above, the OUT 1 signal from the phase detector circuit 100 switches from low to high on the rising edge of the CLK 2 signal, and from high to low on the falling edge of the CLK 1 signal. Also, the OUT 2 signal from the phase detector circuit 101 switches from low to high on the falling edge of the CLK 2 signal, and from high to low on the rising edge of the CLK 1 signal. Since the CLK 1 signal is shown in FIG. 4 a as being in phase with the CLK 2 signal, the duty cycles of the OUT 1 and OUT 2 signals are both 50 percent, and the two signals will never be at the same logic level simultaneously.

Now consider the case where CLK 1 is leading CLK 2 by φ, as shown in FIG. 4 b . When CLK 1 is leading CLK 2 by φ, the OUT 1 signal from the phase detector circuit 100 and the OUT 2 signal from phase the detector circuit 101 have duty cycles less than 50 percent, and may be at a low logic level simultaneously. Finally, consider the case where CLK 1 is lagging CLK 2 by φ, as shown in FIG. 4 c . When CLK 1 is lagging CLK 2 by φ, the resulting OUT 1 and OUT 2 signals from phase detector circuits 100 and 101 , respectively, have duty cycles greater than 50 percent. Thus, the OUT 1 and OUT 2 signals may be at a high logic level simultaneously.

The OUT 1 , OUT 1 *, OUT 2 , OUT 2 * signals are transmitted from the phase detector circuits 100 , 101 on signal lines 106 , 107 , 108 , 109 , respectively, to the input of a charge pump, such as a charge pump 200 , as shown in FIG. 5. The charge pump 200 includes a charging circuit 205 , a current source 270 , and a current sink 272 . The function of the charging circuit 205 is to direct the current of the current source 270 and current sink 272 into, or out of the capacitor 20 (FIG. 2), respectively, depending upon the relative duty cycles of the OUT 1 and OUT 2 signals. Significantly, no current flows into or out of the capacitor 20 when the CLK 1 and CLK 2 signals are in phase. Thus, the resulting control signal may have virtually no ripple when the phase detector 10 (FIG. 2) is used in a voltage controlled delay circuit, as explained above. A clock signal generated using the voltage controlled delay circuit has significantly less phase jitter compared to a clock signal generated by a voltage controlled delay circuit using the phase detector of FIG. 1.

The charge pump 200 includes transistors 245 - 248 on the left leg of the charging circuit 205 to form a compensation circuit 206 to compensate for current and voltage changes in a current driving circuit formed by transistors 243 , 244 , 249 , and 250 on the right leg of the charging circuit 205 . The compensation circuit 206 is provided so that the voltage across the charging circuit 205 is relatively constant during operation, regardless of where the currents of the current source 270 and the current sink 272 are being directed.

A voltage follower 260 is connected between the output 280 of the charging circuit 205 and node 262 of the compensation circuit 206 . The voltage follower 260 provides a current path from the current source 270 to ground when current from the current sink 272 is being directed out of the capacitor 20 . The voltage follower 260 also provides a current path from the current sink 272 to the positive supply when current from the current source 270 is directed to the output 280 . As will be explained in greater detail below, both of these situations occur where the CLK 1 and CLK 2 signals are not in phase. As a result, the current through the charging circuit 205 is through two PMOS transistors and two NMOS transistors when current is being directed into or out of the capacitor 20 , namely, the transistors 242 , 244 , 247 , 251 or the transistors 241 , 245 , 250 , 252 . Similarly, in the situations where no current is being directed into or out of the capacitor 20 , the current through the charging circuit 205 is also through two PMOS transistors and two NMOS transistors, namely, the transistors 242 , 243 , 248 , 251 or the transistors 241 , 246 , 249 , 252 . Consequently, the operating points of the active transistors will remain relatively constant, and any capacitive charge pumping on the internal nodes of the charging circuit 205 will be minimized. It will be appreciated by one ordinarily skilled in the art that the transistors of the charging circuit 205 must be scaled accordingly.

To illustrate the operation of the charge pump 200 in conjunction with the phase detector circuits 100 , 101 , consider again the three situations that were described earlier: where CLK 1 and CLK 2 are in phase; where CLK 1 is leading CLK 2 by φ; and where CLK 1 is lagging CLK 2 by φ.

As shown in FIG. 4 a , when OUT 1 is low and OUT 2 is high the current provided by the current source 270 and sunk by the current sink 272 bypasses the output 280 of the charging circuit 205 and simply flows through the transistors 242 , 243 , 248 , 251 (indicated in FIG. 4 a as “ 0 (A)”). Similarly, when OUT 1 is high and OUT 2 is low current flows from the current source 270 to the current sink 272 through the transistors 241 , 246 , 249 , 252 (indicated in FIG. 4 a as “ 0 (B)”). In either case, the charging circuit 205 does not charge or discharge the capacitor 20 so the voltage on the capacitor 20 remains constant.

As shown in FIG. 4 b , when both the OUT 1 and OUT 2 signals are low, the charging circuit 205 directs the current provided by the current source 270 through the PMOS transistors 242 , 244 to charge the capacitor 20 (indicated in FIG. 4 b as “I+”). A path for the current from the current sink 272 is provided through the voltage follower 260 and the NMOS transistors 247 , 251 . During the time the OUT 1 and OUT 2 signals are at different logic levels, the charging circuit 205 does not charge or discharge the capacitor 20 so the voltage on the capacitor 20 remains constant, as was previously explained (indicated in FIG. 4 b as 0 (A) or 0 (B)).

As shown in FIG. 4 c , when both the OUT 1 and OUT 2 signals are high, the NMOS transistors 250 , 252 provide a conductive path for the current sink 272 to sink current from the capacitor 20 (indicated in FIG. 4 c as “I−”). A current path for the current of the current source 270 is provided through the voltage follower 260 and the PMOS transistors 241 , 245 . As mentioned before, whenever the OUT 1 and OUT 2 signals are at different logic levels, the charging circuit 205 does not charge or discharge the capacitor 20 so the voltage on the capacitor 20 remains constant (indicated in FIG. 4 c as 0 (A) or 0 (B)).

Any change in the control voltage V ₀ depends upon whether current is flowing into or out of the capacitor 20 , as explained above. When the CLK 1 and CLK 2 signals are in phase, as illustrated in FIG. 4 a , OUT 1 and OUT 2 never have the same logic level so no current flows either into or out of the capacitor 20 . In contrast, when the CLK 1 signal and the CLK 2 signal have different phases, OUT 1 and OUT 2 are both high or both low for a portion of each cycle. As illustrated in FIG. 4 b , when the CLK 1 signal leads the CLK 2 signal, OUT 1 and OUT 2 are low for more than 50 percent of each cycle so that OUT 1 and OUT 2 are both low for a portion of each cycle. As a result, as explained above, current flows into the capacitor 20 , thereby increasing the control voltage V ₀ . Similarly, when the CLK 1 signal lags the CLK 2 signal as illustrated in FIG. 4 c , OUT 1 and OUT 2 are high for more than 50 percent of each cycle so that OUT 1 and OUT 2 are both high for a portion of each cycle. As a result, current flows out of the capacitor 20 , thereby decreasing the control voltage V ₀ .

The discussion of the phase detector 10 has so far only considered the case where the CLK 1 and CLK 2 signals are adjusted so that they are approximately in phase. However, the phase detector 10 may be modified to produce a control signal that adjust the CLK 1 and CLK 2 signals to have a 180 degrees phase relationship. As shown in FIG. 3, the CLK 1 * and CLK 2 signals are transmitted to nodes 95 , 96 of the phase detector circuit 100 , while the CLK 1 and CLK 2 * signals are transmitted to nodes 97 , 98 of the phase detector circuit 101 , resulting in a phase detector that generates a non-varying control signal when the CLK 1 and CLK 2 signals are in phase. However, when the CLK 1 and CLK 1 * signals are reconnected to the nodes 95 and 97 , respectively, or the CLK 2 and CLK 2 * signals are reconnected to the nodes 98 and 96 , respectively, the phase detector circuits 100 , 101 transmit the OUT 1 , OUT 1 *, OUT 2 , OUT 2 * signals to the charge pump 200 so that the phase detector 10 generates a non-varying control signal when the CLK 1 and CLK 2 signals have a 180 degree phase relationship.

The current source 270 and the current sink 272 of the charge pump 200 may be of any current source circuit known in the art. In a preferred embodiment, a high-swing cascode current mirror, as described in “CMOS Circuit Design, Layout, and Simulation,” published by IEEE Press, is used for both the current source 270 and the current sink 272 . The use of this particular current source is meant for illustrative purposes only, and is not intended to limit the scope of the present invention.

The charge pump 200 (FIG. 2) has been described with respect to the embodiment illustrated in FIG. 5. However, an integrator circuit using an operational amplifier may also be used for the charge pump 200 . Such an integrator circuit is formed by coupling a capacitor across the output of the operational amplifier and the inverting input. The OUT 1 and OUT 2 signals generated by the phase detector circuits 100 and 101 are applied through two resistors of equal resistance to the non-inverting input of the operational amplifier, and the OUT 1 * and OUT 2 * signals are applied through two resistors of equal resistance to the inverting input. The resulting charge pump will generate increasing and decreasing control signals when the CLK 1 and CLK 2 signals are not in phase, and generate a control signal with virtually no ripple when the clock signals are in phase.

Shown in FIG. 6 is a block diagram of a clock generator circuit that may be used in packetized DRAMs to provide a sequence of clock signals that have predetermined phases relative to a master clock signal. The clock generator circuit contains a first delay-locked loop 301 and a second delay-locked loop 302 , each having a phase detector 10 of FIG. 2. A multiplexer 330 having a plurality of output lines coupled to respective clock drivers 314 a - n may be coupled to the first delay-lock loop 301 to couple one of the clock signals produced by the multi-tap voltage controlled delay circuit 310 to a clock output terminal 316 for use, for example, with a latch 340 to latch command data CMD DATA in packetized DRAM. The multiplexer 330 couples the input of each of the clock drivers 314 a - n to any one of the clock signals produced by the multi-tap voltage controlled delay circuit 310 .

The first delay-locked loop includes a multi-tap voltage controlled delay circuit 310 and a first phase detector 10 a . The multi-tap voltage controlled delay circuit 310 generates a sequence of clock signals on output lines 312 a - 312 n that are increasingly delayed from a first clock signal on line 312 a to a last clock signal on line 312 n . Two of the clock signals, preferably the first and last clock signals, are locked to each other using the delay-locked loop 301 so that they have a predetermined phase with respect to each other. For example, the first clock signal on line 312 a and the last clock signal on line 312 n may be locked so that they are the inverse of each other, that is, the predetermined phase relationship is 180 degrees from each other. Alternatively, the predetermined phase relationship could be 360 degrees so the first and last clock signals are in phase. The first phase detector 10 a compares the phase of the clock signals on lines 312 a and 312 n and generates the first control signal as a function of the phase difference therebetween. The first control signal is provided to the multi-tap voltage-controlled delay circuit 310 on line 311 to adjust the relative delay between the clock signal on line 312 a and line 312 n . The phase detector 10 a will continue to provide the first control signal until the first and last clock signals have obtained the predetermined phase relationship.

Likewise, the second delay-locked loop 302 includes a second voltage controlled delay circuit 320 and a second phase detector 10 b . A second delay-locked loop locks a clock signal from the multi-tap voltage controlled circuit 310 to a master clock signal CMD CLK on line 305 so that the increasingly delayed clock signals of the multi-tap voltage controlled delay circuit 310 have phase delays with respect to the CMD CLK signal. The clock signal from the multi-tap voltage controlled circuit 310 is provided to an input of the second phase detector 10 b through a simulated multiplexer 317 and a clock driver 318 . The relative phase delays of the simulated multiplexer 317 and the clock driver 318 are nearly identical to that of the multiplexer 330 and the clock drivers 314 a - n . Consequently, the phase detector 10 b will receive a clock signal having the same relative phase delay as a clock signal output by the clock drivers 314 a - n.

For example, the second delay-lock loop 302 may delay lock the first clock signal on line 312 a to the CMD CLK signal so that they have substantially the same phase, that is, the predetermined phase relationship is zero degrees from each other. The voltage controlled delay circuit 320 receives the CMD CLK signal and generates a reference clock signal on line 322 having a delay relative to the CMD CLK signal that is a function of a second control signal on line 321 . The clock signal on line 322 is provided to the multi-tap voltage controlled circuit 310 and used to generate the sequence of increasingly delayed clock signals 312 a - 312 n.

The second phase detector 10 b compares the phase of the CMD CLK signal to the phase of the first clock signal on line 312 a and generates a second control signal as a function of the difference therebetween. The clock signal provided to the phase detector 10 b is delayed through the simulated multiplexer 317 and the clock driver 318 approximately the same amount as the clock signals output by the clock drivers 314 a - n . The second control signal is used to adjust the delay value of the voltage controlled delay circuit 320 . The second control signal is provided by the second phase dete