Jeddeloh, Joseph M. (Shoreview, MN, US)

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08/26/2008

04/19/2006

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Micron Technology, Inc. (Boise, ID, US)

710/15

711/137, 710/33, 711/144, 711/154, 710/39, 710/5, 712/237

G06F3/00; G06G12/00

711/169, 710/36-39, 711/137, 710/29, 710/74, 710/15-19, 710/5-7, 711/144-146, 711/154-160, 712/233-240

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5729709	Memory controller with burst addressing circuit	March, 1998	Harness	395/405
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5822255	Semiconductor integrated circuit for supplying a control signal to a plurality of object circuits	October, 1998	Uchida	365/194
5832250	Multi set cache structure having parity RAMs holding parity bits for tag data and for status data utilizing prediction circuitry that predicts and generates the needed parity bits	November, 1998	Whittaker	395/471
5875352	Method and apparatus for multiple channel direct memory access control	February, 1999	Gentry et al.	395/843
5875454	Compressed data cache storage system	February, 1999	Craft et al.	711/113
5887159	Dynamically determining instruction hint fields	March, 1999	Burrows	395/567
5928343	Memory module having memory devices containing internal device ID registers and method of initializing same	July, 1999	Farmwald et al.	710/104
5966724	Synchronous memory device with dual page and burst mode operations	October, 1999	Ryan	711/105
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5973951	Single in-line memory module	October, 1999	Bechtolsheim et al.	365/52
5978567	System for distribution of interactive multimedia and linear programs by enabling program webs which include control scripts to define presentation by client transceiver	November, 1999	Rebane et al.	395/200.49
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6029250	Method and apparatus for adaptively adjusting the timing offset between a clock signal and digital signals transmitted coincident with that clock signal, and memory device and system using same	February, 2000	Keeth	713/400
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6038630	Shared access control device for integrated system with multiple functional units accessing external structures over multiple data buses	March, 2000	Foster et al.	710/132
6061263	Small outline rambus in-line memory module	May, 2000	Boaz et al.	365/51
6061296	Multiple data clock activation with programmable delay for use in multiple CAS latency memory devices	May, 2000	Ternullo, Jr. et al.	365/233
6067262	Redundancy analysis for embedded memories with built-in self test and built-in self repair	May, 2000	Irrinki et al.	365/201
6067649	Method and apparatus for a low power self test of a memory subsystem	May, 2000	Goodwin	714/718
6073190	System for dynamic buffer allocation comprising control logic for controlling a first address buffer and a first data buffer as a matched pair	June, 2000	Rooney	710/56
6076139	Multimedia computer architecture with multi-channel concurrent memory access	June, 2000	Welker et al.	711/104
6079008	Multiple thread multiple data predictive coded parallel processing system and method	June, 2000	Clery, III	712/11
6092158	Method and apparatus for arbitrating between command streams	July, 2000	Harriman et al.	711/151
6098158	Software-enabled fast boot	August, 2000	Lay et al.	711/162
6105075	Scatter gather memory system for a hardware accelerated command interpreter engine	August, 2000	Ghaffari	710/5
6125431	Single-chip microcomputer using adjustable timing to fetch data from an external memory	September, 2000	Kobayashi	711/154
6128703	Method and apparatus for memory prefetch operation of volatile non-coherent data	October, 2000	Bourekas et al.	711/138
6128706	Apparatus and method for a load bias--load with intent to semaphore	October, 2000	Bryg et al.	711/141
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6137709	Small outline memory module	October, 2000	Boaz et al.	365/51
6144587	Semiconductor memory device	November, 2000	Yoshida	365/189.05
6145033	Management of display FIFO requests for DRAM access wherein low priority requests are initiated when FIFO level is below/equal to high threshold value	November, 2000	Chee	710/57
6157743	Method for retrieving compressed texture data from a memory system	December, 2000	Goris et al.	382/233
6157962	Multipath I/O storage systems with multiipath I/O request mechanisms	December, 2000	Hodges et al.	710/1
6167465	System for managing multiple DMA connections between a peripheral device and a memory and performing real-time operations on data carried by a selected DMA connection	December, 2000	Parvin et al.	710/22
6167486	Parallel access virtual channel memory system with cacheable channels	December, 2000	Lee et al.	711/120
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6185676	Method and apparatus for performing early branch prediction in a microprocessor	February, 2001	Poplingher et al.	712/239
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6223301	Fault tolerant memory	April, 2001	Santeler et al.	714/6
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6243769	Dynamic buffer allocation for a computer system	June, 2001	Rooney	710/56
6243831	Computer system with power loss protection mechanism	June, 2001	Mustafa et al.	714/24
6246618	Semiconductor integrated circuit capable of testing and substituting defective memories and method thereof	June, 2001	Yamamoto et al.	365/200
6247107	Chipset configured to perform data-directed prefetching	June, 2001	Christie	711/216
6249802	Method, system, and computer program product for allocating physical memory in a distributed shared memory network	June, 2001	Richardson et al.	709/200
6252821	Method and apparatus for memory address decode in memory subsystems supporting a large number of memory devices	June, 2001	Nizar et al.	365/238.6
6256692	CardBus interface circuit, and a CardBus PC having the same	July, 2001	Yoda et al.	710/104
6272609	Pipelined memory controller	August, 2001	Jeddeloh	711/169
6285349	Correcting non-uniformity in displays	September, 2001	Smith	345/147
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6294937	Method and apparatus for self correcting parallel I/O circuitry	September, 2001	Crafts et al.	327/158
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6327642	Parallel access virtual channel memory system	December, 2001	Lee et al.	711/120
6330205	Virtual channel synchronous dynamic random access memory	December, 2001	Shimizu et al.	365/230.06
6347055	Line buffer type semiconductor memory device capable of direct prefetch and restore operations	February, 2002	Motomura	365/189.05
6349363	Multi-section cache with different attributes for each section	February, 2002	Cai et al.	711/129
6356573	Vertical cavity surface emitting laser	March, 2002	Jonsson et al.	372/46
6367074	Operation of a system	April, 2002	Bates et al.	717/11
6370068	Semiconductor memory devices and methods for sampling data therefrom based on a relative position of a memory cell array section containing the data	April, 2002	Rhee	365/196
6370611	Raid XOR operations to synchronous DRAM using a read buffer and pipelining of synchronous DRAM burst read data	April, 2002	Callison et al.	711/105
6373777	Semiconductor memory	April, 2002	Suzuki	365/230.03
6381190	Semiconductor memory device in which use of cache can be selected	April, 2002	Shinkai	365/230.03
6389514	Method and computer system for speculatively closing pages in memory	May, 2002	Rokicki	711/136
6392653	Device for processing acquisition data, in particular image data	May, 2002	Malandain et al.	345/501
6401213	Timing circuit for high speed memory	June, 2002	Jeddeloh	713/401
6405280	Packet-oriented synchronous DRAM interface supporting a plurality of orderings for data block transfers within a burst sequence	June, 2002	Ryan	711/105
6421744	Direct memory access controller and method therefor	July, 2002	Morrison et al.	710/22
6430696	Method and apparatus for high speed data capture utilizing bit-to-bit timing correction, and memory device using same	August, 2002	Keeth	713/503
6433785	Method and apparatus for improving processor to graphics device throughput	August, 2002	Garcia et al.	345/531
6434639	System for combining requests associated with one or more memory locations that are collectively associated with a single cache line to furnish a single memory operation	August, 2002	Haghighi	710/39
6434696	Method for quickly booting a computer system	August, 2002	Kang	713/2
6434736	Location based timing scheme in memory design	August, 2002	Schaecher et al.	716/17
6438622	Multiprocessor system including a docking system	August, 2002	Haghighi et al.	710/1
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6453393	Method and apparatus for interfacing to a computer memory	September, 2002	Holman et al.	711/154
6460108	Low cost data streaming mechanism	October, 2002	McCoskey et al.	710/310
6460114	Storing a flushed cache line in a memory buffer of a controller	October, 2002	Jeddeloh	711/120
6462978	Method of designing semiconductor integrated circuit device and semiconductor integrated circuit device	October, 2002	Shibata et al.	365/63
6463059	Direct memory access execution engine with indirect addressing of circular queues in addition to direct memory addressing	October, 2002	Movshovich et al.	370/389
6467013	Memory transceiver to couple an additional memory channel to an existing memory channel	October, 2002	Nizar	711/1
6470422	Buffer memory management in a system having multiple execution entities	October, 2002	Cai et al.	711/129
6473828	Virtual channel synchronous dynamic random access memory	October, 2002	Matsui	711/104
6477592	System for I/O interfacing for semiconductor chip utilizing addition of reference element to each data element in first data stream and interpret to recover data elements of second data stream	November, 2002	Chen et al.	710/52
6477614	Method for implementing multiple memory buses on a memory module	November, 2002	Leddige et al.	711/5
6477621	Parallel access virtual channel memory system	November, 2002	Lee et al.	711/120
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6487556	Method and system for providing an associative datastore within a data processing system	November, 2002	Downs et al.	707/101
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6490188	Semiconductor devices having mirrored terminal arrangements, devices including same, and methods of testing such semiconductor devices	December, 2002	Nuxoll et al.	365/63
6493803	Direct memory access controller with channel width configurability support	December, 2002	Pham et al.	711/147
6496193	Method and apparatus for fast loading of texture data into a tiled memory	December, 2002	Surti et al.	345/552
6496909	Method for managing concurrent access to virtual memory data structures	December, 2002	Schimmel	711/163
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6502161	Memory system including a point-to-point linked memory subsystem	December, 2002	Perego et al.	711/5
6505287	Virtual channel memory access controlling circuit	January, 2003	Uematsu	711/170
6523092	Cache line replacement policy enhancement to avoid memory page thrashing	February, 2003	Fanning	711/134
6523093	Prefetch buffer allocation and filtering system	February, 2003	Bogin et al.	711/137
6526483	Page open hint in transactions	February, 2003	Cho et al.	711/154
6539490	Clock distribution without clock delay or skew	March, 2003	Forbes et al.	713/401
6552564	Technique to reduce reflections and ringing on CMOS interconnections	April, 2003	Forbes et al.	326/30
6564329	System and method for dynamic clock generation	May, 2003	Cheung et al.	713/322
6587912	Method and apparatus for implementing multiple memory buses on a memory module	July, 2003	Leddige et al.	711/5
6590816	Integrated memory and method for testing and repairing the integrated memory	July, 2003	Perner	365/200
6594713	Hub interface unit and application unit interfaces for expanded direct memory access processor	July, 2003	Fuoco et al.	710/31
6594722	Mechanism for managing multiple out-of-order packet streams in a PCI host bridge	July, 2003	Willke, II et al.	710/313
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6622227	Method and apparatus for utilizing write buffers in memory control/interface	September, 2003	Zumkehr et al.	711/167
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6629220	Method and apparatus for dynamic arbitration between a first queue and a second queue based on a high priority transaction type	September, 2003	Dyer	711/158
6631440	Method and apparatus for scheduling memory calibrations based on transactions	October, 2003	Jenne et al.	711/105
6633959	Non-uniform memory access (NUMA) data processing system that provides notification of remote deallocation of shared data	October, 2003	Arimilli et al.	711/141
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6646929	Methods and structure for read data synchronization with minimal latency	November, 2003	Moss et al.	365/194
6647470	Memory device having posted write per command	November, 2003	Janzen	711/154
6658509	Multi-tier point-to-point ring memory interface	December, 2003	Bonella et al.	710/100
6662304	Method and apparatus for bit-to-bit timing correction of a high speed memory bus	December, 2003	Keeth et al.	713/400
6665202	Content addressable memory (CAM) devices that can identify highest priority matches in non-sectored CAM arrays and methods of operating same	December, 2003	Lindahl et al.	365/49
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6681292	Distributed read and write caching implementation for optimized input/output applications	January, 2004	Creta et al.	711/119
6681302	Page open hint in transactions	January, 2004	Cho et al.	711/154
6697926	Method and apparatus for determining actual write latency and accurately aligning the start of data capture with the arrival of data at a memory device	February, 2004	Johnson et al.	711/167
6704817	Computer architecture and system for efficient management of bi-directional bus	March, 2004	Steinman et al.	710/100
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6735679	Apparatus and method for optimizing access to memory	May, 2004	Herbst et al.	711/167
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6745275	Feedback system for accomodating different memory module loading	June, 2004	Chang	710/305
6751703	Data storage systems and methods which utilize an on-board cache	June, 2004	Chilton	711/113
6754812	Hardware predication for conditional instruction path branching	June, 2004	Abdallah et al.	712/234
6756661	Semiconductor device, a semiconductor module loaded with said semiconductor device and a method of manufacturing said semiconductor device	June, 2004	Tsuneda et al.	257/673
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6771538	Semiconductor integrated circuit and nonvolatile memory element	August, 2004	Shukuri et al.	365/185.05
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6799246	Memory interface for reading/writing data from/to a memory	September, 2004	Wise et al.	711/117
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6807630	Method for fast reinitialization wherein a saved system image of an operating system is transferred into a primary memory from a secondary memory	October, 2004	Lay et al.	713/2
6811320	System for connecting a fiber optic cable to an electronic device	November, 2004	Abbott	385/58
6816947	System and method for memory arbitration	November, 2004	Huffman	711/151
6820181	Method and system for controlling memory accesses to memory modules having a memory hub architecture	November, 2004	Jeddeloh et al.	711/169
6821029	High speed serial I/O technology using an optical link	November, 2004	Grung et al.	385/92
6823023	Serial bus communication system	November, 2004	Hannah	375/296
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6845409	Data exchange methods for a switch which selectively forms a communication channel between a processing unit and multiple devices	January, 2005	Talagala et al.	710/20
6889304	Memory device supporting a dynamically configurable core organization	May, 2005	Perego et al.	711/170
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Shin, Christopher

Dorsey & Whitney, LLP

CROSS-REFERENCE TO RELATED APPLICATION

This application is a continuation of pending U.S. patent application Ser. No. 10/812,950, filed Mar. 29, 2004.

The invention claimed is:

1. A memory module, comprising: a plurality of memory devices; and a memory hub coupled to the memory devices, the memory hub comprising: a link interface receiving memory requests for access to memory cells in at least one of the memory devices, at least some of the memory requests including respective memory hints providing information about the subsequent operation of the memory devices; a memory device interface coupled to the memory devices and to the link interface, the memory device interface being operable to couple memory requests to the memory devices for access to memory cells in at least one of the memory devices and to receive read data responsive to at least some of the memory requests; and a memory sequencer coupled to the link interface and the memory device interface, the memory sequencer being operable to couple memory requests to the memory device interface responsive to memory requests received from the link interface, the memory sequencer further being operable to dynamically adjust operability of the memory devices responsive to the memory hints.

2. The memory module of claim 1 wherein the memory devices are disposed on a substrate.

3. The memory module of claim 2 wherein the memory hub is disposed on the substrate.

4. The memory module of claim 1 wherein the link interface comprises an optical input/output port.

5. The memory module of claim 1 wherein at least one of the hints comprises signals placing the memory devices in a page mode.

6. The memory module of claim 5 wherein at least one of the hints comprises a number of pages to remain open.

7. The memory module of claim 1 wherein at least one of the hints comprises a prefetching hint.

8. The memory module of claim 1 wherein at least one of the hints comprises a number of cache lines that will be sent.

9. The memory module of claim 1 wherein at least one of the hints comprises a stride indicative of a sequence of addresses from which data are to be fetched.

10. The memory module of claim 1 wherein at least one of the hints comprises a number of cache lines to skip.

11. The memory module of claim 1 wherein the memory devices comprise dynamic random access memory devices.

12. The memory module of claim 1, further comprising a request decoder coupled to the link interface and the memory sequencer, the request decoder being operable to decode the hint in the memory requests.

13. A memory hub, comprising: a link interface receiving memory requests for access to memory cells in at least one of the memory devices, at least some of the memory requests including respective memory hints providing information about the subsequent operation of the memory devices; a memory device interface coupled to the memory devices, the memory device interface being operable to couple memory requests to the memory devices for access to memory cells in at least one of the memory devices and to receive read data responsive to at least some of the memory requests; and a memory sequencer coupled to the link interface and the memory device interface, the memory sequencer being operable to couple memory requests to the memory device interface responsive to memory requests received from the link interface, the memory sequencer further being operable to dynamically adjust operability of the memory devices responsive to the memory hints.

14. The memory hub of claim 13 wherein the link interface comprises an optical input/output port.

15. The memory hub of claim 13 wherein at least one of the hints comprises signals placing the memory devices in a page mode.

16. The memory hub of claim 15 wherein at least one of the hints comprises a number of pages to remain open.

17. The memory hub of claim 13 wherein at least one of the hints comprises a prefetching hint.

18. The memory hub of claim 13 wherein at least one of the hints comprises a number of cache lines that will be sent.

19. The memory hub of claim 13 wherein at least one of the hints comprises a stride indicative of a sequence of addresses from which data are to be fetched.

20. The memory hub of claim 13 wherein at least one of the hints comprises a number of cache lines to skip.

21. The memory hub of claim 13 wherein the memory devices comprise dynamic random access memory devices.

22. The memory hub of claim 13 further comprising a request decoder coupled to the link interface and the memory sequencer, the request decoder being operable to decode the hint.

23. A method of adjusting memory sequencing in a memory module containing a plurality of memory devices, comprising: generating memory requests for access to a memory device mounted on the memory module, at least some of the memory request including a memory hint, the memory hint being other than a page hint indication; providing information about the subsequent operation of the memory devices; receiving the memory requests at the memory module; adjusting operability of the memory module based on the memory hint; and coupling the memory request to the memory device responsive to the received memory request.

24. The method of claim 23 wherein the act of adjusting operability of the memory module based on the memory hint comprises adjusting operability of the memory sequencer based on the memory hint.

25. The method of claim 23 wherein the act of adjusting operability of the memory module based on the memory hint comprises adjusting operability of the memory devices based on the memory hint.

26. The method of claim 23 wherein the act of coupling the memory request to the memory device comprises coupling the memory request over a link interface comprising an optical input/output port.

27. The method of claim 23 wherein the act of adjusting operability of the memory module comprises placing the memory devices in page mode.

28. The method of claim 23 wherein act of adjusting operability of the memory module comprises leaving a number of pages open.

29. The method of claim 23 wherein the hint generated by the system controller comprises a prefetching hint.

30. The method of claim 23 wherein the hint generated by the system controller comprises a number of cache lines that will be sent.

31. The method of claim 23, wherein the hint generated by the system controller comprises a stride indicative of a sequence of addresses from which data are to be fetched.

32. The method of claim 23 wherein the hint comprises a number of cache lines to skip.

33. The method of claim 23 wherein the memory devices comprise dynamic random access memory devices.

34. The method of claim 23 further comprising decoding the hint with a request decoder.

TECHNICAL FIELD

This invention relates to computer systems, and, more particularly, to a computer system having a memory hub coupling several memory devices to a processor or other memory access device.

BACKGROUND OF THE INVENTION

Computer systems use memory devices, such as dynamic random access memory (“DRAM”) devices, to store data that are accessed by a processor. These memory devices are normally used as system memory in a computer system. In a typical computer system, the processor communicates with the system memory through a processor bus and a memory controller. The processor issues a memory request, which includes a memory command, such as a read command, and an address designating the location from which data or instructions are to be read. The memory controller uses the command and address to generate appropriate command signals as well as row and column addresses, which are applied to the system memory. In response to the commands and addresses, data are transferred between the system memory and the processor. The memory controller is often part of a system controller, which also includes bus bridge circuitry for coupling the processor bus to an expansion bus, such as a PCI bus.

Although the operating speed of memory devices has continuously increased, this increase in operating speed has not kept pace with increases in the operating speed of processors. Even slower has been the increase in operating speed of memory controllers coupling processors to memory devices. The relatively slow speed of memory controllers and memory devices limits the data bandwidth between the processor and the memory devices.

In addition to the limited bandwidth between processors and memory devices, the performance of computer systems is also limited by latency problems that increase the time required to read data from system memory devices. More specifically, when a memory device read command is coupled to a system memory device, such as a synchronous DRAM (“SDRAM”) device, the read data are output from the SDRAM device only after a delay of several clock periods. Therefore, although SDRAM devices can synchronously output burst data at a high data rate; the delay in initially providing the data can significantly slow the operating speed of a computer system using such SDRAM devices.

One approach to alleviating the memory latency problem is to use multiple memory devices coupled to the processor through a memory hub. In a memory hub architecture, a system controller or memory controller is coupled to several memory modules, each of which includes a memory hub coupled to several memory devices. The memory hub efficiently routes memory requests and responses between the controller and the memory devices. Computer systems employing this architecture can have a higher bandwidth because a processor can access one memory device while another memory device is responding to a prior memory access. For example, the processor can output write data to one of the memory devices in the system while another memory device in the system is preparing to provide read data to the processor.

Although computer systems using memory hubs may provide superior performance, they nevertheless often fail to operate at optimum speed for several reasons. For example, even though memory hubs can provide computer systems with a greater memory bandwidth, they still suffer from latency problems of the type described above. More specifically, although the processor may communicate with one memory device while another memory device is preparing to transfer data, it is sometimes necessary to receive data from one memory device before the data from another memory device can be used. In the event data must be received from one memory device before data received from another memory device can be used, the latency problem continues to slow the operating speed of such computer systems.

One technique that has been used to reduce latency in memory devices is to prefetch data, i.e., read data from system memory before a program being executed requests the data. Generally the data that are to be prefetched are selected based on a pattern of previously fetched data. The pattern may be as simple as a sequence of addresses from which data are fetched so that data can be fetched from subsequent addresses in the sequence before the data are needed by the program being executed. The pattern, which is known as a “stride,” may, of course, be more complex.

Further, even though memory hubs can provide computer systems with a greater memory bandwidth, they still suffer from throughput problems. For example, before data can be read from a particular row of memory cells, digit lines in the array are typically precharged by equilibrating the digit lines in the array. The particular row is then opened by coupling the memory cells in the row to a digit line in respective columns. A respective sense amplifier coupled between the digit lines in each column then responds to a change in voltage corresponding to the data stored in respective memory cell. Once the row has been opened, data can be coupled from each column of the open row by coupling the digit lines to a data read path. Opening a row, also referred to as a page, therefore consumes a finite amount of time and places a limit on the memory throughput.

Finally, the optimal decision of whether or not to prefetch data (and which data to prefetch), as well as whether or not to precharge or open a row, and whether or not to cache accessed data, may change over time and vary as a function of an application being executed by a processor that is coupled to the memory hub.

There is therefore a need for a computer architecture that provides the advantages of a memory hub architecture and also minimizes the latency and/or throughput problems common in such systems, thereby providing memory devices with high bandwidth, high throughput, and low latency. Such a system would also desirably allow the operation of the memory hub to change over time.

SUMMARY OF THE INVENTION

According to one aspect of the invention, a memory module and method is provided including a plurality of memory devices and a memory hub. The memory hub contains a link interface, such as an optical input/output port, that receives memory requests for access to memory cells in at least one of the memory devices. The memory hub further contains a memory device interface coupled to the, memory devices, the memory device interface being operable to couple memory requests to the memory devices for access to memory cells in at least one of the memory devices and to receive read data responsive to at least some of the memory requests. The memory hub further is coupled to a system controller, the system controller operable to generate a memory hint. The memory hub further contains a memory sequencer coupled to the link interface and the memory device interface. The memory sequencer is operable to couple memory requests to the memory device interface responsive to memory requests received from the link interface. The memory sequencer is further operable to dynamically adjust operability responsive to the memory hint.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram of a computer system according to one example of the invention in which a memory hub is included in each of a plurality of memory modules.

FIG. 2 is a block diagram of a memory hub used in the computer system of FIG. 1 according to an example of the invention.

FIG. 3 is a schematic outline of a write command packet according to one example of the invention.

FIG. 4 is a schematic outline of a read command packet according to one example of the invention.

FIG. 5 is a block diagram of a memory hub used in the computer system of FIG. 1 according to an example of the invention.

DETAILED DESCRIPTION OF THE INVENTION

A computer system 100 according to one example of the invention is shown in FIG. 1. The computer system 100 includes a processor 104 for performing various computing functions, such as executing specific software to perform specific calculations or tasks. The processor 104 includes a processor bus 106 that normally includes an address bus, a control bus, and a data bus. The processor bus 106 is typically coupled to cache memory 108 , which, as previously mentioned, is usually static random access memory (“SRAM”). Finally, the processor bus 106 is coupled to a system controller 110 , which is also sometimes referred to as a “North Bridge” or “memory controller.”

The system controller 110 serves as a communications path to the processor 104 for a variety of other components. More specifically, the system controller 110 includes a graphics port that is typically coupled to a graphics controller 112 , which is, in turn, coupled to a video terminal 114 . The system controller 110 is also coupled to one or more input devices 118 , such as a keyboard or a mouse, to allow an operator to interface with the computer system 100 . Typically, the computer system 100 also includes one or more output devices 120 , such as a printer, coupled to the processor 104 through the system controller 110 . One or more data storage devices 124 are also typically coupled to the processor 104 through the system controller 110 to allow the processor 104 to store data or retrieve data from internal or external storage media (not shown). Examples of typical storage devices 124 include hard and floppy disks, tape cassettes, and compact disk read-only memories (CD-ROMs).

The system controller 110 is coupled to several memory modules 130 a,b . . . n , which serve as system memory for the computer system 100 . The memory modules 130 are preferably coupled to the system controller 110 through a high-speed link 134 , which may be an optical or electrical communication path or some other type of communications path. The high-speed link 134 may be either a bi-directional link, or it may include two separate bi-directional links, one of which couples signals from the system controller 110 lo the memory modules 130 and the other of which couples signals from the memory modules 130 to the system controller 110 . In the event the high-speed link 134 is implemented as an optical communication path, the optical communication path may be in the form of one or more optical fibers, for example. In such case, the system controller 110 and the memory modules will include an optical input/output port or separate input and output ports coupled to the optical communication path. The memory modules 130 are shown coupled to the system controller 110 in a point-to-point coupling arrangement in which a separate segment of the high-speed link 134 is used to couple each of the memory modules 130 to either each other or to the system controller 110 . However, it will be understood that other topologies may also be used, such as a multi-drop arrangement in which the single high-speed link (not shown) is coupled to all of the memory modules 130 . A switching topology may also be used in which the system controller 110 is selectively coupled to each of the memory modules 130 through a switch (not shown). Other topologies that may be used will be apparent to one skilled in the art.

The high-speed link 134 serves as the path for communicating command, address and data signals between the system controller 110 and the memory modules. The command, address and data signals can assume a variety of formats. However, in the embodiment shown in FIG. 1, the command, address and write data signals are all embedded in memory packets that are transmitted from the system controller 100 to the memory modules 130 . Memory packets containing read data signals are embedded in packets coupled from the memory modules 130 to the system controller 110 .

Each of the memory modules 130 includes a memory hub 140 for controlling access to 32 memory devices 148 , which, in the example illustrated in FIG. 1, are synchronous dynamic random access memory (“SDRAM”) devices. However, a fewer or greater number of memory devices 148 may be used, and memory devices other than SDRAM devices may, of course, also be used. In the example illustrated in FIG. 1, the memory hubs 140 communicate over 4 independent memory channels 149 over the high-speed link 134 . In this example, although not shown in FIG. 1, 4 memory hub controllers 128 are provided, each to receive data from one memory channel 149 . A fewer or greater number of memory channels 149 may be used, however. The memory hub 140 is coupled to each of the system memory devices 148 through a bus system 150 , which normally includes a control bus, an address bus and a data bus.

A memory hub 200 according to an embodiment of the present invention is shown in FIG. 2. The memory hub 200 can be substituted for the memory hub 140 of FIG. 1. The memory hub 200 is shown in FIG. 2 as being coupled to four memory devices 240 a - d , which, in the present example are conventional SDRAM devices. In an alternative embodiment, the memory hub 200 is coupled to four different banks of memory devices, rather than merely four different memory devices 240 a - d , with each bank typically having a plurality of memory devices. However, for the purpose of providing an example, the present description will be with reference to the memory hub 200 coupled to the four memory devices 240 a - d . It will be appreciated that the necessary modifications to the memory hub 200 to accommodate multiple banks of memory is within the knowledge of those ordinarily skilled in the art.

Further included in the memory hub 200 are link interfaces 210 a - d and 212 a - d for coupling the memory module on which the memory hub 200 is located to a first high speed data link 220 and a second high speed data link 222 , respectively. As previously discussed with respect to FIG. 1, the high speed data links 220 , 222 can be implemented using an optical or electrical communication path or some other type of communication path. The link interfaces 210 a - d , 212 a - d are conventional, and include circuitry used for transferring data, command, and address information to and from the high speed data links 220 , 222 . As well known, such circuitry includes transmitter and receiver logic known in the art. It will be appreciated that those ordinarily skilled in the art have sufficient understanding to modify the link interfaces 210 a - d , 212 a - d to be used with specific types of communication paths, and that such modifications to the link interfaces 210 a - d , 212 a - d can be made without departing from the scope of the present invention. For example, in the event the high-speed data link 220 , 222 is implemented using an optical communications path, the link interfaces 210 a - d , 212 a - d will include an optical input/output port that can convert optical signals coupled through the optical communications path into electrical signals.

The link interfaces 210 a - d , 212 a - d are coupled to a switch 260 through a plurality of bus and signal lines, represented by busses 214 . The busses 214 are conventional, and include a write data bus and a read data bus, although a single bi-directional data bus may alternatively be provided to couple data in both directions through the link interfaces 210 a - d , 212 a - d . It will be appreciated by those ordinarily skilled in the art that the busses 214 are provided by way of example, and that the busses 214 may include fewer or greater signal lines, such as further including a request line and a snoop line, which can be used for maintaining cache coherency.

The link interfaces 210 a - d , 212 a - d include circuitry that allow the memory hub 200 to be connected in the system memory in a variety of configurations. For example, the point-to-point arrangement, as shown in FIG. 1, can be implemented by coupling each memory module 130 to either another memory module 130 or to the memory hub controller 128 through either the link interfaces 210 a - d or 212 a - d . This type of interconnection provides better signal coupling between the processor 104 and the memory hub 200 for several reasons, including relatively low capacitance, relatively few line discontinuities to reflect signals and relatively short signal paths. Alternatively, a multi-drop or daisy chain configuration can be implemented by coupling the memory modules in series. For example, the link interfaces 210 a - d can be used to couple a first memory module and the link interfaces 212 a - d can be used to couple a second memory module. The memory module coupled to a processor, or system controller, will be coupled thereto through one set of the link interfaces and further coupled to another memory module through the other set of link interfaces. In one embodiment of the present invention, the memory hub 200 of a memory module is coupled to the processor in a multi-drop arrangement.

The switch 260 is further coupled to four memory interfaces 270 a - d which are, in turn, coupled to the system memory devices 240 a - d , respectively. By providing a separate and independent memory interface 270 a - d for each system memory device 240 a - d , respectively, the memory hub 200 avoids bus or memory bank conflicts that typically occur with single channel memory architectures. The switch 260 is coupled to each memory interface through a plurality of bus and signal lines, represented by busses 274 . The busses 274 include a write data bus, a read data bus, and a request line. However, it will be understood that a single bi-directional data bus may alternatively be used instead of a separate write data bus and read data bus. Moreover, the busses 274 can include a greater or lesser number of signal lines than those previously described.

In an embodiment of the present invention, each memory interface 270 a - d is specially adapted to the system memory devices 240 a - d to which it is coupled. More specifically, each memory interface 270 a - d is specially adapted to provide and receive the specific signals received and generated, respectively, by the system memory device 240 a - d to which it is coupled. Also, the memory interfaces 270 a - d are capable of operating with system memory devices 240 a - d operating at different clock frequencies. As a result, the memory interfaces 270 a - d isolate the processor 104 from changes that may occur at the interface between the memory hub 230 and memory devices 240 a - d coupled to the memory hub 200 , and it provides a more controlled environment to which the memory devices 240 a - d may interface.

The switch 260 coupling the link interfaces 210 a - d , 212 a - d and the memory interfaces 270 a - d can be any of a variety of conventional or hereinafter developed switches. For example, the switch 260 may be a cross-bar switch that can simultaneously couple link interfaces 210 a - d , 212 a - d and the memory interfaces 270 a - d to each other in a variety of arrangements. The switch 260 can also be a set of multiplexers that do not provide the same level of connectivity as a cross-bar switch but nevertheless can couple the some or all of the link interfaces 210 a - d , 212 a - d to each of the memory interfaces 270 a - d . The switch 260 may also includes arbitration logic (not shown) to determine which memory accesses should receive priority over other memory accesses. Bus arbitration performing this function is well known to one skilled in the art.

With further reference to FIG. 2, each of the memory interfaces 270 a - d includes a respective memory controller 280 , a respective write buffer 282 , and a respective cache memory unit 284 . The memory controller 280 performs the same functions as a conventional memory controller by providing control, address and data signals to the system memory device 240 a - d to which it is coupled and receiving data signals from the system memory device 240 a - d to which it is coupled. The write buffer 282 and the cache memory unit 284 include the normal components of a buffer and cache memory, including a tag memory, a data memory, a comparator, and the like, as is well known in the art. The memory devices used in the write buffer 282 and the cache memory unit 284 may be either DRAM devices, static random access memory (“SRAM”) devices, other types of memory devices, or a combination of all three. Furthermore, any or all of these memory devices as well as the other components used in the cache memory unit 284 may be either embedded or stand-alone devices.

The write buffer 282 in each memory interface 270 a - d is used to store write requests while a read request is being serviced. In such a system, the processor 104 can issue a write request to a system memory device 240 a - d even if the memory device to which the write request is directed is busy servicing a prior write or read request. Using this approach, memory requests can be serviced out of order since an earlier write request can be stored in the write buffer 282 while a subsequent read request is being serviced. The ability to buffer write requests to allow a read request to be serviced can greatly reduce memory read latency since read requests can be given first priority regardless of their chronological order. For example, a series of write requests interspersed with read requests can be stored in the write buffer 282 to allow the read requests to be serviced in a pipelined manner followed by servicing the stored write requests in a pipelined manner. As a result, lengthy settling times between coupling write request to the memory devices 270 a - d and subsequently coupling read request to the memory devices 270 a - d for alternating write and read requests can be avoided.

The use of the cache memory unit 284 in each memory interface 270 a - d allows the processor 104 to receive data responsive to a read command directed to a respective system memory device 240 a - d without waiting for the memory device 240 a - d to provide such data ill the event that the data was recently read from or written to that memory device 240 a - d . The cache memory unit 284 thus reduces the read latency of the system memory devices 240 a - d to maximize the memory bandwidth of the computer system. Similarly, the processor 104 can store write data in the cache memory unit 284 and then perform other functions while the memory controller 280 in the same memory interface 270 a - d transfers the write data from the cache memory unit 284 to the system memory device 240 a - d to which it is coupled.

Further included in the memory hub 200 is a built in self-test (BIST) and diagnostic engine 290 coupled to the switch 260 through a diagnostic bus 292 . The diagnostic engine 290 is further coupled to a maintenance bus 296 , such as a System Management Bus (SMBus) or a maintenance bus according to the Joint -Test Action Group (JTAG) and IEEE 1149.1 standards. Both the SMBus and JTAG standards are well known by those ordinarily skilled in the art. Generally, the maintenance bus 296 provides a user access to the diagnostic engine 290 in order to perform memory channel and link diagnostics. For example, the user can couple a separate PC host via the maintenance bus 296 to conduct diagnostic testing or monitor memory system operation. By using the maintenance bus 296 to access diagnostic test results, issues related to the use of test probes, as previously discussed, can be avoided. It will be appreciated that the maintenance bus 296 can be modified from conventional bus standards without departing from the scope of the present invention. It will be further appreciated that the diagnostic engine 290 should accommodate the standards of the maintenance bus 296 , where such a standard maintenance bus is employed. For example, the diagnostic engine should have a maintenance bus interface compliant with the JTAG bus standard where such a maintenance bus is used.

Further included in the memory hub 200 is a DMA engine 286 coupled to the switch 260 through a bus 288 . The DMA engine 286 enables the memory hub 200 to move blocks of data from one location in the system memory to another location in the system memory without intervention from the processor 104 . The bus 288 includes a plurality of conventional bus lines and signal lines, such as address, control, data busses, and the like, for handling data transfers in the system memory. The DMA engine 286 can implement conventional DMA operations well known by those ordinarily skilled in the art. The DMA engine 286 is able to read a link list in the system memory to execute the DMA memory operations without processor intervention, thus, freeing the processor 104 and the bandwidth limited system bus from executing the memory operations. The DMA engine 286 can also include circuitry to accommodate DMA operations on multiple channels, for example, for each of the system memory devices 240 a - d . Such multiple channel DMA engines are well known in the art and can be implemented using conventional technologies.

The diagnostic engine 290 and the DMA engine 286 are preferably embedded circuits in the memory hub 200 . However, including separate a diagnostic engine and a separate DMA device coupled to the memory hub 200 is also within the scope of the present invention.

As mentioned above, the command, address and data signals are preferably coupled between the memory hub controller 128 and the memory modules 130 in the form of memory packets. In accordance with one embodiment of the present invention, a “hint,” which are bits indicative of the expected future performance of the memory modules 130 , is embedded in the memory packets and coupled to one or more of the memory hubs 140 in the memory modules 130 . The hint, or hints, modifies the behavior of one or more memory hubs 140 , as explained in greater detail below. In particular, the hint modifies the memory sequencing based on information known to or estimated by the controller 128 . For example, the controller 128 may have access to addressing information such as the memory requestor or address stride.

In one example of an addressing hint, the controller 128 communicates a command placing the hub 140 in page mode and identifying a number of pages to keep open. In another example, the controller 128 provides a hint related to prefetching—such as 1, 2, or 4 cache lines that will follow. In another example, the controller 128 communicates a stride to the hub 140 —such as skip the next 1, 2, or 4 cache lines. In another example of a hint, the controller 128 may indicate whether or not to place a particular cache line in a hub cache. Of course, other hints may be used, or other specific information provided with the hints described.

FIG. 3 depicts a write command packet 300 including a hint 301 . The write command packet 300 is generated by the controller 128 and communicated to the hub 140 . The packet 300 includes the hint 301 and a command code 302 . The write command packet 300 further includes write data 310 , write address information 305 , and may include other information such as a tag 311 , a stride 312 , a reservation 313 , a length 314 , and error check information 315 .

FIG. 4 depicts a read command packet 350 including a hint 351 . The read command packet 350 is generated by the controller 128 and communicated to the hub 140 . The packet 350 includes the hint 351 and a command code 352 . The read command packet 350 further includes read address information 355 , and may include other information such as a tag 361 , a stride 362 , a reservation 363 , a length 364 , and error check information 365 .

Read and write command packets, such as the packets 300 and 350 , are sent to the hub 140 . One implementation of the hub 140 for receiving the packets 300 and/or 350 is shown in FIG. 5. A read or write packet is received from a link in 400 . A request decoder 405 receives the packet and decodes the request and any hint or hints, which are provided to request queue 410 . The request decoder 405 further decodes a read address, and provides the read address to a comparator 415 . A write buffer queue 420 further receives packets from the link in 400 and provides a write address to the comparator 415 . The comparator 415 compares the read and write addresses, and notifies the request queue 410 of any write conflicts. If the request queue 410 identifies a read buffer hit, it accesses a prefetch buffer 425 to fulfill the request. Requests and hints are provided to a memory sequencer 430 connected to a memory interface 435 . The memory sequencer 430 acts on any hint information, and sends request over the memory interface 435 . Memory read data are coupled into the prefetch buffer 425 for storage, if appropriate.

From the foregoing it will be appreciated that, although specific embodiments of the invention have been described herein for purposes of illustration, various modifications ma)y be made without deviating from the spirit and scope of the invention. Accordingly, the invention is not limited except as by the appended claims.