Tsai, Richard H. (Alhambra, CA, US)

Plaque It!

10/760480

09/09/2008

01/21/2004

Images are available in PDF form when logged in. To view PDFs, Login  or  Create Account (Free!)

Click for automatic bibliography generation

Micron Technology, Inc. (Boise, ID, US)

250/208.1

348/302

H01L27/00; H04N3/14

250/208.1, 348/302, 250/214R

4622670	Error-correction coding for multilevel transmission system	November, 1986	Martin
4910162	Method of manufacturing decoder circuit	March, 1990	Yasaka et al.
5125048	Obtaining access to a two-dimensional portion of a digital picture signal	June, 1992	Virtue et al.	382/205
5195053	Semiconductor memory device wired to accommodate increased capacity without increasing the size of the semiconductor memory device	March, 1993	Hayano
5208875	Digital picture signal processing apparatus	May, 1993	Virtue et al.	382/260
5220518	Integrated circuit memory with non-binary array configuration	June, 1993	Haq
5295116	Row address decoder and word line driver unit with pull-down transistors operable in saturation region for rapidly driving word lines	March, 1994	Iwashita
5297085	Semiconductor memory device with redundant block and cell array	March, 1994	Choi et al.
5301162	Semiconductor random access memory device having shared sense amplifiers serving as a cache memory	April, 1994	Shimizu
5323357	Noise-free semiconductor memory device capable of disconnecting word line decoder from ground terminal	June, 1994	Kaneko
5336879	Pixel array having image forming pixel elements integral with peripheral circuit elements	August, 1994	Sauer	250/208.1
5369281	Matrix screen, particularly a large screen, and a method of manufacturing it	November, 1994	Spinnler et al.	250/370.09
5446859	Register addressing control circuit including a decoder and an index register	August, 1995	Shin et al.
5553026	Non-volatile semiconductor memory device	September, 1996	Nakai et al.
5583822	Single chip controller-memory device and a memory architecture and methods suitable for implementing the same	December, 1996	Rao
5621690	Nonvolatile memory blocking architecture and redundancy	April, 1997	Jungroth et al.
5736724	Oblique access to image data for reading dataforms	April, 1998	Ju et al.	235/462.11
5777672	Photosensitive device with juxtaposed reading registers	July, 1998	Cazaux et al.	348/316
5909026	Integrated sensor with frame memory and programmable resolution for light adaptive imaging	June, 1999	Zhou et al.	250/208.1
5949061	Active pixel sensor with switched supply row select	September, 1999	Guidash et al.	250/208.1
5978277	Bias condition and X-decoder circuit of flash memory array	November, 1999	Hsu et al.
5982680	Semiconductor memory	November, 1999	Wada
6026021	Semiconductor memory array partitioned into memory blocks and sub-blocks and method of addressing	February, 2000	Hoang
6055207	Synchronous semiconductor memory device having a column disabling circuit	April, 2000	Nam
6057539	Integrated sensor with frame memory and programmable resolution for light adaptive imaging	May, 2000	Zhou et al.	250/208.1
6204792	Ping-pong readout	March, 2001	Andersson
6236683	Image predictor	May, 2001	Mougeat et al.
6314042	Fast accessible semiconductor memory device	November, 2001	Tomishima et al.
6366526	Static random access memory (SRAM) array central global decoder system and method	April, 2002	Naffziger et al.
6424589	Semiconductor memory device and method for accessing memory cell	July, 2002	Mochida
6452149	Image input system including solid image sensing section and signal processing section	September, 2002	Yamashita et al.	250/208.1
6487315	Image decoding apparatus using pixel values from at least three reference pixels	November, 2002	Kadono
6496400	Memory architecture and addressing for optimized density in integrated circuit package or on circuit board	December, 2002	Chevallier
6529639	Modulation transfer function characterization employing phased slit reticle	March, 2003	Young	382/276
6642494	Photoelectric conversion apparatus, production method thereof, and information processing apparatus having the photoelectric conversion apparatus	November, 2003	Endo	250/208.1
6642965	Solid-state image sensing device with light-shielding member having openings spaced at an equal pitch	November, 2003	Nagata et al.	348/340
6690076	Stitched circuits larger than the maximum reticle size in sub-micron process	February, 2004	Fossum et al.	257/431
6710847	Exposure method and exposure apparatus	March, 2004	Irie	355/53
6787749	Integrated sensor with frame memory and programmable resolution for light adaptive imaging	September, 2004	Zhou et al.	250/208.1
6822682	Solid state image pickup device and its read method	November, 2004	Kawajiri et al.	348/315
6842225	Exposure apparatus, microdevice, photomask, method of exposure, and method of production of device	January, 2005	Irie	355/67
20010041297	Mask producing method	November, 2001	Nishi	430/5
20030193593	X-y addressable CMOS APS with compact pixel pitch	October, 2003	Lee et al.	348/302
20040036846	Mask producing method	February, 2004	Nishi	355/18
20040070740	Exposure method and exposure apparatus	April, 2004	Irie	355/52
20060113460	Image sensor with optimized wire routing	June, 2006	Tay	250/208.1

Whitmore, Stacey A.

Dickstein Shapiro LLP

This application is a divisional of and claims priority to U.S. Application Ser. No. 09/860,031, filed on May 16, 2001, now issued as U.S. Pat. No. 6,795,367, entitled “Layout Technique for Address Signal Lines in Decoders Including Stitched Blocks,” which claims priority to U.S. Provisional Application Ser. No. 60/204,371, filed on May 16, 2000, entitled “An Optimal Layout Technique for Row/Column Decoders to Reduce Number of Blocks,” the entirety of which are incorporated herein by reference.

The invention claimed is:

1. A method comprising: patterning a pixel section of an image sensor including pixel features having a first pitch on a surface; and patterning a decoder section of the image sensor including features having a second pitch which is smaller than the first pitch on the surface, wherein said features include routing lines, wherein a ratio of the second pitch to the first pitch is less than approximately 0.98; and wherein the first pitch is approximately 9 μm and the second pitch is approximately 8.75 μm.

2. A method comprising: patterning a pixel section of an image sensor including pixel features having a first pitch on a surface; and patterning a decoder section of the image sensor including features having a second pitch which is smaller than the first pitch on the surface, wherein said features include routing lines, wherein a ratio of the second pitch to the first pitch is less than approximately 0.95, and wherein the first pitch is approximately 18 μm and the second pitch is approximately 17 μm.

BACKGROUND

Many semiconductor processing foundries have a maximum lithographic size they may use to form a chip. A common limit, for example, is 20×20 mm ² . Making a chip larger than that maximum size may be carried out using stitching. Stitching forms different portions of the chip in different areas of the wafer. The different areas are then “stitched” together with interconnect lines to form the overall chip.

Complicated chips may require a large number of stitches to form an entire circuit. The complexity of the chips may increase the cost and defect rate of the chips and lower throughput in the chip production process.

SUMMARY

A binary decoder block according to an embodiment includes a number N of generic blocks which are stitched together. Each generic decoder block includes a number of address lines for addressing decoders in the generic decoder block, and no more than 2*(2 ^k −1)+N block address lines for addressing the generic blocks, where k is the whole number portion of log ₂ (N−1).

A gray decoder block according to an embodiment includes a number N of generic blocks which are stitched together. Each generic decoder block includes a number of address lines for addressing decoders in the generic decoder block, and no more than 2*(2 ^k −1)+2(N−1) block address lines for addressing the generic blocks.

A decoder block according to an alternate embodiment includes a number N of generic blocks which are stitched together. Each generic decoder block includes a number of address lines for addressing decoders in the generic decoder block, and no more than N block address lines. The decoder block includes a block address decoder for selecting block address lines corresponding to a selected generic block in the decoder block.

In a sensor including the decoder block and a pixel section, the features in the decoder block may have a smaller pitch than the features in the pixel section, for example, a ratio of 0.98 or less. The smaller pitch of the decoder block may provide more area on the silicon surface of the chip for the-routing liens used to stitch together the component blocks of the decoder block. Interconnects between the decoder block and the pixel section may be angled to accommodate the larger stitching sections.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic diagram of a binary decoder including four stitched generic blocks according to an embodiment.

FIG. 2 is a schematic diagram of a block address line section in a generic block for use in a binary decoder including five stitched blocks according to an embodiment.

FIG. 3 is a schematic diagram of a block address line section in a generic block for use in a gray code decoder including four stitched blocks according to an embodiment.

FIG. 4 is a schematic diagram of a block address line section in a generic block for use in a gray code decoder including five stitched blocks according to an embodiment.

FIG. 5 is a schematic diagram of a block address line section in a generic block for use in a gray code decoder including eight stitched blocks according to an embodiment.

FIG. 6 is a schematic diagram of an interconnect layout for use in a decoder block including stitched blocks according to an embodiment.

FIG. 7 is an enlarged portion of the diagram of FIG. 6 illustrating a layout for interconnect lines in the decode block.

FIG. 8 is a schematic diagram showing pixel sections and decoder sections of a pixel array.

DETAILED DESCRIPTION

The present disclosure describes a layout technique for stitching blocks together to form row and/or column decoders for use in large image sensors. These sensors are often larger than the typical reticle size of 20×20 mm ² . Thus, these sensors may need to be stitched together using several blocks. A decoder block for use in the image sensor may include a number of different blocks stitched together to form the complete decoder block. An exemplary column decoder block 100 may use 1024 column decoders 102 with a 25 μm pitch, as shown in FIG. 1. To accommodate a typical reticle size of 20×20 mm ² , requires that this block be divided into four pieces. According to an embodiment, instead of using four blocks with different designs, a block with a generic design may be used repeatedly. The use of generic blocks may save area on the reticle and reduce the complexity of the overall design.

Each generic block 104 - 107 includes 256row or column decoders 102 , numbered from 0 to 1023 in the decoder block 100 . In order to address each decoder 102 individually, each generic block includes address signal lines 112 , i.e., address signal lines NB 0 - 9 capable of generating a 10-bit address for the 1024 decoders. The signals on lines NB 0 -NB 9 are the inverse signals of lines B 0 -B 9 , respectively. The 10-bit addresses of decoders may be split logically into an 8-bit portion (NB 0 -B 7 ) to identify the 256 inblock decoder positions, and a 2-bit portion (NB 8 -B 9 ) to identify the four generic blocks 104 - 107 . The block signal lines NB 8 -B 9 are a subset of the address signal lines NB 0 -B 9 . Although FIG. 1 is described with reference to signal lines NB 0 -B 9 . for simplicity address signal lines NB 1 -B 7 are not shown.

The block signal lines are NB 8 -B 9 are interleaved such that they switch position between adjacent blocks. The position of lines N 38 and B 8 switch between each block. The bottom signal line 120 of the four lines in the NB 9 /B 9 section in a block 104 , 105 , 106 crosses over the other three lines and switches position to be the top line 122 in the next adjacent block 105 , 106 , 107 , respectively. Also, the NB 9 and B 9 lines are arranged such that the type of the top signal line 122 in the NB 9 /B 9 section changes in the sequence NB 9 , NB 9 , B 9 , B 9 in generic blocks 204204 104 - 107 . With B 9 =1 and NB 9 =0, this sequence is [0011].

Each decoder 102 in the generic block includes block addressing lines 110 representing the two most significant bits of the decoder's 10-bit address. The address signal lines 111 for each decoder 102 in the generic block are connected to the top signal line in each NB 8 /B 8 and NB 9 /B 9 sections, respectively. With the described layout, each of the generic blocks 104 - 107 has a different block addresses, [00], [10], [01], and [11], respectively.

The technique may be expanded to accommodate a larger number of generic blocks. FIG. 2 illustrates an exemplary decoder block 200 including five generic blocks 202 - 206 stitched together to provided 1280 decoders. Each decoder has an 11-bit address, including an 8-bit portion to identify the 256 in-block decoder positions, as described above, and a 3-bit portion to identify the generic block position. The block address signal lines 110 includes an NB 8 /B 8 section with two block address signal lines, an NB 9 /B 9 section with a four block address signal lines, and an NBa/Ba section, corresponding to the third bit of the block address, with five block address signal lines. Address signal lines in the NBa/Ba section are arranged such that the type of top signal lines 220 changes in the sequence [00001111]. Accordingly, in the five block example, the sequence is [00001] from block 202 to block 206 .

The number of signal lines, S(N), required for a given number of blocks, N, may be expressed by the series S (2)=2, S(3)=2+3=5, S(4)=2+4=6, S (5)=2+4+5=11, S (6)=2+4+6=12, etc., or generically by the following formula:
S ( N )=2*(2 ^k −1)+ N; k =[(log ₂ ( N− 1)], where k is the
whole number portion of the logarithm.

Decoder blocks used in very large sensors may use gray code rather than straight binary code. Gray code is an ordering of binary numbers such that only one bit changes from one state to the next. This may avoid errors, since there is no way of guaranteeing that all bits will change simultaneously at the boundary between two encoded values. For example, using straight binary, it would be possible to generate an output of 0111 ₂ (15 ₁₀ ) in going from 1110 ₂ (7 ₁₀ ) to 1000 ₂ (8 ₁₀ ).

FIG. 3 illustrates an exemplary gray code decoder block 300 including four generic blocks 302 - 305 stitched together. For the gray decoder, signal lines NB 7 and B 7 switch position between generic blocks. In each generic block 302 - 305 , the address lines of the decoders in relative positions 0-127 (first half) are connected to NB 7 , and the address lines of the decoders in relative positions 128-255 (second half) are connected to B 7 . There are four signal lines in each of the NB 8 /N 8 and NB 9 /B 9 sections. The sequence of the type of the top signal line 320 in the NB 8 /N 8 section is [0110], and the sequence of the type of the top signal line 330 in the NB 9 /B 9 section is [0011].

The technique may be expanded to accommodate a larger number of blocks. FIG. 4 illustrates an exemplary gray decoder block 400 including five generic blocks 402 - 406 stitched together to provide 1280 decoders. The NB 8 /B 8 section includes four signal lines, and each of the NB 9 /B 9 and NBa/Ba sections include five signal lines. The number of signal lines, S(N), required for a given number of blocks, N, may be expressed generically by the formula S(N) =2*(2k−1)+2 (N−1).

In an alternate embodiment, a three-bit block address line decoder 502 is used to select the block address line in a gray decoder block 500 with eight stitched generic blocks 504 - 511 , each including 512 decoders, as shown in FIG. 5. Only eight signal lines B 1 to B 8 are needed to address the eight generic blocks 504 - 511 . The technique may be expanded to accommodate a larger number of blocks. The number of signal lines, S(N), required for a given number of blocks, N, may be expressed generically by the formula S(N)=N.

For the gray decoder, signal lines A 8 b and A 8 are switched between adjacent generic blocks. For a straight binary decoder, A 8 b and A 8 are not switched.

To provide more area for the stitching routing lines between generic decoder blocks, a smaller pitch may be applied to the decoder array than the pixel pitch. FIG. 6 illustrates a decoder array 600 for use in a sensor with a 9 μm pixel pitch, where the pitch of the decoder array is reduced to 8.75 μm. In a sensor including thirty-two generic blocks, this provides an additional 8 μm of additional silicon space in which to provide the routing lines. FIG. 7 illustrates a layout for the angled connection 602 between the decoder array and the pixel array in order to minimize the distance (y 2 -yl).

A number of embodiments have been described. Nevertheless, it will be understood that various modifications may be made without departing from the spirit and scope of the invention. Accordingly, other embodiments are within the scope of the following claims.

FIG. 8 is a schematic diagram showing pixel sections 701 and decoder sections 702 of an example pixel array. The pixel sections 701 have an associated routing line 703 having a first pitch. The decoder sections 702 have an associated routing line 602 having a second pitch. Although it may not be apparent, the first pitch is larger than the second pitch.