Forbes, Leonard (Corvallis, OR, US)
Ahn, Kie Y. (Chappaqua, NY, US)
Bhattacharyya, Arup (Essex Junction, VT, US)

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11/514533

10/07/2008

08/31/2006

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Micron Technology, Inc. (Boise, ID, US)

257/325

257/E21.008, 257/E27.084, 257/E29.343, 438/240, 257/E21.267

H01L29/792; H01L21/8242

257/324, 257/310, 257/325, 257/E21.008, 257/E29.242, 257/E27.084, 438/591, 438/240, 257/410, 257/E21.267

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20070145454	SCALABLE INTEGRATED LOGIC AND NON-VOLATILE MEMORY	June, 2007	Bhattacharyya
20070181931	HAFNIUM TANTALUM OXIDE DIELECTRICS	August, 2007	Ahn et al.
20070187831	Conductive layers for hafnium silicon oxynitride films	August, 2007	Ahn et al.
20070234949	Atomic layer deposited titanium-doped indium oxide films	October, 2007	Ahn et al.

WO-0197257

December, 2001

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Coleman, David W.

Schwegman, Lundberg & Woessner, P.A.

What is claimed is:

1. An electronic device comprising: a substrate; a dielectric layer disposed on the substrate, the dielectric layer including a layer of SiLnON, the layer of SiLnON having a layered structure of one or more monolayers; and a metal electrode on and contacting the dielectric layer.

2. The electronic device of claim 1, wherein the electronic device includes a capacitor having the dielectric layer as a capacitor dielectric.

3. The electronic device of claim 1, wherein the electronic device includes a transistor in which the dielectric layer is disposed.

4. The electronic device of claim 1, wherein the electronic device includes a memory in which the dielectric layer is disposed.

5. The electronic device of claim 1, wherein the dielectric layer consists essentially of the SiLnON layer.

6. The electronic device of claim 1, wherein the electronic device includes contacts to couple the electronic device to other apparatus of a system.

7. The electronic device of claim 1, wherein the layer of SiLnON includes the SiLnON having more Si than Ln.

8. A method comprising: forming a dielectric layer on a substrate, the dielectric layer including a layer of SiLnON such that forming the layer of SiLnON includes layering a structure with one or more monolayers; and forming a metal electrode on and contacting the dielectric layer.

9. The method of claim 8, wherein the method includes using atomic layer deposition to form the layer of SiLnON.

10. The method of claim 8, wherein forming a metal electrode includes forming a metal gate of a transistor.

11. The method of claim 8, wherein forming a metal electrode includes forming an electrode of a capacitor.

12. The method of claim 8, wherein the method includes forming the dielectric layer and the metal electrode structured as a memory storage capacitor.

13. The method of claim 8, wherein the method includes forming the dielectric layer and the metal electrode structured as a capacitor in an analog integrated circuit.

14. The method of claim 8, wherein the method includes forming the dielectric layer and the metal electrode structured as a capacitor in a RF integrated circuit.

15. The method of claim 8, wherein the method includes forming the dielectric layer and the metal electrode structured as a capacitor in a mixed signal integrated circuit.

16. The method of claim 8, wherein the method includes forming the dielectric layer structured as a tunnel gate insulator in a flash memory and the metal electrode structured as a floating gate in the flash memory.

17. The method of claim 8, wherein the method includes forming the dielectric layer structured as an inter-gate insulator in a flash memory and the metal electrode structured as a control gate in the flash memory.

18. The method of claim 8, wherein the method includes forming the dielectric layer structured as a nanolaminate dielectric in a NROM flash memory.

19. The method of claim 8, wherein forming a metal electrode includes forming the metal electrode by atomic layer deposition.

20. The method of claim 8, wherein forming a metal electrode includes forming the metal electrode by substituting a desired metal material for a previously disposed substitutable material.

21. The method of claim 8, wherein forming a metal electrode includes forming a self aligned metal electrode on and contacting the dielectric layer.

22. The method of claim 10, wherein forming a metal gate of a transistor includes forming a gate of a silicon MOSFET.

23. The method of claim 10, wherein forming a metal gate of a transistor includes forming a gate of a germanium MOSFET.

24. The method of claim 10, wherein forming a metal gate of a transistor includes forming a gate of a SiGe MOSFET.

25. A method comprising: forming a dielectric layer on a substrate, the dielectric layer including a layer of SiLaON, wherein forming the layer of SiLaON includes: forming a layer of SiLaO arranged as a layered structure having one or more monolayers; and nitridizing the SiLaO to form SiLaON; and forming a metal electrode on and contacting the dielectric layer.

26. The method of claim 25, wherein forming a layer of SiLaO includes using atomic layer deposition to form the layer of SiLaO.

27. The method of claim 25, wherein nitridizing the SiLaO to form SiLaON includes nitridizing at temperatures equal to or above 500° C.

28. The method of claim 25, wherein nitridizing the SiLaO to form SiLaON includes introducing nitrogen by a microwave plasma.

29. The method of claim 25, wherein nitridizing the SiLaO to form SiLaON includes introducing nitrogen by a NH₃ anneal.

30. The method of claim 25, wherein forming a layer of SiLaO includes: forming a layer of silicon oxide by atomic layer deposition; forming a layer of lanthanum oxide by atomic layer deposition; and annealing the layer of silicon oxide with the layer of lanthanum oxide to form SiLaO.

31. A method comprising: forming a dielectric layer on a substrate, the dielectric layer including a layer of SiLaON, wherein forming the layer of SiLaON formed includes: forming a layer of SiN arranged as a layered structure having one or more monolayers; forming a layer of LaN arranged as a layered structure having one or more monolayers; annealing the layer of SiN with the layer of LaN; and oxidizing the layers of SiN and LaN to form SiLaON.

32. The method of claim 31, wherein forming the layer of SiN includes forming the layer of SiN by atomic layer deposition and forming the layer of LaN includes forming the layer of LaN by atomic layer deposition.

33. The method of claim 31, wherein the method includes forming a metal electrode on and contacting the dielectric layer.

34. The method of claim 31, wherein the annealing and the oxidizing are performed together.

35. The method of claim 31, wherein the layer of SiN and the layer of LaN are annealed and oxidized by rapid thermal oxidation to form SiLaON.

36. The method of claim 31, wherein the method includes forming alternating layers of SiN and LaN prior to annealing.

37. A method comprising: forming a dielectric layer on a substrate, the dielectric layer including a layer of SiLaON, wherein forming the layer of SiLaON includes: forming a layer of SiON arranged as a layered structure having one or more monolayers; forming a layer of LaON arranged as a layered structure having one or more monolayers; and annealing the layer of SiON with the layer of LaON to form SiLaON.

38. The method of claim 37, wherein forming the layer of SiON includes forming the layer of SiON by atomic layer deposition and forming the layer of LaON includes forming the layer of LaON by atomic layer deposition.

39. The method of claim 37, wherein the method includes forming a metal electrode on and contacting the dielectric layer.

40. The method of claim 37, wherein the method includes forming alternating layers of SiON and LaON prior to annealing.

41. A method comprising: forming a dielectric layer on a substrate, the dielectric layer including a layer of SiLaON such that forming the layer of SiLaON includes layering a structure with one or more monolayers; and forming a metal electrode on and contacting the dielectric layer, the metal electrode formed by: forming a layer of substitutable material on the dielectric layer, the substitutable material including one or more materials selected from the group consisting of carbon, polysilicon, germanium, and silicon-germanium; and substituting a desired metal material for the substitutable material to provide the metal electrode on the dielectric layer.

42. The method of claim 41, wherein the method includes using atomic layer deposition to form the layer of SiLaON.

43. The method of claim 41, wherein the method including forming a layer of the desired metal material on the layer of substitutable material and heating the layers at a temperature below the eutectic temperature of the desired metal material.

44. The method of claim 41, wherein forming a layer of substitutable material includes forming a carbon structure.

45. The method of claim 41, wherein forming a layer of substitutable material includes forming one or more of polysilicon, germanium, or silicon-germanium.

46. The method of claim 44, wherein substituting a desired metal material for the substitutable material includes substituting for the carbon structure one or more materials from the group consisting of gold, silver, a gold alloy, a silver alloy, copper, platinum, rhenium, ruthenium, rhodium, nickel, osmium, palladium, iridium, and cobalt.

47. The method of claim 45, wherein substituting a desired metal material for the substitutable material includes substituting one or more materials from the group consisting of aluminum, copper, silver, gold, and alloys of silver and gold.

48. A method comprising: forming a dielectric layer on a substrate, the dielectric layer including a layer of SiLaON wherein forming the layer of SiLaON includes layering a structure with one or more monolayers; and forming a self aligned metal electrode on and contacting the dielectric layer using a previously disposed sacrificial carbon layer on the dielectric layer and sacrificial carbon sidewall spacers adjacent to the sacrificial carbon layer.

49. The method of claim 48, wherein the method includes using atomic layer deposition to form the layer of SiLaON.

50. The method of claim 48, wherein forming a self aligned metal electrode includes forming a sacrificial carbon gate on the dielectric layer; forming sacrificial carbon sidewall spacers adjacent to the sacrificial carbon gate; forming source/drain regions for a transistor using the sacrificial carbon sidewall spacers to define the source/drain regions; replacing the sacrificial carbon sidewall spacers with non-carbon sidewall spacers; and replacing the sacrificial carbon gate with a desired metal gate material.

51. The method of claim 50, wherein replacing the sacrificial carbon sidewall spacers with non-carbon sidewall spacers includes performing a plasma oxidation process to remove the carbon sidewall spacers.

52. The method of claim 51, wherein replacing the sacrificial carbon gate with a desired metal gate material includes replacing the sacrificial carbon gate with one or more materials from a group consisting of aluminum, tungsten, molybdenum, gold, alloys of gold, silver, alloys of silver, platinum, rhenium, ruthenium, rhodium, nickel, osmium, palladium, iridium, cobalt, and germanium.

53. A method comprising: forming an array of memory cells on a substrate, each memory cell including a dielectric layer having a layer of SiLaON, wherein forming each memory cell includes: forming the layer of SiLaON by layering a structure with one or more monolayers; and forming a metal electrode on and contacting the dielectric layer.

54. The method of claim 53, wherein the method includes: forming a layer of SiLaO using atomic layer deposition; and nitridizing the SiLaO to form SiLaON.

55. The method of claim 53, wherein the method includes: forming a layer of SiN by atomic layer deposition; forming a layer of LaN by atomic layer deposition; annealing the layer of SiN with the layer of LaN; and oxidizing the layers of SiN and the LaN to form SiLaON.

56. The method of claim 53, wherein the method includes: forming a layer of SiON by atomic layer deposition; forming a layer of LaON by atomic layer deposition; and annealing the layer of SiON with the layer of LaON to form SiLaON.

57. The method of claim 53, wherein forming a metal electrode includes: forming a layer of substitutable material on the dielectric layer; and substituting a desired metal material for the substitutable material to provide the metal electrode on the dielectric layer.

58. The method of claim 53, wherein forming a metal electrode includes forming a metal gate of a transistor, the metal gate formed by: forming a sacrificial carbon gate on the dielectric layer; forming sacrificial carbon sidewall spacers adjacent to the sacrificial carbon gate; forming source/drain regions for the transistor using the sacrificial carbon sidewall spacers to define the source/drain regions; replacing the sacrificial carbon sidewall spacers with non-carbon sidewall spacers; and replacing the sacrificial carbon gate with a desired metal gate material to provide the desired metal gate material on the gate dielectric.

59. The method of claim 1, wherein forming the layer of SiLnON includes forming the SiLnON having more Si than Ln.

60. The method of claim 57, wherein forming a layer of substitutable material includes forming a structure having one of more materials of a group consisting of carbon, polysilicon, germanium, and silicon-germanium.

61. The method of claim 58, wherein replacing the sacrificial carbon gate with a desired metal gate material includes replacing the sacrificial carbon gate with one or more materials from a group consisting of aluminum, tungsten, molybdenum, gold, alloys of gold, silver, alloys of silver, platinum, rhenium, ruthenium, rhodium, nickel, osmium, palladium, iridium, cobalt, and germanium.

62. The method of claim 60, wherein substituting a desired metal material for the substitutable material includes substituting one or more materials from the group consisting of aluminum, gold, silver, a gold alloy, a silver alloy, copper, platinum, rhenium, ruthenium, rhodium, nickel, osmium, palladium, iridium, and cobalt.

63. A method comprising: providing a controller; and coupling an electronic device to the controller, the electronic device having a metal electrode disposed on a dielectric layer on a substrate for an integrated circuit, the dielectric layer having a layer of SiLaON such that forming the layer of SiLaON includes layering a structure with one or more monolayers.

64. The method of claim 63, wherein the method includes forming the layer of SiLaON using atomic layer deposition including: forming a layer of silicon oxide by atomic layer deposition; forming a layer of lanthanum oxide by atomic layer deposition; annealing the layer of silicon oxide with the layer of lanthanum oxide to form SiLaO; and nitridizing the SiLaO to form SiLaON.

65. The method of claim 63, wherein the method includes forming the layer of SiLaON using atomic layer deposition including: forming a layer of SiN by atomic layer deposition; forming a layer of LaN by atomic layer deposition; annealing the layer of SiN with the layer of LaN; and oxidizing the layers of SiN and the LaN to form SiLaON.

66. The method of claim 63, wherein the method includes forming the layer of SiLaON using atomic layer deposition including: forming a layer of SiON by atomic layer deposition; forming a layer of LaON by atomic layer deposition; and annealing the layer of SiON with the layer of LaON to form SiLaON.

67. The method of claim 63, wherein the metal electrode is formed by atomic layer deposition.

68. The method of claim 63, wherein the metal electrode is formed by substituting a desired metal material for previously disposed substitutable material.

69. The method of claim 63, wherein the metal electrode is formed by forming a self aligned metal electrode on and contacting the dielectric layer using a previously disposed sacrificial carbon gate on the dielectric layer and sacrificial carbon sidewall spacers adjacent to the sacrificial carbon gate.

70. The method of claim 63, wherein providing a controller includes providing a processor.

71. The method of claim 63, wherein coupling an electronic device to the controller includes coupling a memory to the controller.

72. The method of claim 63, wherein the method includes forming an information handling system.

73. The method of claim 72, wherein forming an information handling system includes forming a portable wireless device.

RELATED APPLICATIONS

This application is related to the co-pending and commonly assigned applications U.S. application Ser. No. 10/229,903, entitled “ATOMIC LAYER DEPOSITED HfSiON DIELECTRIC FILMS,” filed on 28 Aug. 2002, now issued as U.S. Pat. No. 7,199,023, U.S. application Ser. No. 11/216,474, entitled “LANTHANUM ALUMINUM OXYNITRIDE DIELECTRIC FILMS,” filed on 31 Aug. 2005, U.S. application Ser. No. 11/355,490, entitled “CONDUCTIVE LAYERS FOR HAFNIUM SILICON OXYNITRIDE FILMS,” filed on 16 Feb. 2006, U.S. application Ser. No. 11/010,529, entitled “ATOMIC LAYER DEPOSITED LANTHANUM HAFNIUM OXIDE DIELECTRICS,” filed on 13 Dec. 2004, now issued as U.S. Pat. No. 7,235,501, and U.S. application Ser. No. 10/352,507, entitled “Atomic layer deposition of metal oxynitride layers as gate dielectrics and semiconductor device structures utilizing metal oxynitride layer,” filed on 27 Jan. 2003, which applications are incorporated herein by reference.

This application is also related to U.S. patent applications filed herewith on the same date. These patent applications are U.S. application Ser. No. 11/514,655, entitled “ATOMIC LAYER DEPOSITED TANTALUM ALUMINUM OXYNITRIDE FILMS”, U.S. application Ser. No. 11/515,143, entitled “HAFNIUM LANTHANIDE OXYNITRIDE FILMS”, U.S. application Ser. No. 11/514,601, entitled “TANTALUM SILICON OXYNITRIDE HIGH-K DIELECTRICS AND METAL GATES”, U.S. application Ser. No. 11/514,545, entitled “TANTALUM LANTHANIDE OXYNITRIDE FILMS”, U.S. application Ser. No. 11/498,578, entitled “DEPOSITION OF ZrAlON FILMS”, U.S. application Ser. No. 11/515,114, entitled “ATOMIC LAYER DEPOSITED HAFNIUM TANTALUM OXYNITRIDE FILMS”, and U.S. application Ser. No. 11/514,558, entitled “ATOMIC LAYER DEPOSITED HAFNIUM ALUMINUM OXYNITRIDE FILMS”, which patent applications are incorporated herein by reference.

TECHNICAL FIELD

This disclosure relates generally to semiconductor devices and device fabrication.

BACKGROUND

The semiconductor device industry has a market driven need to reduce the size of devices used in products such as processor chips, mobile telephones, and memory devices such as dynamic random access memories (DRAMs). Currently, the semiconductor industry relies on the ability to reduce or scale the dimensions of its basic devices. This device scaling includes scaling a dielectric layer in devices such as, for example, capacitors and silicon-based metal oxide semiconductor field effect transistors (MOSFETs), which have primarily been fabricated using silicon dioxide. A thermally grown amorphous SiO ₂ provides an electrically and thermodynamically stable material, where the interface of the SiO ₂ layer with underlying silicon provides a high quality interface as well as superior electrical isolation properties. However, increased scaling and other requirements in microelectronic devices have created the need to use other materials as dielectric regions in a variety of electronic structures.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 depicts an embodiment of an atomic layer deposition system for processing a silicon lanthanide oxynitride film.

FIG. 2A shows a flow diagram of features of an embodiment for forming a silicon lanthanide oxynitride film using atomic layer deposition and nitridization.

FIG. 2B shows a flow diagram of features of an embodiment for forming silicon lanthanide oxide using atomic layer deposition for nitridization to a silicon lanthanide oxynitride film.

FIG. 3 shows a flow diagram of features of an embodiment for forming a silicon lanthanide oxynitride film using atomic layer deposition and oxidation.

FIG. 4 shows a flow diagram of features of an embodiment for forming silicon lanthanide oxynitride film using atomic layer deposition and annealing.

FIGS. 5A-5E illustrate an embodiment of a process for forming a metal substituted electrode.

FIG. 6 illustrates a flow diagram of features of an embodiment of a metal substitution technique.

FIGS. 7A-7D illustrate an embodiment of a process for forming a self aligned conductive layer.

FIG. 8 illustrates an embodiment of a method for forming a self aligned metal gate on high-κ gate dielectrics containing a silicon lanthanide oxynitride film.

FIG. 9 illustrates a wafer containing integrated circuits having a silicon lanthanide oxynitride film.

FIG. 10 shows an embodiment of a transistor having a dielectric layer including a silicon lanthanide oxynitride film.

FIG. 11 shows an embodiment of a floating gate transistor having a dielectric layer including a silicon lanthanide oxynitride film.

FIG. 12 shows an embodiment of a capacitor having a dielectric layer including a silicon lanthanide oxynitride film.

FIG. 13 depicts an embodiment of a dielectric layer having multiple layers including a silicon lanthanide oxynitride layer.

FIG. 14 is a simplified diagram for an embodiment of a controller coupled to an electronic device having a dielectric layer including a silicon lanthanide oxynitride film.

FIG. 15 illustrates a diagram for an embodiment of an electronic system including devices with a dielectric film including a silicon lanthanide oxynitride film.

DETAILED DESCRIPTION

The following detailed description refers to the accompanying drawings that show, by way of illustration, various embodiments of the present invention. These embodiments are described in sufficient detail to enable those skilled in the art to practice these and other embodiments. Other embodiments may be utilized, and structural, logical, and electrical changes may be made to these embodiments. The various embodiments are not necessarily mutually exclusive, as some embodiments can be combined with one or more other embodiments to form new embodiments. The following detailed description is, therefore, not to be taken in a limiting sense.

In the following description, the terms wafer and substrate may be used interchangeably to refer generally to any structure on which integrated circuits are formed and also to such structures during various stages of integrated circuit fabrication. The term substrate is understood to include a semiconductor wafer. The term substrate is also used to refer to semiconductor structures during processing and may include other layers that have been fabricated thereupon. Both wafer and substrate include doped and undoped semiconductors, epitaxial semiconductor layers supported by a base semiconductor or insulator, as well as other semiconductor structures well known to one skilled in the art. The term conductor is understood to generally include n-type and p-type semiconductors and the term insulator or dielectric is defined to include any material that is less electrically conductive than the materials referred to as conductors. The following detailed description is, therefore, not to be taken in a limiting sense.

To scale a dielectric region to reduce feature sizes to provide high density electronic devices, the dielectric region should have a reduced equivalent oxide thickness (t _eq ). The equivalent oxide thickness quantifies the electrical properties, such as capacitance, of a dielectric in terms of a representative physical thickness. t _eq is defined as the thickness of a theoretical SiO ₂ layer that would be required to have the same capacitance density as a given dielectric, ignoring leakage current and reliability considerations.

A SiO ₂ layer of thickness, t, deposited on a silicon surface will have a t _eq larger than its thickness, t. This t _eq results from the capacitance in the surface on which the SiO ₂ is deposited due to the formation of a depletion/inversion region. This depletion/inversion region can result in t _eq being from 3 to 6 Angstroms (Å) larger than the SiO ₂ thickness, t. Thus, with the semiconductor industry driving to someday scale a gate dielectric equivalent oxide thickness to less than 10 Å, the physical thickness requirement for a SiO ₂ layer used for a gate dielectric may need to be approximately 4 to 7 Å. Additional requirements on a SiO ₂ layer would depend on the electrode used in conjunction with the SiO ₂ dielectric. Using a conventional polysilicon electrode may result in an additional increase in t _eq for the SiO ₂ layer. Thus, designs for future devices may be directed towards a physical SiO ₂ dielectric layer of about 5 Å or less. Such a small thickness requirement for a SiO ₂ oxide layer creates additional problems.

Silicon dioxide is used as a dielectric layer in devices, in part, due to its electrical isolation properties in a SiO ₂ —Si based structure. This electrical isolation is due to the relatively large band gap of SiO ₂ (8.9 eV), making it a good insulator from electrical conduction. Significant reductions in its band gap may eliminate it as a material for a dielectric region in an electronic device. As the thickness of a SiO ₂ layer decreases, the number of atomic layers or monolayers of the material decreases. At a certain thickness, the number of monolayers will be sufficiently small that the SiO ₂ layer will not have a complete arrangement of atoms as in a larger or bulk layer. As a result of incomplete formation relative to a bulk structure, a thin SiO ₂ layer of only one or two monolayers may not form a full band gap. The lack of a full band gap in a SiO ₂ dielectric may cause an effective short between an underlying electrode and an overlying electrode. This undesirable property sets a limit on the physical thickness to which a SiO ₂ layer can be scaled. The minimum thickness due to this monolayer effect is thought to be about 7-8 Å. Therefore, for future devices to have a t _eq less than about 10 Å, other dielectrics than SiO ₂ need to be considered for use as a dielectric region in such future devices.

In many cases, for a typical dielectric layer, the capacitance is determined as one for a parallel plate capacitance: C=κ∈ ₀ A/t, where κ is the dielectric constant, ∈ ₀ is the permittivity of free space, A is the area of the capacitor, and t is the thickness of the dielectric. The thickness, t, of a material is related to its t _eq for a given capacitance, with SiO ₂ having a dielectric constant κ _ox =3.9, as
t =(κ/κ _ox ) t _eq =(κ/3.9) t _eq .
Thus, materials with a dielectric constant greater than that of SiO ₂ , 3.9, will have a physical thickness that can be considerably larger than a desired t _eq , while providing the desired equivalent oxide thickness. For example, an alternative dielectric material with a dielectric constant of 10 could have a thickness of about 25.6 Å to provide a t _eq of 10 Å, not including any depletion/inversion layer effects. Thus, a reduced equivalent oxide thickness for transistors can be realized by using dielectric materials with higher dielectric constants than SiO ₂ .

The thinner equivalent oxide thickness required for lower device operating voltages and smaller device dimensions may be realized by a significant number of materials, but additional fabricating requirements make determining a suitable replacement for SiO ₂ difficult. The current view for the microelectronics industry is still for silicon-based devices. This may require that the dielectric material employed be grown on a silicon substrate or a silicon layer, which places significant constraints on the substitute dielectric material. During the formation of the dielectric on the silicon layer, there exists the possibility that a small layer of SiO ₂ could be formed in addition to the desired dielectric. The result would effectively be a dielectric layer consisting of two sublayers in parallel with each other and the silicon layer on which the dielectric is formed. In such a case, the resulting capacitance would be that of two dielectrics in series. As a result, the t _eq of the dielectric layer would be the sum of the SiO ₂ thickness and a multiplicative factor of the thickness, t, of the dielectric being formed, written as
t _eq =t _{SiO 2} +(κ _ox /κ) t.
Thus, if a SiO ₂ layer is formed in the process, the t _eq is again limited by a SiO ₂ layer. In the event that a barrier layer is formed between the silicon layer and the desired dielectric in which the barrier layer prevents the formation of a SiO ₂ layer, the t _eq would be limited by the layer with the lowest dielectric constant. However, whether a single dielectric layer with a high dielectric constant or a barrier layer with a higher dielectric constant than SiO ₂ is employed, the layer interfacing with the silicon layer should provide a high quality interface.

Using SiO ₂ as a dielectric layer in a device has allowed the formation of a SiO ₂ layer that results in an amorphous dielectric. Having an amorphous structure for a dielectric provides for reducing problems of leakage current associated with grain boundaries in polycrystalline dielectrics that provide high leakage paths. Additionally, grain size and orientation changes throughout a polycrystalline dielectric can cause variations in the film's dielectric constant, along with uniformity and surface topography problems. Materials having a high dielectric constant relative to SiO ₂ may also have a crystalline form, at least in a bulk configuration. The best candidates for replacing SiO ₂ as a dielectric in a device are those that can be fabricated as a thin layer with an amorphous form and that have high dielectric constants.

Capacitor applications have used high-κ dielectric materials, which are insulating materials having a dielectric constant greater than silicon dioxide. Such high-κ dielectric materials include silicon oxynitride (SiON, κ˜6), alumina (Al ₂ O ₃ , κ˜9), and oxide/nitride composites (SiO ₂ /Si ₃ N ₄ , κ˜6). Other possible candidates include metal oxides (κ˜8-80), nitrides (κ˜7-30), oxynitrides (κ˜6-25), silicates (κ˜6-20), carbides (κ˜6-15), and complex titanates (κ˜>100). Factors for selecting appropriate materials include physical, chemical and thermal stability as well as etch-ability and stoichiometric reproducibility. In field effect transistor (FET) applications, there are other factors to consider while addressing device scalability. The selected dielectric should provide stable amorphous and adherent films in the thickness range of 1 nm to 100 nm at temperatures ranging from room temperature to 1000° C. A relatively defect-free composition that is uniform and reproducible with a fixed charge density and trap density of less than 10 ¹¹ cm ⁻² in films of such composition is a factor. A factor includes dielectric materials that provide a stable non-reactive interface with a silicon substrate such that the interface has an interface state density much less than 10 ¹¹ cm ⁻² . Such interface state densities may occur when silicon bonds at the interface are saturated with high strength covalent bonds with molecular elements of the dielectric material. Another factor deals with current transport through the dielectric that should be controlled by tunneling, which is independent of temperature, rather than by trap-assisted thermally dependent transport. The conductivity of the dielectric should be equal to or lower than SiO ₂ films when voltage is stressed to a field strength of 5×10 ⁶ V/cm. To address the current transport, a dielectric material having a bandgap greater than 5 eV and having an electron and hole barrier height greater than 2 eV at a silicon interface may be considered. An additional factor to consider is using dielectric materials with a destructive breakdown strength greater than 6×10 ⁶ V/cm. Other factors for selecting a dielectric material for use in a variety of electronic devices, such as for the dielectric in FETs, relates to processing characteristics. Such processing characteristics include compatibility with gate material, selective etch-ability, chemical inertness to contaminants, dopant and post processing environments (temperature, pressure, ambients), and intrinsic properties associated with annealing of defects/damages caused by post-processing such as ion-implantation, plasma-radiation, and gate/back-end processing.

In various embodiments, mixed metal oxynitrides (with silicon included as a metal) are constructed as dielectric films in a variety of electronic devices and systems. Most oxynitrides are thermally stable and can integrate into semiconductor device processing. With nitrogen concentration in an oxynitride film at 30% or higher, such oxynitrides are chemically inert. With processing conditions controlled to provide appropriately low partial pressures of hydrogen and ON ions, oxynitride films with a wide range of nitrogen to oxygen ratio can be deposited over a silicon substrate with low fixed charge and interface states density. On the other hand, charge trapping and transport characteristics are dependent on relative ratio of nitrogen to oxygen content in the constructed film. Films with nitrogen concentration twice that of oxygen (for example, approximately 40 atomic percent nitrogen, approximately 20 atomic percent oxygen, and approximately 40 atomic percent metal or silicon) have a lower bandgap, higher trap density, and transport characteristics dominated by Frenkel-Poole conduction. Such materials may not be well suited for gate dielectric applications. However, such films exhibit higher κ values. With increasing oxygen concentration in oxynitride films, the bandgap is raised, current leakage is reduced, and the low frequency κ value is also somewhat reduced. In addition with increasing oxygen concentration, the trap density is reduced, the trap energy depth is increased, and the carrier transport ceases to be trap-assisted, exhibits tunneling conduction, and has a weak temperature dependence, if any. In various embodiments, a dielectric layer includes an oxynitride film having approximately 30 atomic % oxygen and approximately 30-35 atomic % nitrogen. With high enough nitrogen content, oxygen-vacancy induced defects in films is negligible when compared with metal oxides.

Silicon oxynitride (SiON) has been used as a gate dielectric and gate insulator for a non-volatile FET device. Silicon oxynitride at a composition range of Si ₂ ON ₂ exhibits a dielectric constant of 6.5 and a bandgap of approximately 6.5 eV compared to a stoichiometric nitride of κ=7.5 and a bandgap of 5.1 eV. Aluminum oxynitride (AlON) is expected to have a bandgap greater than 5 eV with a κ value similar to SiON. Compared to SiON, metal oxynitrides such as ZrON, HfON, LaON, and TaON and other single metal oxynitrides are expected to have a lower bandgap.

In various embodiments, bimetal (or metal/silicon) oxynitrides based on Si, Al, Hf, La, and Ta are used as dielectric films in a variety of electronic devices and systems. These bimetal oxynitrides may provide a bandgap range from 5 eV to greater than 7 eV. Estimates for bandgaps include a bandgap of Si—Al—ON of greater than 7 eV, a bandgap of Si—Hf—ON of about 6.9 eV, a bandgap of Al—Hf—ON of about 6.8 eV, a bandgap of Si—Ta—ON of about 6 eV, a bandgap of Al—Ta—ON of about 6 eV. Bimetal oxynitrides Hf—Ta—ON, Hf—La—ON, Al—La—ON, Ta—La—ON, and Si—La—ON are estimated to exhibit significantly lower bandgaps. The κ value for Si—Al—ON is estimated at approximately 7 to 8, while the κ values for the other oxynitrides of this group are estimated to be in the range from about 15 to 25.

In an embodiment, a film of silicon lanthanide oxynitride may be used as a dielectric layer for application in a variety of electronic devices, replacing the use of silicon oxide to provide a higher dielectric constant. The silicon lanthanide oxynitride film may be formed as a silicon lanthanum oxynitride film. In other embodiments, one of more lanthanides may be used to form a silicon lanthanide oxynitride film. The lanthanide, represented by the expression Ln, may include one or more elements from the lanthanide group consisting of lanthanum (La), cerium (Ce), praseodymium (Pr), neodymium (Nd), promethium (Pm), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Th), dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm), ytterbium (Yb), and lutetium (Lu). In various embodiments, a dielectric layer may be constructed containing silicon lanthanide oxynitride formed using atomic layer deposition with a metal electrode formed in contact with the dielectric layer. The metal electrode may be formed by atomic layer deposition. The metal electrode may be formed by substituting a desired metal material for a previously disposed substitutable material. The metal electrode may be formed as a self aligned metal electrode on and contacting the dielectric layer. The metal electrode may be formed on the dielectric layer using a previously disposed sacrificial carbon layer on the dielectric layer and sacrificial carbon sidewall spacers adjacent to the sacrificial carbon layer.

The term silicon lanthanide oxynitride is used herein with respect to a composition that essentially consists of silicon, lanthanide, oxygen, and nitrogen in a form that may be stoichiometric, non-stoichiometric, or a combination of stoichiometric and non-stoichiometric. In an embodiment, the lanthanide may be lanthanum. Alternatively, the lanthanide may be one or more elements from the lanthanide group of elements. A silicon lanthanide oxynitride film may also be referred to as a silicon lanthanide oxygen nitrogen film. Other nomenclature for a composition that essentially consists of silicon, lanthanide, oxygen, and nitrogen may be known to those skilled in the art. In an embodiment, silicon lanthanide oxynitride may be formed substantially as a stoichiometric silicon lanthanide oxynitride film. In an embodiment, silicon lanthanide oxynitride may be formed substantially as a non-stoichiometric silicon lanthanide oxynitride film. In an embodiment, silicon lanthanide oxynitride may be formed substantially as a combination film of non-stoichiometric silicon lanthanide oxynitride and stoichiometric silicon lanthanide oxynitride. Herein, a silicon lanthanide oxynitride composition may be expressed as SiLnON, SiLnON _x , Si _x Ln _y O _z N _r , or other equivalent form. Herein, a silicon lanthanum oxynitride composition may be expressed as SiLaON, SiLaON _r , Si _x La _y O _z N _r , or other equivalent form. The expression SiLnON or its equivalent forms may be used to include SiLnON in a form that is stoichiometric, non-stoichiometric, or a combination of stoichiometric and non-stoichiometric silicon lanthanide oxynitride. The expressions LnO, LnO _z , or its equivalent forms may be used to include lanthanide oxide in a form that is stoichiometric, non-stoichiometric, or a combination of stoichiometric and non-stoichiometric. With respect to forms that are stoichiometric, non-stoichiometric, or a combination of stoichiometric and non-stoichiometric, expressions such as LnN, LaO, LaN, SiON, LnON, LaON, LaO _z , LaN _r , SiO _t , SiN _s , SiON _r , LnON _r , LaON _r etc. may be used in a similar manner as LnO _z . In various embodiments, a silicon lanthanide oxynitride film may be doped with elements or compounds other than silicon, lanthanide, oxygen, and nitrogen.

In an embodiment, a silicon lanthanide oxynitride dielectric film may be formed using atomic layer deposition (ALD). Forming such structures using atomic layer deposition may allow control of transitions between material layers. As a result of such control, atomic layer deposited silicon lanthanide oxynitride dielectric films can have an engineered transition with a surface on which it is formed.

ALD, also known as atomic layer epitaxy (ALE), is a modification of chemical vapor deposition (CVD) and is also called “alternatively pulsed-CVD.” In ALD, gaseous precursors are introduced one at a time to the substrate surface mounted within a reaction chamber (or reactor). This introduction of the gaseous precursors takes the form of pulses of each gaseous precursor. In a pulse of a precursor gas, the precursor gas is made to flow into a specific area or region for a short period of time. Between the pulses, the reaction chamber may be purged with a gas, where the purging gas may be an inert gas. Between the pulses, the reaction chamber may be evacuated. Between the pulses, the reaction chamber may be purged with a gas and evacuated.

In a chemisorption-saturated ALD (CS-ALD) process, during the first pulsing phase, reaction with the substrate occurs with the precursor saturatively chemisorbed at the substrate surface. Subsequent pulsing with a purging gas removes precursor excess from the reaction chamber.

The second pulsing phase introduces another precursor on the substrate where the growth reaction of the desired film takes place. Subsequent to the film growth reaction, reaction byproducts and precursor excess are purged from the reaction chamber. With favorable precursor chemistry where the precursors absorb and react with each other aggressively on the substrate, one ALD cycle can be performed in less than one second in properly designed flow type reaction chambers. Typically, precursor pulse times range from about 0.5 sec to about 2 to 3 seconds. Pulse times for purging gases may be significantly longer, for example, pulse times of about 5 to about 30 seconds.

In ALD, the saturation of all the reaction and purging phases makes the growth self-limiting. This self-limiting growth results in large area uniformity and conformality, which has important applications for such cases as planar substrates, deep trenches, and in the processing of porous silicon and high surface area silica and alumina powders. Atomic layer deposition provides control of film thickness in a straightforward manner by controlling the number of growth cycles.

The precursors used in an ALD process may be gaseous, liquid or solid. However, liquid or solid precursors should be volatile. The vapor pressure should be high enough for effective mass transportation. Also, solid and some liquid precursors may need to be heated inside the atomic layer deposition system and introduced through heated tubes to the substrates. The necessary vapor pressure should be reached at a temperature below the substrate temperature to avoid the condensation of the precursors on the substrate. Due to the self-limiting growth mechanisms of ALD, relatively low vapor pressure solid precursors can be used, though evaporation rates may vary somewhat during the process because of changes in their surface area.

There are several other characteristics for precursors used in ALD. The precursors should be thermally stable at the substrate temperature, because their decomposition may destroy the surface control of the ALD method that relies on the reaction of the precursor at the substrate surface. A slight decomposition, if slow compared to the ALD growth, may be tolerated.

The precursors should chemisorb on or react with the surface, though the interaction between the precursor and the surface as well as the mechanism for the adsorption is different for different precursors. The molecules at the substrate surface should react aggressively with the second precursor to form the desired solid film. Additionally, precursors should not react with the film to cause etching, and precursors should not dissolve in the film. Using highly reactive precursors in ALD contrasts with the selection of precursors for conventional CVD.

The by-products in the reaction should be gaseous in order to allow their easy removal from the reaction chamber. Further, the by-products should not react or adsorb on the surface.

In a reaction sequence ALD (RS-ALD) process, the self-limiting process sequence involves sequential surface chemical reactions. RS-ALD relies on chemistry between a reactive surface and a reactive molecular precursor. In an RS-ALD process, molecular precursors are pulsed into the ALD reaction chamber separately. A metal precursor reaction at the substrate may be followed by an inert gas pulse to remove excess precursor and by-products from the reaction chamber prior to pulsing the next precursor of the fabrication sequence.

By RS-ALD, films can be layered in equal metered sequences that may all be identical in chemical kinetics, deposition per cycle, composition, and thickness. RS-ALD sequences generally deposit less than a full layer per cycle. Typically, a deposition or growth rate of about 0.25 to about 2.00 Å per RS-ALD cycle may be realized.

Processing by RS-ALD provides continuity at an interface avoiding poorly defined nucleating regions that are typical for chemical vapor deposition (<20 Å) and physical vapor deposition (<50 Å), conformality over a variety of substrate topologies due to its layer-by-layer deposition technique, use of low temperature and mildly oxidizing processes, lack of dependence on the reaction chamber, growth thickness dependent solely on the number of cycles performed, and ability to engineer multilayer laminate films with a resolution of one to two monolayers. RS-ALD processes allow for deposition control on the order of monolayers and the ability to deposit monolayers of amorphous films.

Herein, a sequence refers to the ALD material formation based on an ALD reaction of a precursor with its reactant precursor. For example, forming silicon nitride from a SiCl ₄ precursor and NH ₃ , as its reactant precursor, includes a silicon/nitrogen sequence. In various ALD processes that form a nitride or a composition that contains nitrogen, a reactant precursor that contains nitrogen is used to supply nitrogen. Herein, a precursor that contains nitrogen and that supplies nitrogen to be incorporated in the ALD composition formed, which may be used in an ALD process with precursors supplying the other elements in the ALD composition, is referred to as a nitrogen reactant precursor. In the above example, NH ₃ is a nitrogen reactant precursor. Similarly, an ALD