Campbell, Kristy A. (Boise, ID, US)
Daley, Jon (Boise, ID, US)
Brooks, Joseph F. (Nampa, ID, US)

Plaque It!

11/892003

10/07/2008

08/17/2007

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Micron Technolohy, Inc. (Boise, ID, US)

438/95

257/4, 365/163

G11C11/00; H01L47/00; H01L21/00

438/95, 365/100, 257/2-4, 365/163, 365/148

3271591	Symmetrical current controlling device	September, 1966	Ovshinsky
3622319	NONREFLECTING PHOTOMASKS AND METHODS OF MAKING SAME	November, 1971	Sharp
3743847	AMORPHOUS SILICON FILM AS A UV FILTER	July, 1973	Boland
3961314	Structure and method for producing an image	June, 1976	Klose et al.
3966317	Dry process production of archival microform records from hard copy	June, 1976	Wacks et al.
3983542	Method and apparatus for recording information	September, 1976	Ovshinsky
3988720	Recording and retrieving information in an amorphous memory material using a catalytic material	October, 1976	Ovshinsky
4177474	High temperature amorphous semiconductor member and method of making the same	December, 1979	Ovshinsky
4267261	Method for full format imaging	May, 1981	Hallman et al.
4269935	Process of doping silver image in chalcogenide layer	May, 1981	Masters et al.
4312938	Method for making a broadband reflective laser recording and data storage medium with absorptive underlayer	January, 1982	Drexler et al.
4316946	Surface sensitized chalcogenide product and process for making and using the same	February, 1982	Masters et al.
4320191	Pattern-forming process	March, 1982	Yoshikawa et al.
4405710	Ion beam exposure of (g-Ge.sub.x -Se.sub.1-x) inorganic resists	September, 1983	Balasubramanyam et al.
4419421	Ion conductor material	December, 1983	Wichelhaus et al.
4499557	Programmable cell for use in programmable electronic arrays	February, 1985	Holmberg et al.
4597162	Method for making, parallel preprogramming or field programming of electronic matrix arrays	July, 1986	Johnson et al.
4608296	Superconducting films and devices exhibiting AC to DC conversion	August, 1986	Keem et al.
4637895	Gas mixtures for the vapor deposition of semiconductor material	January, 1987	Ovshinsky et al.
4646266	Programmable semiconductor structures and methods for using the same	February, 1987	Ovshinsky et al.
4664939	Vertical semiconductor processor	May, 1987	Ovshinsky
4668968	Integrated circuit compatible thin film field effect transistor and method of making same	May, 1987	Ovshinsky et al.
4670763	Thin film field effect transistor	June, 1987	Ovshinsky et al.
4671618	Liquid crystalline-plastic material having submillisecond switch times and extended memory	June, 1987	Wu et al.
4673957	Integrated circuit compatible thin film field effect transistor and method of making same	June, 1987	Ovshinsky et al.
4678679	Continuous deposition of activated process gases	July, 1987	Ovshinsky
4696758	Gas mixtures for the vapor deposition of semiconductor material	September, 1987	Ovshinsky et al.
4698234	Vapor deposition of semiconductor material	October, 1987	Ovshinsky et al.
4710899	Data storage medium incorporating a transition metal for increased switching speed	December, 1987	Young et al.
4728406	Method for plasma - coating a semiconductor body	March, 1988	Banerjee et al.
4737379	Plasma deposited coatings, and low temperature plasma method of making same	April, 1988	Hudgens et al.
4766471	Thin film electro-optical devices	August, 1988	Ovshinsky et al.
4769338	Thin film field effect transistor and method of making same	September, 1988	Ovshinsky et al.
4775425	P and n-type microcrystalline semiconductor alloy material including band gap widening elements, devices utilizing same	October, 1988	Guha et al.
4788594	Solid state electronic camera including thin film matrix of photosensors	November, 1988	Ovshinsky et al.
4795657	Method of fabricating a programmable array	January, 1989	Formigoni et al.
4800526	Memory element for information storage and retrieval system and associated process	January, 1989	Lewis
4809044	Thin film overvoltage protection devices	February, 1989	Pryor et al.
4818717	Method for making electronic matrix arrays	April, 1989	Johnson et al.
4843443	Thin film field effect transistor and method of making same	June, 1989	Ovshinsky et al.
4845533	Thin film electrical devices with amorphous carbon electrodes and method of making same	July, 1989	Pryor et al.
4847674	High speed interconnect system with refractory non-dogbone contacts and an active electromigration suppression mechanism	July, 1989	Sliwa et al.
4853785	Electronic camera including electronic signal storage cartridge	August, 1989	Ovshinsky et al.
4891330	Method of fabricating n-type and p-type microcrystalline semiconductor alloy material including band gap widening elements	January, 1990	Guha et al.
5128099	Congruent state changeable optical memory material and device	July, 1992	Strand et al.
5159661	Vertically interconnected parallel distributed processor	October, 1992	Ovshinsky et al.
5166758	Electrically erasable phase change memory	November, 1992	Ovshinsky et al.
5177567	Thin-film structure for chalcogenide electrical switching devices and process therefor	January, 1993	Klersy et al.
5219788	Bilayer metallization cap for photolithography	June, 1993	Abernathey et al.
5238862	Method of forming a stacked capacitor with striated electrode	August, 1993	Blalock et al.
5272359	Reversible non-volatile switch based on a TCNQ charge transfer complex	December, 1993	Nagasubramanian et al.
5296716	Electrically erasable, directly overwritable, multibit single cell memory elements and arrays fabricated therefrom	March, 1994	Ovshinsky et al.
5314772	High resolution, multi-layer resist for microlithography and method therefor	May, 1994	Kozicki
5315131	Electrically reprogrammable nonvolatile memory device	May, 1994	Kishimoto et al.
5335219	Homogeneous composition of microcrystalline semiconductor material, semiconductor devices and directly overwritable memory elements fabricated therefrom, and arrays fabricated from the memory elements	August, 1994	Ovshinsky et al.
5341328	Electrically erasable memory elements having reduced switching current requirements and increased write/erase cycle life	August, 1994	Ovshinsky et al.
5350484	Method for the anisotropic etching of metal films in the fabrication of interconnects	September, 1994	Gardner et al.
5359205	Electrically erasable memory elements characterized by reduced current and improved thermal stability	October, 1994	Ovshinsky
5360981	Amorphous silicon memory	November, 1994	Owen et al.
5406509	Electrically erasable, directly overwritable, multibit single cell memory elements and arrays fabricated therefrom	April, 1995	Ovshinsky et al.
5414271	Electrically erasable memory elements having improved set resistance stability	May, 1995	Ovshinsky et al.
5500532	Personal electronic dosimeter	March, 1996	Kozicki et al.
5512328	Method for forming a pattern and forming a thin film used in pattern formation	April, 1996	Yoshimura et al.
5512773	Switching element with memory provided with Schottky tunnelling barrier	April, 1996	Wolf et al.
5534711	Electrically erasable, directly overwritable, multibit single cell memory elements and arrays fabricated therefrom	July, 1996	Ovshinsky et al.
5534712	Electrically erasable memory elements characterized by reduced current and improved thermal stability	July, 1996	Ovshinsky et al.
5536947	Electrically erasable, directly overwritable, multibit single cell memory element and arrays fabricated therefrom	July, 1996	Klersy et al.
5543737	Logical operation circuit employing two-terminal chalcogenide switches	August, 1996	Ovshinsky
5591501	Optical recording medium having a plurality of discrete phase change data recording points	January, 1997	Ovshinsky et al.
5596522	Homogeneous compositions of microcrystalline semiconductor material, semiconductor devices and directly overwritable memory elements fabricated therefrom, and arrays fabricated from the memory elements	January, 1997	Ovshinsky et al.
5687112	Multibit single cell memory element having tapered contact	November, 1997	Ovshinsky
5694054	Integrated drivers for flat panel displays employing chalcogenide logic elements	December, 1997	Ovshinsky et al.
5714768	Second-layer phase change memory array on top of a logic device	February, 1998	Ovshinsky et al.
5726083	Process of fabricating dynamic random access memory device having storage capacitor low in contact resistance and small in leakage current through tantalum oxide film	March, 1998	Takaishi
5751012	Polysilicon pillar diode for use in a non-volatile memory cell	May, 1998	Wolstenholme et al.
5761115	Programmable metallization cell structure and method of making same	June, 1998	Kozicki et al.
5789277	Method of making chalogenide memory device	August, 1998	Zahorik et al.
5814527	Method of making small pores defined by a disposable internal spacer for use in chalcogenide memories	September, 1998	Wolstenholme et al.
5818749	Integrated circuit memory device	October, 1998	Harshfield
5825046	Composite memory material comprising a mixture of phase-change memory material and dielectric material	October, 1998	Czubatyj et al.
5841150	Stack/trench diode for use with a muti-state material in a non-volatile memory cell	November, 1998	Gonzalez et al.
5846889	Infrared transparent selenide glasses	December, 1998	Harbison et al.
5851882	ZPROM manufacture and design and methods for forming thin structures using spacers as an etching mask	December, 1998	Harshfield
5869843	Memory array having a multi-state element and method for forming such array or cells thereof	February, 1999	Harshfield
5896312	Programmable metallization cell structure and method of making same	April, 1999	Kozicki et al.
5912839	Universal memory element and method of programming same	June, 1999	Ovshinsky et al.
5914893	Programmable metallization cell structure and method of making same	June, 1999	Kozicki et al.
5920788	Chalcogenide memory cell with a plurality of chalcogenide electrodes	July, 1999	Reinberg
5933365	Memory element with energy control mechanism	August, 1999	Klersy et al.
5998066	Gray scale mask and depth pattern transfer technique using inorganic chalcogenide glass	December, 1999	Block et al.
6011757	Optical recording media having increased erasability	January, 2000	Ovshinsky
6031287	Contact structure and memory element incorporating the same	February, 2000	Harshfield
6072716	Memory structures and methods of making same	June, 2000	Jacobson et al.
6077729	Memory array having a multi-state element and method for forming such array or cellis thereof	June, 2000	Harshfield
6084796	Programmable metallization cell structure and method of making same	July, 2000	Kozicki et al.
6087674	Memory element with memory material comprising phase-change material and dielectric material	July, 2000	Ovshinsky et al.
6117720	Method of making an integrated circuit electrode having a reduced contact area	September, 2000	Harshfield
6141241	Universal memory element with systems employing same and apparatus and method for reading, writing and programming same	October, 2000	Ovshinsky et al.
6143604	Method for fabricating small-size two-step contacts for word-line strapping on dynamic random access memory (DRAM)	November, 2000	Chiang et al.
6177338	Two step barrier process	January, 2001	Liaw et al.
6236059	Memory cell incorporating a chalcogenide element and method of making same	May, 2001	Wolsteinholme et al.
RE37259	Multibit single cell memory element having tapered contact	July, 2001	Ovshinsky
6297170	Sacrificial multilayer anti-reflective coating for mos gate formation	October, 2001	Gabriel et al.
6300684	Method for fabricating an array of ultra-small pores for chalcogenide memory cells	October, 2001	Gonzalez et al.
6316784	Method of making chalcogenide memory device	November, 2001	Zahorik et al.
6329606	Grid array assembly of circuit boards with singulation grooves	December, 2001	Freyman et al.
6339544	Method to enhance performance of thermal resistor device	January, 2002	Chiang et al.
6348365	PCRAM cell manufacturing	February, 2002	Moore et al.
6350679	Methods of providing an interlevel dielectric layer intermediate different elevation conductive metal layers in the fabrication of integrated circuitry	February, 2002	McDaniel et al.
6376284	Method of fabricating a memory device	April, 2002	Gonzalez et al.
6388324	Self-repairing interconnections for electrical circuits	May, 2002	Kozicki et al.
6391688	Method for fabricating an array of ultra-small pores for chalcogenide memory cells	May, 2002	Gonzalez et al.
6404665	Compositionally modified resistive electrode	June, 2002	Lowery et al.
6414376	Method and apparatus for reducing isolation stress in integrated circuits	July, 2002	Thakur et al.
6418049	Programmable sub-surface aggregating metallization structure and method of making same	July, 2002	Kozicki et al.
6420725	Method and apparatus for forming an integrated circuit electrode having a reduced contact area	July, 2002	Harshfield
6423628	Method of forming integrated circuit structure having low dielectric constant material and having silicon oxynitride caps over closely spaced apart metal lines	July, 2002	Li et al.
6429064	Reduced contact area of sidewall conductor	August, 2002	Wicker
6437383	Dual trench isolation for a phase-change memory cell and method of making same	August, 2002	Xu
6440837	Method of forming a contact structure in a semiconductor device	August, 2002	Harshfield
6462984	Biasing scheme of floating unselected wordlines and bitlines of a diode-based memory array	October, 2002	Xu et al.
6469364	Programmable interconnection system for electrical circuits	October, 2002	Kozicki
6473332	Electrically variable multi-state resistance computing	October, 2002	Ignatiev et al.
6480438	Providing equal cell programming conditions across a large and high density array of phase-change memory cells	November, 2002	Park
6487106	Programmable microelectronic devices and method of forming and programming same	November, 2002	Kozicki
6487113	Programming a phase-change memory with slow quench time	November, 2002	Park et al.
6501111	Three-dimensional (3D) programmable device	December, 2002	Lowery
6507061	Multiple layer phase-change memory	January, 2003	Hudgens et al.
6511862	Modified contact for programmable devices	January, 2003	Hudgens et al.
6511867	Utilizing atomic layer deposition for programmable device	January, 2003	Lowery et al.
6512241	Phase change material memory device	January, 2003	Lai
6514805	Trench sidewall profile for device isolation	February, 2003	Xu et al.
6531373	Method of forming a phase-change memory cell using silicon on insulator low electrode in charcogenide elements	March, 2003	Gill et al.
6534781	Phase-change memory bipolar array utilizing a single shallow trench isolation for creating an individual active area region for two memory array elements and one bipolar base contact	March, 2003	Dennison
6545287	Using selective deposition to form phase-change memory cells	April, 2003	Chiang
6545907	Technique and apparatus for performing write operations to a phase change material memory device	April, 2003	Lowery et al.
6555860	Compositionally modified resistive electrode	April, 2003	Lowery et al.
6563164	Compositionally modified resistive electrode	May, 2003	Lowery et al.
6566700	Carbon-containing interfacial layer for phase-change memory	May, 2003	Xu
6567293	Single level metal memory cell using chalcogenide cladding	May, 2003	Lowery et al.
6569705	Metal structure for a phase-change memory device	May, 2003	Chiang et al.
6570784	Programming a phase-change material memory	May, 2003	Lowery
6576921	Isolating phase change material memory cells	June, 2003	Lowery
6586761	Phase change material memory device	July, 2003	Lowery
6589714	Method for making programmable resistance memory element using silylated photoresist	July, 2003	Maimon et al.
6590807	Method for reading a structural phase-change memory	July, 2003	Lowery
6593176	METHOD FOR FORMING PHASE-CHANGE MEMORY BIPOLAR ARRAY UTILIZING A SINGLE SHALLOW TRENCH ISOLATION FOR CREATING AN INDIVIDUAL ACTIVE AREA REGION FOR TWO MEMORY ARRAY ELEMENTS AND ONE BIPOLAR BASE CONTACT	July, 2003	Dennison
6597009	Reduced contact area of sidewall conductor	July, 2003	Wicker
6605527	Reduced area intersection between electrode and programming element	August, 2003	Dennison et al.
6613604	Method for making small pore for use in programmable resistance memory element	September, 2003	Maimon et al.
6621095	Method to enhance performance of thermal resistor device	September, 2003	Chiang et al.
6625054	Method and apparatus to program a phase change memory	September, 2003	Lowery et al.
6642102	Barrier material encapsulation of programmable material	November, 2003	Xu
6646297	Lower electrode isolation in a double-wide trench	November, 2003	Dennison
6649928	Method to selectively remove one side of a conductive bottom electrode of a phase-change memory cell and structure obtained thereby	November, 2003	Dennison
6667900	Method and apparatus to operate a memory cell	December, 2003	Lowery et al.
6671710	Methods of computing with digital multistate phase change materials	December, 2003	Ovshinsky et al.
6673648	Isolating phase change material memory cells	January, 2004	Lowery
6673700	Reduced area intersection between electrode and programming element	January, 2004	Dennison et al.
6674115	Multiple layer phrase-change memory	January, 2004	Hudgens et al.
6687153	Programming a phase-change material memory	February, 2004	Lowery
6687427	Optic switch	February, 2004	Ramalingam et al.
6690026	Method of fabricating a three-dimensional array of active media	February, 2004	Peterson
6696355	Method to selectively increase the top resistance of the lower programming electrode in a phase-change memory	February, 2004	Dennison
6707712	Method for reading a structural phase-change memory	March, 2004	Lowery
6714954	Methods of factoring and modular arithmetic	March, 2004	Ovshinsky et al.
7138290	Methods of depositing silver onto a metal selenide-comprising surface and methods of depositing silver onto a selenium-comprising surface	November, 2006	McTeer	438/95
20020000666	SELF-REPAIRING INTERCONNECTIONS FOR ELECTRICAL CIRCUITS	January, 2002	Kozicki et al.
20020072188	Non-volatile resistance variable devices and method of forming same, analog memory devices and method of forming same, programmable memory cell and method of forming same, and method of structurally changing a non-volatile device	June, 2002	Gilton
20020106849	Method of forming non-volatile resistance variable devices, method of precluding diffusion of a metal into adjacent chalcogenide material, and non-volatile resistance variable devices	August, 2002	Moore
20020123169	Methods of forming non-volatile resistance variable devices, and non-volatile resistance variable devices	September, 2002	Moore et al.
20020123170	PCRAM cell manufacturing	September, 2002	Moore et al.
20020123248	METHODS OF METAL DOPING A CHALCOGENIDE MATERIAL	September, 2002	Moore et al.
20020127886	Method to manufacture a buried electrode PCRAM cell	September, 2002	Moore et al.
20020132417	Agglomeration elimination for metal sputter deposition of chalcogenides	September, 2002	Li
20020160551	Memory elements and methods for making same	October, 2002	Harshfield
20020163828	Memory device with a self-assembled polymer film and method of making the same	November, 2002	Krieger et al.
20020168820	Microelectronic programmable device and methods of forming and programming the same	November, 2002	Kozicki
20020168852	PCRAM memory cell and method of making same	November, 2002	Kozicki
20020190289	PCRAM memory cell and method of making same	December, 2002	Harshfield et al.
20020190350	Programmable sub-surface aggregating metallization structure and method of making same	December, 2002	Kozicki et al.
20030001229	Chalcogenide comprising device	January, 2003	Moore et al.
20030027416	METHOD OF FORMING INTEGRATED CIRCUITRY, METHOD OF FORMING MEMORY CIRCUITRY, AND METHOD OF FORMING RANDOM ACCESS MEMORY CIRCUITRY	February, 2003	Moore
20030032254	Resistance variable device, analog memory device, and programmable memory cell	February, 2003	Gilton
20030035314	Programmable microelectronic devices and methods of forming and programming same	February, 2003	Kozicki
20030035315	Microelectronic device, structure, and system, including a memory structure having a variable programmable property and method of forming the same	February, 2003	Kozicki
20030038301	Apparatus and method for dual cell common electrode PCRAM memory device	February, 2003	Moore
20030043631	Method of retaining memory state in a programmable conductor RAM	March, 2003	Gilton et al.
20030045049	Method of forming chalcogenide comprising devices	March, 2003	Campbell et al.
20030045054	Method of forming non-volatile resistance variable devices, method of forming a programmable memory cell of memory circuitry, and a non-volatile resistance variable device	March, 2003	Campbell et al.
20030047765	Stoichiometry for chalcogenide glasses useful for memory devices and method of formation	March, 2003	Campbell
20030047772	Agglomeration elimination for metal sputter deposition of chalcogenides	March, 2003	Li
20030047773	Agglomeration elimination for metal sputter deposition of chalcogenides	March, 2003	Li
20030048519	Microelectronic photonic structure and device and method of forming the same	March, 2003	Kozicki
20030048744	Increased data storage in optical data storage and retrieval systems using blue lasers and/or plasmon lenses	March, 2003	Ovshinsky et al.
20030049912	METHOD OF FORMING CHALCOGENIDE COMPRSING DEVICES AND METHOD OF FORMING A PROGRAMMABLE MEMORY CELL OF MEMORY CIRCUITRY	March, 2003	Campbell et al.
20030068861	Integrated circuit device and fabrication using metal-doped chalcogenide materials	April, 2003	Li et al.
20030068862	Integrated circuit device and fabrication using metal-doped chalcogenide materials	April, 2003	Li et al.
20030095426	Complementary bit PCRAM sense amplifier and method of operation	May, 2003	Hush et al.
20030096497	Electrode structure for use in an integrated circuit	May, 2003	Moore et al.
20030107105	Programmable chip-to-substrate interconnect structure and device and method of forming same	June, 2003	Kozicki
20030117831	Programmable conductor random access memory and a method for writing thereto	June, 2003	Hush
20030128612	PCRAM rewrite prevention	July, 2003	Moore et al.
20030137869	Programmable microelectronic device, structure, and system and method of forming the same	July, 2003	Kozicki
20030143782	METHODS OF FORMING GERMANIUM SELENIDE COMPRISING DEVICES AND METHODS OF FORMING SILVER SELENIDE COMPRISING STRUCTURES	July, 2003	Gilton et al.
20030155589	Silver-selenide/chalcogenide glass stack for resistance variable memory	August, 2003	Campbell et al.
20030155606	Method to alter chalcogenide glass for improved switching characteristics	August, 2003	Campbell et al.
20030156447	Programming circuit for a programmable microelectronic device, system including the circuit, and method of forming the same	August, 2003	Kozicki
20030156463	Programmable conductor random access memory and method for sensing same	August, 2003	Casper et al.
20030209728	Microelectronic programmable device and methods of forming and programming the same	November, 2003	Kozicki et al.
20030209971	Programmable structure, an array including the structure, and methods of forming the same	November, 2003	Kozicki et al.
20030210564	Tunable cantilever apparatus and method for making same	November, 2003	Kozicki et al.
20030212724	METHODS OF COMPUTING WITH DIGITAL MULTISTATE PHASE CHANGE MATERIALS	November, 2003	Ovshinsky et al.
20030212725	Methods of factoring and modular arithmetic	November, 2003	Ovshinsky et al.
20040035401	Hydrogen powered scooter	February, 2004	Ramachandran et al.
20040233728	Chalcogenide glass constant current device, and its method of fabrication and operation	November, 2004	Campbell	365/185.24

JP56126916	October, 1981
WO/1997/048032	December, 1997			PROGRAMMABLE METALLIZATION CELL AND METHOD OF MAKING
WO/1999/028914	June, 1999			PROGRAMMABLE SUB-SURFACE AGGREGATING METALLIZATION STRUCTURE AND METHOD OF MAKING SAME
WO/2000/048196	August, 2000			PROGRAMMABLE MICROELECTRONIC DEVICES AND METHODS OF FORMING AND PROGRAMMING SAME
WO/2002/021542	March, 2002			MICROELECTRONIC PROGRAMMABLE DEVICE AND METHODS OF FORMING AND PROGRAMMING THE SAME

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Elms, Richard T.

Byrne, Harry W.

Dickstein Shapiro LLP

This is a divisional of U.S. patent application Ser. No. 11/193,425, filed on Aug. 1, 2005 now U.S. Pat. No. 7,274,034, the entirety of which is hereby incorporated by reference.

What is claimed as new and desired to be protected by Letters Patents of the United States is:

1. A method of forming a memory device, comprising: providing a first electrode; forming a chalcogenide glass layer over said first electrode; sputtering a plurality of alternating tin chalcogenide layers and silver layers over said chalcogenide glass layer; and providing a second electrode over said plurality of alternating tin chalcogenide layers and silver layers.

2. The method of claim 1, wherein said tin chalcogenide is tin selenide.

3. The method of claim 1, wherein each sputtered tin chalcogenide layer is about 200 Å to about 400 Å thick.

4. The method of claim 1, wherein each sputtered silver layer is about 50Å to about 100 Å thick.

5. The method of claim 1, wherein said plurality of alternating tin chalcogenide and silver layers forms a region that is about 1,000 Å to about 2,000 Å thick.

6. The method of claim 1, wherein said chalcogenide glass comprises germanium selenide.

7. The method of claim 6, wherein said germanium selenide has a stoichiometry of about Ge₂Se₃.

8. The method of claim 1, further comprising: forming a second chalcogenide glass layer over said plurality of alternating tin chalcogenide and silver layers; forming a metal layer over said second chalcogenide glass layer, said metal layer comprising silver; and forming a third chalcogenide glass layer over said metal layer.

9. A method of forming a memory device, comprising: providing a first electrode; providing a first germanium selenide layer over said first electrode; sputtering a plurality of alternating tin selenide layers and silver layers over said first germanium selenide layer; providing a second germanium selenide layer over said plurality of alternating tin selenide layers and silver layers; providing a metal layer over said second germanium selenide layer, said metal layer comprising silver; providing a third germanium selenide layer over said metal layer; and providing a second electrode over said third germanium selenide layer.

10. The method of claim 9, wherein said plurality of alternating tin seleinde layers and silver layers form a region about 1,000 Å to about 2,000 Å thick.

11. The method of claim 9, wherein said first germanium selenide layer is about 300 Å thick.

12. The method of claim 9, wherein said tin selenide layers are each about 200 Å to about 400 Å thick.

13. The method of claim 9, wherein said silver layers are each about 50 Å to about 100 Å thick.

FIELD OF THE INVENTION

The invention relates to the field of random access memory (RAM) devices formed using a resistance variable material.

BACKGROUND

Resistance variable memory elements, which include chalcogenide-based programmable conductor elements, have been investigated for suitability as semi-volatile and non-volatile random access memory devices. A typical such device is disclosed, for example, in U.S. Pat. No. 6,849,868 to Campbell, which is incorporated by reference.

In a typical chalcogenide-based programmable conductor memory device, a conductive material, such as silver, is incorporated into a chalcogenide glass. The resistance of the chalcogenide glass can be programmed to stable higher resistance and lower resistance states. An unprogrammed chalcogenide-based programmable conductor memory device is normally in a higher resistance state. A write operation programs the chalcogenide-based programmable conductor memory device to a lower resistance state by applying a voltage potential across the chalcogenide glass. The chalcogenide-based programmable conductor memory device may then be read by applying a voltage pulse of a lesser magnitude than required to program it; the resistance across the memory device is then sensed as higher or lower to define the ON and OFF states.

The programmed lower resistance state of a chalcogenide-based programmable conductor memory device can remain intact for an indefinite period, typically ranging from hours to weeks, after the voltage potentials are removed. The chalcogenide-based programmable conductor memory device can be returned to its higher resistance state by applying a reverse voltage potential of about the same order of magnitude as used to write the device to the lower resistance state. Again, the higher resistance state is maintained in a semi- or non-volatile manner once the voltage potential is removed. In this way, such a device can function as a variable resistance memory having at least two resistance states, which can define two respective logic states, i.e., at least a bit of data.

One exemplary chalcogenide-based programmable conductor memory device uses a germanium selenide (i.e., Ge _x Se _100-x ) chalcogenide glass as a backbone. The germanium selenide glass has, in the prior art, incorporated silver (Ag) and silver selenide (Ag ₂ Se).

Previous work by the inventor, Kristy A. Campbell, has been directed to chalcogenide-based programmable conductor memory devices incorporating a silver-chalcogenide material as a layer of silver selenide (e.g., Ag ₂ Se) or silver sulfide (e.g., Ag ₂ S) in combination with a silver-metal layer and a chalcogenide glass layer. The silver-chalcogenide materials are suitable for assisting in the formation of a conducting channel through the chalcogenide glass layer for silver ions to move into to form a conductive pathway.

Tin (Sn) has a reduced thermal mobility in Ge _x Se _100-x compared to silver and the tin-chalcogenides are less toxic than the silver-chalcogenides, therefore tin-chalcogenides (e.g., SnSe) have also been found to be useful in chalcogenide-based programmable conductor memory devices to replace silver selenide. However, sputtering of tin selenide to form such devices has proven difficult due to the increased density of the sputtered layers. This increased density (e.g., ˜6 g/cm ³ sputtered compared to ˜3 g/cm ³ evaporated) can prevent the motion of silver ions into the chalcogenide glass, thereby preventing the memory device from functioning. Therefore, evaporative deposition techniques have been used to deposit such material, which is generally a less efficient, more costly, slower, and less controlled technique for deposition. However, evaporation deposition of tin selenide and silver also incorporates some oxygen into the resulting layer, which provides for the lower density and allows for more mobility of silver ions.

SUMMARY

In an exemplary embodiment, the invention provides a chalcogenide-based programmable conductor memory device having a layered stack with a region containing tin-chalcogenide and silver proximate a chalcogenide glass layer. The device comprising a chalcogenide glass layer and the region of tin-chalcogenide and silver is formed between two conductive layers or electrodes. The tin-chalcogenide and silver region is formed by sputter deposition of tin-chalcogenide and silver.

In an exemplary embodiment of the invention, the chalcogenide-based programmable conductor memory device contains alternating layers of tin selenide (e.g., Sn _x Se, where x is between about 0 and 2) and silver.

In an exemplary embodiment of the invention, the tin-chalcogenide and silver region is formed by alternation of sputtering of tin selenide and silver layers over the chalcogenide glass layer.

The above and other features and advantages of the invention will be better understood from the following detailed description, which is provided in connection with the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1 and 2 show exemplary embodiments of memory devices in accordance with the invention.

FIGS. 3-6 show exemplary sequential stages of processing during the fabrication of a memory device as in FIG. 2, in accordance with the invention.

FIG. 7 shows an exemplary processor-based system incorporating a memory device in accordance with the invention.

DETAILED DESCRIPTION

In the following detailed description, reference is made to various specific embodiments of the invention. These embodiments are described with sufficient detail to enable those skilled in the art to practice the invention. It is to be understood that other embodiments may be employed, and that various structural, logical and electrical changes may be made without departing from the spirit or scope of the invention.

The term “substrate” used in the following description may include any supporting structure including, but not limited to, a semiconductor substrate that has an exposed substrate surface. A semiconductor substrate should be understood to include silicon, epitaxial silicon, silicon-on-insulator (SOI), silicon-on-sapphire (SOS), doped and undoped semiconductors, epitaxial layers of silicon supported by a base semiconductor foundation, and other semiconductor structures. When reference is made to a semiconductor substrate or wafer in the following description, previous process steps may have been utilized to form regions or junctions in or over the base semiconductor or foundation. The substrate need not be semiconductor-based, but may be any support structure suitable for supporting an integrated circuit, including, but not limited to, metals, alloys, glasses, polymers, ceramics, and any other supportive materials as is known in the art.

The term “silver” is intended to include not only elemental silver, but silver with other trace metals or in various alloyed combinations with other metals as known in the semiconductor industry, as long as such silver alloy is conductive, and as long as the physical and electrical properties of the silver remain unchanged.

The term “tin” is intended to include not only elemental tin, but tin with other trace metals or in various alloyed combinations with other metals as known in the semiconductor industry, as long as such tin alloy is conductive, and as long as the physical and electrical properties of the tin remain unchanged.

The term “tin-chalcogenide” is intended to include various alloys, compounds, and mixtures of tin and chalcogens (e.g., sulfur (S), selenium (Se) tellurium (Te), polonium (Po), and oxygen (O)), including some species which have an excess or deficit of tin. For example, tin selenide, a species of tin-chalcogenide, is a preferred material for use in the invention and may be represented by the general formula Sn _+/− Se. Though not being limited by a particular stoichiometric ratio between Sn and Se, devices of the present invention typically comprise an Sn _x Se species where x ranges between about 0 and about 2, e.g., SnSe.

The term “chalcogenide glass” is intended to include glasses that comprise at least one element from group VIA (also know as group 16) of the periodic table. Group VIA elements (e.g., O, S, Se, Te, and Po) are also referred to as chalcogens.

The invention is now explained with reference to the figures, which illustrate exemplary embodiments and throughout which like reference numbers indicate like features. FIG. 1 shows an exemplary embodiment of a memory device 100 constructed in accordance with the invention. The device 100 shown in FIG. 1 is supported by a substrate 10 . Over the substrate 10 , though not necessarily directly so, is a conductive address line 12 , which serves as an interconnect for the device 100 shown and a plurality of other similar devices of a portion of a memory array of which the shown device 100 is a part. It is possible to incorporate an optional insulating layer (not shown) between the substrate 10 and address line 12 , and this may be preferred if the substrate 10 is semiconductor-based.

The conductive address line 12 can be any material known in the art as being useful for providing an interconnect line, such as doped polysilicon, silver (Ag), gold (Au), copper (Cu), tungsten (W), nickel (Ni), aluminum (Al), platinum (Pt), titanium (Ti), and other materials. Over the address line 12 is a first electrode 16 , which can be defined within an insulating layer 14 , if desired, and which is also over the address line 12 . This electrode 16 can be any conductive material that will not migrate into chalcogenide glass, but is preferably tungsten (W). The insulating layer 14 should not allow the migration of silver (or other metal, e.g., copper) ions and can be an insulating nitride, such as silicon nitride (Si ₃ N ₄ ), a low dielectric constant material, an insulating glass, or an insulating polymer, but is not limited to such materials.

A memory element, i.e., the portion of the memory device 100 which stores information, is formed over the first electrode 16 . In the embodiment shown in FIG. 1, a layer of chalcogenide glass 18 , preferably a germanium chalcogenide such as germanium selenide (Ge _x Se _100-x ), can be provided over the first electrode 16 . The germanium selenide can be within a stoichiometric range of about Ge ₂₀ Se ₈₀ to about Ge ₄₃ Se ₅₇ , preferably about Ge ₄₀ Se ₆₀ , i.e., Ge ₂ Se ₃ . The layer of chalcogenide glass 18 can be between about 100 Å and about 1000 Å thick, preferably about 300 Åthick. Layer 18 need not be a single layer of glass, but may also be comprised of multiple sub-layers of chalcogenide glass having the same or different stoichiometries. This layer of chalcogenide glass 18 is in electrical contact with the underlying electrode 16 .

Over the chalcogenide glass layer 18 is a region 20 of tin-chalcogenide; preferably tin selenide (Sn _x Se, where x is between about 0 and 2), and silver, which are layered as shown in FIG. 14. Alternating layers of tin selenide and silver are utilized to provide a region 20 incorporating both materials, wherein the silver is dispersed throughout the tin selenide. It is also possible that other chalcogenide materials may be substituted for selenium here, such as sulfur, oxygen, or tellurium; however, selenium is preferred and the remainder of the description will describe the invention utilizing tin selenide. The tin selenide and silver region 20 is preferably about 1,000 Å to about 2,000 Å thick; however, its thickness depends, in part, on the thickness of the underlying chalcogenide glass layer 18 . The ratio of the thickness of the tin selenide and silver region 20 to that of the underlying chalcogenide glass layer 18 can be at least about 1:1, preferably about 3.33:1 to about 6.67:1.

Still referring to FIG. 1, over the tin selenide and silver region 20 is a second electrode 24 . The second electrode 24 can be made of the same material as the first electrode 16 , but is not required to be so. In the exemplary embodiment shown in FIG. 1, the second electrode 24 is preferably tungsten (W). The device(s) may be isolated by an insulating layer 26 . The memory device 100 shown in FIG. 1 is a simplified exemplary embodiment of the invention. Other alternative embodiments may have more glass layers, as shown, for example, in FIG. 2, or may be provided within a via or may be made of blanket layers over an electrode such as electrode 16 . Also, alternative embodiments may provide a common electrode in place of the dedicated electrode 16 , shown in FIG. 1.

In accordance with the embodiment shown at FIG. 1, in a completed memory device 100 , the tin selenide and silver region 20 provides a source of tin selenide and silver, which is incorporated into chalcogenide glass layer 18 during a conditioning step after formation of the memory device 100 . The tin selenide and silver region 20 may also provide silver selenide (Ag ₂ Se) and silver tin selenide (Ag _x Sn _y Se _z ) to condition the chalcogenide glass layer 18 . Specifically, the conditioning step comprises applying a potential across the memory element structure of the device 100 such that material from the region 20 is incorporated into the chalcogenide glass layer 18 , thereby forming a conducting channel in the chalcogenide glass layer 18 . Movement of silver ions into or out of the conducting channel during subsequent programming respectively forms or dissolves a conductive pathway, which causes a detectable resistance change across the memory device 100 .

FIG. 2 shows another exemplary embodiment of a memory device 101 constructed in accordance with the invention. Memory device 101 has many similarities to memory device 100 of FIG. 1 and layers designated with like reference numbers are preferably the same materials and have the same thicknesses as those described in relation to the embodiment shown in FIG. 1. The primary difference between device 100 and device 101 is the addition to device 101 of an optional second chalcogenide glass layer 18 a , a metal layer 22 , and an optional third chalcogenide glass layer 18 b.

The optional second chalcogenide glass layer 18 a is formed over the tin selenide and silver region 20 , is preferably Ge ₂ Se ₃ , and is preferably about 150 Å thick. Over this optional second chalcogenide glass layer 18 a is a metal layer 22 , which is preferably silver (Ag) and is preferably about 500 Å thick. Over the metal layer 22 is an optional third chalcogenide glass layer 18 b , which is preferably Ge ₂ Se ₃ and is preferably about 100 Å thick. The optional third chalcogenide glass layer 18 b provides an adhesion layer for subsequent electrode formation. As with layer 18 of FIG. 1, layers 18 a and 18 b are not necessarily a single layer, but may be comprised of multiple sub-layers. Additionally, the optional second and third chalcogenide layers 18 a and 18 b may be a different chalcogenide glass from the first chalcogenide glass layer 18 or from each other.

Over the optional third chalcogenide glass layer 18 b is a second electrode 24 , which may be any conductive material, but is preferably not one that will migrate into the memory element stack and alter memory operation (e.g., not Cu or Ag), as discussed above for the preceding embodiments. Preferably, the second electrode 24 is tungsten (W).

FIGS. 3-6 illustrate a cross-sectional view of a wafer during the fabrication of a memory device 101 as shown by FIG. 2. Although the processing steps shown in FIGS. 3-6 most specifically refer to memory device 101 of FIG. 2, the methods and techniques discussed may also be used to fabricate other memory device structures, such as shown in FIG. 1, as would be understood by a person of ordinary skill in the art based on a reading of this specification.

As shown by FIG. 3, a substrate 10 is provided. As indicated above, the substrate 10 can be semiconductor-based or another material useful as a supporting structure for an integrated circuit, as is known in the art. If desired, an optional insulating layer (not shown) may be formed over the substrate 10 ; the optional insulating layer may be silicon nitride or other insulating materials used in the art. Over the substrate 10 (or optional insulating layer, if desired), a conductive address line 12 is formed by depositing a conductive material, such as doped polysilicon, aluminum, platinum, silver, gold, nickel, but preferably tungsten, patterning one or more conductive lines, for example, with photolithographic techniques, and etching to define the address line 12 . The conductive material maybe deposited by any technique known in the art, such as sputtering, chemical vapor deposition, plasma enhanced chemical vapor deposition, evaporation, or plating.

Still referring to FIG. 3, over the address line 12 is formed an insulating layer 14 . This layer 14 can be silicon nitride, a low dielectric constant material, or many other insulators known in the art that do not allow silver ion migration, and may be deposited by any method known in the art. An opening 14 a in the insulating layer is made, for example, by photolithographic and etching techniques, thereby exposing a portion of the underlying address line 12 . Over the insulating layer 14 , within the opening 14 a , and over the address line 12 is formed a conductive material, preferably tungsten (W). A chemical mechanical polishing (CMP) step may then be utilized, using the insulating layer 14 as a stop, to remove the conductive material from over the insulating layer 14 , to leave it as a first electrode 16 over the address line 12 , and planarize the wafer.

FIG. 4 shows the cross-section of the wafer of FIG. 3 at a subsequent stage of processing. A series of layers making up the memory device 101 (FIG. 2) are blanket-deposited over the wafer. A chalcogenide glass layer 18 is formed to a preferred thickness of about 300 Å over the first electrode 16 and insulating layer 14 . The chalcogenide glass layer 18 is preferably Ge ₂ Se ₃ . Deposition of this chalcogenide glass layer 18 may be accomplished by any suitable method, such as evaporative techniques or chemical vapor deposition using germanium tetrahydride (GeH ₄ ) and selenium dihydride (SeH ₂ ) gases; however, the preferred technique utilizes either sputtering from a germanium selenide target having the desired stoichiometry or co-sputtering germanium and selenium in the appropriate ratios.

Still referring to FIG. 4, the tin selenide and silver region 20 is formed over the chalcogenide glass layer 18 . To form region 20 , alternating layers of tin selenide 20 a and silver 20 b are deposited by sputtering. Each tin selenide layer 20 a is preferably between about 200 Å and about 400 Å. Each silver layer 20 b is preferably between about 50 Å and about 100 Å. Sputtering these layers is preferred to evaporation deposition because of the increased efficiency, cost effectiveness, speed of fabrication, control of deposition rate, control of layer thickness, and control of layer properties provided by sputtering. Although the sputtered tin selenide and silver region 20 is denser than a like evaporated region, the proximity of the silver and the tin selenide layers 20 b and 20 a , respectively, allows for mixing and migration of these materials, heretofore not available to such sputtered regions.

Again, the thickness of region 20 is selected based, in part, on the thickness of layer 18 ; therefore, where the chalcogenide glass layer 18 is preferably about 300 Å thick, the alternating tin selenide layers 20 a and silver layers 20 b should make for a region 20 that is about 1,000 Å to about 2,000 Å thick. It should be noted that, as the processing steps outlined in relation to FIGS. 3-6 may be adapted for the formation of other devices in accordance the invention.

Still referring to FIG. 4, a second chalcogenide glass layer 18 a is formed over the tin selenide and silver region 20 , which can be sputtered similarly to the formation of layer 18 . The second chalcogenide glass layer 18 a is preferably a germanium selenide layer with a stoichiometry of Ge ₂ Se ₃ and is preferably about 150 Å thick. Over the second chalcogenide glass layer 18 a , a metal layer 22 is formed. The metal layer 22 is preferably silver (Ag), or at least contains silver, and is formed to a preferred thickness of about 500 Å. The metal layer 22 may be deposited by any technique known in the art. A third chalcogenide glass layer 18 b is formed over the metal layer 22 . This third chalcogenide glass layer 18 b is also preferably germanium selenide with a stoichiometry of Ge ₂ Se ₃ , can be about 100 Å thick, and is preferably deposited by sputtering.

Still referring to FIG. 4, over the third chalcogenide glass layer 18 b , a conductive material is deposited to form a second electrode 24 layer. Again, this conductive material may be any material suitable for a conductive electrode, but is preferably tungsten; however other materials may be used such as titanium nitride or tantalum, for example.

Now referring to FIG. 5, a layer of photoresist 30 is deposited over the top electrode 24 layer, masked and patterned to define the stacks for the memory device 101 , which is one of a plurality of like memory devices of a memory array. An etching step is used to remove portions of layers 18 , 20 a , 20 b , 18 a , 22 , 18 b , and 24 , with the insulating layer 14 used as an etch stop, leaving stacks as shown in FIG. 5. The photoresist 30 is removed, leaving a substantially complete memory device 101 , as shown by FIG. 6. An insulating layer 26 may be formed over the device 101 to achieve a structure as shown by FIG. 2. This isolation step can be followed by the forming of connections to other circuitry of the integrated circuit (e.g., logic circuitry, sense amplifiers, etc.) of which the memory device 101 is a part, as is known in the art.

A conditioning step is performed by applying a voltage pulse of a given duration and magnitude to incorporate material from the tin selenide and silver region 20 into the chalcogenide glass layer 18 to form a conducting channel in the chalcogenide glass layer 18 . The conducting channel will support a conductive pathway during operation of the memory device 101 , the presence or lack of which provides at least two detectable resistance states for the memory device 101 .

The embodiments described above refer to the formation of only a few possible chalcogenide-based programmable conductor memory device in accordance with the invention, which may be part of a memory array. It must be understood, however, that the invention contemplates the formation of other memory structures within the spirit of the invention, which can be fabricated as a memory array and operated with memory element access circuits.

FIG. 7 illustrates a processor system 400 which includes a memory circuit 448 employing chalcogenide-based programmable conductor memory devices (e.g., device 100 and 101 ) fabricated in accordance with the invention. A processor system, such as a computer system, generally comprises a central processing unit (CPU) 444 , such as a microprocessor, a digital signal processor, or other programmable digital logic devices, which communicates with an input/output (I/O) device 446 over a bus 452 . The memory circuit 448 communicates with the CPU 444 over bus 452 , typically through a memory controller.

In the case of a computer system, the processor system may include peripheral devices, such as a floppy disk drive 454 and a compact disc (CD) ROM drive 456 , which also communicate with CPU 444 over the bus 452 . Memory circuit 448 is preferably constructed as an integrated circuit, which includes one or more resistance variable memory devices, e.g., device 101 . If desired, the memory circuit 448 may be combined with the processor, for example CPU 444 , in a single integrated circuit.

The above description and drawings should only be considered illustrative of exemplary embodiments that achieve the features and advantages of the invention. Modification and substitutions to specific process conditions and structures can be made without departing from the spirit and scope of the invention. Accordingly, the invention is not to be considered as being limited by the foregoing description and drawings, but is only limited by the scope of the appended claims.