Forbes, Leonard (Corvallis, OR, US)
Ahn, Kie Y. (Chappaqua, NY, US)

Plaque It!

11/458854

10/07/2008

07/20/2006

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Micron Technology, Inc. (Boise, ID, US)

365/185.18

257/324, 365/185.24, 365/185.21

G11C16/02; G11C16/06

365/185.18, 365/185.24, 365/185.21, 257/760, 365/51, 257/324, 365/210.1, 365/185.2, 257/325, 365/185.05, 365/210, 365/185.03, 365/63, 365/72

3641516	WRITE ONCE READ ONLY STORE SEMICONDUCTOR MEMORY	February, 1972	Casruccci et al.
3665423	MEMORY MATRIX USING MIS SEMICONDUCTOR ELEMENT	May, 1972	Nakamuma et al.
3877054	Semiconductor memory apparatus with a multilayer insulator contacting the semiconductor	April, 1975	Boulin et al.
3964085	Method for fabricating multilayer insulator-semiconductor memory apparatus	June, 1976	Kahng et al.
3978577	Fixed and variable threshold N-channel MNOSFET integration technique	September, 1976	Bhattacharyya et al.
4152627	Low power write-once, read-only memory array	May, 1979	Priel et al.
4173791	Insulated gate field-effect transistor read-only memory array	November, 1979	Bell
4217601	Non-volatile memory devices fabricated from graded or stepped energy band gap insulator MIM or MIS structure	August, 1980	DeKeersmaecker et al.
4295150	Storage transistor	October, 1981	Adam
4412902	Method of fabrication of Josephson tunnel junction	November, 1983	Michikami et al.
4449205	Dynamic RAM with non-volatile back-up storage and method of operation thereof	May, 1984	Hoffman
4495219	Process for producing dielectric layers for semiconductor devices	January, 1985	Kato et al.
4507673	Semiconductor memory device	March, 1985	Aoyama et al.
4661833	Electrically erasable and programmable read only memory	April, 1987	Mizutani
4717943	Charge storage structure for nonvolatile memories	January, 1988	Wolf et al.
4757360	Floating gate memory device with facing asperities on floating and control gates	July, 1988	Faraone et al.
4780424	Process for fabricating electrically alterable floating gate memory devices	October, 1988	Holler
4794565	Electrically programmable memory device employing source side injection	December, 1988	Wu et al.
4829482	Current metering apparatus for optimally inducing field emission of electrons in tunneling devices and the like	May, 1989	Owen
4870470	Non-volatile memory cell having Si rich silicon nitride charge trapping layer	September, 1989	Bass, Jr. et al.
4888733	Non-volatile memory cell and sensing method	December, 1989	Mobley
4939559	Dual electron injector structures using a conductive oxide between injectors	July, 1990	DiMaria et al.
5016215	High speed EPROM with reverse polarity voltages applied to source and drain regions during reading and writing	May, 1991	Tigelaar
5017977	Dual EPROM cells on trench walls with virtual ground buried bit lines	May, 1991	Richardson	257/316
5021999	Non-volatile semiconductor memory device with facility of storing tri-level data	June, 1991	Kohda et al.
5027171	Dual polarity floating gate MOS analog memory device	June, 1991	Reedy et al.
5042011	Sense amplifier pulldown device with tailored edge input	August, 1991	Casper et al.
5043946	Semiconductor memory device	August, 1991	Yamauchi et al.
5071782	Vertical memory cell array and method of fabrication	December, 1991	Mori
5073519	Method of fabricating a vertical FET device with low gate to drain overlap capacitance	December, 1991	Rodder
5111430	Non-volatile memory with hot carriers transmitted to floating gate through control gate	May, 1992	Morie
5253196	MOS analog memory with injection capacitors	October, 1993	Shimabukuro
5274249	Superconducting field effect devices with thin channel layer	December, 1993	Xi et al.
5280205	Fast sense amplifier	January, 1994	Green et al.
5293560	Multi-state flash EEPROM system using incremental programing and erasing methods	March, 1994	Harari
5298447	Method of fabricating a flash memory cell	March, 1994	Hong
5317535	Gate/source disturb protection for sixteen-bit flash EEPROM memory arrays	May, 1994	Talreja et al.
5332915	Semiconductor memory apparatus	July, 1994	Shimoji et al.
5350738	Method of manufacturing an oxide superconductor film	September, 1994	Hase et al.
5388069	Nonvolatile semiconductor memory device for preventing erroneous operation caused by over-erase phenomenon	February, 1995	Kokubo
5399516	Method of making shadow RAM cell having a shallow trench EEPROM	March, 1995	Bergendahl et al.
5409859	Method of forming platinum ohmic contact to p-type silicon carbide	April, 1995	Glass et al.
5410504	Memory based on arrays of capacitors	April, 1995	Ward
5418389	Field-effect transistor with perovskite oxide channel	May, 1995	Watanabe
5424993	Programming method for the selective healing of over-erased cells on a flash erasable programmable read-only memory device	June, 1995	Lee et al.
5430670	Differential analog memory cell and method for adjusting same	July, 1995	Rosenthal
5434815	Stress reduction for non-volatile memory cell	July, 1995	Smarandoiu et al.
5438544	Non-volatile semiconductor memory device with function of bringing memory cell transistors to overerased state, and method of writing data in the device	August, 1995	Makino
5445984	Method of making a split gate flash memory cell	August, 1995	Hong et al.
5449941	Semiconductor memory device	September, 1995	Yamazaki et al.
5455792	Flash EEPROM devices employing mid channel injection	October, 1995	Yi
5457649	Semiconductor memory device and write-once, read-only semiconductor memory array using amorphous-silicon and method therefor	October, 1995	Eichman et al.
5467306	Method of using source bias to increase threshold voltages and/or to correct for over-erasure of flash eproms	November, 1995	Kaya et al.
5477485	Method for programming a single EPROM or FLASH memory cell to store multiple levels of data that utilizes a floating substrate	December, 1995	Bergemont et al.
5485422	Drain bias multiplexing for multiple bit flash cell	January, 1996	Bauer et al.
5493140	Nonvolatile memory cell and method of producing the same	February, 1996	Iguchi
5497494	Method for saving and restoring the state of a CPU executing code in protected mode	March, 1996	Combs et al.
5498558	Integrated circuit structure having floating electrode with discontinuous phase of metal silicide formed on a surface thereof and process for making same	March, 1996	Kapoor
5508543	Low voltage memory	April, 1996	Hartstein et al.
5508544	Three dimensional FAMOS memory devices	April, 1996	Shah
5510278	Method for forming a thin film transistor	April, 1996	Nguyen et al.
5530581	Protective overlayer material and electro-optical coating using same	June, 1996	Cogan
5530668	Ferroelectric memory sensing scheme using bit lines precharged to a logic one voltage	June, 1996	Chern et al.
5539279	Ferroelectric memory	July, 1996	Takeuchi et al.
5541871	Nonvolatile ferroelectric-semiconductor memory	July, 1996	Nishimura et al.
5541872	Folded bit line ferroelectric memory device	July, 1996	Lowrey et al.
5550770	Semiconductor memory device having ferroelectric capacitor memory cells with reading, writing and forced refreshing functions and a method of operating the same	August, 1996	Kuroda
5557569	Low voltage flash EEPROM C-cell using fowler-nordheim tunneling	September, 1996	Smayling et al.
5572459	Voltage reference for a ferroelectric 1T/1C based memory	November, 1996	Wilson et al.
5600587	Ferroelectric random-access memory	February, 1997	Koike
5600592	Nonvolatile semiconductor memory device having a word line to which a negative voltage is applied	February, 1997	Atsumi et al.
5617351	Three-dimensional direct-write EEPROM arrays and fabrication methods	April, 1997	Bertin et al.
5618575	Process and apparatus for the production of a metal oxide layer	April, 1997	Peter
5619642	Fault tolerant memory system which utilizes data from a shadow memory device upon the detection of erroneous data in a main memory device	April, 1997	Nielson et al.
5621683	Semiconductor memory with non-volatile memory transistor	April, 1997	Young
5627781	Nonvolatile semiconductor memory	May, 1997	Hayashi et al.
5627785	Memory device with a sense amplifier	May, 1997	Gilliam et al.
5646430	Non-volatile memory cell having lightly-doped source region	July, 1997	Kaya et al.
5670790	Electronic device	September, 1997	Katoh et al.
5677867	Memory with isolatable expandable bit lines	October, 1997	Hazani
5691230	Technique for producing small islands of silicon on insulator	November, 1997	Forbes
5714766	Nano-structure memory device	February, 1998	Chen et al.
5740104	Multi-state flash memory cell and method for programming single electron differences	April, 1998	Forbes
5754477	Differential flash memory cell and method for programming	May, 1998	Forbes
5768192	Non-volatile semiconductor memory cell utilizing asymmetrical charge trapping	June, 1998	Eitan
5801401	Flash memory with microcrystalline silicon carbide film floating gate	September, 1998	Forbes
5801993	Nonvolatile memory device	September, 1998	Choi
5828605	Snapback reduces the electron and hole trapping in the tunneling oxide of flash EEPROM	October, 1998	Peng et al.
5852306	Flash memory with nanocrystalline silicon film floating gate	December, 1998	Forbes
5856688	Integrated circuit memory devices having nonvolatile single transistor unit cells therein	January, 1999	Lee et al.
5856943	Scalable flash EEPROM memory cell and array	January, 1999	Jeng
5880991	Structure for low cost mixed memory integration, new NVRAM structure, and process for forming the mixed memory and NVRAM structure	March, 1999	Hsu et al.
5886368	Transistor with silicon oxycarbide gate and methods of fabrication and use	March, 1999	Forbes et al.
5912488	Stacked-gate flash EEPROM memory devices having mid-channel injection characteristics for high speed programming	June, 1999	Kim et al.
5923056	Electronic components with doped metal oxide dielectric materials and a process for making electronic components with doped metal oxide dielectric materials	July, 1999	Lee et al.
5936274	High density flash memory	August, 1999	Forbes et al.
5943262	Non-volatile memory device and method for operating and fabricating the same	August, 1999	Choi
5952692	Memory device with improved charge storage barrier structure	September, 1999	Nakazato et al.
5959896	Multi-state flash memory cell and method for programming single electron differences	September, 1999	Forbes
5963476	Fowler-Nordheim (F-N) tunneling for pre-programming in a floating gate memory device	October, 1999	Hung et al.
5973356	Ultra high density flash memory	October, 1999	Noble et al.
5981335	Method of making stacked gate memory cell structure	November, 1999	Chi
5981350	Method for forming high capacitance memory cells	November, 1999	Geusic et al.
5986932	Non-volatile static random access memory and methods for using same	November, 1999	Ratnakumar et al.
5989958	Flash memory with microcrystalline silicon carbide film floating gate	November, 1999	Forbes
5991225	Programmable memory address decode array with vertical transistors	November, 1999	Forbes et al.
6011725	Two bit non-volatile electrically erasable and programmable semiconductor memory cell utilizing asymmetrical charge trapping	January, 2000	Eitan
6025228	Method of fabricating an oxynitride-capped high dielectric constant interpolysilicon dielectric structure for a low voltage non-volatile memory	February, 2000	Ibok et al.
6025627	Alternate method and structure for improved floating gate tunneling devices	February, 2000	Forbes et al.
6031263	DEAPROM and transistor with gallium nitride or gallium aluminum nitride gate	February, 2000	Forbes et al.
6034882	Vertically stacked field programmable nonvolatile memory and method of fabrication	March, 2000	Johnson et al.
6049479	Operational approach for the suppression of bi-directional tunnel oxide stress of a flash cell	April, 2000	Thurgate et al.
6069380	Single-electron floating-gate MOS memory	May, 2000	Chou et al.
6069816	High-speed responding data storing device for maintaining stored data without power supply	May, 2000	Nishimura
6072209	Four F.sup.2 folded bit line DRAM cell structure having buried bit and word lines	June, 2000	Noble et al.
6101131	Flash EEPROM device employing polysilicon sidewall spacer as an erase gate	August, 2000	Chang
6111788	Method for programming and erasing a triple-poly split-gate flash	August, 2000	Chen et al.
6115281	Methods and structures to cure the effects of hydrogen annealing on ferroelectric capacitors	September, 2000	Aggarwal et al.
6122201	Clipped sine wave channel erase method to reduce oxide trapping charge generation rate of flash EEPROM	September, 2000	Lee et al.
6124729	Field programmable logic arrays with vertical transistors	September, 2000	Noble et al.
6125062	Single electron MOSFET memory device and method	September, 2000	Ahn et al.
6127227	Thin ONO thickness control and gradual gate oxidation suppression by b. N.su2 treatment in flash memory	October, 2000	Lin et al.
6134175	Memory address decode array with vertical transistors	October, 2000	Forbes et al.
6140181	Memory using insulator traps	October, 2000	Forbes et al.
6141237	Ferroelectric non-volatile latch circuits	October, 2000	Eliason et al.
6141238	Dynamic random access memory (DRAM) cells with repressed ferroelectric memory methods of reading same, and apparatuses including same	October, 2000	Forbes et al.
6141248	DRAM and SRAM memory cells with repressed memory	October, 2000	Forbes et al.
6141260	Single electron resistor memory device and method for use thereof	October, 2000	Ahn et al.
6143636	High density flash memory	November, 2000	Forbes et al.
6150687	Memory cell having a vertical transistor with buried source/drain and dual gates	November, 2000	Noble et al.
6153468	Method of forming a logic array for a decoder	November, 2000	Forbes et al.
6163049	Method of forming a composite interpoly gate dielectric	December, 2000	Bui
6166401	Flash memory with microcrystalline silicon carbide film floating gate	December, 2000	Forbes
6169306	Semiconductor devices comprised of one or more epitaxial layers	January, 2001	Gardner et al.
6185122	Vertically stacked field programmable nonvolatile memory and method of fabrication	February, 2001	Johnson et al.
6201734	Programmable impedance device	March, 2001	Sansbury et al.
6208164	Programmable logic array with vertical transistors	March, 2001	Noble et al.
6210999	Method and test structure for low-temperature integration of high dielectric constant gate dielectrics into self-aligned semiconductor devices	April, 2001	Gardner et al.
6212103	Method for operating flash memory	April, 2001	Ahrens et al.
6229175	Nonvolatile memory	May, 2001	Uchida
6232643	Memory using insulator traps	May, 2001	Forbes et al.
6238976	Method for forming high density flash memory	May, 2001	Noble et al.
6243300	Substrate hole injection for neutralizing spillover charge generated during programming of a non-volatile memory cell	June, 2001	Sunkavalli
6246606	Memory using insulator traps	June, 2001	Forbes et al.
6249020	DEAPROM and transistor with gallium nitride or gallium aluminum nitride gate	June, 2001	Forbes et al.
6249460	Dynamic flash memory cells with ultrathin tunnel oxides	June, 2001	Forbes et al.
6252793	Reference cell configuration for a 1T/1C ferroelectric memory	June, 2001	Allen et al.
6255683	Dynamic random access memory	July, 2001	Radens et al.
6269023	Method of programming a non-volatile memory cell using a current limiter	July, 2001	Derhacobian et al.
6288419	Low resistance gate flash memory	September, 2001	Prall et al.
6294813	Information handling system having improved floating gate tunneling devices	September, 2001	Forbes et al.
6307775	Deaprom and transistor with gallium nitride or gallium aluminum nitride gate	October, 2001	Forbes et al.
6310376	Semiconductor storage device capable of improving controllability of density and size of floating gate	October, 2001	Ueda et al.
6323844	Cursor controlling device and the method of the same	November, 2001	Yeh et al.
6337805	Discrete devices including EAPROM transistor and NVRAM memory cell with edge defined ferroelectric capacitance, methods for operating same, and apparatuses including same	January, 2002	Forbes et al.
6351411	Memory using insulator traps	February, 2002	Forbes et al.
6365470	Method for manufacturing self-matching transistor	April, 2002	Maeda
6407435	Multilayer dielectric stack and method	June, 2002	Ma et al.
6424001	Flash memory with ultra thin vertical body transistors	July, 2002	Forbes et al.
6438031	Method of programming a non-volatile memory cell using a substrate bias	August, 2002	Fastow
6444545	Device structure for storing charge and method therefore	September, 2002	Sadd et al.
6445030	Flash memory erase speed by fluorine implant or fluorination	September, 2002	Wu et al.
6449188	Low column leakage nor flash array-double cell implementation	September, 2002	Fastow
6456531	Method of drain avalanche programming of a non-volatile memory cell	September, 2002	Wang et al.
6456536	Method of programming a non-volatile memory cell using a substrate bias	September, 2002	Sobek et al.
6459618	Method of programming a non-volatile memory cell using a drain bias	October, 2002	Wang
6461931	Thin dielectric films for DRAM storage capacitors	October, 2002	Eldridge
6475857	Method of making a scalable two transistor memory device	November, 2002	Kim et al.
6487121	Method of programming a non-volatile memory cell using a vertical electric field	November, 2002	Thurgate et al.
6490205	Method of erasing a non-volatile memory cell using a substrate bias	December, 2002	Wang et al.
6495436	Formation of metal oxide gate dielectric	December, 2002	Ahn et al.
6498362	Weak ferroelectric transistor	December, 2002	Forbes et al.
6504755	Semiconductor memory device	January, 2003	Katayama et al.
6514828	Method of fabricating a highly reliable gate oxide	February, 2003	Ahn et al.
6521950	Ultra-high resolution liquid crystal display on silicon-on-sapphire	February, 2003	Shimabukuro et al.
6521958	MOSFET technology for programmable address decode and correction	February, 2003	Forbes et al.
6534420	Methods for forming dielectric materials and methods for forming semiconductor devices	March, 2003	Ahn et al.
6541280	High K dielectric film	April, 2003	Kaushik et al.
6541816	Planar structure for non-volatile memory devices	April, 2003	Ramsbey et al.
6545314	Memory using insulator traps	April, 2003	Forbes et al.
6552387	Non-volatile electrically erasable and programmable semiconductor memory cell utilizing asymmetrical charge trapping	April, 2003	Eitan
6559014	Preparation of composite high-K / standard-K dielectrics for semiconductor devices	May, 2003	Jeon
6566699	Non-volatile electrically erasable and programmable semiconductor memory cell utilizing asymmetrical charge trapping	May, 2003	Eitan
6567303	Charge injection	May, 2003	Hamilton et al.
6567312	Non-volatile semiconductor memory device having a charge storing insulation film and data holding method therefor	May, 2003	Torii et al.
6570787	Programming with floating source for low power, low leakage and high density flash memory devices	May, 2003	Wang et al.
6580124	Multigate semiconductor device with vertical channel current and method of fabrication	June, 2003	Cleeves et al.
6586785	Aerosol silicon nanoparticles for use in semiconductor device fabrication	July, 2003	Flagan et al.
6586797	Graded composition gate insulators to reduce tunneling barriers in flash memory devices	July, 2003	Forbes et al.
6600188	EEPROM with a neutralized doping at tunnel window edge	July, 2003	Jiang et al.
6618290	Method of programming a non-volatile memory cell using a baking process	September, 2003	Wang et al.
6630381	Preventing dielectric thickening over a floating gate area of a transistor	October, 2003	Hazani
6642573	Use of high-K dielectric material in modified ONO structure for semiconductor devices	November, 2003	Halliyal et al.
6674138	Use of high-k dielectric materials in modified ONO structure for semiconductor devices	January, 2004	Halliyal et al.
6867097	Method of making a memory cell with polished insulator layer	March, 2005	Ramsbey et al.
6996009	NOR flash memory cell with high storage density	February, 2006	Forbes
7045430	Atomic layer-deposited LaAlO3 films for gate dielectrics	May, 2006	Ahn et al.
7193893	Write once read only memory employing floating gates	March, 2007	Forbes
7221017	Memory utilizing oxide-conductor nanolaminates	May, 2007	Forbes et al.
7221586	Memory utilizing oxide nanolaminates	May, 2007	Forbes et al.
20010013621	Memory Device	August, 2001	Nakazato
20020003252	FLASH MEMORY CIRCUIT WITH WITH RESISTANCE TO DISTURB EFFECT	January, 2002	Iyer
20020027264	MOSFET technology for programmable address decode and correction	March, 2002	Forbes et al.
20020036939	Qualfication test method and circuit for a non-volatile memory	March, 2002	Tsai et al.
20020074565	Aerosol silicon nanoparticles for use in semiconductor device fabrication	June, 2002	Flagan et al.
20020106536	Dielectric layer for semiconductor device and method of manufacturing the same	August, 2002	Lee et al.
20020109158	Dynamic memory based on single electron storage	August, 2002	Forbes et al.
20020115252	Dielectric interface films and methods therefor	August, 2002	Haukka et al.
20020137250	High K dielectric film and method for making	September, 2002	Nguyen et al.
20020192974	Dielectric layer forming method and devices formed therewith	December, 2002	Ahn et al.
20030017717	METHODS FOR FORMING DIELECTRIC MATERIALS AND METHODS FOR FORMING SEMICONDUCTOR DEVICES	January, 2003	Ahn et al.
20030032270	Fabrication method for a device for regulating flow of electric current with high dielectric constant gate insulating layer and source/drain forming schottky contact or schottky-like region with substrate	February, 2003	Snyder et al.
20030042527	Programmable array logic or memory devices with asymmetrical tunnel barriers	March, 2003	Forbes et al.
20030042532	In service programmable logic arrays with low tunnel barrier interpoly insulators	March, 2003	Forbes
20030043622	DRAM Cells with repressed floating gate memory, low tunnel barrier interpoly insulators	March, 2003	Forbes
20030043630	DEAPROM WITH INSULATING METAL OXIDE INTERPOLY INSULATORS	March, 2003	Forbes et al.
20030043632	Programmable memory address and decode circuits with low tunnel barrier interpoly insulators	March, 2003	Forbes
20030043633	Programmable array logic or memory with p-channel devices and asymmetrical tunnel barriers	March, 2003	Forbes et al.
20030043637	Flash memory with low tunnel barrier interpoly insulators	March, 2003	Forbes et al.
20030045082	Atomic layer deposition of metal oxide and/or low asymmetrical tunnel barrier interploy insulators	March, 2003	Eldridge et al.
20030048666	Graded composition metal oxide tunnel barrier interpoly insulators	March, 2003	Eldridge et al.
20030235077	Write once read only memory employing floating gates	December, 2003	Forbes
20030235081	Nanocrystal write once read only memory for archival storage	December, 2003	Forbes
20030235085	WRITE ONCE READ ONLY MEMORY EMPLOYING CHARGE TRAPPING IN INSULATORS	December, 2003	Forbes
20040004245	Memory utilizing oxide-conductor nanolaminates	January, 2004	Forbes et al.
20040004247	Memory utilizing oxide-nitride nanolaminates	January, 2004	Forbes et al.
20040004859	Memory utilizing oxide nanolaminates	January, 2004	Forbes et al.
20040063276	Process for producing semiconductor integated circuit device	April, 2004	Yamamoto et al.
20060001080	Write once read only memory employing floating gates	January, 2006	Forbes
20060002188	Write once read only memory employing floating gates	January, 2006	Forbes
20060008966	Memory utilizing oxide-conductor nanolaminates	January, 2006	Forbes et al.
20070178643	Memory utilizing oxide-conductor nanolaminates	August, 2007	Forbes et al.

JP61166078	July, 1986			FLOATING-GATE TYPE NONVOLATILE MEMORY ELEMENT
JP03222367	October, 1991			INSULATED GATE TYPE FIELD EFFECT TRANSISTOR
JP06224431	August, 1994			THIN-FILM TRANSISTOR AND LIQUID CRYSTAL DISPLAY PANEL
JP06302828	October, 1994			NONVOLATILE SEMICONDUCTOR MEMORY DEVICE
JP08255878	October, 1996			FLOATING GATE TRANSISTOR AND FABRICATION THEREOF
WO-9907000	February, 1999
WO-9917371	April, 1999

US 7,262,094, 08/2007, Forbes (withdrawn)
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Hur J. H.

Schwegman, Lundberg & Woessner, P.A.

CROSS REFERENCE TO RELATED APPLICATIONS

This application is a continuation of U.S. patent application Ser. No. 10/190,717, filed Jul. 8, 2002 and issued on May 22, 2007 as U.S. Pat. No. 7,221,586, which is incorporated herein by reference.

This application is related to the following co-pending, commonly assigned U.S. patent applications: “Memory Utilizing Oxide-Nitride Nanolaminates,” Ser. No. 10/190,689, and “Memory Utilizing Oxide-Conductor Nanolaminates,” U.S. Pat. No. 7,221,017, each of which disclosure is herein incorporated by reference.

What is claimed is:

1. A transistor device, comprising: a first source/drain region a second source/drain region a channel region between the first and the second source/drain regions, and a gate separated from the channel region by a multilayer gate insulator; wherein the multilayer gate insulator includes oxide insulator nanolaminate layers, wherein at least one charge trapping layer is substantially amorphous; and circuitry coupled to the source/drain regions to program the transistor in a first direction, and read the transistor in a second direction opposite the first direction.

2. The transistor device of claim 1, wherein the insulator nanolaminate layers include-transition metal oxides.

3. The transistor device of claim 2, wherein the insulator nanolaminate layers including transition metal oxides are formed by atomic layer deposition (ALD).

4. The transistor device of claim 1, wherein the insulator nanolaminate layers include silicon oxycarbide.

5. The transistor device of claim 4, wherein the insulator nanolaminate layers including silicon oxycarbide include silicon oxycarbide deposited using chemical vapor deposition.

6. A vertical memory cell, comprising: a vertical metal oxide semiconductor field effect transistor (MOSFET) extending outwardly from a substrate, the MOSFET having a first source/drain region, a second source/drain region, a channel region between the first and the second source/drain regions, and a gate separated from the channel region by a multilayer gate insulator, wherein the multilayer gate insulator includes oxide insulator nanolaminate layers, at least one amorphous charge trapping nanolaminate layer formed using reaction sequence atomic layer deposition (RS-ALD) techniques; a sourceline coupled to the first source/drain region; a transmission line coupled to the second source/drain region; and circuitry coupled to the source/drain regions to program the MOSFET in a first direction, and read the MOSFET in a second direction opposite the first direction.

7. The vertical memory cell of claim 6, wherein the insulator nanolaminate layers includes transition metal oxides.

8. The vertical memory cell of claim 7, wherein all the insulator nanolaminate layers including transition metal oxides are formed by atomic layer deposition (ALD).

9. The vertical memory cell of claim 6, wherein the insulator nanolaminate layers include silicon oxycarbide.

10. The vertical memory cell of claim 9, wherein the insulator nanolaminate layers including silicon oxycarbide include silicon oxycarbide deposited using chemical vapor deposition.

11. The vertical memory cell of claim 6, wherein the first source/drain region of the MOSFET includes a source region and the second source/drain region of the MOSFET includes a drain region.

12. The vertical memory cell of claim 6, further including an electron charge trapped in the amorphous charge trapping nanolaminate layer adjacent the first source/drain region.

13. The vertical memory cell of claim 6, wherein the gate insulator has a thickness of approximately 10 nanometers (nm).

14. A vertical memory cell, comprising: a vertical metal oxide semiconductor field effect transistor (MOSFET) extending outwardly from a substrate, the MOSFET having a source region, a drain region, a channel region between the source region and the drain region, and a gate separated from the channel region by a multilayer gate insulator wherein the multilayer gate insulator includes oxide insulator nanolaminate layers, wherein at least one charge trapping layer is substantially amorphous; a wordline coupled to the gate; a sourceline formed in a trench adjacent to the vertical MOSFET, wherein the source region is coupled to the sourceline; a bit line coupled to the drain region; and circuitry coupled to the source/drain regions to program the MOSFET in a first direction, and read the MOSFET in a second direction opposite the first direction.

15. The memory cell of claim 14, wherein the insulator nanolaminate layers including transition metal oxides are formed by atomic layer deposition (ALD).

16. The memory cell of claim 14, wherein the gate insulator has a thickness of approximately 10 nanometers (nm).

17. A vertical memory cell, comprising: a vertical metal oxide semiconductor field effect transistor (MOSFET) extending outwardly from a substrate, the MOSFET having a source region, a drain region, a channel region between the source region and the drain region, and a gate separated from the channel region by a multilayer gate insulator wherein the multilayer gate insulator includes oxide insulator nanolaminate layers, wherein at least one charge trapping layer is substantially amorphous, at least one nanolaminate layer formed using reaction sequence atomic layer deposition (RS-ALD) techniques; a wordline coupled to the gate; a sourceline formed in a trench adjacent to the vertical MOSFET, wherein the source region is coupled to the sourceline; a bit line coupled to the drain region; and circuitry coupled to the source/drain regions to program the MOSFET in a first direction, and read the MOSFET in a second direction opposite the first direction.

18. The memory cell of claim 17, wherein the insulator nanolaminate layers including silicon oxycarbide include silicon oxycarbide deposited using chemical vapor deposition.

19. A transistor array, comprising: a number of transistor cells formed on a substrate, wherein each transistor cell includes a first source/drain region, a second source/drain region, a channel region between the first and the second source/drain regions, and a gate separated from the channel region by a multilayer gate insulator, and wherein the multilayer gate insulator includes oxide insulator nanolaminate layers, wherein at least one charge trapping layer is substantially amorphous; a number of bit lines coupled to the second source/drain region of each transistor cell along rows of the transistor array; a number of word lines coupled to the gate of each transistor cell along columns of the transistor array; a number of sourcelines, wherein the first source/drain region of each transistor cell is coupled to the number of sourcelines along rows of the transistor cells; and circuitry coupled to at least one transistor cell to program the transistor cell in a first direction, and read the transistor cell in a second direction opposite the first direction.

20. The transistor array of claim 19, wherein the insulator nanolaminate layers include transition metal oxides.

21. The transistor array of claim 20, wherein the insulator nanolaminate layers including transition metal oxides are formed by atomic layer deposition (ALD).

22. The transistor array of claim 19, wherein the insulator nanolaminate layers include silicon oxycarbide.

23. The transistor array of claim 22, wherein the insulator nanolaminate layers including silicon oxycarbide include silicon oxycarbide deposited using chemical vapor deposition.

24. The transistor array of claim 19, wherein a charge trapped in the charge trapping layer includes a charge adjacent to the source of approximately 100 electrons.

25. The transistor array of claim 19, wherein the first source/drain region of the transistor cell includes a source region and the second source/drain region of the transistor cell includes a drain region.

26. The transistor array of claim 19, wherein the gate insulator of each transistor cell has a thickness of approximately 10 nanometers (nm).

27. The transistor array of claim 19, wherein the number of transistor cells extending from the substrate operate as equivalent to a transistor having a size equal to or less than 1.0 lithographic feature squared (1F²).

28. A method for forming a transistor device, comprising: forming a first source/drain region, a second source/drain region, and a channel region therebetween in a substrate; forming a multilayer gate insulator opposing the channel region, wherein forming the multilayer gate insulator includes forming oxide insulator nanolaminate layers, wherein at least one charge trapping layer is substantially amorphous; forming a gate over the multilayer gate insulator; and coupling operation circuitry to the source/drain regions to program the transistor in a first direction and to read the transistor in a second direction opposite the first direction.

29. The method of claim 28, wherein forming oxide insulator nanolaminate layers includes forming oxide insulator nanolaminate layers of transition metal oxides.

30. The method of claim 29, wherein forming oxide insulator nanolaminate layers of transition metal oxides includes forming transition metal oxide insulator nanolaminate layers using atomic layer deposition (ALD).

31. The method of claim 28, wherein forming oxide insulator nanolaminate layers includes forming a nanolaminate layer of silicon oxycarbide.

32. The method of claim 31, wherein forming a nanolaminate layer of silicon oxycarbide includes forming a silicon oxycarbide layer using chemical vapor deposition.

FIELD OF THE INVENTION

The present invention relates generally to semiconductor intergrated circuits and, more particularly, to memory utilizing oxide nanolaminates.

BACKGROUND OF THE INVENTION

Many electronic products need various amounts of memory to store information, e.g. data. One common type of high speed, low cost memory includes dynamic random access memory (DRAM) comprised of individual DRAM cells arranged in arrays. DRAM cells include an access transistor, e.g a metal oxide semiconducting field effect transistor (MOSFET), coupled to a capacitor cell.

Another type of high speed, low cost memory includes floating gate memory cells. A conventional horizontal floating gate transistor structure includes a source region and a drain region separated by a channel region in a horizontal substrate. A floating gate is separated by a thin tunnel gate oxide. The structure is programmed by storing a charge on the floating gate. A control gate is separated from the floating gate by an intergate dielectric. A charge stored on the floating gate effects the conductivity of the cell when a read voltage potential is applied to the control gate. The state of cell can thus be determined by sensing a change in the device conductivity between the programmed and un-programmed states.

With successive generations of DRAM chips, an emphasis continues to be placed on increasing array density and maximizing chip real estate while minimizing the cost of manufacture. It is further desirable to increase array density with little or no modification of the DRAM optimized process flow.

Multilayer insulators have been previously employed in memory devices. The devices in the above references employed oxide-tungsten oxide-oxide layers. Other previously described structures described have employed charge-trapping layers implanted into graded layer insulator structures.

More recently oxide-nitride-oxide structures have been described for high density nonvolatile memories. All of these are variations on the original MNOS memory structure described by Fairchild Semiconductor in 1969 which was conceptually generalized to include trapping insulators in general for constructing memory arrays.

Studies of charge trapping in MNOS structures have also been conducted by White and others.

Some commercial and military applications utilized non-volatile MNOS memones.

However, these structures did not gain widespread acceptance and use due to their variability in characteristics and unpredictable charge trapping phenomena. They all depended upon the trapping of charge at interface states between the oxide and other insulator layers or poorly characterized charge trapping centers in the insulator layers themselves. Since the layers were deposited by CVD, they are thick, have poorly controlled thickness and large surface state charge-trapping center densities between the layers.

Thus, there is an ongoing need for improved DRAM technology compatible transistor cells. It is desirable that such transistor cells be fabricated on a DRAM chip with little or no modification of the DRAM process flow. It is further desirable that such transistor cells provide increased density and high access and read speeds.

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BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1A is a block diagram of a metal oxide semiconductor field effect transistor (MOSFET) in a substrate according to the teachings of the prior art.

FIG. 1B illustrates the MOSFET of FIG. 1A operated in the forward direction showing some degree of device degradation due to electrons being trapped in the gate oxide near the drain region over gradual use.

FIG. 1C is a graph showing the square root of the current signal (Ids) taken at the drain region of the conventional MOSFET versus the voltage potential (VGS) established between the gate and the source region.

FIG. 2A is a diagram of an embodiment for a programmed MOSFET, having oxide insulator nanolaminate layers, which can be used as a transistor cell according to the teachings of the present invention.

FIG. 2B is a diagram suitable for explaining a method embodiment by which a MOSFET, having oxide insulator nanolaminate layers, can be programmed to achieve the embodiments of the present invention.

FIG. 2C is a graph plotting the current signal (Ids) detected at the drain region versus a voltage potential, or drain voltage, (VDS) set up between the drain region and the source region (Ids vs. VDS).

FIG. 3 illustrates a portion of an embodiment of a memory array according to the teachings of the present invention.

FIG. 4 illustrates an electrical equivalent circuit 400 for the portion of the memory array shown in FIG. 3.

FIG. 5 illustrates an energy band diagram for an embodiment of a gate stack according to the teachings of the present invention.

FIG. 6 is a graph which plots electron affinity versus the energy bandgap for various insulators.

FIGS. 7A-7B illustrates an embodiment for the operation of a transistor cell having oxide insulator nanolaminate layers according to the teachings of the present invention.

FIG. 8 illustrates the operation of a conventional DRAM cell.

FIG. 9 illustrates an embodiment of a memory device according to the teachings of the present invention.

FIG. 10 is a schematic diagram illustrating a conventional NOR-NOR programmable logic array.

FIG. 11 is a schematic diagram illustrating generally an architecture of one embodiment of a programmable logic array (PLA) with logic cells, having oxide insulator nanolaminate layers according to the teachings of the present invention.

FIG. 12 is a block diagram of an electrical system, or processor-based system, utilizing oxide nanolaminates constructed in accordance with the present invention.

DETAILED DESCRIPTION

In the following detailed description of the invention, reference is made to the accompanying drawings which form a part hereof, and in which is shown, by way of illustration, specific embodiments in which the invention may be practiced. In the drawings, like numerals describe substantially similar components throughout the several views. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention. Other embodiments may be utilized and structural, logical, and electrical changes may be made without departing from the scope of the present invention.

The terms wafer and substrate used in the following description include any structure having an exposed surface with which to form the integrated circuit (IC) structure of the invention. The term substrate is understood to include semiconductor wafers. The term substrate is also used to refer to semiconductor structures during processing, and may include other layers that have been fabricated thereupon. Both wafer and substrate include doped and undoped semiconductors, epitaxial semiconductor layers supported by a base semiconductor or insulator, as well as other semiconductor structures well known to one skilled in the art. The term conductor is understood to include semiconductors, and the term insulator is defined to include any material that is less electrically conductive than the materials referred to as conductors. The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of the present invention is defined only by the appended claims, along with the full scope of equivalents to which such claims are entitled.

FIG. 1A is useful in illustrating the conventional operation of a MOSFET such as can be used in a DRAM array. FIG. 1A illustrates the normal hot electron injection and degradation of devices operated in the forward direction. As is explained below, since the electrons are trapped near the drain they are not very effective in changing the device characteristics.

FIG. 1A is a block diagram of a metal oxide semiconductor field effect transistor (MOSFET) 101 in a substrate 100 . The MOSFET 101 includes a source region 102 , a drain region 104 , a channel region 106 in the substrate 100 between the source region 102 and the drain region 104 . A gate 108 is separated from the channel region 108 by a gate oxide 110 . A sourceline 112 is coupled to the source region 102 . A bitline 114 is coupled to the drain region 104 . A wordline 116 is coupled to the gate 108 .

In conventional operation, a drain to source voltage potential (Vds) is set up between the drain region 104 and the source region 102 . A voltage potential is then applied to the gate 108 via a wordline 116 . Once the voltage potential applied to the gate 108 surpasses the characteristic voltage threshold (Vt) of the MOSFET a channel 106 forms in the substrate 100 between the drain region 104 and the source region 102 . Formation of the channel 106 permits conduction between the drain region 104 and the source region 102 , and a current signal (Ids) can be detected at the drain region 104 .

In operation of the conventional MOSFET of FIG. 1A, some degree of device degradation does gradually occur for MOSFETs operated in the forward direction by electrons 117 becoming trapped in the gate oxide 110 near the drain region 104 . This effect is illustrated in FIG. 1B. However, since the electrons 117 are trapped near the drain region 104 they are not very effective in changing the MOSFET characteristics.

FIG. 1C illustrates this point. FIG. 1C is a graph showing the square root of the current signal (Ids) taken at the drain region versus the voltage potential (VGS) established between the gate 108 and the source region 102 . The change in the slope of the plot of SQRT Ids versus VGS represents the change in the charge carrier mobility in the channel 106 .

In FIG. 1C, ΔVT represents the minimal change in the MOSFET's threshold voltage resulting from electrons gradually being trapped in the gate oxide 110 near the drain region 104 , under normal operation, due to device degradation. This results in a fixed trapped charge in the gate oxide 110 near the drain region 104 . Slope 103 represents the charge carrier mobility in the channel 106 for FIG. 1A having no electrons trapped in the gate oxide 110 . Slope 105 represents the charge mobility in the channel 106 for the conventional MOSFET of FIG. 1B having electrons 117 trapped in the gate oxide 110 near the drain region 104 . As shown by a comparison of slope 103 and slope 105 in FIG. 1C, the electrons 117 trapped in the gate oxide 110 near the drain region 104 of the conventional MOSFET do not significantly change the charge mobility in the channel 106 .

There are two components to the effects of stress and hot electron injection. One component includes a threshold voltage shift due to the trapped electrons and a second component includes mobility degradation due to additional scattering of carrier electrons caused by this trapped charge and additional surface states. When a conventional MOSFET degrades, or is “stressed,” over operation in the forward direction, electrons do gradually get injected and become trapped in the gate oxide near the drain. In this portion of the conventional MOSFET there is virtually no channel underneath the gate oxide. Thus the trapped charge modulates the threshold voltage and charge mobility only slightly.

One of the inventors, along with others, has previously described programmable memory devices and functions based on the reverse stressing of MOSFET's in a conventional CMOS process and technology in order to form programmable address decode and correction in U.S. Pat. No. 6,521,950 entitled “MOSFET Technology for Programmable Address Decode and Correction.” That disclosure, however, did not describe write once read only memory solutions, but rather address decode and correction issues. One of the inventors also describes write once read only memory cells employing charge trapping in gate insulators for conventional MOSFETs and write once read only memory employing floating gates. The same are described in co-pending, commonly assigned U.S. patent applications, entitled “Write Once Read Only Memory Employing Charge Trapping in Insulators,” Ser. No. 10/177,077, and “Write Once Read Only Memory Employing Floating Gates,” Ser. No. 10/177,083. The present application, however, describes transistor cells having oxide insulator nanolaminate layers and their use in integrated circuit device structures.

According to the teachings of the present invention, normal flash memory type cells can be programmed by operation in the reverse direction and utilizing avalanche hot electron injection to trap electrons in the gate insulator nanolaminate. When the programmed floating gate transistor is subsequently operated in the forward direction the electrons trapped in the gate insulator nanolaminate cause the channel to have a different threshold voltage. The novel programmed flash memory type transistors of the present invention conduct significantly less current than conventional flash cells which have not been programmed. These electrons will remain trapped in the gate insulator nanolaminate unless negative control gate voltages are applied. The electrons will not be removed from the gate insulator nanolaminate when positive or zero control gate voltages are applied. Erasure can be accomplished by applying negative control gate voltages and/or increasing the temperature with negative control gate bias applied to cause the trapped electrons in the gate insulator nanolaminate to be re-emitted back into the silicon channel of the MOSFET.

FIG. 2A is a diagram of an embodiment for a programmed transistor cell 201 having oxide insulator nanolaminate layers according to the teachings of the present invention. As shown in FIG. 2A the transistor cell 201 includes a transistor in a substrate 200 which has a first source/drain region 202 , a second source/drain region 204 , and a channel region 206 between the first and second source/drain regions, 202 and 204 . In one embodiment, the first source/drain region 202 includes a source region 202 for the transistor cell 201 and the second source/drain region 204 includes a drain region 204 for the transistor cell 201 . FIG. 2A further illustrates the transistor cell 201 having oxide insulator nanolaminate layers 208 separated from the channel region 206 by an oxide 210 . An sourceline or array plate 212 is coupled to the first source/drain region 202 and a transmission line 214 is coupled to the second source/drain region 204 . In one embodiment, the transmission line 214 includes a bit line 214 . Further as shown in FIG. 2A, a gate 216 is separated from the oxide insulator nanolaminate layers 208 by another oxide 218 .

As stated above, transistor cell 201 illustrates an embodiment of a programmed transistor. This programmed transistor has a charge 217 trapped in potential wells in the oxide insulator nanolaminate layers 208 formed by the different electron affinities of the insulators 208 , 210 and 218 . In one embodiment, the charge 217 trapped on the floating gate 208 includes a trapped electron charge 217 .

FIG. 2B is a diagram suitable for explaining the method by which the oxide insulator nanolaminate layers 208 of the transistor cell 201 of the present invention can be programmed to achieve the embodiments of the present invention. As shown in FIG. 2B the method includes programming the floating gate transistor. Programming the floating gate transistor includes applying a first voltage potential V 1 to a drain region 204 of the floating gate transistor and a second voltage potential V 2 to the source region 202 .

In one embodiment, applying a first voltage potential V 1 to the drain region 204 of the floating gate transistor includes grounding the drain region 204 of the floating gate transistor as shown in FIG. 2B. In this embodiment, applying a second voltage potential V 2 to the source region 202 includes biasing the array plate 212 to a voltage higher than VDD, as shown in FIG. 2B. A gate potential VGS is applied to the control gate 216 of the transistor. In one embodiment, the gate potential VGS includes a voltage potential which is less than the second voltage potential V 2 , but which is sufficient to establish conduction in the channel 206 of the transistor between the drain region 204 and the source region 202 . As shown in FIG. 2B, applying the first, second and gate potentials (V 1 , V 2 , and VGS respectively) to the transistor creates a hot electron injection into the oxide insulator nanolaminate layers 208 of the transistor adjacent to the source region 202 . In other words, applying the first, second and gate potentials (V 1 , V 2 , and VGS respectively) provides enough energy to the charge carriers, e.g. electrons, being conducted across the channel 206 that, once the charge carriers are near the source region 202 , a number of the charge carriers get excited into the oxide insulator nanolaminate layers 208 adjacent to the source region 202 . Here the charge carriers become trapped in potential wells in the oxide insulator nanolaminate layers 208 formed by the different electron affinities of the insulators 208 , 210 and 218 .

In an alternative embodiment, applying a first voltage potential V 1 to the drain region 204 of the transistor includes biasing the drain region 204 of the transistor to a voltage higher than VDD. In this embodiment, applying a second voltage potential V 2 to the source region 202 includes grounding the sourceline or array plate 212 . A gate potential VGS is applied to the control gate 216 of the transistor. In one embodiment, the gate potential VGS includes a voltage potential which is less than the first voltage potential V 1 , but which is sufficient to establish conduction in the channel 206 of the transistor between the drain region 204 and the source region 202 . Applying the first, second and gate potentials (V 1 , V 2 , and VGS respectively) to the transistor creates a hot electron injection into the oxide insulator nanolaminate layers 208 of the transistor adjacent to the drain region 204 . In other words, applying the first, second and gate potentials (V 1 , V 2 , and VGS respectively) provides enough energy to the charge carriers, e.g. electrons, being conducted across the channel 206 that, once the charge carriers are near the drain region 204 , a number of the charge carriers get excited into the oxide insulator nanolaminate layers 208 adjacent to the drain region 204 . Here the charge carriers become trapped in potential wells in the oxide insulator nanolaminate layers 208 formed by the different electron affinities of the insulators 208 , 210 and 218 , as shown in FIG. 2A.

In one embodiment of the present invention, the method is continued by subsequently operating the transistor in the forward direction in its programmed state during a read operation. Accordingly, the read operation includes grounding the source region 202 and precharging the drain region a fractional voltage of VDD. If the device is addressed by a wordline coupled to the gate, then its conductivity will be determined by the presence or absence of stored charge in the oxide insulator nanolaminate layers 208 . That is, a gate potential can be applied to the gate 216 by a wordline 220 in an effort to form a conduction channel between the source and the drain regions as done with addressing and reading conventional DRAM cells.

However, now in its programmed state, the conduction channel 206 of the transistor will have a higher voltage threshold and will not conduct.

FIG. 2C is a graph plotting a current signal (IDS) detected at the second source/drain region 204 versus a voltage potential, or drain voltage, (VDS) set up between the second source/drain region 204 and the first source/drain region 202 (IDS vs. VDS). In one embodiment, VDS represents the voltage potential set up between the drain region 204 and the source region 202 . In FIG. 2C, the curve plotted as 205 represents the conduction behavior of a conventional transistor where the transistor is not programmed (is normal or not stressed) according to the teachings of the present invention. The curve 207 represents the conduction behavior of the programmed transistor (stressed), described above in connection with FIG. 2A, according to the teachings of the present invention. As shown in FIG. 2C, for a particular drain voltage, VDS, the current signal (IDS 2 ) detected at the second source/drain region 204 for the programmed transistor (curve 207 ) is significantly lower than the current signal (IDS 1 ) detected at the second source/drain region 204 for the conventional transistor cell (curve 205 ) which is not programmed according to the teachings of the present invention. Again, this is attributed to the fact that the channel 206 in the programmed transistor of the present invention has a different voltage threshold.

Some of these effects have recently been described for use in a different device structure, called an NROM, for flash memories. This latter work in Israel and Germany is based on employing charge trapping in a silicon nitride layer in a non-conventional flash memory device structure. Charge trapping in silicon nitride gate insulators was the basic mechanism used in MNOS memory devices, charge trapping in aluminum oxide gates was the mechanism used in MIOS memory devices, and one of the present inventors, along with another, has previously disclosed charge trapping at isolated point defects in gate insulators. However, none of the above described references addressed forming transistor cells utilizing charge trapping in potential wells in oxide insulator nanolaminate layers formed by the different electron affinities of the insulators.

FIG. 3 illustrates an embodiment for a portion of a memory array 300 according to the teachings of the present invention. The memory in FIG. 3, is shown illustrating a number of vertical pillars, or transistor cells, 301 - 1 , 301 - 2 , . . . , 301 -N, formed according to the teachings of the present invention. As one of ordinary skill in the art will appreciate upon reading this disclosure, the number of vertical pillar are formed in rows and columns extending outwardly from a substrate 303 . As shown in FIG. 3, the number of vertical pillars, 301 - 1 , 301 - 2 , . . . , 301 -N, are separated by a number of trenches 340 . According to the teachings of the present invention, the number of vertical pillars, 301 - 1 , 301 - 2 , . . . , 301 -N, serve as transistors including a first source/drain region, e.g. 302 - 1 and 302 - 2 respectively. The first source/drain region, 302 - 1 and 302 - 2 , is coupled to a sourceline 304 . As shown in FIG. 3, the sourceline 304 is formed in a bottom of the trenches 340 between rows of the vertical pillars, 301 - 1 , 301 - 2 , . . . , 301 -N. According to the teachings of the present invention, the sourceline 304 is formed from a doped region implanted in the bottom of the trenches 340 . A second source/drain region, e.g. 306 - 1 and 306 - 2 respectively, is coupled to a bitline (not shown). A channel region 305 is located between the first and the second source/drain regions.

As shown in FIG. 3, oxide insulator nanolaminate layers, shown generally as 309 , are separated from the channel region 305 by a first oxide layer 307 in the trenches 340 along rows of the vertical pillars, 301 - 1 , 301 - 2 , . . . , 301 -N. In the embodiment shown in FIG. 3, a wordline 313 is formed across the number of pillars and in the trenches 340 between the oxide insulator nanolaminate layers 309 . The wordline 313 is separated from the pillars and the oxide insulator nanolaminate layers 309 by a second oxide layer 317 .

FIG. 4 illustrates an electrical equivalent circuit 400 for the portion of the memory array shown in FIG. 3. As shown in FIG. 4, a number of vertical transistor cells, 401 - 1 , 401 - 2 , . . . , 401 -N, are provided. Each vertical transistor cell, 401 - 1 , 401 - 2 , . . . , 401 -N, includes a first source/drain region, e.g. 402 - 1 and 402 - 2 , a second source/drain region, e.g. 406 - 1 and 406 - 2 , a channel region 405 between the first and the second source/drain regions, and oxide insulator nanolaminate layers, shown generally as 409 , separated from the channel region by a first oxide layer.

FIG. 4 further illustrates a number of bit lines, e.g. 411 - 1 and 411 - 2 . According to the teachings of the present invention as shown in the embodiment of FIG. 4, a single bit line, e.g. 411 - 1 is coupled to the second source/drain regions, e.g. 406 - 1 and 406 - 2 , for a pair of transistor cells 401 - 1 and 401 - 2 since, as shown in FIG. 3, each pillar contains two transistor cells. As shown in FIG. 4, the number of bit lines, 411 - 1 and 411 - 2 , are coupled to the second source/drain regions, e.g. 406 - 1 and 406 - 2 , along rows of the memory array. A number of word lines, such as wordline 413 in FIG. 4, are coupled