Kaifu, Noriyuki (Tokyo, JP)
Sato, Toshiaki (Shizuoka-ken, JP)
Morishita, Masakazu (Kanagawa-ken, JP)
Plaque It!
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1. A radiation image pickup apparatus comprising: a photoelectric conversion circuit section having a pixel group comprising a plurality of pixels each including a photoelectric conversion element and a switching element of an amorphous semiconductor, and a plurality of signal wires arranged over an insulating substrate in order to output parallel signals from the pixel group; a first switch connected to the signal wires to reset the signal wires; a wavelength converter for converting a radiation into light which can be sensed by the photoelectric conversion element; and a reading circuit section for converting the parallel signals transferred through said signal wires to serial signals to output the serial signals, wherein the reading circuit section has at least one analog operational amplifier connected to each signal wire and includes a function for reducing its power consumption based on an external signal, a first capacitor element being connected in series to an output terminal of the analog operational amplifier for passing through only an alternating component, a second switch for DC restoration of the first capacitor element, a third switch for sampling each parallel signal amplified by the analog operational amplifier and outputted through the first capacitor element, a second capacitor element for holding the parallel signal transferred through the third switch, and a fourth switch for reading the parallel signal from the second capacitor element as a serial signal sequentially, and wherein after the parallel signal outputted through the first capacitor element from the analog operational amplifier is sampled and held through the third switch by the second capacitor element, the first switch resets the signal wire of the analog operational amplifier, and the second switch is turned on together with the first switch simultaneously, and is turned off with a delay after turning off the first switch.
2. The radiation image pickup apparatus according to claim 1, wherein the analog operational amplifier has a controllable amplification ratio.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a photoelectric conversion apparatus and a photoelectric conversion system having the apparatus. More particularly, the invention relates to a photoelectric conversion apparatus applicable to X-ray detectors for non-destructive examination such as medical care or internal examination, to image input units for business machines such as digital copiers, electronic blackboards, and facsimile machines, and so on, and also relates to a system having the apparatus.
2. Related Background Art
Presently, the majority of X-ray image pickup apparatus used for medical diagnosis employs a so-called film method in which X-rays are radiated to a human body, then the X-rays transmitted by the human body irradiate a fluorescent member for converting X-rays to visible light, and a film is exposed to fluorescence therefrom.
However, not only in Japan going into aging society, but also in the world, strong desires exist to improve the diagnostic efficiency in hospitals and to have higher-accuracy medical equipment. Even under such circumstances, the X-ray image pickup apparatus of the conventional film method requires a lot of time because of intervention of a development step of film before a doctor obtains a patient's X-ray image. In some incidents where the patient moves during X-ray photography and where exposure is misadjusted, photography must be carried out again. These are factors to impede an improvement in the efficiency of diagnosis and treatment in hospitals and also force a great load on the patient, which would be great hindrance against development to new medical society in future.
The demand for “digitization of X-ray image information” is increasing in the medical field these years. Once digitization is achieved, the doctor can know the patient's X-ray image information at optimum angles in real time, and the X-ray image information obtained can be recorded and managed using a medium such as a magneto-optical disk. Utilizing facsimile or another communication method or the like, the patient's X-ray image information can be sent within a short time to any hospital in the world.
In the non-destructive examination typified by examination of the inside of an object such as a building body, it is not permissible to repeat setting of various devices for X-ray photography or to repeat photography of necessary parts, either. In the case of the film method, however, whether photography of necessary parts is completed cannot be found before the end of development in such examination, either. Since expert's judgment is made after completion of development of film, it is not possible for the expert to give an instruction of photography at another in situ angle or an instruction of treatment in situ when necessary.
Accordingly, a demand is also high for acquisition of X-ray image information of desired parts in real time in this field.
Then, recently proposed in order to meet the demand for “digitization of X-ray image information” are X-ray image pickup devices using CCD solid state image sensing devices or amorphous silicon photoelectric conversion elements instead of the film.
FIG. 1 is an equivalent circuit diagram of an example of the two-dimensional photoelectric conversion apparatus applicable to such X-ray image pickup apparatus. FIG. 1 illustrates the two-dimensional photoelectric conversion apparatus of 3×3 for simplifying the description, but practical photoelectric conversion apparatus are constructed of much more bits, though depending upon the purpose of apparatus.
In FIG. 1, each of T 1 - 1 , T 1 - 2 , T 1 - 3 , T 2 - 1 , . . . , T 3 - 3 designates a switching element, each of S 1 - 1 , S 1 - 2 , S 1 - 3 , S 2 - 1 , . . . , S 3 - 3 a photoelectric conversion element, SR 1 a shift register, SR 2 a shift register, each of G 1 , G 2 , G 3 a gate drive wire, each of M 1 , M 2 , M 3 a signal wire, each of C 1 , C 2 , C 3 an accumulating capacitors (e.g. equivalent additional capacitors added to a wiring), each of RES 1 , RES 2 , RES 3 a reset switch, CRES a voltage pulse input section for reset, OP an operational amplifier, Ca an accumulated capacitance, each of U 1 , U 2 , U 3 a switching element for read, each of N 1 , N 2 , N 3 a gate drive wire for switching element U 1 to U 3 , respectively, numeral 1 a photoelectric conversion circuit section, and numeral 2 a reading circuit section.
In FIG. 1, light hv incident to photoelectric conversion elements S 1 - 1 to S 3 - 3 is photoelectrically converted by the photoelectric conversion elements S 1 - 1 to S 3 - 3 to charges of photoelectric conversion signals, which are accumulated in interelectrode capacitances of the respective photoelectric conversion elements S 1 - 1 to S 3 - 3 . These photoelectric conversion signals pass through transfer switch T 1 - 1 to T 3 - 3 and signal wire M 1 to M 3 to become parallel voltage outputs. Further, they are converted to serial signals by the reading switch circuit section to be taken out to the outside.
In the structural example of the photoelectric conversion apparatus of FIG. 1, the photoelectric conversion elements of 9-bit pixels in total are separated in three rows, each including three bits. The above-stated operation is carried out in row units in order.
FIG. 2 is a timing chart to show an example of the operation of the photoelectric conversion apparatus shown in FIG. 1.
Optical information (hν) input to the photoelectric conversion elements S 1 - 1 to S 1 - 3 in the first row is photoelectrically converted to signal charges, which are accumulated in interelectrode capacitors in the respective photoelectric conversion elements of S 1 - 1 to S 1 - 3 . After a lapse of constant accumulation time, the shift register SR 1 gives a first voltage pulse for transfer to the gate driving wire G 1 during a period of time T 1 to switch the transfer switch elements T 1 - 1 to T 1 - 3 on. This causes the signal charges accumulated in the respective interelectrode capacitors (S 1 - 1 to S 1 - 3 ) in the photoelectric conversion elements S 1 - 1 to S 1 - 3 to be transferred through the respective signal wires M 1 to M 3 to load capacitances C 1 to C 3 , whereby potentials V 1 to V 3 of the respective load capacitances C 1 to C 3 are raised by a charge amount of signal (transfer operation).
Subsequently, the shift register SR 2 successively gives voltage pulses to gate driving wires N 1 to N 3 to switch reading switches U 1 to U 3 on in order, thereby converting the signals of the first row having been transferred to the load capacitances C 1 to C 3 to serial signals, and after impedance transformation by the voltage follower type operational amplifier OP, the signal of three pixels (Vout) is output to the outside of the photoelectric conversion apparatus during a period of time T 3 (reading operation).
After that, a voltage pulse CRES for reset is applied to reset switches RES 1 to RES 3 during a period of time T 2 to reset the load capacitances C 1 to C 3 , thereby getting ready for the reading operation of the next row (reset operation).
Then the shift register SR 1 successively drives the gate driving wires G 2 , G 3 , thereby outputting data of the all pixels of the photoelectric conversion elements S 2 - 1 to S 3 - 3 in time series.
Since the photoelectric conversion apparatus of an area type in which photosensors are arrayed two-dimensionally is generally arranged to successively perform the operations of transfer, reading, and reset in row units as described above, the image signals from the photoelectric conversion apparatus are intermittently output as shown by Vout in FIG. 2. Namely, the time necessary for reading one row is T 1 +T 3 +T 2 , and in the case of the two-dimensional photoelectric conversion apparatus of 3×3 shown in FIG. 1, the time of three times thereof is necessary for reading the all bits. For example, the size of the photoelectric conversion apparatus portion of the medical X-ray image pickup apparatus is said to be approximately 40 cm×40 cm necessary for the example of the X-ray image pickup apparatus for photographing the lung part. Supposing it is formed in pixel pitch of 100 μm, the total pixel number will be as huge as 4000×4000=16 million pixels. Simply assuming that the structure shown in FIG. 1 is used to perform the reading operation, the time of 4000×(T 1 +T 2 +T 3 ) is necessary. Actually, the time necessary for T3 becomes longer, and therefore, a normal arrangement is provided with a plurality of (N) reading circuit sections to permit parallel reading scanning of N bits, thereby reading the all pixels in the time of 4000×(T 1 +T 2 +T 3 /N).
However, in the photoelectric conversion apparatus for successively performing the operations of from transfer through reading to reset, even with employing such structure, the time necessary for reading pixels in one line (=4000/N pixels) needs to include the transfer time T 1 and reset time T 2 every time of reading the pixels in each line, and therefore, the apparatus has a problem that the scanning time of photoelectric conversion, especially, with a lot of pixels was sometimes longer than expected. Especially, when the transfer switching elements (T 1 - 1 to T 3 - 3 ) are constructed of amorphous silicon (hereinafter referred to as “a-Si”) TFTs (Thin Film Transistors) highly advantageous in respect of cost, they are not sufficient in switching performance as compared with switch elements made of single-crystal silicon, which leaves a subject of an improvement in achieving higher-speed reading of photoelectric conversion apparatus.
The load capacitors are illustrated as capacitance elements of reading capacitors C 1 to C 3 in FIG. 1, but practically, without a need for provision of separate elements, they are normally comprised of the interelectrode capacitances (Cgs) formed by the gate electrodes of the switching elements T 1 - 1 to T 3 - 3 and the electrodes on the side of signal wires M 1 to M 3 . For example, when the signal charge of S 1 - 1 in the first row is transferred, the capacitance of the load capacitor (reading capacitor) C 1 is the sum of Cgs of the switching elements T 1 - 1 , T 2 - 1 , and T 3 - 1 parasitic on the signal wire M 1 . Similarly, for example, when the signal charge of S 2 - 2 in the second row is transferred, the capacitance of C 2 is the sum of Cgs of the switching elements T 1 - 2 , T 2 - 2 , and T 3 - 2 parasitic on the signal wire M 2 . In summary, whenever a signal charge of any photoelectric conversion element is transferred, the load capacitor (C 1 to C 3 ) is given by addition of three capacitances of Cgs of the switching elements. Similarly, when the two-dimensional photoelectric conversion apparatus is constructed of 4000×4000 pixels, the load capacitance of each signal line in the matrix will have the capacitance of Cgs×4000. On the other hand, when the signal charges of the load capacitances are converted to serial signals by the switching elements U 1 to U 3 in the reading circuit section, each signal charge is virtually transferred to the input capacitance (Ca in FIG. 1) parasitic to the input of the analog operational amplifier (OP amp) OP. When the transfer switching elements are made of a-Si, impedance transformation is achieved with little reducing the signal potential of the load capacitance, because the load capacitance of Cgs×4000>>Ca.
Also, there is a possibility of raising a problem that upon performing the transfer operation from the load capacitor (C 1 to C 3 ) to the operational amp OP side through the switching element (U 1 to U 3 ) controlled by the shift register SR 2 , the thermal noise occurring due to thermal agitation of carriers in the switching elements might degrade S/N of the photoelectric conversion apparatus in some cases. The effective value Vj of this thermal noise voltage is given, generally, by
Vj= (4 KTRB ) 1/2 ( Vrms ).
Here, K is the Boltzmann constant, 1.38×10 −23 (J/K), T is an absolute temperature (K), and B is the frequency bandwidth (Hz) of system. Further, R is a resistance (Ω) in the case of the thermal noise occurring in a resistor. In the case of this system, it may be considered as ON resistance (Ω) of the switching elements.
Letting CL be the matrix-side capacitance (Cgs×4000) and Ca be the input capacitance on the operational amp OP side, the frequency bandwidth B can be approximated as B=1/(4R(CL∥Ca)) in the thermal noise voltage Vj=(4KTRB) 1/2 (Vrms), and therefore,
Vj= (4 KTR/( 4 R ( CL∥Ca ))) 1/2
=( KT/ ( CL∥Ca )) 1/2 .
Here, CL∥Ca is series combined capacitance of CL and Ca.
Incidentally, if it is expressed as a charge amount, Qj=CV=(KT/(CL∥Ca)) 1/2 (Vrms). Namely, the thermal noise voltage Vj occurring in such a system is determined only by the Boltzmann constant K, temperature T, and capacitance C (=CL∥Ca), which is normally called KTC noise. Unless otherwise stated, the thermal noise voltage will be called “KTC noise” hereinafter. This KTC noise is given in the simplified form of (KT/(CL∥Ca)) 1/2 (Vrms). Since CL>>Ca, the KTC noise is determined nearly by (kT/Ca) 1/2 . The noise of this type can be reduced by increasing Ca, but there is limitation on increase in the capacitance formed in an integrated circuit (IC).
Similarly, the KTC noise also occurs upon resetting the load capacitances to the reset potential by the reset switches RES 1 to RES 3 , which raises the problem of reduction in S/N of the photoelectric conversion apparatus. This KTC noise upon reset is given by (KT/CL) 1/2 (V). The KTC noise occurring upon transfer and the KTC noise occurring upon reset appears as random noise of photoelectric conversion apparatus. Especially, if high-definition and high-gradation-level information is desired to obtain as in the medical X-ray image pickup apparatus, the apparatus will necessitate the photoelectric conversion apparatus with higher S/N ratios than the business machines such as copiers or electronic blackboards, and, the KTC noise could be a big problem.
In the photoelectric conversion circuit section, letting CS be the interelectrode capacitance of single photoelectric conversion element, CL be the load capacitance in the matrix signal wire, and Q be a total amount of accumulated signal charge after photoelectrically converted by the photoelectric conversion element, the signal potential V of the load capacitance CL on the matrix signal wire, after transfer by the transfer switching element, is given by V=Q/(CS+CL). Since single interelectrode capacitance CS is much smaller than the load capacitance CL composed of the 4000 interelectrode capacitances Cgs, it is practically approximated by V=Q/CL. When the switching elements having the interelectrode capacitance Cgs are made of an a-Si semiconductor thin film, individual differences will appear in capacitance values of load capacitance CL among apparatus because of dispersion in film thickness on fabrication of thin film, which would raise a problem that apparatus with high output and apparatus with low output are manufactured. In order to overcome it, upon constructing the system, such a countermeasure is taken as to add a general-purpose OP amp to adjust the gain, but the above example necessitates N general-purpose amplifiers, which will raise the cost of apparatus when also taking the adjustment process into consideration.
Also, the N reading circuit sections (ICs), especially in the equipment requiring high S/N ratios like the medical equipment, are not preferred to be located with long extension of the signal wires also in respect of an anti-noise property, but the necessary circuits are desired to be mounted near the photoelectric conversion circuit section. However, if many (N) ICs are provided, heat generation thereof will increase the temperature of the photoelectric conversion circuit section in some cases. Especially, when the switching elements are amorphous silicon TFTs, it is said that the dark current during OFF will increase, and there is a possibility of raising another problem that the heat generation of ICs could increase fixed pattern noise of photoelectric conversion apparatus.
For example, when the photoelectric conversion apparatus portion of the medical X-ray image pickup apparatus is constructed of a solid state image sensing apparatus, the noise quantity required for the whole apparatus including the photoelectric conversion elements is said to be 1/10000 or less against the dynamic range of signal if the image quality higher than that of the film method is desired to achieve. Namely, the resolution of 14 or more bits is required as performance of the A/D converter necessary for achieving the “digitization of X-ray image information.” A/D converters of 16 bits are commercially available presently, but it is a present status that the conversion speed decreases with increase of bit number, and to date there has been and is no high-speed A/D converter of 14 or more bits that can be used practically and actually in the X-ray image pickup apparatus having the photoelectric conversion apparatus of 4000×4000 pixels as described above.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a photoelectric conversion apparatus that can reduce the read scanning time so as to enable high-speed reading and also to provide a system having the apparatus.
Another object of the present invention is to provide a photoelectric conversion apparatus that can perform signal reading at high S/N with little generation of thermal noise (KTC noise) and also to provide a system having the apparatus.
An additional object of the present invention is to provide a photoelectric conversion apparatus that can obtain good image information without density unevenness or unnecessary stripes, reduced in fixed pattern noise, and also to provide a system having the apparatus.
A further object of the present invention is to provide a photoelectric conversion apparatus that can obtain image information excellent in tone level and also to provide a system having the apparatus.
Still another object of the present invention is to provide a photoelectric conversion apparatus that can be corrected readily for nonuniformity of characteristic such as one caused by manufacturing dispersion of photoelectric conversion element or the like, thereby enabling further promotion of cost reduction and also to provide a system having the apparatus.
An object of the present invention is to provide a photoelectric conversion apparatus having a photoelectric conversion circuit section comprising a plurality of photoelectric conversion elements, switching elements, matrix signal wires, and gate drive wires arranged on a same substrate in order to output parallel signals, a driving circuit section for applying a driving signal to said gate drive wire, and a reading circuit section for converting the parallel signals transferred through said matrix signal wires to serial signals to output the serial signals,
wherein said reading circuit section comprises at least one analog operational amplifier connected with each of said matrix signal wires, transfer switches for transferring output signals from said respective matrix signal wires, output through each said analog operational amplifier, reading capacitors for accumulating said output signals transferred, and reading switches for successively reading signals out of said reading capacitors in the form of serial signals.
A further object of the present invention is to provide a photoelectric conversion system having at least: a photoelectric conversion apparatus having a photoelectric conversion circuit section comprising a plurality of photoelectric conversion elements, switching elements, matrix signal wires, and gate drive wires arranged on a same substrate in order to output parallel signals, a driving circuit section for applying a driving signal to said gate drive wire, and a reading circuit section for converting the parallel signals transferred through said matrix signal wires to serial signals to output the serial signals; and a light source;
wherein said reading circuit section of said photoelectric conversion apparatus comprises at least one analog operational amplifier connected with each of said matrix signal wires, transfer switches for transferring output signals from said respective matrix signal wires, output through each said analog operational amplifier, reading capacitors for accumulating said output signals transferred, and reading switches for successively reading signals out of said reading capacitors in the form of serial signals.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a schematic circuit diagram for explaining an example of the photoelectric conversion apparatus;
FIG. 2 is a timing chart for explaining an example of the driving method of the photoelectric conversion apparatus;
FIG. 3 is a schematic circuit diagram for explaining an example of the photoelectric conversion apparatus;
FIG. 4 is a timing chart for explaining an example of the driving method of the photoelectric conversion apparatus;
FIG. 5A is a schematic top plan view for explaining an example of the photoelectric conversion element;
FIG. 5B is a schematic cross-sectional view for explaining an example of the photoelectric conversion element;
FIG. 6 is a schematic circuit diagram for explaining an example of the photoelectric conversion apparatus;
FIG. 7 is a schematic structural drawing for explaining an example of a device having the photoelectric conversion apparatus;
FIG. 8 is a schematic circuit diagram for explaining an example of the photoelectric conversion apparatus;
FIG. 9 is a timing chart for explaining an example of drive of the photoelectric conversion apparatus;
FIG. 10 is a schematic circuit diagram for explaining an example of the photoelectric conversion apparatus;
FIG. 11 is a schematic circuit diagram for explaining an example of the operational amplifier;
FIG. 12 is a schematic circuit diagram for explaining an example of the operational amplifier;
FIG. 13 is a schematic circuit diagram for explaining an example of the A/D conversion circuit;
FIG. 14 is a schematic circuit diagram for explaining an example of a selector circuit section;
FIG. 15 is a schematic circuit diagram for explaining an example of a bit conversion circuit section;
FIG. 16 is a schematic circuit diagram for explaining an example of the photoelectric conversion apparatus;
FIG. 17 is a schematic circuit diagram for explaining an example of the photoelectric conversion apparatus;
FIG. 18 is a timing chart for explaining an example of input/output to and from a delay circuit shown in FIG. 17;
FIG. 19 is a schematic circuit diagram for explaining an example of a sample hold circuit;
FIG. 20 is a schematic circuit diagram for explaining an example of the photoelectric conversion apparatus;
FIG. 21 is a timing chart for explaining an example of drive of the photoelectric conversion apparatus;
FIGS. 22A, 22 B and 22 C are schematic energy band diagrams for explaining an example of drive of photoelectric conversion element;
FIG. 23 is a schematic circuit diagram for explaining an example of the photoelectric conversion apparatus; and
FIG. 24 is a timing chart for explaining an example of drive of the photoelectric conversion apparatus.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
The present invention will be described with reference to the drawings if necessary.
For solving the above various problems, for example, a photoelectric conversion apparatus of the present invention has a photoelectric conversion circuit section comprising a plurality of photoelectric conversion elements, switching elements, matrix signal wires, and gate drive wires arranged on a same substrate in order to output parallel signals, a driving circuit section for applying a driving signal to said gate drive wire, and a reading circuit section for converting the parallel signals transferred through said matrix signal wires to serial signals to output them, wherein said reading circuit section comprises at least one analog operational amplifier connected in cascade connection with each of said matrix signal wires, transfer switches for transferring output signals from said respective matrix signal wires, output through the analog operational amplifiers, reading capacitors for accumulating said output signals transferred, and reading switches for successively reading signals out of said reading capacitors in the form of serial signals.
Also, it is preferable that in said reading circuit section, said analog operational amplifier of first stage connected to each of the matrix signal wires have a noise voltage density Vn (V/√{square root over (Hz)}) converted at an input terminal portion thereof and a frequency band B (Hz) enough to amplify a signal from said photoelectric conversion circuit section and satisfy the relation of: Vn×√{square root over (B)}≦Tn against thermal noise effective voltage Tn (Vrms) of said switching element at the input terminal portion of said analog operational amplifier, occurring when the switching element in said photoelectric conversion circuit section is turned on.
Further, it is preferable that in said reading circuit section, a capacitor element for letting only alternating-current components pass be connected to midway of an output wire from an output terminal of said analog operational amplifier connected with each of said matrix signal wires and that a reset switch for DC restoration of said capacitor element be provided.
Also, it is preferable that in said reading circuit section, the at least one analog operational amplifier connected with each of the matrix signal wires be provided with a function to change an amplification factor thereof by a signal from the outside.
In addition, it is preferable that in said reading circuit section, the analog operational amplifier connected with each of the matrix signal wires be provided with a function to reduce a consumption electric current thereof by a signal from the outside.
Also, it is preferable that an A/D conversion circuit section for converting an analog signal to a digital signal be connected to said reading circuit section, that this A/D conversion circuit section comprise N (N is an integer of not less than 2) operational amplifiers for amplifying a signal from said reading circuit section and N A/D converters of M bits, that a ratio of amplification factors G 1 , G 2 , . . . , GN of said N operational amplifiers be set to G 1 :G 2 : . . . :GN=2 0 :2 1 : . . . :2 N−1 , that outputs from said N operational amplifiers each be input to said N A/D converters, and that an output of one A/D converter be selected out of said N A/D converters in accordance with an output level of an analog signal from said reading circuit section and be output as a digital value of (N+M−1) bits.
Also, the foregoing reading circuit section is configured preferably in such an arrangement that near the first analog operational amplifier (amp 1 ) connected to each of the matrix signal wires there is provided another analog operational amplifier (amp 2 ), the amp 1 is constructed as a non-inverting amplifier having an amplification factor of not less than 1×, the amp 2 is constructed as a buffer amplifier having an amplification factor of 1×, and a reference potential to be a reference of operation of the amp 1 is supplied from an output terminal of the amp 2 .
Also, the reading circuit section is configured preferably in such an arrangement that a capacitor element for passing only ac components is connected to midway of an output wire from an output terminal of the analog operational amplifier connected to each of the matrix signal wires, a reset switch for dc restoration of the capacitor element is provided, and a resistance element is interposed between the capacitor element and the reset switch.
Also, the reading circuit section is configured preferably in such an arrangement that a capacitor element for passing only ac components is connected to midway of an output wire from an output terminal of the analog operational amplifier connected to each of the matrix signal wires, a reset switch for dc restoration of the capacitor element is provided, a resistance element is interposed between the capacitor element and the reset switch, and there is provided a function for varying an on/off time of the reset switch by a signal from the outside.
Also, the reading circuit section is configured preferably in such an arrangement that a capacitor element for passing only ac components is connected to midway of an output wire from an output terminal of the analog operational amplifier connected to each of the matrix signal wires, a reset switch for dc restoration of the capacitor element is provided, and a low-pass filter circuit is connected to a terminal out of those of the capacitor element, opposite to a terminal connected to the output of the analog operational amplifier.
Also, the reading circuit section is configured preferably in such an arrangement that the at least one analog operational amplifier connected with each of the matrix signal wires has a function to vary a slew rate thereof by a signal from the outside.
Further, it is preferable that the photoelectric conversion elements and switching elements in said photoelectric conversion circuit section be made using an amorphous silicon semiconductor as a semiconductor material.
Also, the apparatus may be configured in such an arrangement that each of the photoelectric conversion elements is comprised of, from the insulating substrate side, a first metal thin-film layer (first electroconductive layer) as a lower electrode, an amorphous silicon nitride insulating layer (a-SiNx) for preventing passage of electron carriers and hole carriers, a hydrogenated amorphous silicon photoelectric conversion layer (a-Si:H) as a semiconductor layer, an n-type injection preventing layer for preventing injection of hole carriers, and a transparent electroconductive layer or a second metal thin-film layer located in a part on the injection preventing layer, as an upper electrode (second electroconductive layer), that each of the switching elements (thin-film transistors) is comprised of, from the insulating substrate side, a first metal thin-film layer as a lower gate electrode, a gate insulating layer (a-SiNx) of amorphous silicon nitride, a hydrogenated amorphous silicon semiconductor layer (a-Si:H), an n-type ohmic contact layer, and a transparent electroconductive layer or a second metal thin-film layer as a source or drain electrode, that the photoelectric conversion elements and the switching elements are formed on the same insulating substrate, that in a refresh mode an electric field is applied to the photoelectric conversion elements in such a direction as to guide hole carriers from the photoelectric conversion layer to the second metal thin-film layer, that in a photoelectric conversion mode an electric field is applied to the photoelectric conversion elements in such a direction as to keep carriers generated by light incident to the photoelectric conversion layer, staying in the photoelectric conversion layer and as to guide electron carriers to the second metal thin-film layer, and that the photoelectric conversion mode is arranged to detect as a light signal the hole carriers accumulated in the photoelectric conversion layer or the electron carriers guided to the second metal thin-film layer.
Also, the apparatus may be configured in such an arrangement that the photoelectric conversion elements are divided into a plurality of groups, the photoelectric conversion elements in each group can be set in the refresh mode independently of the other groups, and the photoelectric conversion elements in each group can be set in the photoelectric conversion mode independently of the other groups.
In addition, the apparatus may have a wavelength converting member such as a fluorescent member.
It is preferable to provide a grid between the light source and the photoelectric conversion apparatus.
According to the present invention, row scanning can be performed almost within only the reading time in reading scanning of each row, as compared with the operation time in the case of one set including the sequence of from transfer through reading to reset, thus enabling great increase in the reading speed of the photoelectric conversion apparatus.
Also, in said reading circuit section, the first-stage analog operational amplifier connected to each of the matrix signal wires has a noise voltage density Vn (V/√{square root over (Hz)}) converted at an input terminal portion thereof and a frequency band B (Hz) enough to amplify a signal from said photoelectric conversion circuit section and satisfies the relation of: Vn×√{square root over (B)}≦Tn against thermal noise effective voltage Tn (Vrms) of said switching element at the input terminal portion of said analog operational amplifier, occurring when the switching element in said photoelectric conversion circuit section is turned on, which can reduce the drop of S/N due to the KTC noise upon transfer.
Further, in said reading circuit section, a capacitor element for letting only alternating-current components pass is connected to midway of an output wire from an output terminal of the analog operational amplifier connected in cascade connection with each of the matrix signal wires and a reset switch for DC restoration of the capacitor element is provided, which can reduce the drop of S/N due to the KTC noise upon reset. Further, the reduction in the drop of S/N due to those KTC noise will result in the operational effect of achieving high-quality image information with less random noise.
Also, in said reading circuit section, the analog operational amplifier connected with each of the matrix signal wires is provided with a function to reduce a consumption electric current thereof by a signal from the outside, which can reduce the dark current upon OFF of the transfer switching elements due to heat generation of IC, which can reduce the fixed pattern noise, and which can achieve images without density unevenness and without stripes in the image plane.
In addition, according to the present invention, an output of one A/D converter is selected out of the N A/D converters in accordance with an output level of an analog signal from the reading circuit section and is output as a digital value of (N+M−1) bits, which enables high-resolution and high-speed A/D conversion of photoelectric conversion signals, which achieves a high-tone-level photoelectric conversion apparatus, and which can provide a high-performance X-ray image pickup apparatus using it.
Further, the photoelectric conversion elements and switching elements in said photoelectric conversion circuit section are made of the amorphous silicon semiconductor material, which permits a large-area photoelectric conversion apparatus to be provided cheaply. In addition, when in said reading circuit section the at least one analog operational amplifier connected with each of the matrix signal wires is provided with the function capable of controlling the amplification factor by a signal from the outside, it can compensate for the gain dispersion caused by the film thickness dispersion on fabrication of amorphous silicon semiconductor thin film easily and cheaply.
The reference potential of amp 1 can be stabilized so as to obtain accurate photoelectric conversion signals and also enhance S/N by configuring the reading circuit section in such an arrangement that near the first analog operational amplifier (amp 1 ) connected to each of the matrix signal wires there is provided another analog operational amplifier (amp 2 ), the amp 1 is constructed as a non-inverting amplifier having an amplification factor of not less than 1×, the amp 2 is constructed as a buffer amplifier having an amplification factor of 1×, and a reference potential to be a reference of operation of the amp 1 is supplied from an output terminal of the amp 2 .
The low-pass filter can be configured upon dc restoration so as to decrease the random noise of the analog operational amplifiers and also enhance S/N by configuring the reading circuit section in such an arrangement that a capacitor element for passing only ac components is connected to midway of an output wire from an output terminal of the analog operational amplifier connected to each of the matrix signal wires, a reset switch for dc restoration of the capacitor element is provided, and a resistance element is interposed between the capacitor element and the reset switch.
S/N can be enhanced in a still image mode and the frame rate can be increased in a moving-picture mode so as to improve operability furthermore by configuring the reading circuit section in such an arrangement that a capacitor element for passing only ac components is connected to midway of an output wire from an output terminal of the analog operational amplifier connected to each of the matrix signal wires, a reset switch for dc restoration of the capacitor element is provided, a resistance element is interposed between the capacitor element and the reset switch, and there is provided a function for varying an on/off time of the reset switch by a signal from the outside.
The random noise of the analog operational amplifiers can be decreased so as to enhance S/N by configuring the reading circuit section in such an arrangement that a capacitor element for passing only ac components is connected to midway of an output wire from an output terminal of the analog operational amplifier connected to each of the matrix signal wires, a reset switch for dc restoration of the capacitor element is provided, and a low-pass filter circuit is connected to a terminal out of those of the capacitor element, opposite to a terminal connected to the output of the analog operational amplifier.
The apparatus becomes advantageous in reading weak photoelectric conversion signals necessitating noise reduction by configuring the reading circuit section in such an arrangement that the at least one analog operational amplifier connected with each of the matrix signal wires has a function to vary a slew rate thereof by a signal from the outside.
The apparatus becomes easier to get ready for the moving-picture mode by such an arrangement that each of the photoelectric conversion elements is comprised of, from the insulating substrate side, a first metal thin-film layer (first electroconductive layer) as a lower electrode, an amorphous silicon nitride insulating layer (a-SiNx) for preventing passage of electron carriers and hole carriers, a hydrogenated amorphous silicon photoelectric conversion layer (a-Si:H) as a semiconductor layer, an n-type injection preventing layer for preventing injection of hole carriers, and a transparent electroconductive layer or a second metal thin-film layer located in a part on the injection preventing layer, as an upper electrode (second electroconductive layer), that each of the switching elements (thin-film transistors) is comprised of, from the insulating substrate side, a first metal thin-film layer as a lower gate electrode, a gate insulating layer (a-SiNx) of amorphous silicon nitride, a hydrogenated amorphous silicon semiconductor layer (a-Si:H), an n-type ohmic contact layer, and a transparent electroconductive layer or a second metal thin-film layer as a source or drain electrode, that the photoelectric conversion elements and the switching elements are formed on the same insulating substrate, that in a refresh mode an electric field is applied to the photoelectric conversion elements in such a direction as to guide hole carriers from the photoelectric conversion layer to the second metal thin-film layer, that in a photoelectric conversion mode an electric field is applied to the photoelectric conversion elements in such a direction as to keep carriers generated by light incident to the photoelectric conversion layer, staying in the photoelectric conversion layer and as to guide electron carriers to the second metal thin-film layer, and that the photoelectric conversion mode is arranged to detect as a light signal the hole carriers accumulated in the photoelectric conversion layer or the electron carriers guided to the second metal thin-film layer.
The frame rate can be increased substantially in the moving-picture mode so as to obtain a lot of sequential images by such an arrangement that the photoelectric conversion elements are divided into a plurality of groups, the photoelectric conversion elements in each group can be set in the refresh mode independently of the other groups, and the photoelectric conversion elements in each group can be set in the photoelectric conversion mode independently of the other groups.
The contents of the present invention will be described in detail with embodiments thereof with reference to the drawings.
Embodiment 1
FIG. 3 is a circuit diagram of a photoelectric conversion apparatus to show the first embodiment of the present invention. For simplifying the description, the figure illustrates the structure of 3×3, nine pixels in total. Further, the same members as those in FIG. 1 will be denoted by the same symbols. S 1 - 1 to S 3 - 3 are photoelectric conversion elements for receiving the visible light and converting it to electric signals, and T 1 - 1 to T 3 - 3 are switch elements for transferring signal charges obtained by photoelectric conversion in the photoelectric conversion elements S 1 - 1 to S 3 - 3 to the matrix signal wires M 1 to M 3 . G 1 to G 3 represent wires for driving the gates of switches, connected to the shift register (SR 1 ) and connected to the switch elements T 1 - 1 to T 3 - 3 . The capacitance comprised of three interelectrode capacitances (Cgs) of switch elements is applied to the matrix signal wire M 1 upon transfer, as described above, and it is not illustrated as a capacitor element in FIG. 3. The same is also applied to the other matrix signal wires M 2 , M 3 . There are photoelectric conversion elements S 1 - 1 to S 3 - 3 , switching elements T 1 - 1 to T 3 - 3 , gate drive wires G 1 to G 3 , and matrix signal wires M 1 to M 3 illustrated in the photoelectric conversion circuit section 101 in the drawing, and they are placed on one insulating substrate, though not shown. Numeral 102 denotes a driving circuit section comprised of a shift register (SR 1 ) for switching the switch elements T 1 - 1 to T 3 - 3 . A 1 to A 3 are OP amps for amplifying signal charges of the matrix signal wires M 1 to M 3 and performing impedance transformation thereof, each being described only as a buffer amplifier constituting a voltage follower circuit in the drawing. Sn 1 to Sn 3 are transfer switches, each reading an output from the OP amp A 1 to A 3 , i.e., an output on each matrix signal wire M 1 to M 3 and transferring it to a capacitor CL 1 to CL 3 . The reading capacitors CL 1 to CL 3 are read out by reading switchs Sr 1 to Sr 3 through buffer amplifiers B 1 to B 3 constituting a voltage follower circuit. Numeral 103 designates a shift register (SR 2 ) for switching the reading switches Sr 1 to Sr 3 . The parallel signals of CL 1 to CL 3 are converted to serial signals by Sr 1 to Sr 3 and shift register (SR 2 ) 103 and they are input into an OP amp 104 constituting a final-stage voltage follower circuit and further are digitized by an A/D conversion circuit section 105 . RES 1 to RES 3 are reset switches for resetting the signal components accumulated in the capacitances (three Cgs's) applied to the matrix signal wires M 1 to M 3 , which are reset to the reset potential (or reset to the GND potential in the drawing) by a pulse from CRES terminal. Further, 106 designates a power supply for applying a bias to the photoelectric conversion elements S 1 - 1 to S 3 - 3 . The reading circuit section 107 is composed of the buffer amplifiers A 1 to A 3 , transfer switches Sn 1 to Sn 3 , reading capacitors CL 1 to CL 3 , buffer amplifiers B 1 to B 3 , reading switches Sr 1 to Sr 3 , shift register SR 2 , final-stage OP amp 104 , and reset switches RES 1 to RES 3 .
FIG. 4 is a timing chart to illustrate the operation of the photoelectric conversion apparatus shown in FIG. 3. Using FIG. 4, the details of the operation will be explained. The signal charges obtained by photoelectric conversion in the photoelectric conversion elements S 1 - 1 to S 3 - 3 are accumulated in the capacitance components formed in the photoelectric conversion elements only during a selected period. The signal charges having been accumulated in the photoelectric conversion elements S 1 - 1 to S 1 - 3 in the first row are transferred to the capacitance components (the capacitances of three Cgs's of the switching elements T 1 - 1 to T 3 - 3 ) formed in the respective matrix signal wires M 1 to M 3 while the gate pulse signal G 1 of the shift register (SR 1 ) 102 keeps the switching elements T 1 - 1 to T 1 - 3 “ON” only during a period of time t 1 . In FIG. 4 M 1 to M 3 indicate states of the transfer and show a case of different signal quantities stored in the respective photoelectric conversion elements. Namely, in the first-row photoelectric conversion elements (from S 1 - 1 to S 1 - 3 ), the output levels thereof indicate S 1 - 2 >S 1 - 1 >S 1 - 3 . The signal outputs on the matrix signal wires M 1 to M 3 are subjected to impedance transformation by the respective OP amps A 1 to A 3 .
After that, the switching elements Sn 1 to Sn 3 in the reading circuit section are turned “ON” only during a period of time t 2 by the SMPL pulse shown in FIG. 4 to transfer the signals to the reading capacitors CL 1 to CL 3 . The signals in the reading capacitors CL 1 to CL 3 are subjected to impedance transformation by the respective buffer amplifiers B 1 to B 3 . After that, the reading switches Sr 1 to Sr 3 are successively turned “ON” by shift pulses Sp 1 to Sp 3 from the shift register (SR 2 ) 103 , whereby the parallel signal charges having been transferred to the reading capacitors CL 1 to CL 3 are converted to serial signals to be read out. Supposing pulse widths of the shift pulses of Sp 1 , Sp 2 , Sp 3 are determined to be Sp 1 =Sp 2 =Sp 3 =t 3 , the time necessary for this serial conversion read-out is given by t 3 ×3. The serially converted signals are output from the final-stage OP amp 104 to be further digitized by the A/D conversion circuit section 105 .
Vout shown in FIG. 4 indicates an analog signal before input to the A/D conversion circuit section. As shown in FIG. 4, the parallel signals of S 1 - 1 to S 1 - 3 in the first row, that is, the parallel signals of signal potentials on the matrix signal wires M 1 to M 3 are serially converted on the Vout signal in proportion to magnitudes of those signals. Finally, the signal potentials of the matrix signal wires M 1 to M 3 are reset to the predetermined reset potential (the GND potential) through the reset switch elements RES 1 to RES 3 by turning the CRES pulse “ON” only during a period of time t 4 , thereby getting ready for next transfer of signal charges in the second row of the photoelectric conversion elements S 2 - 1 to S 2 - 3 . After that, photoelectrically converted signals of the second row and the third row are repetitively read out in the same manner.
Here, as seen from FIG. 4, according to the present invention, the two operations, the reset operation of capacitances of the matrix signal wires M 1 to M 3 in the first row and the transfer operation by the gate pulse G 2 for the second-row photoelectric conversion elements S 2 - 1 to S 2 - 3 , can be performed within the time range of t 3 ×3 necessary for the reading operation of signal charges of CL 1 to CL 3 in the first row. Namely, the time necessary for reading of one row is t 4 +t 1 +t 2 , and this time can be set to be nearly equal to (t 3 ×3)+t 2 . The capacitance formed in one of the matrix signal wires M 1 to M 3 is, in the case of FIG. 3, at most three times the interelectrode capacitance Cgs of the switching element connected to the photoelectric conversion element S 2 - 1 to S 2 - 3 . However, as discussed above, each row includes several hundred to several thousand bits in the case of construction of actual photoelectric conversion elements, and therefore, the capacitance value becomes very large as compared with the reading capacitor CL. In that case, the time t 2 necessary for transfer by the SMPL pulse is sufficiently determined to be about the time of several times the time constant determined by the product of the capacitance value of reading capacitor CL and the ON resistance value of the switch element Snx (x:1 to 3). If the reading circuit section 107 is constructed of an integrated circuit (IC) formed on a substrate material of ordinary crystal silicon, the operation can be carried out during the period of time t 2 determined as a time sufficiently shorter than each time of t 1 , t 3 , or t 3 ×3. Namely, the time necessary for reading the signal charges of the first-row photoelectric conversion elements can be set to approximately t 4 +t 1 =t 3 ×3. This means that reading of one row in the aforementioned example required the time of (the time t 1 necessary for transfer from the photoelectric conversion elements to the matrix signal wires)+(the time t 3 ×3 necessary for reading the signals of matrix signal wires out)+(the time t 4 necessary for resetting the capacitance components of matrix signal wires), whereas the present invention permits one row to be read out for the time of (the time t 3 ×3 necessary for reading the signals of matrix signal wires), thus greatly decreasing the reading time of the photoelectric conversion apparatus.
FIG. 5A is a schematic top plan view of the photoelectric conversion circuit section where the photoelectric conversion elements and switching elements are made using the amorphous silicon semiconductor thin film, and FIG. 5B is a schematic cross-sectional structural view along 5 A- 5 B in FIG. 5A. The photoelectric conversion elements 301 and switching elements 302 (amorphous silicon TFTs, which will be referred hereinafter simply as TFTs) are formed on a same substrate 303 , a same first metal thin film layer 304 is used in common to the lower electrodes of the photoelectric conversion elements 301 and the lower electrodes (gate electrodes) of TFTs 302 , and a same second metal thin film layer 305 is used in common to the upper electrodes of photoelectric conversion elements 301 and the upper electrodes (source electrodes and drain electrodes) of TFTs 302 . In addition, the first and second metal thin film layers are also used in common to the gate driving wires 306 and matrix signal wires 307 in the photoelectric conversion circuit section. In FIG. 5A, the pixel number of 2×2, four pixels in total, are drawn. In FIG. 5A the hatching portions represent light receiving surfaces of the photoelectric conversion elements. Numeral 309 designates power-supply lines for giving a bias to the photoelectric conversion elements. Further, 310 denotes contact holes for connecting the photoelectric conversion elements 301 with TFTs 302 .
Now, explained is the method for forming the photoelectric conversion circuit section in the present invention. First, chromium (Cr) is evaporated over the insulating substrate 303 by sputtering or by resistance heating to form the first metal thin film layer 304 approximately 500 Å thick, it is patterned by photolithography, and unnecessary areas are etched. This first metal thin film layer 304 becomes the lower electrodes of photoelectric conversion elements 301 and the gate electrodes of switching elements 302 . Next, by CVD, a-SiNx ( 311 ), a-Si:H ( 312 ), and N + layer ( 313 ) are successively deposited in the thicknesses of 3000, 5000, and 1000 Å, respectively, in a same vacuum. These layers are insulating layer/photoelectric conversion semiconductor layer/hole injection preventing layer of the photoelectric conversion elements 301 and also become gate insulating film/semiconductor layer/ohmic contact layer of the switching elements 302 (TFTs). Further, they are also utilized as insulating layers at cross portions ( 314 in FIG. 5A) between the first metal thin film layer 304 and the second metal thin film layer 305 . Without having to be limited to the above thicknesses, the film thicknesses of the respective layers are optimally designed depending upon the voltage in use as a photoelectric conversion apparatus, charge, quantity of incident light to the light receiving surfaces of photoelectric conversion elements, or the like. At least, a-SiNx is desirably 500 or more Å so as not to permit electrons and holes to pass and so as to well function as a gate insulating film of TFT 302 . After deposition of each layer, the areas to become contact holes (see 310 in FIG. 5A) are subjected to dry etching by RIE or CDE or the like, and thereafter aluminum (Al) is deposited in the thickness of about 10000 Å as a second metal thin film layer 305 by sputtering or by resistance heating. Further, patterning is carried out by photolithography and unnecessary areas are etched. The second metal thin film layer becomes the upper electrodes of photoelectric conversion elements 301 , the source and drain electrodes of switching TFTs 302 , the other wires, and so on. The upper and lower metal thin film layers are connected to each other at the contact hole portions 310 at the same time as film formation of the second metal thin film layer 305 . Further, for forming the channel portions of TFTs 302 , parts between the source electrode and drain electrode are etched by RIE, and thereafter unnecessary a-SiNx layer, a-Si:H layer, and N + layer are etched by RIE, thereby separating the elements from each other. This forms the photoelectric conversion elements 301 , switching TFTs 302 , other wires ( 306 , 307 , 309 ), and contact hole portions 310 . Although the schematic cross-sectional view of FIG. 5B illustrates only two pixels, it is needless to mention that a number of pixels are formed on the insulating substrate 303 at the same time. Finally, in order to improve resistance to humidity, the elements and wires are coated with a passivation film (protection film) 315 of SiNx. As described above, the photoelectric conversion elements, switching TFTs, and wires are formed by the common first metal thin film layer, a-SiNx, a-Si:H, N + layer, and second metal thin film layer each deposited at the same time and only etching of each layer.
Using the process with the main material of amorphous silicon semiconductor as described above, the photoelectric conversion elements, switching elements, gate driving wires, and matrix signal wires can be fabricated at the same time on the same substrate, thereby providing the large-area photoelectric conversion circuit section easily and cheaply.
In general, the amorphous silicon TFTs have lower mobility of electron as a material thereof than the switch elements of crystal silicon, and thus have extremely large ON resistance. For example, the ON resistance of TFT in the channel size (W/L): 50 μm/10 μm fabricated by the above process will be very large as 8 MΩ with application of the bias (Vgs) of 12 V. If the photoelectric conversion circuit section as shown in FIG. 5A and FIG. 5B is constructed at the pixel pitch 100 μm using this TFT, the capacitance components formed in the photoelectric conversion elements will be 2 to 3 (pF) and the time necessary for transfer from the photoelectric conversion elements to the matrix signal wires will be approximately 20 (μsec) as a time constant τ. For sufficient transfer, the time of several times the time constant is necessary. Supposing the time of 4τ is set, the pulse width of the driving gate pulse of TFT will be 80 (μsec).
If Cgs of one above TFT is about 0.05 (pF) and if the number of pixels in one row is 4000, the capacitance component formed in a single matrix signal wire is
4000× Cgs= 200 ( pF ).
The ON resistance of the reset switch elements (RES 1 to RES 3 ) in the reading circuit section shown in FIG. 3 can be readily made in the range of about several hundred Ω and several kΩ if the reading circuit section is of IC (crystal silicon); and the time constant τ R necessary for reset thereof is below 1 (μsec) as long as the resistance components of wires can be ignored. However, the passing line of the reset current in the reset operation flows via Cgs of TFT through the gate drive wire (G 1 , G 2 , or G 3 in FIG. 1, for example). If the material for the gate drive wires is chromium and if the photoelectric conversion circuit section is constructed in the structure as shown in FIG. 5A and FIG. 5B, the resistance value of the wires is expected to be high. If the wire width is made wider in order to decrease the resistance value, the area occupied by the light receiving surface of the photoelectric conversion element against the pixel region of 100 (μm)×100 (μm) will decrease, which will result in failing to ensure sufficient signal quantities; if the film thickness of wire is made thicker, the coverage property of the protection film 315 will be lowered, which will degrade the reliability. Accordingly, the appropriate size on design is approximately the wire width 10 (μm) and the film thickness of wire 1000 (Å) or so.
When chromium is used for the gate drive wires, the sheet resistance thereof is approximately 2 Ω/□, and the wire length is 4000 (pixels)×100 (μm) in the above example, which is approximately 40 or more (cm), so that the resistance of wire can be even 80 (kΩ). In that case τ R =1 (μsec) is not sufficient for the time necessary for resetting the capacitance of about 200 (pF) formed in the matrix signal wire. In actual reset operation, the circuit is a two-dimensional, distributed constant circuit and, though cannot be expressed simply by the CR time constant, the time of several times 200 (pF)×80 (kΩ)=16 (μsec) is necessitated for sufficient reset, thus necessitating the time nearly equal to the width 80 (μsec) of driving gate pulse.
If the reading circuit section (IC) to which the matrix signal wires for 4000 pixels are connected is composed of a single IC, the size of the IC will be very large and the yield of the IC itself will be lowered. Also, in the case of the single IC, it takes a very long time for serial reading of data for one row=4000 pixels. Therefore, the reading circuit section is divided into an appropriate number of segments: N segments, and the N segments are operated at the same time. For example, N is so set as to achieve serial conversion in the time (t 1 +t 4 ), which is the sum of the transfer time (t 1 ) from the photoelectric conversion elements to the matrix signal wires and the reset time (t 4 ) of the matrix signal wires. In the case of the above example, the transfer time t 1 :80 (μsec)+the reset time t 4 :80 (μsec)=160 (μsec), and when the conversion rate for serial conversion (the pulse width:t 3 of Sp of shift register 2 ) is 1.6 (μsec), N=20 reading circuit sections capable of accepting inputs of 100 pixels need to be prepared.
Speaking with this example, the time necessary for reading of one row was t 1 +t 4 +(t 3 ×100)=320 (μsec), whereas in the present invention the time necessary for reading of one row is t 3 ×100=160 (μsec), which means that the speed is substantially doubled.
If such high-speed operation is not required in use of the photoelectric conversion apparatus, the same reading speed as before can be used with setting of longer transfer time t 1 and reset time t 4 , which enables more sufficient transfer and reset.
It is also easy to further shorten t 3 in the reading circuit section than t 3 =1.6 (μsec) in the above example, with use of ordinary ICs of crystal silicon. In this case, since the time necessary for reading of one row is determined by ts+t 4 , there is no change in the reading speed, but the number (N) of ICs of the reading circuit sections can be decreased, whereby cheaper photoelectric conversion apparatus can be provided.
As having been described above, as compared with the operation time of transfer plus reading plus reset necessary and indispensable for reading scanning of each row in the conventional technology, the present invention enables reading scanning of each row to be performed substantially in the time of only reading, thereby greatly increasing the speed of reading of the photoelectric conversion apparatus.
Embodiment 2
FIG. 6 is a circuit diagram of a photoelectric conversion apparatus to show the second embodiment of the present invention, which is an example where the photoelectric conversion circuit section is constructed of 3×3=9 pixels. The same constituent members as those in FIG. 3 showing Embodiment 1 are denoted by the same reference symbols and description thereof is omitted herein. FIG. 6 is different from FIG. 3 in that the buffer amplifiers L 1 to L 3 connected to the respective matrix signal wires in the reading circuit section are replaced by non-inverting amplifiers with an amplification factor G determined by resistors R 1 , R 2 . Further, though not shown in FIG. 6, the OP amps of the buffer amplifiers L 1 to L 3 are excellent in very low noise performance as compared with the other amplifiers. The amplification factor is 1+(R 2 /R 1 ).
In general, the OP amps generate random voltage-nature noise, it is dominated by noise occurring in transistors incorporated, especially in first-stage transistors. For example, if the first-stage section is composed of a bipolar transistor, it is said that the thermal noise occurring in the base resistance determines the noise quantity of OP amp. The noise quantity is normally expressed against unit bandwidth, and the unit thereof is (Volt/√{square root over (Hz)}). When the OP amps are used in the form of non-inverting amplifiers as shown in FIG. 6, the noise quantity is also multiplied by 1+(R 2 /R 1 ) in accordance with the frequency band to operate. In the following description, the noise occurring in the OP amps will be considered to be a noise value before multiplied by the amplification factor, i.e., equivalent input noise voltage, which will be represented by Vn (V/√{square root over (Hz)}).
In the present invention, Vn of OP amps (L 1 to L 3 ) shown in FIG. 6 is set below a certain selected value. The certain selected value is the noise value due to the so-called KTC noise occurring upon the transfer operation through the switching elements T 1 - 1 to T 3 - 3 in the photoelectric conversion circuit section 101 . Namely, noise quantities occurring in the first-stage OP amp portions (L 1 to L 3 ) in the reading circuit section are set to be not more than the KTC noise quantity occurring in the photoelectric conversion circuit section 101 . Either noise is intrinsic noise potentially occurring on principle, which cannot be made to be “zero” on design.
Next, with an example of the photoelectric conversion apparatus having 4000×4000=16 million pixels as also explained in the first embodiment, each noise will be roughly estimated. When the layers of a-SiNx, a-Si, and N + are stacked in the thicknesses of 3000, 5000, and 1000 Å, respectively, and the pixel pitch is 100 μm, the capacitor (C 1 ) in the photoelectric conversion elements S 1 - 1 to S 3 - 3 is about 3 pF and the reading capacitor (C 2 ) of one of the matrix signal wires M 1 to M 3 is Cgs×4000=200 pF. The KTC noise (Tn) occurring upon performing the transfer operation by the switching elements (TFTs) T 1 - 1 to T 3 - 3 is as follows when obtained as voltage noise on the capacitance C 2 of the matrix signal wire M 1 to M 3 .
Tn= ( K×T× ( C 1∥ C 2)) 1/2 /( C 1+ C 2)
Here, K: the Boltzmann constant (1.38×10 −23 (J/K)), T is an absolute temperature, and C 1 ∥C 2 is a series combined capacitance of C 1 and C 2 .
This noise Tn statistic-probabilistically shows a Gaussian distribution and is expressed by an effective noise voltage value (Vrms). Calculating Tn at room temperature (300 K), Tn=0.55 (μVrms). On the other hand, the noise occurring in the OP amps L 1 to L 3 varies depending upon the handling frequency band B. As explained in the first embodiment, when the transfer time 80 (μs)+reset time 80 (μs), the OP amps receive input of signal of ( 1/160 (μs))=6.25 (kHz). Supposing the OP amps are operated in the frequency band B of four times that value, i.e., 25 (kHz), the photoelectric conversion signals transferred and the KTC noise occurring in the photoelectric conversion circuit section are amplified sufficiently (G times). In addition, the effective noise An (=Vn×√{square root over (B)}) of the OP amp input portions occurring in the operation frequency band is also amplified G times. The noise An occurring in the OP amps and the KTC noise Tn in the photoelectric conversion circuit section 101 are independent from each other, and effective noise Jn at the amp input portion including the both noise is expressed by Jn=(An 2 +Tn 2 ) 1/2 while the total effective noise at the amp output terminal is Jn×G.
Here, if An>>Tn, Jn is determined by An, which is disadvantageous in terms of S/N of the photoelectric conversion apparatus. Accordingly, desirably, An=Tn or An<Tn. When the frequency band B=25 (kHz) in the foregoing example, the equivalent input noise voltage Vn of OP amp is desirably 3.5 or less (nV/√{square root over (Hz)}) from Tn≧(Vn×B 1/2 ) (=An). When Vn=3.5 (nV/√{square root over (Hz)}), the effective noise of amp becomes equal to the KTC noise Tn, and the effective noise Jn of a combination of the two noises at the amp input portions becomes √{square root over (2)} times Tn from Jn=(Vn 2 +Tn 2 ) 1/2 . Namely, Jn=0.55×√{square root over (2)}=0.78 (μVrms) in the above example.
For obtaining images comparable to those by the conventional film method as applying the photoelectric conversion apparatus according to the present invention to the X-ray image pickup apparatus, it is said that the S/N ratios required for the apparatus are very high, normally S/N=10000 or more.
Here is first described an example wherein the photoelectric conversion apparatus with the two-dimensional array of photoelectric conversion elements is applied to the X-ray image pickup apparatus.
FIG. 7 is a schematic cross-sectional view of a medical X-ray detecting apparatus constructed using the two-dimensional photoelectric conversion apparatus. X-rays emitted from an X-ray source 1501 are radiated to a subject 1502 such as a human body (the affected part of patient or an examined part of an object), and X-rays associated with intracorporeal information about lung part, bone, focus, or the like or associated with internal information about a structure or an inner space travel toward a grid plate 1503 . The grid plate 1503 is provided for the purpose to prevent the X-rays scattered in the subject from irradiating the fluorescent member 1504 and photoelectric conversion apparatus 1506 , and is constructed of a substance 1507 for absorbing X-rays, such as lead, and a substance 1508 for transmitting X-rays, such as aluminum. The X-rays passing through the grid irradiate the X-ray-to-visible conversion fluorescent member 1504 , being a wavelength conversion member, to be converted to wavelengths in the range including the sensitivity of photoelectric conversion element, for example, to visible light therein. Fluorescence from the X-ray-to-visible conversion fluorescent member is photoelectrically converted by the photoelectric conversion apparatus 1506 . Here, 1509 denotes the photoelectric conversion elements, 1510 the switching elements, and 1511 a protection film for protecting the photoelectric conversion elements 1509 and switching elements 1510 . Numeral 1512 designates an insulating substrate on which the photoelectric conversion elements 1509 and switching elements 1510 are placed.
Incidentally, when the X-ray-visible conversion fluorescent member is in close contact with the photoelectric conversion apparatus as shown in FIG. 7, the illuminance obtained on the light receiving surfaces of photoelectric conversion elements becomes maximum, and the illuminance at that time can be that of several (Lx) or so, though depending upon the fluorescent member used or a dose of the X-ray source. Photocurrent flowing in the photoelectric conversion elements with light of 1 (Lx) is about 5 (pA) per photoelectric conversion element in the foregoing example of the photoelectric conversion apparatus of 4000×4000; if the photocurrent is accumulated in the capacitor C 1 of 3 (pF) in the photoelectric conversion element during the period of 500 (msec), the signal output S in the capacitor C 2 of 200 (pF) of matrix signal wire after transfer through the switching TFT becomes 5 pF×500 msec/(3 pA+200 pA)=12.3 (mV). The noise value Jn in the capacitance C 2 of 200 (pF) of matrix signal wire is Jn=0.78 (μVrms), and regarding the effective noise Jn as N, the S/N ratio is 12.3 (mV)/0.78 (μV)=15800. Namely, the apparatus can fully function as a photoelectric conversion section of the X-ray image pickup apparatus.
The noise in the OP amp portion includes not only Vn, but also the thermal noise occurring in the resistance of R 1 , R 2 , for example. It can be easily reduced far smaller than the noise due to Vn by decreasing their resistance values. Also, there exists a current-nature noise component (In) in the input portion in the OP amps. This can be decreased to be far smaller than the noise due to Vn by using field-effect transistors for the first-stage transistors of the OP amps. Namely, since the equivalent input noise voltage Vn owned by the OP amps greatly affects S/N of the photoelectric conversion apparatus, Vn of OP amps is specified in the present invention.
Embodiment 3
FIG. 8 is a circuit diagram of a photoelectric conversion apparatus to show the third embodiment of the present invention, which is an example in which the photoelectric conversion circuit section is constructed of 3×3=9 pixels. The same constituent members as those in FIG. 6 shown in the second embodiment are denoted by the same reference symbols and description thereof is omitted. FIG. 8 is different from FIG. 6 in that in the reading circuit section capacitor elements CC 1 to CC 3 for letting only AC components pass are connected to midway of output wires from the output terminals of OP amps L 1 to L 3 and in that reset switches D 1 to D 3 for DC restoration of the capacitor elements are provided. Further, a buffer amplifier A 1 to A 3 for impedance transformation is connected to each capacitor element CC 1 to CC 3 .
Also, FIG. 9 is a timing chart to show the operation in FIG. 8, which especially illustrates the operation related to the capacitor elements CC 1 to CC 3 and reset switches D 1 to D 3 , and the other operation is the same as in FIG. 4. The operation of the present embodiment will be explained using FIG. 8 and FIG. 9.
CRES is a control signal of the switches RES 1 to RES 3 for resetting the capacitor CL (three Cgs of TFTs T 1 - 1 to T 3 - 3 which are not shown in FIG. 8) formed in the matrix signal wire M 1 to M 3 to the reset potential (GND). P 1 shows states of change of potential at a node (for example, represented by P 1 on FIG. 8) of matrix signal wire. Essentially, the node P 1 should be reset to GND being the reset potential by the CRES signal “Hi.” However, when the capacitor C 2 of matrix signal wire is reset, the thermal noise probabilistically occurs as KTC noise because of the ON resistance of switch RES 2 . The noise quantity thereof. Rn=(KT/C 2 ) 1/2 (Vrms). In the foregoing example of C 2 =200 pF, the noise reaches even Rn=4.55 (μVrms), which will be the main factor of noise in the photoelectric conversion apparatus as exceeding foregoing Jn=0.78 (μVrms).
If reading is carried out in the state wherein this noise quantity Rn is superimposed on the capacitor C 2 of matrix signal wire, S/N of photoelectric conversion apparatus will be naturally lowered. In the waveform P 1 of FIG. 9, deviation amounts (which are denoted by “error” in FIG. 9) from the reset potential GND after “OFF” of CRES are due to the KTC noise occurring upon this reset. This noise is also multiplied by the amplification factor G=1+(R 2 /R 1 ) by the OP amp L 1 to L 3 . Although not shown in FIG. 8, the output of G times the waveform P 1 always appears in the output from the OP amp L 1 to L 3 . P 2 in FIG. 9 is a waveform of the opposed electrode of the capacitor element connected in series to the output of amp L 2 . Namely, it represents the waveform at node P 2 shown in FIG. 8.
Here, the reset switch D 2 is connected to the node P 2 and is controlled by control signal DRES. DRES becomes “ON” nearly at the same time as CRES and DRES becomes “OFF” a little after “OFF” of CRES. During the period of “ON” of DRES the reset potential GND is given at the node P 2 . Even after DRES becomes “OFF” to change the switch element D 2 into a high-impedance state, the node P 2 is held at the GND potential. In that state, for example, when the gate (G 2 ) of transfer TFT is turned “ON,” the signal charge accumulated in the capacitance of photoelectric conversion element S 22 is transferred to the capacitor C 2 of matrix signal wire. Its state is shown in the waveform P 1 of FIG. 9, and the KTC noise Rn upon reset, preliminarily held after end of CRES, is also superimposed upon the transfer operation. However, the waveform at the node P 2 in this transfer operation process appears so that only the change of voltage of C 2 due to the signal of photoelectric conversion element is multiplied by G, because the DC component of Rn multiplied by G in the OP amp L 1 to L 3 is shut off by the capacitor element CC 2 . Namely, it results in canceling the KTC noise upon reset. After that, the output of P 2 is transferred to the capacitor element CL 2 by the SMPL pulse, and then it is subjected to serial conversion by SR 2 to be output from the OP amp 104 . The operation of this part is the same as that explained in Embodiment 1.
As explained above, the present invention involves such an arrangement that in the reading circuit section 107 the capacitor elements CC 1 to CC 3 for letting only the AC components pass are connected to midway of the output wires from the output terminals of OP amps L 1 to L 3 and that the reset switches D 1 to D 3 for DC restoration of the capacitor elements are provided, whereby the KTC noise occurring upon reset of capacitance formed in each matrix signal wire can be removed, thus permitting enhancement of S/N of photoelectric conversion apparatus and permitting high-quality images to be obtained.
Embodiment 4
FIG. 10 is a circuit diagram of a photoelectric conversion apparatus to show the fourth embodiment of the present invention, which is an example in which the photoelectric conversion circuit section is constructed of 3×3=9 pixels. The same constituent members as those in FIG. 8 shown in the third embodiment are denoted by the same reference symbols, and description thereof is omitted. FIG. 10 is different from FIG. 8 in that in the reading circuit section 107 OP amps K 1 to K 3 having a function capable of variably controlling the amplification factor thereof by a signal from the outside are added. In FIG. 10 there are four signal lines A 1 to A 4 for controlling the amplification factor from the outside, thereby permitting selection of four amplification factors. FIG. 11 shows schematic circuitry inside of the amplification-factor-variable OP amp K 1 to K 3 in FIG. 10. The function will be explained briefly.
Terminals A 1 , A 2 , A 3 , A 4 are those for inputting a signal for selecting an amplification factor from the outside, and only one of the four terminals is assumed to be “Hi.” When the signal of “Hi” is input to either one of the terminals A 1 , A 2 , A 3 , A 4 , the switch element S 1 , S 2 , S 3 , S 4 connected to either terminal A 1 , A 2 , A 3 , A 4 is turned on. When either one switch is turned on, the OP amp K 1 to K 3 operates as a non-inverting amplifier. For example, if resistance values of resistors R 3 to R 7 are taken as sufficiently larger than the ON resistance of each switch element and if all are set to a same value R (Ω), the amplification factor with S 1 on is 1+¼=1.25×, the amplification factor with S 2 on is 1+⅔=1.66×, the amplification factor with S 3 on is 1+ 3/2=2.5×, and the amplification factor with S 4 on is 1+ 4/1=5×. By properly selecting the resistance values of the resistors R 3 to R 7 , other four desired amplification factors can be obtained.
The present embodiment showed an example of switching the four amplification factors by the four control signals, but without having to be limited to four, a desired number of control signals may be arranged to switch associated amplification factors. If a multiplexer circuit is connected to the control terminals, N external control signals permits switch of 2 N ways.
Overcoming the problem that individual differences of photoelectric conversion outputs occur due to dispersion on fabrication of a-Si semiconductor thin film as pointed out previously, the photoelectric conversion apparatus of the present invention can compensate for the output dispersion easily because of the function capable of controlling the amplification factor by a signal from the outside in the reading circuit section, and therefore, it has a merit of decrease in the cost of apparatus as a result.
Embodiment 5
FIG. 12 is an example of a circuit diagram of one of OP amps incorporated in the reading circuit section of a photoelectric conversion apparatus according to the fifth embodiment of the present invention. In this figure the feature of the present invention resides in provision of a switch element SWp controlled by a signal from a terminal PS. Explanation of the operation concerning the function of this switch element SWp will be given.
Terminals Vdd, Vss are power terminals of the OP amp, and the power of Vdd>Vss is input. Normally, assuming that the GND of the system of photoelectric conversion apparatus is the zero potential, positive voltage is applied to Vdd while negative voltage to Vss, respectively. When a control signal from PS terminal is not input to the switch element SWp, that is, when SWp is “OFF,” current flows through resistor R 9 , diode D 1 , and diode D 2 to bias the base potential of transistor Q 7 to the potential given by forward threshold voltage of D 1 , D 2 . Then the transistor Q 7 turns into the “ON” state, the collector current I of transistors Q 6 , Q 7 flows from Vdd terminal to resistor R 8 . Since Q 6 and Q 5 , and, Q 6 and Q 8 are in the relation of current mirror structure, when the transistors of Q 5 , Q 6 , Q 8 have the same performance, current equal to the collector current I of Q 6 flows to the collectors of Q 5 , Q 8 . Q 5 becomes a constant current supply for implementing the function as an OP amp. Bipolar transistors Q 1 , Q 2 are input-stage transistors, current according to input difference voltage between input terminals VIN(+), VIN(−) flows into (or flows out of) the base of transistor Q 9 , and it is amplified in the output stage comprised of transistors Q 8 , Q 9 , Q 10 to be output from the terminal Vout. Transistors Q 3 , Q 4 compose current mirror structure to function as an active load on the input-stage transistors Q 1 , Q 2 . In practical use, it is used as a negative feedback circuit for effecting negative feedback from the output terminal Vout to the VIN(−) terminal of input terminal, a non-inverting amplifier circuit, or an impedance converting circuit, a voltage follower circuit, or the like. Also, it is often used as an inverting amplifier circuit.
Now, normally, when the OP amps are constructed using bipolar transistors as shown in FIG. 12, the power-supply current often exceeds 100 μA in common sense, though depending upon resistance values used. When several OP amps are connected to one matrix signal wire, as shown in FIG. 3, FIG. 6, FIG. 8, and FIG. 10, supposing the consumption current of 1 mA is necessary for reading one pixel and when the photoelectric conversion apparatus of 4000×4000 pixels is read, the power-supply current of 1 mA×4000 (columns)=4 (A) flows. Supposing the power-supply voltage of Vdd, Vss is +5 (V), −5 (V), respectively, the consumption power of 40 (W) is necessary in the reading circuit section. This power is always consumed as long as the power is input to each OP amp, even in the state where SR 1 , SR 2 , or the other switches, etc. do not operate in FIG. 3, FIG. 6, FIG. 8, or FIG. 10, that is, even in the non-reading state. This is converted to heat in the reading circuit section (IC), and the heat is radiated to the surroundings.
The switch element SWp shown in FIG. 12 is purposed to decrease the above consumption power during the periods except for reading. The operation will be described below. During the periods except for reading, a control signal from the terminal PS turns the switch element SWp “ON,” thereby keeping no current flowing in the diodes of D 1 , D 2 . By doing so, the transistors Q 6 , Q 7 become “OFF,” so that no current flows. At the same time the collector current of transistors Q 5 , Q 8 is also shut off. Namely, the control signal from the terminal PS causes the constant current supply in the OP amp to be shut off, which enables the consumption current to be reduced greatly. The switching element SWp may be, for example, an MOS transistor where it is switched by the voltage signal of 0 (V)/5 (V).
By providing the OP amps in the reading circuit section with such a switch for reducing the consumption current in the above manner as shown in FIG. 12, the temperature of the photoelectric conversion circuit section disposed around it can be prevented from increasing because of heat generation of the reading circuit section (IC), increase in the dark current “upon OFF” of TFTs of the switching elements can be decreased, and the fixed pattern noise of the photoelectric conversion apparatus can be decreased. Also, the decrease in the consumption power of the reading circuit section (IC) during the periods except for reading is of course economically advantageous.
Embodiment 6
FIG. 13 is a schematic circuit diagram of the A/D conversion circuit section of the photoelectric conversion apparatus, for explaining the sixth embodiment of the present invention. The A/D conversion circuit section of the present embodiment is composed mainly of three OP amps, three A/D converters, two selector circuits, and a bit converting circuit. The operation thereof will be explained.
The analog signal Va as serially converted in the reading circuit section is input into the three OP amps in the A/D conversion circuit section. The three OP amps will be referred to as amp 1 , amp 2 , and amp 3 , and amplification factors G 1 , G 2 , G 3 thereof are set in the ratio of 1:2:4. Each amplification factor is determined by a resistance value connected to the OP amp. In the present embodiment, for explanation's sake, the amplification factors G 1 , G 2 , G 3 of amp 1 , amp 2 , and amp 3 are set to be ×1, ×2, and ×4, respectively. Also, the signal Va from the reading circuit section is assumed to be output in the range of 0 (V) to 1 (V). Namely, a signal over 1 (V) or a signal of minus voltage will never be input to the A/D conversion circuit section. The signal Va from the reading circuit section is amplified by amp 1 , amp 2 , and amp 3 , and an output from each amp is input to the A/D converter AD 1 , AD 2 , AD 3 . Two reference voltages are supplied to terminal REF+ and to terminal REF− in the A/D converter AD 1 , AD 2 , AD 3 , and the analog input signal is digitized with respect to difference voltage between the reference terminals. The present embodiment employs 12-bit A/D converters. Namely, a signal is digitized in 2 12 =4096 steps. The two reference voltages of the A/D converters are set to 0 (V) and 4 (V).
Since AD 3 is connected to the OP amp having the fourfold gain, A/D conversion is effected when Va is between 0 (V) inclusive and 0.25 (V) inclusive. When the signal Va is over 0.25 (V), overflow terminal OF outputs the logic signal of “Hi.” Since AD 2 is connected to the OP amp having the twofold gain, A/D conversion is effected when Va is between 0 (V) inclusive and 0.5 (V) inclusive. When Va is over 0.5 (V), the overflow terminal OF outputs the logic signal of “Hi.” Since AD 1 is connected to the OP amp having the onefold gain, A/D conversion is effected when Va is between 0 (V) inclusive and 1 (V) inclusive. When the signal Va is over 1 (V), the OF terminal of overflow terminal outputs the logic signal of “Hi.”
Also, selector 1 has such a function that when the digital signals from AD 3 and AD 2 are input thereto and if the OF terminal of AD 3 is “Lo” then it outputs the digital signal from AD 3 as it is but if the OF terminal of AD 3 is “Hi” then it outputs the digital signal from AD 2 as it is. Also, selector 2 has such a function that when the digital signals from selector 1 and AD 1 are input thereto and if the OF terminal of AD 2 is “Lo” then it outputs the digital signal from selector 1 as it is but if the OF terminal of AD 2 is “Hi” then it outputs the digital signal from AD 3 as it is. Namely, from the output terminal of selector 2 , AD 3 is output when Va: 0 (V) to 0.25 (V); AD 2 is output when Va: 0.25 (V) to 0.5 (V); AD 1 is output when Va: 0.5 (V) to 1 (V). The selector 1 and selector 2 are identical on a circuit basis, and FIG. 14 shows an example of schematic circuitry of selector 1 in FIG. 13.
When OF of each A/D converter is “Lo,” that is, when the signal Va is smaller than 0.25 (V), a ratio of the digital outputs from AD 1 , AD 2 , AD 3 becomes the gain ratio of amps G 1 :G 2 :G 3 =1:2:4. Namely, the digital output from AD 2 is one obtained by shifting the digits of bits of the digital output from AD 1 by one bit to the MSB side, and the digital output from AD 3 is one obtained by shifting the digits of bits of the digital output from AD 2 by one bit to the MSB side.
For example, when the output from AD 1 is as follows from the MSB side
-
- {000100101101},
the output from AD 2 is - {001001011010},
and the output from AD 3 is - {010010110100}.
- {000100101101},
FIG. 15 is an example of schematic circuitry of the bit conversion circuit in FIG. 13. In the bit conversion circuit, the 12-bit digital signal of selector 2 input thereto, i.e., the digital signal of the selected A/D converter, is converted to 14 bits. On that occasion the shift operation of bits corresponding to the selected A/D converter is carried out.
For example, if the A/D converter AD 1 is selected and if the output thereof is as follows from the MSB side:
-
- {10100100101101},
the 14-bit output from the bit conversion circuit is as follows - {1010010010110100};
if AD 2 is selected and if the output thereof is as follows from the MSB side: - {100101001001},
the 14-bit output from the bit conversion circuit is as follows - {01001010010010};
if AD 3 is selected and if the output thereof is as follows from the MSB side: - {101010111010},
the 14-bit output from the bit conversion circuit is as follows - {00101010111010}.
The desired bit shift operation is carried out according to the digital signal of selected A/D converter by an input signal of terminal SEL 1 , terminal SEL 2 , or terminal SEL 3 of the bit conversion circuit section. That signal can be made by a simple logic circuit, using the signal from the OF terminal of each A/D converter. In FIG. 12, when terminal SEL 1 is “Hi,” bit conversion is carried out for the digital output from AD 1 ; when terminal SEL 2 is “Hi,” bit conversion is carried out for the digital output from AD 2 ; when terminal SEL 3 is “Hi,” bit conversion is carried out for the digital output from AD 3 .
- {10100100101101},
As a result, the A/D conversion circuit section of the present embodiment is arranged so that AD 3 performs digitization in 2 12 =4096 steps when Va: 0 (V) to 0.25 (V); AD 2 performs digitation in 2 11 =2048 steps when Va: 0.25 (V) to 0.5 (V); AD 1 performs digitization in 2 11 =2048 steps when Va: 0.5 (V) to 1 (V). Namely, it can cut the analog signal from the reading circuit section ranging from Va: 0 (V) to 1 (V) in 4096+2048+2048=8192 steps and can give an output as a 14-bit digital value. This 14-bit digital output is stored, for example, in a memory, and is subjected to digital processing with a computer.
In the present embodiment, signals with Va not more than 0.25 (V) are quantized in ½ 14 for the dynamic range: 1 (V). Namely, signals in low levels of ¼ or less are expressed in high resolution, and it is suitable, especially, for applications such as medical X-ray image pickup apparatus. Since offset components such as the fixed pattern noise (FPN) in the dark state caused in the photoelectric conversion circuit section and FPN caused in the reading circuit are digitized in high resolution, the accuracy of correction is improved in execution of offset correction.
The present embodiment was explained with the example wherein the A/D conversion circuit section included three OP amps and three A/D converters, but it may be provided with a plurality of respective elements (N elements). Also, the amplification factors of the OP amps were explained as ×1, ×2, and ×4, but they do not have to be G 1 :G 2 :G 3 =1:2:4 and may be set at another amplification factor ratio, for example, ×2, ×4, and ×8. In that case, the reference voltage of the A/D converters may be 8 (V) according to the amplification factors. With N OP amps, the ratio of gains of the respective OP amps may be set to 2 0 :2 1 :2 2 : . . . :2 N−1 , and N A/D converters are to be used. Further, the present embodiment employed the 12-bit A/D converters, but any-bit A/D converters may be used.
As seen from the above description, use of N OP amps and N M-bit A/D converters in the A/D conversion circuit section permits us to obtain digital outputs of (M+N−1) bits, and the data can be processed as digital values of (M+N−1) bits in a succeeding data processing apparatus using a computer and a memory circuit.
Also, analog signals of ½ N−1 or less to the dynamic range can be converted to digital signals substantially in the same accuracy as in the case of using the A/D converters of (M+N−1) bits. This means that if the A/D converters of (M+N−1) bits do not exist or if they exist but cannot be used because of their conversion speed, (M+N−1) bit-equivalent digital conversion can be achieved by using N M-bit A/D converters.
Embodiment 7
FIG. 16 is a circuit diagram of a photoelectric conversion apparatus showing the seventh embodiment of the present invention. In FIG. 16 the number of pixels of the photoelectric conversion circuit section 101 is not 3×3, but FIG. 16 illustrates an arrangement assuming a lot of pixels. Although the capacitor elements CL 1 to CL 3 , switches Sn 1 to Sn 3 , amplifiers B 1 to B 3 , and switches Sr 1 to Sr 3 shown in the reading circuit section of FIG. 6 are not illustrated in FIG. 16, there actually exist 128 elements for each of them. It is also noted that the shift register 103 , amplifier 104 , and A/D conversion circuit section in FIG. 6 are not illustrated in FIG. 16, either.
In FIG. 16 the number of inputs to the reading circuit section 107 is 128 as illustrated. If the number of columns in the two-dimensional photoelectric conversion element circuit section 101 is, for example, 2560 , twenty reading circuit sections 107 (ICs) will be used. BND 1 to BND 128 indicate interconnections between the matrix signal wires (M 1 to M 128 ) in the photoelectric conversion circuit section and the reading circuit section, which are connected by the wire bonding method or the anisotropic connection method.
FIG. 16 is different from FIG. 6 in that the potential (GND) to be a reference of the first-stage operational amplifier L 1 to L 128 for amplifying a signal from the matrix signal wire is supplied from buffer amplifier E 1 to E 128 , respectively. As also described in Embodiment 2, the operational amplifiers L 1 to L 128 are purposed to amplify signals from the photoelectric conversion circuit section and are those having characteristics excellent in noise performance. At the same time, upon amplification by the operational amplifier, there also occurs the thermal noise at a resistor in the configuration as a non-inverting amplifier, in addition to the random noise occurring in the operational amplifiers of L 1 to L 128 . Especially, the thermal noise (4KTRB) occurring at input resistor RA 1 to RA 128 interposed between the inverting terminal and GND of operational amplifier will result in being amplified by an amplification factor of non-inverting amplifier by the operational amplifiers of L 1 to L 128 . Therefore, the input resistors of L 1 to L 128 need to be set small in order to keep the thermal noise occurring in the resistors smaller.
On the other hand, when a signal from the photoelectric conversion circuit section is input into the operational amplifier L 1 to L 128 , an electric current according to a voltage of the input flows through the input resistor RA 1 to RA 128 . For example, supposing the output voltage from the matrix signal wire M 1 , i.e., the input voltage of the operational amplifier L 1 is V 1 , the electric current I 1 flowing through the input resistor RA 1 is given by I 1 =V 1 /RA 1 . Namely, as the input resistance becomes smaller, the thermal noise decreases, while the electric current flowing through the input resistor increases. The electric current will flow to GND. If the impedance of GND is large, the electric current flowing through the input resistor will cause a voltage drop. For example, in the case where GND is supplied at a single point from the outside to the reading circuit section 107 , GND wiring is routed from that point to supply GND to the operational amplifiers of L 1 to L 128 . In the case of the reading circuit section wherein the number of inputs is 128 as shown in FIG. 16, electric currents flowing in the 128 input resistors all flow into the GND wire, which would change the reference potentials (GND) of operational amplifiers existing away from the supply point of GND. In addition, amounts of the change will be dependent on input signals of the other signal wires, which could cause failure in obtaining correct photoelectric conversion signals. The voltage drop amount of reference potential can be decreased by increasing the line width of the GND wire thus routed, but it will also increase the chip area, which is not a desirable solution. Also, the impedance can be lowered by supplying GND from the outside to each operational amplifier of from L 1 to L 128 , but it is not practical to provide lead-out pads in the same number as the number of inputs.
In the present embodiment, the operational amplifiers of L 1 to L 128 are provided each with the individual buffer amplifiers E 1 to E 128 to supply the reference potential (GND) for the low-noise amplifiers of L 1 to L 128 from the respective outputs of the buffer amplifiers of E 1 to E 128 . As a result, even if the input resistors RA 1 to RA 128 of the operational amplifiers L 1 to L 128 are set small, so as to increase the electric currents flowing through the input resistors, a good-quality GND potential can be always supplied as the reference of the low-noise operational amplifiers L 1 to L 128 , whereby accurate photoelectric conversion signals can be attained. Of course, the thermal noise occurring at the input resistors is low because of the small input resistances RA 1 to RA 128 , so that S/N can be enhanced. Resistance values of the input resistors do not have to be too small and may be set in consideration of the thermal noise occurring at the resistors and the noise occurring at the buffer amplifiers E 1 to E 128 .
The present embodiment was described with the number of inputs in the reading circuit section being 128 , but the reading circuit section may include much more inputs without raising any problem.
Embodiment 8
FIG. 17 is a circuit diagram of a photoelectric conversion apparatus for explaining the eighth embodiment of the present invention. The same members as those in FIG. 8 are denoted by the same reference symbols and description thereof will be omitted.
There are roughly the following four points in FIG. 17 different from FIG. 8. First, the capacitor elements CC 1 to CC 3 are connected through resistance elements RB 1 to RB 3 to the switch elements D 1 to D 3 . Second, a signal for opening/closing the switch element D 1 to D 3 , i.e., a DRES signal is made by CRES signal and delay circuit DL 1 (or DL 2 ) and, in addition, it can be selected by control signal DSEL from the outside. Third, a low-pass filter comprised of buffer amplifier F 1 to F 3 , resistance element RF 1 to RF 3 , and capacitor element CF 1 to CF 3 is provided between the capacitor element CC 1 to CC 3 and the buffer amplifier A 1 to A 3 . Fourth, the slew rate of buffer amplifier A 1 to A 3 functioning in sampling a signal into the capacitor element CL 1 to CL 3 for sample and hold is arranged as capable of being varied by a control signal SR from the outside.
Although the photoelectric conversion apparatus of the present embodiment is illustrated with nine pixels of 3×3, the apparatus may be constructed with much more pixels without departing from the spirit of the invention. Since no inconvenience will occur with description about only one line of matrix signal wire, the present embodiment will be described with the drawing as to only the line of matrix signal wire of M 1 .
The operational amplifier L 1 of first stage in the reading circuit section 107 , for amplifying the signal from the photoelectric conversion circuit section 101 , is excellent in low-noise performance, as also described in Embodiment 2. The frequency band thereof may be a band in which the photoelectric conversion signal transmitted by the transfer operation at TFT in the photoelectric conversion circuit section can be amplified enough. However, if the operational amplifier L 1 has a frequency band broader than necessary, the photoelectric conversion signal can be amplified, while the high-frequency components of random noise occurring at L 1 will be also amplified. The noise of high-frequency components appears in the output of the photoelectric conversion circuit section upon resetting it and results in being terminated at the capacitor element CC 1 . This will be a cause to degrade S/N. The high-frequency components of noise of L 1 are also amplified in transfer of photoelectric conversion signal at TFT, which also degrades S/N. Namely, the performance required for the o