Title:
Deposition of metal oxide and/or low asymmetrical tunnel barrier interpoly insulators
Document Type and Number:
United States Patent 7446368

Abstract:
Structures and methods for programmable array type logic and/or memory devices with asymmetrical low tunnel barrier intergate insulators are provided. The programmable array type logic and/or memory devices include non-volatile memory which has a first source/drain region and a second source/drain region separated by a channel region in a substrate. A floating gate opposing the channel region and is separated therefrom by a gate oxide. A control gate opposes the floating gate. The control gate is separated from the floating gate by an asymmetrical low tunnel barrier intergate insulator formed by atomic layer deposition. The asymmetrical low tunnel barrier intergate insulator includes a metal oxide insulator selected from the group consisting of Al2O3, Ta2O5, TiO2, ZrO2, Nb2O5, SrBi2Ta2O3, SrTiO3, PbTiO3, and PbZrO3.

Inventors:
Eldridge, Jerome M. (Los Gatos, CA, US)
Ahn, Kie Y. (Chappaqua, NY, US)
Forbes, Leonard (Corvallis, OR, US)
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Application Number:
11/704458
Publication Date:
11/04/2008
Filing Date:
02/09/2007
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Assignee:
Micron Technology, Inc. (Boise, ID, US)
Primary Class:
Other Classes:
257/325, 257/314, 257/E29.274, 257/315, 257/E29.129
International Classes:
H01L29/76
Field of Search:
257/314, 257/E29.129
US Patent References:
3738817June, 1973Benjamin
3833386METHOD OF PREPAIRING POROUS CERAMIC STRUCTURES BY FIRING A POLYURETHANE FOAM THAT IS IMPREGNATED WITH INORGANIC MATERIALSeptember, 1974Wood et al.
3903232Dental and biomedical foams and methodSeptember, 1975Wood et al.
3926568High strength corrosion resistant nickel-base alloyDecember, 1975Benjamin et al.
3959191Novel hydrophobic polyurethane foamsMay, 1976Kehr et al.
4017322April, 1977Kawai et al.
4137200Crosslinked hydrophilic foams and methodJanuary, 1979Wood et al.
4293679Composition and method of controlling solid polyurethane particle size with water reactantOctober, 1981Cogliano
4295150Storage transistorOctober, 1981Adam
4302620Reactions involving zeolite catalysts modified with group IV A metalsNovember, 1981Chu
4358397Zeolite catalysts modified with group IV A metalsNovember, 1982Chu
4403083Preparation of solid polyurethane particlesSeptember, 1983Marans et al.
4412902Method of fabrication of Josephson tunnel junctionNovember, 1983Michikami et al.
4510584MOS Random access memory cell with nonvolatile storageApril, 1985Dias et al.
4545035Dynamic RAM with nonvolatile shadow memoryOctober, 1985Guterman et al.
4556975Programmable redundancy circuitDecember, 1985Smith et al.
4665417Non-volatile dynamic random access memory cellMay, 1987Lam
4672240Programmable redundancy circuitJune, 1987Smith et al.
4688078Partially relaxable composite dielectric structureAugust, 1987Hseih
4757360Floating gate memory device with facing asperities on floating and control gatesJuly, 1988Faraone et al.
4780424Process for fabricating electrically alterable floating gate memory devicesOctober, 1988Holler
4939559Dual electron injector structures using a conductive oxide between injectorsJuly, 1990DiMaria et al.
4940636Optical interference filterJuly, 1990Brock et al.
4961004X-ray intensifying screen including a titanium activated hafnium dioxide phosphor containing samarium to reduce afterglowOctober, 1990Bryan et al.
4963753X-ray intensifying screen including a titanium activated hafnium dioxide phosphor containing gadolinium to reduce afterglowOctober, 1990Bryan et al.
4963754X-ray intensifying screen including a titanium activated hafnium dioxide phosphor containing thulium to reduce afterglowOctober, 1990Bryan et al.
4967085X-ray intensifying screen including a titanium activated hafnium dioxide phosphor containing neodymium to reduce afterglowOctober, 1990Bryan et al.
4967087X-ray intensifying screen including a titanium activated hafnium dioxide phosphor containing ytterbium to reduce afterglowOctober, 1990Bryan et al.
4972086X-ray intensifying screen including a titanium activated hafnium dioxide phosphor containing erbium to reduce afterglowNovember, 1990Bryan et al.
4972516X-ray intensifying screen including a titanium activated hafnium dioxide phosphur containing holmium to reduce afterglowNovember, 1990Bryan et al.
4975014High temperature low thermal expansion fastenerDecember, 1990Rufin et al.
4975588X-ray intensifying screen including a titanium activated hafnium dioxide phosphor containing lutetium to reduce afterglowDecember, 1990Bryan et al.
4980559X-ray intensifying screen including a titanium activated hafnium dioxide phospher containing europium to reduce afterglowDecember, 1990Bryan et al.
4980560X-ray intensifying screen including a titanium activated hafnium dioxide phosphor containing scandiumDecember, 1990Bryan et al.
4983847X-ray intensifying screen including a titanium activated hafnium dioxide phosphor containing indiumJanuary, 1991Bryan et al.
4988880X-ray intensifying screen containing hafnia phosphorJanuary, 1991Bryan et al.
4990282Titanium activated hafnia and/or zirconia host phosphor containing scandiumFebruary, 1991Bryan et al.
4992205Titanium activated hafnia and/or zirconia host phosphor containing indiumFebruary, 1991Bryan et al.
4994205Composition containing a hafnia phosphor of enhanced luminescenceFebruary, 1991Bryan et al.
4996003Titanium activated hafnia and/or zirconia host phosphor containing a selected rare earthFebruary, 1991Bryan et al.
5008034Titanium activated hafnia and/or zirconia host phosphor containing neodymiumApril, 1991Bryan et al.
5017791X-ray intensifying screen including a titanium activated hafnium dioxide phosphor containing yttrium to reduce afterglowMay, 1991Bryan et al.
5042011Sense amplifier pulldown device with tailored edge inputAugust, 1991Casper et al.
5057448Method of making a semiconductor device having DRAM cells and floating gate memory cellsOctober, 1991Kuroda
5071782Vertical memory cell array and method of fabricationDecember, 1991Mori
5073519Method of fabricating a vertical FET device with low gate to drain overlap capacitanceDecember, 1991Rodder
5075536Heating element assembly for glow plugDecember, 1991Towe et al.
5084606Encapsulated heating filament for glow plugJanuary, 1992Bailey et al.
5095218X-ray intensifying screen with enhanced emissionMarch, 1992Bryan et al.
5153880Field-programmable redundancy apparatus for memory arraysOctober, 1992Owen et al.
5280205Fast sense amplifierJanuary, 1994Green et al.
5315142High performance trench EEPROM cellMay, 1994Acovic et al.
5331188Non-volatile DRAM cellJuly, 1994Acovic et al.
5338953Electrically erasable and programmable semiconductor memory device with trench memory transistor and manufacturing method of the sameAugust, 1994Wake
5350738Method of manufacturing an oxide superconductor filmSeptember, 1994Hase et al.
5353431Memory address decoder with storage for memory attribute informationOctober, 1994Doyle et al.
5399516Method of making shadow RAM cell having a shallow trench EEPROMMarch, 1995Bergendahl et al.
5418389Field-effect transistor with perovskite oxide channelMay, 1995Watanabe
5429966Method of fabricating a textured tunnel oxide for EEPROM applicationsJuly, 1995Wu et al.
5474947Nonvolatile memory processDecember, 1995Chang et al.
5488612Method and apparatus for field testing field programmable logic arraysJanuary, 1996Heybruck
5497494Method for saving and restoring the state of a CPU executing code in protected modeMarch, 1996Combs et al.
5498558Integrated circuit structure having floating electrode with discontinuous phase of metal silicide formed on a surface thereof and process for making sameMarch, 1996Kapoor
5508544Three dimensional FAMOS memory devicesApril, 1996Shah
5576567Vertical memory cell array and method of fabricationNovember, 1996Mori
5600592Nonvolatile semiconductor memory device having a word line to which a negative voltage is appliedFebruary, 1997Atsumi et al.
5608670Flash memory with improved erasability and its circuitryMarch, 1997Akaogi et al.
5618575Process and apparatus for the production of a metal oxide layerApril, 1997Peter
5618761Method of manufacturing a perovskite thin film dielectricApril, 1997Eguchi et al.
5619051Semiconductor nonvolatile memory cellApril, 1997Endo
5619450Drive circuit for flash memory with improved erasabilityApril, 1997Takeguchi
5619642Fault tolerant memory system which utilizes data from a shadow memory device upon the detection of erroneous data in a main memory deviceApril, 1997Nielsen et al.
5627785Memory device with a sense amplifierMay, 1997Gilliam et al.
5677867Memory with isolatable expandable bit linesOctober, 1997Hazani
5691209Lattice interconnect method and apparatus for manufacturing multi-chip modulesNovember, 1997Liberkowski
5691230Technique for producing small islands of silicon on insulatorNovember, 1997Forbes
5703387Split gate memory cell with vertical floating gateDecember, 1997Hong
5705415Process for forming an electrically programmable read-only memory cellJanuary, 1998Orlowski et al.
5739544Quantization functional device utilizing a resonance tunneling effect and method for producing the sameApril, 1998Yuki et al.
5739567Highly compact memory device with nonvolatile vertical transistor memory cellApril, 1998Wong
5751038Electrically erasable and programmable read only memory (EEPROM) having multiple overlapping metallization layersMay, 1998Mukherjee
5768192Non-volatile semiconductor memory cell utilizing asymmetrical charge trappingJune, 1998Eitan
5798548Semiconductor device having multiple control gatesAugust, 1998Fujiwara
5801401Flash memory with microcrystalline silicon carbide film floating gateSeptember, 1998Forbes
5852306Flash memory with nanocrystalline silicon film floating gateDecember, 1998Forbes
5880991Structure for low cost mixed memory integration, new NVRAM structure, and process for forming the mixed memory and NVRAM structureMarch, 1999Hsu et al.
5888867Non-uniform threshold voltage adjustment in flash eproms through gate work function alterationMarch, 1999Wang et al.
5923056Electronic components with doped metal oxide dielectric materials and a process for making electronic components with doped metal oxide dielectric materialsJuly, 1999Lee et al.
5936274High density flash memoryAugust, 1999Forbes et al.
5952692Memory device with improved charge storage barrier structureSeptember, 1999Nakazato et al.
5959465Fast Nor-Nor PLA operating from a single-phase clockSeptember, 1999Beat
5962959Electron emission device and display device for emitting electrons in response to an applied electric field using the electron emission deviceOctober, 1999Iwasaki et al.
5969383Split-gate memory device and method for accessing the sameOctober, 1999Chang et al.
5973355Nonvolatile semiconductor memory device and manufacturing method of the sameOctober, 1999Shirai et al.
5981350Method for forming high capacitance memory cellsNovember, 1999Geusic et al.
5986932Non-volatile static random access memory and methods for using sameNovember, 1999Ratnakumar et al.
5990605Electron emission device and display device using the sameNovember, 1999Yoshikawa et al.
5991225Programmable memory address decode array with vertical transistorsNovember, 1999Forbes et al.
5998528Viscous carrier compositions, including gels, formed with an organic liquid carrier, a layered material: polymer complex, and a di-, and/or tri-valent cationDecember, 1999Tsipursky et al.
6009011Non-volatile memory and method for operating the sameDecember, 1999Yamauchi
6023124Electron emission device and display device using the sameFebruary, 2000Chuman et al.
6023125Electron emission device and display using the sameFebruary, 2000Yoshikawa et al.
6025228Method of fabricating an oxynitride-capped high dielectric constant interpolysilicon dielectric structure for a low voltage non-volatile memoryFebruary, 2000Ibok et al.
6025627Alternate method and structure for improved floating gate tunneling devicesFebruary, 2000Forbes et al.
6031263DEAPROM and transistor with gallium nitride or gallium aluminum nitride gateFebruary, 2000Forbes et al.
6066922Electron emission device and display device using the sameMay, 2000Iwasaki
6069380Single-electron floating-gate MOS memoryMay, 2000Chou et al.
6069816High-speed responding data storing device for maintaining stored data without power supplyMay, 2000Nishimura
6077745Self-aligned diffused source vertical transistors with stack capacitors in a 4F-square memory cell arrayJune, 2000Burns, Jr. et al.
6087222Method of manufacture of vertical split gate flash memory deviceJuly, 2000Jung Lin et al.
6087695Source side injection flash EEPROM memory cell with dielectric pillar and operationJuly, 2000Chen
6091626Low voltage, low power static random access memory cellJuly, 2000Madan
6093606Method of manufacture of vertical stacked gate flash memory deviceJuly, 2000Lin et al.
6103419Solid secondary lithium cell based on lithiated zirconium, titanium or hafnium oxide cathode materialAugust, 2000Saidi et al.
6108240Implementation of EEPROM using intermediate gate voltage to avoid disturb conditionsAugust, 2000Lavi et al.
6118147Double density non-volatile memory cellsSeptember, 2000Liu
6118159Electrically programmable memory cell configurationSeptember, 2000Willer et al.
6124608Non-volatile trench semiconductor device having a shallow drain regionSeptember, 2000Liu et al.
6124729Field programmable logic arrays with vertical transistorsSeptember, 2000Noble et al.
6125062Single electron MOSFET memory device and methodSeptember, 2000Ahn et al.
6130453Flash memory structure with floating gate in vertical trenchOctober, 2000Mei et al.
6130503Electron emission device and display using the sameOctober, 2000Negishi et al.
6134175Memory address decode array with vertical transistorsOctober, 2000Forbes et al.
6135175Tree harvester provided with a rotatable worktableOctober, 2000Gaudreault et al.
6137025Ceramic composition for immobilization of actinidesOctober, 2000Ebbinghaus et al.
6141238Dynamic random access memory (DRAM) cells with repressed ferroelectric memory methods of reading same, and apparatuses including sameOctober, 2000Forbes et al.
6141248DRAM and SRAM memory cells with repressed memoryOctober, 2000Forbes et al.
6141260Single electron resistor memory device and method for use thereofOctober, 2000Ahn et al.
6143636High density flash memoryNovember, 2000Forbes et al.
6144155Electron emission device and display device using the sameNovember, 2000Yoshikawa et al.
6147378Fully recessed semiconductor device and method for low power applications with single wrap around buried drain regionNovember, 2000Liu et al.
6147443Electron emission device and display device using the sameNovember, 2000Yoshikawa et al.
6153468Method of forming a logic array for a decoderNovember, 2000Forbes et al.
6157061Nonvolatile semiconductor memory device and method of manufacturing the sameDecember, 2000Kawata
6163049Method of forming a composite interpoly gate dielectricDecember, 2000Bui
6166487Electron emission device and display device using the sameDecember, 2000Negishi et al.
6169306Semiconductor devices comprised of one or more epitaxial layersJanuary, 2001Gardner et al.
6180461Double sidewall short channel split gate flash memoryJanuary, 2001Ogura
6180980Trench non-volatile memory cellJanuary, 2001Wang
6184612Electron emission device with electron supply layer of hydrogenated amorphous siliconFebruary, 2001Negishi et al.
6191459Electrically programmable memory cell array, using charge carrier traps and insulation trenchesFebruary, 2001Hofmann et al.
62045298 bit per cell non-volatile semiconductor memory structure utilizing trench technology and dielectric floating gateMarch, 2001Lung et al.
6208164Programmable logic array with vertical transistorsMarch, 2001Noble et al.
6210999Method and test structure for low-temperature integration of high dielectric constant gate dielectrics into self-aligned semiconductor devicesApril, 2001Gardner et al.
6229175Nonvolatile memoryMay, 2001Uchida
6238976Method for forming high density flash memoryMay, 2001Noble et al.
6246606Memory using insulator trapsJune, 2001Forbes et al.
6249020DEAPROM and transistor with gallium nitride or gallium aluminum nitride gateJune, 2001Forbes et al.
6249460Dynamic flash memory cells with ultrathin tunnel oxidesJune, 2001Forbes et al.
6259198Flat panel display apparatus with an array of electron emitting devicesJuly, 2001Yanagisawa et al.
6274937Silicon multi-chip module packaging with integrated passive components and method of makingAugust, 2001Ahn et al.
6278230Electron emission device and display device using the sameAugust, 2001Yoshizawa et al.
6281042Structure and method for a high performance electronic packaging assemblyAugust, 2001Ahn et al.
6285123Electron emission device with specific island-like regionsSeptember, 2001Yamada et al.
6297103Structure and method for dual gate oxide thicknessesOctober, 2001Ahn et al.
6306708Fabrication method for an electrically erasable programmable read only memoryOctober, 2001Peng
6307775Deaprom and transistor with gallium nitride or gallium aluminum nitride gateOctober, 2001Forbes et al.
6313518Porous silicon oxycarbide integrated circuit insulatorNovember, 2001Ahn et al.
6316298Fabrication method for a flash memory deviceNovember, 2001Lee
6316873Electron emission device and display device using the sameNovember, 2001Ito et al.
6317364Multi-state memoryNovember, 2001Guterman et al.
6320091Process for making a ceramic composition for immobilization of actinidesNovember, 2001Ebbinghaus et al.
6323844Cursor controlling device and the method of the sameNovember, 2001Yeh et al.
6335554Semiconductor MemoryJanuary, 2002Yoshikawa
6341084Magnetic random access memory circuitJanuary, 2002Numata et al.
6350704Porous silicon oxycarbide integrated circuit insulatorFebruary, 2002Ahn et al.
6351411Memory using insulator trapsFebruary, 2002Forbes et al.
6376312Formation of non-volatile memory device comprised of an array of vertical field effect transistor structuresApril, 2002Yu
6377070In-service programmable logic arrays with ultra thin vertical body transistorsApril, 2002Forbes
6388376Electron emission device with electron supply layer having reduced resistanceMay, 2002Negishi et al.
6396745Vertical two-transistor flash memoryMay, 2002Hong et al.
6400070Electron emission device and display device using the sameJune, 2002Yamada et al.
6404124Electron emission device and display apparatus using the sameJune, 2002Sakemura et al.
6404681Method for erasing data from a non-volatile semiconductor memory deviceJune, 2002Hirano
6424001Flash memory with ultra thin vertical body transistorsJuly, 2002Forbes et al.
6429237Wire coating compositionsAugust, 2002Tooley
6433382Split-gate vertically oriented EEPROM device and processAugust, 2002Orlowski et al.
6433383Methods and arrangements for forming a single interpoly dielectric layer in a semiconductor deviceAugust, 2002Ramsbey et al.
6440801Structure for folded architecture pillar memory cellAugust, 2002Furukawa et al.
6461905Dummy gate process to reduce the Vss resistance of flash productsOctober, 2002Wang et al.
6461931Thin dielectric films for DRAM storage capacitorsOctober, 2002Eldridge
6465836Vertical split gate field effect transistor (FET) deviceOctober, 2002Lin et al.
6472803Electron emission light-emitting device and display apparatus using the sameOctober, 2002Yoshizawa et al.
6475857Method of making a scalable two transistor memory deviceNovember, 2002Kim et al.
64764344 F2 folded bit line dram cell structure having buried bit and word linesNovember, 2002Noble et al.
6489648Semiconductor deviceDecember, 2002Iwasaki et al.
6492288Glass ceramic and temperature compensating memberDecember, 2002Shindo
6495436Formation of metal oxide gate dielectricDecember, 2002Ahn et al.
6504207Method to create EEPROM memory structures integrated with high performance logic and NVRAM, and operating conditions for the sameJanuary, 2003Chen et al.
6514820Method for forming single electron resistor memoryFebruary, 2003Ahn et al.
6514828Method of fabricating a highly reliable gate oxideFebruary, 2003Ahn et al.
6514842Low resistance gate flash memoryFebruary, 2003Prall et al.
6519176Dual threshold SRAM cell for single-ended sensingFebruary, 2003Hamzaoglu et al.
6521943Semiconductor device having thin electrode layer adjacent gate insulator and method of manufactureFebruary, 2003Mine et al.
6534420Methods for forming dielectric materials and methods for forming semiconductor devicesMarch, 2003Ahn et al.
6541280High K dielectric filmApril, 2003Kaushik et al.
6544846Method of manufacturing a single electron resistor memory deviceApril, 2003Ahn et al.
6552383Integrated decoupling capacitorsApril, 2003Ahn et al.
6566682Programmable memory address and decode circuits with ultra thin vertical body transistorsMay, 2003Forbes
6570248Structure and method for a high-performance electronic packaging assemblyMay, 2003Ahn et al.
6574143Memory device using hot charge carrier convertersJune, 2003Nakazato
6580124Multigate semiconductor device with vertical channel current and method of fabricationJune, 2003Cleeves et al.
6586792Structures, methods, and systems for ferroelectric memory transistorsJuly, 2003Ahn et al.
6586797Graded composition gate insulators to reduce tunneling barriers in flash memory devicesJuly, 2003Forbes et al.
6602053Cooling structure and method of manufacturing the sameAugust, 2003Subramanian et al.
6608378Formation of metal oxide gate dielectricAugust, 2003Ahn et al.
6641887Optical recording mediumNovember, 2003Lida et al.
6661058Highly reliable gate oxide and method of fabricationDecember, 2003Ahn et al.
6700132Flat panel display device utilizing electron emission devicesMarch, 2004Chuman et al.
6710465Scalable two transistor memory deviceMarch, 2004Song et al.
6710538Field emission display having reduced power requirements and methodMarch, 2004Ahn et al.
6720216Programmable memory address and decode circuits with vertical body transistorsApril, 2004Forbes
6720221Structure and method for dual gate oxide thicknessesApril, 2004Ahn et al.
6730575Methods of forming perovskite-type material and capacitor dielectric having perovskite-type crystalline structureMay, 2004Eldridge
6740928Semiconductor deviceMay, 2004Yoshii et al.
6744063Image pickup device including electron-emitting devicesJune, 2004Yoshikawa et al.
6753568Memory deviceJune, 2004Nakazato et al.
6753571Nonvolatile memory cells having split gate structure and methods of fabricating the sameJune, 2004Kim et al.
6754108DRAM cells with repressed floating gate memory, low tunnel barrier interpoly insulatorsJune, 2004Forbes
6756298Methods and apparatus for making integrated-circuit wiring from copper, silver, gold, and other metalsJune, 2004Ahn et al.
6759151Multilayer article characterized by low coefficient of thermal expansion outer layerJuly, 2004Lee
6767795Highly reliable amorphous high-k gate dielectric ZrOXNYJuly, 2004Ahn et al.
6774050Doped aluminum oxide dielectricsAugust, 2004Ahn et al.
6778441Integrated circuit memory device and methodAugust, 2004Forbes et al.
6787413Capacitor structure forming methodsSeptember, 2004Ahn
6787992Display device of flat panel structure with emission devices of matrix arraySeptember, 2004Chuman et al.
6790791Lanthanide doped TiOx dielectric filmsSeptember, 2004Ahn et al.
6794250Vertical split gate flash memory cell and method for fabricating the sameSeptember, 2004Chang et al.
6794709Structure and method for dual gate oxide thicknessesSeptember, 2004Ahn et al.
6800895Vertical split gate flash memory cell and method for fabricating the sameOctober, 2004Chang et al.
6803326Porous silicon oxycarbide integrated circuit insulatorOctober, 2004Ahn et al.
6812100Evaporation of Y-Si-O films for medium-k dielectricsNovember, 2004Ahn et al.
6828045Organic electroluminescence element and production method thereofDecember, 2004Tokailin et al.
6833285Method of making a chip packaging device having an interposerDecember, 2004Ahn et al.
6833308Structure and method for dual gate oxide thicknessesDecember, 2004Ahn et al.
6835111Field emission display having porous silicon dioxide layerDecember, 2004Ahn et al.
6838404Metal alkoxides and methods of making sameJanuary, 2005Hentges et al.
6844203Gate oxides, and methods of formingJanuary, 2005Ahn et al.
6846574Honeycomb structure thermal barrier coatingJanuary, 2005Subramanian
6852167Methods, systems, and apparatus for uniform chemical-vapor depositionsFebruary, 2005Ahn
6858120Method and apparatus for the fabrication of ferroelectric filmsFebruary, 2005Ahn et al.
6858444Method for making a ferroelectric memory transistorFebruary, 2005Ahn et al.
6858865Doped aluminum oxide dielectricsFebruary, 2005Ahn et al.
6881994Monolithic three dimensional array of charge storage devices containing a planarized surfaceApril, 2005Lee et al.
6884739Lanthanide doped TiOx dielectric films by plasma oxidationApril, 2005Ahn et al.
6893984Evaporated LaA1O3 films for gate dielectricsMay, 2005Ahn et al.
6894944Semiconductor integrated circuit deviceMay, 2005Ishibashi et al.
6900122Low-temperature grown high-quality ultra-thin praseodymium gate dielectricsMay, 2005Ahn et al.
6903367Programmable memory address and decode circuits with vertical body transistorsJune, 2005Forbes
6914800Structures, methods, and systems for ferroelectric memory transistorsJuly, 2005Ahn et al.
6919266Copper technology for ULSI metallizationJuly, 2005Ahn et al.
6921702Atomic layer deposited nanolaminates of HfO2/ZrO2 films as gate dielectricsJuly, 2005Ahn et al.
6930346Evaporation of Y-Si-O films for medium-K dielectricsAugust, 2005Ahn et al.
6950340Asymmetric band-gap engineered nonvolatile memory deviceSeptember, 2005Bhattacharyya
6952032Programmable array logic or memory devices with asymmetrical tunnel barriersOctober, 2005Forbes et al.
6953730Low-temperature grown high quality ultra-thin CoTiO3 gate dielectricsOctober, 2005Ahn et al.
6958302Atomic layer deposited Zr-Sn-Ti-O films using TiI4October, 2005Ahn et al.
6958937DRAM cells with repressed floating gate memory, low tunnel barrier interpoly insulatorsOctober, 2005Forbes et al.
6960538Composite dielectric forming methods and composite dielectricsNovember, 2005Ahn et al.
6963103SRAM cells with repressed floating gate memory, low tunnel barrier interpoly insulatorsNovember, 2005Forbes
6970053Atomic layer deposition (ALD) high permeability layered magnetic films to reduce noise in high speed interconnectionNovember, 2005Akram et al.
6979855High-quality praseodymium gate dielectricsDecember, 2005Ahn et al.
6989573Lanthanide oxide/zirconium oxide atomic layer deposited nanolaminate gate dielectricsJanuary, 2006Ahn et al.
7026694Lanthanide doped TiOx dielectric films by plasma oxidationApril, 2006Ahn et al.
7042043Programmable array logic or memory devices with asymmetrical tunnel barriersMay, 2006Forbes et al.
7045430Atomic layer-deposited LaAlO3 films for gate dielectricsMay, 2006Ahn et al.
7049192Lanthanide oxide / hafnium oxide dielectricsMay, 2006Ahn et al.
7064058Low-temperature growth high-quality ultra-thin praseodymium gate dieletricsJune, 2006Ahn et al.
7068544Flash memory with low tunnel barrier interpoly insulatorsJune, 2006Forbes et al.
7074673Service programmable logic arrays with low tunnel barrier interpoly insulatorsJuly, 2006Forbes
7075829Programmable memory address and decode circuits with low tunnel barrier interpoly insulatorsJuly, 2006Forbes
7081421Lanthanide oxide dielectric layerJuly, 2006Ahn et al.
7084078Atomic layer deposited lanthanide doped TiOx dielectric filmsAugust, 2006Ahn et al.
7087954In service programmable logic arrays with low tunnel barrier interpoly insulatorsAugust, 2006Forbes
7101813Atomic layer deposited Zr-Sn-Ti-O filmsSeptember, 2006Ahn et al.
7112841Graded composition metal oxide tunnel barrier interpoly insulatorsSeptember, 2006Eldridge et al.
7126183Programmable array logic or memory with p-channel devices and asymmetrical tunnel barriersOctober, 2006Forbes et al.
7133316Program/erase method for P-channel charge trapping memory deviceNovember, 2006Lue
7135734Graded composition metal oxide tunnel barrier interpoly insulatorsNovember, 2006Eldridge et al.257/314
7153744Method of forming self-aligned poly for embedded flashDecember, 2006Chen et al.
7154138Transistor-arrangement, method for operating a transistor arrangement as a data storage element and method for producing a transistor-arrangementDecember, 2006Hofmann et al.
7163863Vertical memory cell and manufacturing method thereofJanuary, 2007Shone
7166886DRAM cells with repressed floating gate memory, low tunnel barrier interpoly insulatorsJanuary, 2007Forbes
7187587Programmable memory address and decode circuits with low tunnel barrier interpoly insulatorsMarch, 2007Forbes
7205601FinFET split gate EEPROM structure and method of its fabricationApril, 2007Lee et al.
7235501Lanthanum hafnium oxide dielectricsJune, 2007Ahn et al.
7274067Service programmable logic arrays with low tunnel barrier interpoly insulatorsSeptember, 2007Forbes
7365027ALD of amorphous lanthanide doped TiOx filmsApril, 2008Ahn et al.
7372096Programmable array logic or memory with p-channel devices and asymmetrical tunnel barriersMay, 2008Forbes et al.
7372097Programmable array logic or memory with p-channel devices and asymmetrical tunnel barriersMay, 2008Forbes et al.
7391072Programmable array logic or memory with p-channel devices and asymmetrical tunnel barriersJune, 2008Forbes et al.
20010013621Memory DeviceAugust, 2001Nakazato
20010017369Electron-emitting device and method of manufacturing the same and display apparatus using the sameAugust, 2001Iwasaki et al.
20010040430ELECTRON EMISSION DEVICE AND DISPLAY DEVICE USING THE SAMENovember, 2001Ito et al.
20010041250Graded thin filmsNovember, 2001Werkhoven et al.
20010055838Nonvolatile memory on SOI and compound semiconductor substrates and method of fabricationDecember, 2001Walker et al.
20020002216Wire coating compositionsJanuary, 2002Tooley
20020004276Structure and method for dual gate oxide thicknessesJanuary, 2002Ahn et al.
20020004277Structure and method for dual gate oxide thicknessesJanuary, 2002Ahn et al.
20020008324Semiconductor device and method of manufacturing sameJanuary, 2002Shinkawata
20020024083DRAM TECHNOLOGY COMPATIBLE NON VOLATILE MEMORY CELLSFebruary, 2002Noble et al.
20020028541Dense arrays and charge storage devices, and methods for making sameMarch, 2002Lee et al.
20020051859Optical recording mediumMay, 2002Iida et al.
20020058578Glass ceramic and temperature compensating memberMay, 2002Shindo
20020076070SpeakerJune, 2002Yoshikawa et al.
20020106536Dielectric layer for semiconductor device and method of manufacturing the sameAugust, 2002Lee et al.
20020109138PROGRAMMABLE MEMORY ADDRESS AND DECODE CIRCUITS WITH ULTRA THIN VERTICAL BODY TRANSISTORSAugust, 2002Forbes
20020110973FABRICATION METHOD AND STRUCTURE OF A FLASH MEMORYAugust, 2002Liou et al.
20020110983Method of fabricating a split-gate flash memory cellAugust, 2002Liu et al.
20020113261Semiconductor deviceAugust, 2002Iwasaki et al.
20020117963Flat panel display deviceAugust, 2002Chuman et al.
20020125490Flat panel display device utilizing electron emission devicesSeptember, 2002Chuman et al.
20020130338Structures, methods, and systems for ferroelectric memory transistorsSeptember, 2002Ahn et al.
20020137250High K dielectric film and method for makingSeptember, 2002Nguyen et al.
20020140022VERTICAL SPLIT GATE FIELD EFFECT TRANSISTOR (FET) DEVICEOctober, 2002Lin et al.
20020155688Highly reliable gate oxide and method of fabricationOctober, 2002Ahn
20020172799Honeycomb structure thermal barrier coatingNovember, 2002Subramanian
20020176293DRAM technology compatible processor/memory chipsNovember, 2002Forbes et al.
20030026697Cooling structure and method of manufacturing the sameFebruary, 2003Subramaniam et al.
20030042528Sram cells with repressed floating gate memory, low tunnel barrier interpoly insulatorsMarch, 2003Forbes
20030043637Flash memory with low tunnel barrier interpoly insulatorsMarch, 2003Forbes et al.
20030048745Image pickup device including electron-emitting devicesMarch, 2003Yoshikawa et al.
20030067046Semiconductor deviceApril, 2003Iwasaki et al.
20030130127Ultrathin dielectric oxide filmsJuly, 2003Hentges et al.
20030134475Method for manufacturing a multi-bit memory cellJuly, 2003Hofmann et al.
20030142569Capacitive techniques to reduce noise in high speed interconnectionsJuly, 2003Forbes
20030162399Method, composition and apparatus for tunable selectivity during chemical mechanical polishing of metallic structuresAugust, 2003Singh et al.
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20040043541Atomic layer deposited lanthanide doped TiOx dielectric filmsMarch, 2004Ahn et al.
20040066484Electrode substrate and production method thereofApril, 2004Tokailin et al.
20040110348Atomic layer deposited Zr-Sn-Ti-O films using TiI4June, 2004Ahn et al.
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20040164357Atomic layer-deposited LaAIO3 films for gate dielectricsAugust, 2004Ahn et al.
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20040183108Low-temperature grown high-quality ultra-thin praseodymium gate dielectricsSeptember, 2004Ahn
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20040189175Field emission display having reduced power requirements and methodSeptember, 2004Ahn et al.
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20050023584Atomic layer deposition and conversionFebruary, 2005Derderian et al.
20050023594Pr2O3-based la-oxide gate dielectricsFebruary, 2005Ahn et al.
20050023595Programmable array logic or memory devices with asymmetrical tunnel barriersFebruary, 2005Forbes et al.
20050023602Programmable array logic or memory with p-channel devices and asymmetrical tunnel barriersFebruary, 2005Forbes et al.
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20050077519Lanthanide oxide/zirconium oxide atomic layer deposited nanolaminate gate dielectricsApril, 2005Ahn et al.
20050124109Top surface roughness reduction of high-k dielectric materials using plasma based processesJune, 2005Quevado-Lopez et al.
20050124174Lanthanide doped TiOx dielectric films by plasma oxidationJune, 2005Ahn et al.
20050124175Lanthanide oxide/zirconium oxide atomic layer deposited nanolaminate gate dielectricsJune, 2005Ahn et al.
20050138262Flash memory having a high-permittivity tunnel dielectricJune, 2005Forbes
20050145957Evaporated LaAlO3 films for gate dielectricsJuly, 2005Ahn et al.
20050158973Low-temperature grown high quality ultra-thin CoTiO3 gate dielectricsJuly, 2005Ahn et al.
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20050169054SRAM cells with repressed floating gate memory, low tunnel barrier interpoly insulatorsAugust, 2005Forbes
20050227442Atomic layer deposited nanolaminates of HfO2/ZrO2 films as gate dielectricsOctober, 2005Ahn et al.
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20060001049Service programmable logic arrays with low tunnel barrier interpoly insulatorsJanuary, 2006Forbes
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20060003517Atomic layer deposited Zr-Sn-Ti-O films using TiI4January, 2006Ahn et al.
20060024975Atomic layer deposition of zirconium-doped tantalum oxide filmsFebruary, 2006Ahn et al.
20060035405Methods of manufacturing a thin film including hafnium titanium oxide and methods of manufacturing a semiconductor device including the sameFebruary, 2006Park et al.
20060043492Ruthenium gate for a lanthanide oxide dielectric layerMarch, 2006Ahn et al.
20060043504Atomic layer deposited titanium aluminum oxide filmsMarch, 2006Ahn et al.
20060046505RUTHENIUM GATE FOR A LANTHANIDE OXIDE DIELECTRIC LAYERMarch, 2006Ahn et al.
20060046522Atomic layer deposited lanthanum aluminum oxide dielectric layerMarch, 2006Ahn et al.
20060054943Flash EEPROM with metal floating gate electrodeMarch, 2006Li et al.
20060128168Atomic layer deposited lanthanum hafnium oxide dielectricsJune, 2006Ahn et al.
20060148180Atomic layer deposited hafnium tantalum oxide dielectricsJuly, 2006Ahn et al.
20060170029Novel process for erase improvement in a non-volatile memory deviceAugust, 2006Liu et al.
20060176645Atomic layer deposition of Dy doped HfO2 films as gate dielectricsAugust, 2006Ahn et al.
20060183272Atomic layer deposition of Zr3N4/ZrO2 films as gate dielectricsAugust, 2006Ahn et al.
20060186458Germanium-silicon-carbide floating gates in memoriesAugust, 2006Forbes et al.
20060189154Atomic layer deposition of Hf3N4/HfO2 films as gate dielectricsAugust, 2006Ahn et al.
20060199338ATOMIC LAYER DEPOSITION OF METAL OXIDE AND/OR LOW ASYMMETRICAL TUNNEL BARRIER INTERPOLY INSULATORSSeptember, 2006Eldridge et al.
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20060244082Atomic layer desposition of a ruthenium layer to a lanthanide oxide dielectric layerNovember, 2006Ahn et al.
20060263981DRAM cells with repressed floating gate memory, low tunnel barrier interpoly insulatorsNovember, 2006Forbes
20060274580DRAM cells with repressed floating gate memory, low tunnel barrier interpoly insulatorsDecember, 2006Forbes
20060278917Floating gate structuresDecember, 2006Forbes et al.
20060281330Iridium / zirconium oxide structureDecember, 2006Ahn et al.
20070018214Magnesium titanium oxide filmsJanuary, 2007Ahn
20070020835Atomic layer deposition of CeO2/Al2O3 films as gate dielectricsJanuary, 2007Ahn et al.
20070048926Lanthanum aluminum oxynitride dielectric filmsMarch, 2007Ahn
20070048953Graded dielectric layersMarch, 2007Gealy et al.
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20070049023Zirconium-doped gadolinium oxide filmsMarch, 2007Ahn et al.
20070049054Cobalt titanium oxide dielectric filmsMarch, 2007Ahn et al.
20070090439HAFNIUM TITANIUM OXIDE FILMSApril, 2007Ahn et al.
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20070134931Lanthanide yttrium aluminum oxide dielectric filmsJune, 2007Ahn et al.
20070145462Low tunnel barrier insulatorsJune, 2007Eldridge et al.
20070158765Gallium lanthanide oxide filmsJuly, 2007Ahn et al.
20070170492Germanium-silicon-carbide floating gates in memoriesJuly, 2007Forbes et al.
20070178635Atomic layer deposition of metal oxide and/or low asymmetrical tunnel barrier interpoly insulatorsAugust, 2007Eldridge et al.
20070195608Germanium-silicon-carbide floating gates in memoriesAugust, 2007Forbes et al.
20080014689Method for making planar nanowire surround gate mosfetJanuary, 2008Cleavelin et al.
20080032424ALD of Zr-substituted BaTiO3 films as gate dielectricsFebruary, 2008Ahn et al.
20080042211Strained semiconductor channels and methods of formationFebruary, 2008Bhattacharyya et al.
20080057659Hafnium aluminium oxynitride high-K dielectric and metal gatesMarch, 2008Forbes
20080057690Tantalum silicon oxynitride high-k dielectrics and metal gatesMarch, 2008Forbes
20080087945SILICON LANTHANIDE OXYNITRIDE FILMSApril, 2008Forbes et al.
Other References:
“Cobalt Titanium Oxide Dielectric Films”, U.S. Appl. No. 11/216,958, filed Aug. 31, 2005.
Aarik, Jaan , et al., “Anomalous effect of temperature on atomic layer deposition of titanium dioxide”, Journal of Crystal Growth, 220(4), (Dec. 2000),531-537.
Aarik, Jaan , “Texture development in nanocrystalline hafnium dioxide thin films grown by atomic layer deposition”, Journal of Crystal Growth, 220(1-2), (Nov. 15, 2000),105-113.
Afanas'ev, V , et al., “Electron energy barriers between (100)Si and ultrathin stacks of SiO2, Al2O3, and ZrO3 and ZrO2 insulators”, Applied Physics Letters, 78(20), (May 14, 2001),3073-3075.
Ahn, U.S. Appl. No. 10/379,470, filed Mar. 4, 2003.
Ahn, “Atomic Layer Deposited Dielectric Layers”, U.S. Appl. No. 10/379,470, filed Mar. 4, 2003.
Ahn, “Conductive Nanoparticles”, U.S. Appl. No. 11/197,184, filed Aug. 4, 2005.
Ahn, “Iridium / Zirconium Oxide Structure”, U.S. Appl. No. 11/152,759, filed Jun. 14, 2005.
Ahn, Kie Y., et al., “Lanthanide Yttrium Aluminum Oxide Dielectric Films”, U.S. Appl. No. 11/297,567, filed Dec. 8, 2005.
Ahn, Kie Y., et al., “Lanthanum Aluminum Oxynitride Dielectric Films”, U.S. Appl. No. 11/216,474, filed Aug. 31, 2005.
Ahn, Kie Y., et al., “Magnesium Titanium Oxide Films”, U.S. Appl. No. 11/189,075, filed Jul. 25, 2005.
Arya, S. P., et al., “Conduction properties of thin Al/sub 2/O/sub 3/ films”, Thin Solid Films, 91(4), (May 28, 1982),363-374.
Dipert, Brian , “Flash Memory Goes Mainstream”, IEEE Spectrum, 30(10), (Oct. 1993),48-52.
Eierdal, L. , et al., “Interaction of oxygen with Ni(110) studied by scanning tunneling microscopy”, Surface Science, 312(1-2), (Jun. 1994),31-53.
Eitan, Boaz , et al., “NROM: A Novel Localized Trapping, 2-Bit Nonvolatile Memory Cell”, IEEE Electron Device Letters, 21(11), (Nov. 2000),543-545.
Eldridge, J. M., et al., “Analysis of ultrathin oxide growth on indium”, Thin Solid Films, 12(2), (Oct. 1972),447-451.
Eldridge, J. , et al., “Measurement of Tunnel Current Density in a Metal-Oxide-Metal System as a Function of Oxide Thickness”, Proc. 12th Inter. Conf. on Low Temperature Physics, (1971),427-428.
Eldridge, J.M. , et al., “The Growth of Thin PbO Layers on Lead Films”, Surface Science, 40, (1973),512-530.
Ferguson, J D., et al., “Atomic layer deposition of Al2O3 and SiO2 on BN particles using sequential surface reactions”, Applied Surface Science, 162-163, (Aug. 1, 2000),280-292.
Gealy, Daniel F., et al., “Graded Dielectric Layers”, U.S. Appl. No. 11/216,542, filed Aug. 30, 2005.
Greiner, J. , “Josephson Tunneling Barriers by rf Sputter Etching in an Oxygen Plasma”, Journal of Applied Physics, 42(12), (Nov. 1971),5151-5155.
Greiner, J. , “Oxidation of lead films by rf sputter etching in an oxygen plasma”, Journal of Applied Physics, 45(1), (Jan. 1974),32-37.
Grimbolt, J. , “I. Interaction of Al Films with O2 at Low Pressures”, Journal of the Electrochemical Society, 129(10), (1982),pp. 2366-2368.
Grimbolt, J. , “II. Oxidation of Al Films”, Journal of Electrochem Soc.: Solid-State Science and Technology, (1982),pp. 2369-2372.
Gundlach, K. , et al., “Logarithmic conductivity of Al-Al/sub 2/O/sub 3/-Al tunneling junctions produced by plasma- and by thermal-oxidation”, Surface Science, 27(1), (Aug. 1971),125-141.
Guo, X. , “High Quality Ultra-thin (1.5 nm) High quality ultra-thin (1.5 nm) TiO/sub 2/-Si/sub 3/N/sub 4/ gate dielectric for deep sub-micron CMOS technology”, International Electron Devices Meeting 1999. Technical Digest, (1999),137-140.
Hodges, D. A., et al., “Analysis and Design of Digital Integrated Circuits”, McGraw-Hill Book Company, 2nd Edition, (1988),394-396.
Hodges, D. A., “Analysis and Design of Digital Integrated Circuits, 2nd Edition”, McGraw-Hill Publishing. New York, (1988),354-357.
Hurych, Z. , “Influence of Non-Uniform Thickness of Dielectric Layers on Capacitance and Tunnel Currents”, Solid-State Electronics, 9, (1966),967-979.
Itokawa, H , “Determination of Bandgap and Energy Band Alignment for High-Dielectric-Constant Gate Insulators Using High-Resolution X-ray Photoelectron Spectroscopy”, Extended Abstracts of the 1999 International Conference on Solid State Devices and Materials, (1999),158-159.
Kim, Yong S., et al., “Effect of rapid thermal annealing on the structure and the electrical properties of atomic-layer-deposited Ta2O5 films”, Journal of the Korean Physical Society, (Dec. 2000),975-979.
Kim, H. , “Leakage current and electrical breakdown in metal-organic chemical vapor deposited TiO/sub 2/ dielectrics on silicon substrates”, Applied Physics Letters, 69(25), (Dec. 16, 1996),3860-3862.
Kim, Yeong K., et al., “Novel capacitor technology for high density stand-alone and embedded DRAMs”, International Electron Devices Meeting 2000. Technical Digest. IEDM, (2000),369-372.
Kubaschewski, O. , et al., “Oxidation of Metals and Alloys”, Butterworths, London, (1962),53-63.
Kubaschewski, O. , et al., “Oxidation of Metals and Alloys,”, Butterworths, London, Second Edition,(1962),1-3, 5,6, 8-12, 24, 36-39.
Kukli, Kaupo , “Atomic Layer Deposition of Titanium Oxide from Til4 and H2O2”, Chemical Vapor Deposition, 6(6), (2000),303-310.
Kukli, Kaupo , et al., “Atomic layer deposition of zirconium oxide from zirconium tetraiodide, water and hydrogen peroxide”, Journal of Crystal Growth, 231(1-2), (Sep. 2001),262-272.
Kukli, Kukli , et al., “Development of Dielectric Properties of Niobium Oxide, Tantalum Oxide, and Aluminum Oxide Based Nanolayered Materials”, Journal of the Electrochemical Society, 148(2), (Feb. 2001),F35-F41.
Kukli, Kaupo , et al., “Real-time monitoring in atomic layer deposition of TiO/sub 2/ from Til/sub 4/ and H/sub 2/O-H/sub 2/O/sub 2/”, Langmuir, 16(21), (Oct. 17, 2000),8122-8128.
Kwo, J. , “Properties of high k gate dielectrics Gd2O3 and Y2O3 for Si”, Journal of Applied Physics, 89(7), (2001),3920-3927.
Lee, J. , et al., “Effect of polysilicon gate on the flatband voltage shift and mobility degradation for ALD-Al/sub 2/O/sub 3/ gate dielectric”, International Electron Devices Meeting 2000. Technical Digest. IEDM, (2000),645-648.
Luan, H. , “High Quality Ta2O5 Gate Dielectrics with Tox,eq less than 10A”, IEDM, (1999),pp. 141-144.
Ma, Yanjun , et al., “Zirconium oxide based gate dielectrics with equivalent oxide thickness of less than 1.0 nm and performance of submicron MOSFET using a nitride gate replacement process”, International Electron Devices Meeting 1999. Technical Digest, (1999),149-152.
Marshalek, R. , et al., “Photoresponse Characteristics of Thin-Film Nickel-Nickel Oxide-Nickel Tunneling Junctions”, IEEE Journal of Quantum Electronics, QE-19(4), (1983),743-754.
Masuoka, F. , et al., “A 256K Flash EEPROM using Triple Polysilicon Technology”, IEEE International Solid-State Circuits Conference, Digest of Technical Papers, (1985),168-169.
Masuoka, F. , et al., “A New Flash EEPROM Cell using Triple Polysilicon Technology”, International Electron Devices Meeting, Technical Digest, San Francisco, CA,(1984),464-467.
Mori, S. , et al., “Reliable CVD Inter-Poly Dielectrics for Advanced E&EEPROM”, Symposium on VSLI Technology, Digest of Technical Papers, (1985),16-17.
Muller, H. , “Electrical and Optical Properties of Sputtered In2O3 Films”, Physica Status Solidi, 27(2), (1968),723-731.
Paranjpe, Ajit , et al., “Atomic layer deposition of AlOx for thin film head gap applications”, Journal of the Electrochemical Society, 148(9), (Sep. 2001),465-471.
Pashley, R. , et al., “Flash Memories: the best of two worlds”, IEEE Spectrum, 26(12), (Dec. 1989),30-33.
Pollack, S. , et al., “Tunneling Through Gaseous Oxidized Films of Al2O3”, Transactions of the Metallurgical Society of AIME, 233, (1965),497-501.
Qi, Wen-Jie , et al., “MOSCAP and MOSFET characteristics using ZrO/sub 2/ gate dielectric deposited directly on Si”, International Electron Devices Meeting 1999, Technical Digest, (1999),145-148.
Robertson, J. , “Band offsets of wide-band-gap oxides and implications for future electronic devices”, Journal of Vacuum Science & Technology B (Microelectronics and Nanometer Structures), 18(3), (May-Jun. 2000),1785-1791.
Robertson, J. , et al., “Schottky Barrier height of Tantalum oxide, barium strontium titanate, lead titanate, and strontium bismuth tantalate”, Applied Physics Letters, 74(8), (Feb. 22, 1999),1168-1170.
Shi, Y. , “Tunneling Leakage Current in Ultrathin (<4 nm) Nitride/Oxide Stack Dielectrics”, IEEE Electron Device Letters, 19(10), (Oct. 1998),388-390.
Shi, Ying , et al., “Tunneling leakage current in ultrathin ( Shi, Y. , et al., “Tunneling Leakage Current in Ultrathin (less than 4nm) Nitride/Oxide Stack Dielectrics”, IEEE Electron Device Letters, 19(10), (Oct. 1998),pp. 388-390.
Simmons, J. , “Generalized Formula for the Electric Tunnel Effect between Similar Electrodes Separated by a Thin Insulating Film”, Journal of Applied Physics, 34(6), (1963),1793-1803.
Smith, Ryan C., “Chemical vapour deposition of the oxides of titanium, zirconium and hafnium for use as high-k materials in microelectronic devices. A carbon-free precursor for the synthesis of hafnium dioxide”, Advanced Materials for Optics and Electronics, 10(3-5), (May-Oct. 2000),105-106.
Swalin, R. , “Equilibrium between Phases of Variable Composition”, In: Thermodynamics of solids, New York, J. Wiley, 2nd Edition,(1972),165-180.
Sze, S. , “Physics of Semiconductor Devices, Second Edition”, John Wiley & Sons, New York, (1981),553-556.
Yan, J. , “Structural and electrical characterization of TiO/sub 2/ grown from titanium tetrakis-isopropoxide (TTIP) and TTIP/H/sub 2/O ambients”, Journal of Vacuum Science & Technology B (Microelectronics and Nanometer Structures), 14(3), (May-Jun. 1996),1706-1711.
Zhang, H. , “Atomic layer deposition of high dielectric constant nanolaminates”, Journal of The Electrochemical Society, 148(4), (Apr. 2001),F63-F66.
“U.S. Appl. No. 09/943,134 Final Office action mailed Jan. 8, 2003”, 13 pgs.
“U.S. Appl. No. 09/943,134 Notice of allowance mailed Apr. 7, 2005”, 4 pgs.
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“U.S. Appl. No. 09/945,395 Non-final office action mailed Nov. 6, 2002”, 13 pgs.
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“U.S. Appl. No. 09/945,498 Notice of allowance mailed Dec. 3, 2002”, 7 pgs.
“U.S. Appl. No. 09/945,498 Notice of allowance mailed Mar. 11, 2004”, 4 pgs.
“U.S. Appl. No. 09/945,498 Notice of allowance mailed May 15, 2003”, 6 pgs.
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“U.S. Appl. No. 09/945,500 Non-final office action mailed Dec. 24, 2002”, 5 pgs.
“U.S. Appl. No. 09/945,500 Notice of allowance mailed Mar. 29, 2005”, 4 pgs.
“U.S. Appl. No. 09/945,500 Notice of allowance mailed May 19, 2004”, 4 pgs.
“U.S. Appl. No. 09/945,500 Notice of allowance mailed Aug. 12, 2005”, 2 pgs.
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“U.S. Appl. No. 09/945,500 Response filed Mar. 24, 2003 to final office action mailed Dec. 24, 2002”, 17 pgs.
“U.S. Appl. No. 09/945,507 Non-final office action mailed Jun. 17, 2003”, 7 pgs.
“U.S. Appl. No. 09/945,507 Notice of allowance mailed Mar. 9, 2004”, 5 pgs.
“U.S. Appl. No. 09/945,507 Notice of allowance mailed Jun. 3, 2005”, 2 pgs.
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“U.S. Appl. No. 09/945,507 Notice of allowance mailed Nov. 18, 2004”, 7 pgs.
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“U.S. Appl. No. 09/945,507 Response filed Oct. 17, 2003 to final office action mailed Jun. 17, 2003”, 15 pgs.
“U.S. Appl. No. 09/945,512 Final office action mailed Oct. 13, 2005”, 6 pgs.
“U.S. Appl. No. 09/945,512 Non final office action mailed Jun. 30, 2005”, 8 pgs.
“U.S. Appl. No. 09/945,512 Non-final office action mailed Dec. 20, 2002”, 9 pgs.
“U.S. Appl. No. 09/945,512 Notice of allowance mailed Jan. 31, 2006”, 4 pgs.
“U.S. Appl. No. 09/945,512 Notice of allowance mailed Feb. 22, 2005”, 7 pgs.
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“U.S. Appl. No. 09/945,512 Response filed Jan. 13, 2006 to final office action mailed Jan. 28, 2006”, 28 pgs.
“U.S. Appl. No. 09/945,512 Response filed Mar. 20, 2003 to non-final office action mailed Dec. 20, 2003”, 30 pgs.
“U.S. Appl. No. 09/945,512 Response filed Sep. 29, 2005 to non-final office action mailed Jun. 30, 2005”, 10 pgs.
“U.S. Appl. No. 09/945,554 Final office action mailed Mar. 12, 2004”, 8 pgs.
“U.S. Appl. No. 09/945,554 Non-final office action mailed Oct. 22, 2003”, 7 pgs.
“U.S. Appl. No. 09/945,544 Non-final office action mailed Dec. 13, 2002”, 13 pgs.
“U.S. Appl. No. 09/945,554 Notice of allowance mailed May 2, 2003”, 8 pgs.
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“U.S. Appl. No. 09/945,554 Response filed Mar. 13, 2003 to final office action mailed Mar. 13, 2003”, 3 pgs.
“U.S. Appl. No. 09/945,554 Response filed May 12, 2004 to final office action mailed Mar. 12, 2004”, 21 pgs.
“U.S. Appl. No. 10/028,001 non-final office action mailed Oct. 12, 2005”, 12 pgs.
“U.S. Appl. No. 10/028,001 non-final office action mailed Nov. 2, 2004”, 5 pgs.
“U.S. Appl. No. 10/028,001 non-final office action mailed Feb. 14, 2003”, 12 pgs.
“U.S. Appl. No. 10/028,001 Notice of allowance mailed Nov. 19, 2003”, 4 pgs.
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“U.S. Appl. No. 10/028,001 Notice of allowance mailed Feb. 25, 2005”, 4 pgs.
“U.S. Appl. No. 10/028,001 Notice of allowance mailed Apr. 16, 2004”, 4 pgs.
“U.S. Appl. No. 10/028,001 Notice of allowance mailed Jun. 2, 2006”, 3 pgs.
“U.S. Appl. No. 10/028,001 Notice of allowance mailed Jun. 3, 2003”, 3 pgs.
“U.S. Appl. No. 10/028,001, Response filed Jan. 12, 2006 Non-Final Office Action mailed Oct. 12, 2005”, 15 pgs.
“U.S. Appl. No. 10/028,001, Response filed Feb. 2, 2005 Non-Final Office Action mailed Nov. 2, 2004”, 12 pgs.
“U.S. Appl. No. 10/028,001, Response filed May 14, 2003 Non-Final Office Action mailed Feb. 14, 2003”, 27 pgs.
“U.S. Appl. No. 10/081,818 Final office action mailed Oct. 5, 2005”, 13 pgs.
“U.S. Appl. No. 10/081,818 Non-final office action mailed Jan. 2, 2003”, 11 pgs.
“U.S. Appl. No. 10/081,818 Non-final office action mailed Mar. 24, 2006”, 14 pgs.
“U.S. Appl. No. 10/081,818 Non-final office action mailed Apr. 29, 2005”, 13 pgs.
“U.S. Appl. No. 10/081,818 Non-final office action mailed Oct. 15, 2004”, 6 pgs.
“U.S. Appl. No. 10/081,818 Notice of allowance mailed Feb. 13, 2004”, 4 pgs.
“U.S. Appl. No. 10/081,818 Notice of allowance mailed Feb. 22, 2005”, 4 pgs.
“U.S. Appl. No. 10/081,818 Notice of allowance mailed Mar. 8, 2007”, 3 pgs.
“U.S. Appl. No. 10/081,818 Notice of allowance mailed Sep. 21, 2006”, 2 pgs.
“U.S. Appl. No. 10/081,818 Notice of allowance mailed Sep. 26, 2003”, 5 pgs.
“U.S. Appl. No. 10/081,818 Response filed Jan. 14, 2005 to non final office action mailed Oct. 15, 2004”, 16 pgs.
“U.S. Appl. No. 10/081,818 Response filed Mar. 3, 2006 to final office action mailed Oct. 5, 2005”, 14 pgs.
“U.S. Appl. No. 10/081,818 Response filed Apr. 2, 2003 to non final office action mailed Jan. 2, 2003”, 12 pgs.
“U.S. Appl. No. 10/081,818 Response filed Jul. 29, 2005 to non final office action mailed Apr. 29, 2005”, 21 pgs.
“U.S. Appl. No. 10/081,818 Response filed Aug. 24, 2006 to non final office action mailed Mar. 24, 2006”, 16 pgs.
“U.S. Appl. No. 10/177,096 Non Final Office Action mailed Jun. 14, 2005”, 18 pgs.
“U.S. Appl. No. 10/177,096 Non-Final Office Action mailed Jun. 10, 2003”, 10 pgs.
“U.S. Appl. No. 10/177,096 Notice of Allowance mailed Apr. 6, 2004”, 7 pgs.
“U.S. Appl. No. 10/177,096 Notice of Allowance mailed May 18, 2006”, 7 pgs.
“U.S. Appl. No. 10/177,096 Notice of Allowance mailed Oct. 6, 2005”, 8 pgs.
“U.S. Appl. No. 10/177,096 Notice of allowance mailed Nov. 14, 2003”, 3 pgs.
“U.S. Appl. No. 10/177,096 Response filed Sep. 8, 2005 to non final office action mailed Jun. 14, 2005”, 34 pgs.
“U.S. Appl. No. 10/177,096 Response filed Oct. 10, 2003 to non final office action mailed Jun. 10, 2003”, 55 pgs.
“U.S. Appl. No. 10/781,035 Final office action mailed Oct. 5, 2005”, 16 pgs.
“U.S. Appl. No. 10/781,035 Non-final office action mailed Jun. 2, 2005”, 14 pgs.
“U.S. Appl. No. 10/781,035 Non-final office action mailed Jun. 22, 2004”, 4 pgs.
“U.S. Appl. No. 10/781,035 Notice of allowance mailed Jan. 30, 2006”, 5 pgs.
“U.S. Appl. No. 10/781,035 Notice of allowance mailed Oct. 28, 2004”, 5 pgs.
“U.S. Appl. No. 10/781,035 Notice of allowance mailed May 18, 2006”, 5 pgs.
“U.S. Appl. No. 10/781,035 Response filed Sep. 1, 2005 to non final office action mailed Jun. 2, 2005”, 26 pgs.
“U.S. Appl. No. 10/781,035 Response filed Sep. 22, 2004 to non final office action mailed Jun. 22, 2004”, 11 pgs.
“U.S. Appl. No. 10/781,035 Response filed Jan. 5, 2006 to final office action mailed Oct. 5, 2005”, 20 pgs.
“U.S. Appl. No. 10/783,695 Non-final office action mailed Jul. 1, 2005”, 8 pgs.
“U.S. Appl. No. 10/783,695 Notice of allowance mailed Aug. 22, 2006”, 5 pgs.
“U.S. Appl. No. 10/783,695 Notice of allowance mailed Dec. 20, 2005”, 4 pgs.
“U.S. Appl. No. 10/783,695 Response filed Oct. 3, 2005 to non final office action mailed Jul. 1, 2005”, 24 pgs.
“U.S. Appl. No. 10/788,810 Non-final office action mailed Aug. 12, 2004”, 15 pgs.
“U.S. Appl. No. 10/788,810 Notice of allowance mailed Jan. 9, 2006”, 9 pgs.
“U.S. Appl. No. 10/788,810 Notice of allowance mailed Mar. 22, 2005”, 7 pgs.
“U.S. Appl. No. 10/788,810 Notice of allowance mailed Jul. 28, 2005”, 9 pgs.
“U.S. Appl. No. 10/788,810 Response filed Dec. 13, 2004 to no-final office action mailed Dec. 13, 2004”, 22 pgs.
“U.S. Appl. No. 10/789,038 Notice of allowance mailed Oct. 7, 2005”, 11 pgs.
“U.S. Appl. No. 10/819,550 Non final office action mailed Sep. 21, 2004”, 18 pgs.
“U.S. Appl. No. 10/819,550 Notice of allowance mailed Jan. 28, 2005”, 7 pgs.
“U.S. Appl. No. 10/819,550 Response filed Dec. 21, 2004 to non-final office action mailed Sep. 21, 2004”, 27 pgs.
“U.S. Appl. No. 10/926,916, Response filed Apr. 26, 2006 Non-Final Office Action mailed Jan. 26, 2006”, 27 pgs.
“U.S. Appl. No. 10/929,916 non-final office action mailed Jan. 26, 2006”, 20 pgs.
“U.S. Appl. No. 10/929,916 non-final office action mailed Dec. 15, 2004”, 4 pgs.
“U.S. Appl. No. 10/929,916 Notice of allowance mailed Apr. 28, 2005”, 5 pgs.
“U.S. Appl. No. 10/929,916 Notice of allowance mailed Jun. 6, 2006”, 4 pgs.
“U.S. Appl. No. 10/929,916 Response filed Mar. 15, 2005 to non-final office action mailed Dec. 15, 2004”, 18 pgs.
“U.S. Appl. No. 10/929,986 Notice of Allowance mailed Jan. 4, 2005”, 7 pgs.
“U.S. Appl. No. 10/929,986 Notice of allowance mailed Mar. 8, 2007”, 6 pgs.
“U.S. Appl. No. 10/929,986 Notice of Allowance mailed Apr. 21, 2005”, 12 pgs.
“U.S. Appl. No. 10/929,986 Notice of allowance mailed May 4, 2006”, 5 pgs.
“U.S. Appl. No. 10/929,986 Notice of allowance mailed Sep. 21, 2006”, 7 pgs.
“U.S. Appl. No. 10/931,704 non-final office action mailed Apr. 19, 2007”, 5 pgs.
“U.S. Appl. No. 10/931,704, Response filed Aug. 20, 2007 to Non-Final Office Action mailed Apr. 19, 2007”, 10 pgs.
“U.S. Appl. No. 10/931,711 Final office action mailed Nov. 15, 2005”, 12 pgs.
“U.S. Appl. No. 10/931,711 Non-final office action mailed Jun. 28, 2005”, 24 pgs.
“U.S. Appl. No. 10/931,711 Notice of allowance mailed May 31, 2006”, 9 pgs.
“U.S. Appl. No. 10/931,711 Notice of allowance mailed Sep. 18, 2006”, 8 pgs.
“U.S. Appl. No. 10/931,711 Response filed Jan. 17, 2006 to final office action mailed Jan. 17, 2006”, 28 pgs.
“U.S. Appl. No. 10/931,711 Response filed Sep. 28, 2005 to non-final office action mailed Jun. 28, 2005”, 34 pgs.
“U.S. Appl. No. 11/212,190 Notice of allowance mailed Jan. 12, 2006”, 6 pgs.
“U.S. Appl. No. 11/062,543 Non final office action mailed Aug. 14, 2006”, 27 pgs.
“U.S. Appl. No. 11/062,543 Notice of Allowance mailed Jan. 26, 2007”, 17 pgs.
“U.S. Appl. No. 11/062,543 Notice of allowance mailed Jun. 27, 2007”, 20 pgs.
“U.S. Appl. No. 11/062,543 Response filed Nov. 3, 2006 to non final office action mailed Aug. 14, 2006”, 20 pgs.
“U.S. Appl. No. 11/063,825 Non-final office action mailed Jun. 1, 2007”, 15 pgs.
“U.S. Appl. No. 11/140,643, Final office action mailed Dec. 13, 2006”, 34 pgs.
“U.S. Appl. No. 11/140,643, Non-final office action mailed Mar. 9, 2006”, 30 pgs.
“U.S. Appl. No. 11/140,643, Non-final office action mailed Jun. 4, 2007”, 30 pgs.
“U.S. Appl. No. 11/140,643, Response filed Jun. 9, 2006 to non-final office action mailed Mar. 9, 2006”, 16 pgs.
“U.S. Appl. No. 11/202,460 Non final office action mailed Jan. 4, 2007 in”, 18 pgs.
“U.S. Appl. No. 11/202,460 Notice of allowance mailed May 17, 2007”, 6 pgs.
“U.S. Appl. No. 11/202,460 Response filed Mar. 23, 2007 to non-final office action mailed Jan. 4, 2007”, 17 pgs.
“U.S. Appl. No. 11/380,599 Non-final office action mailed Mar. 16, 2007”, 21 pgs.
“U.S. Appl. No. 11/380,599 Notice of Allowance Mailed Aug. 16, 2007”, NOAR,8 pgs.
“U.S. Appl. No. 11/380,599 Response filed Jul. 13, 2007 to non-final office action mailed Mar. 16, 2007”, 24 pgs.
“U.S. Appl. No. 11/471,007 Non-Final Office Action Mailed Aug. 16, 2007”, OARN,15 pgs.
“U.S. Appl. No. 11/471,008 Non Final Office Action Mailed Aug. 15, 2007”, OARN,17 pgs.
“U.S. Appl. No. 11/471,348, Non-Final Office Action mailed Aug. 23, 2007”, OARN,12 pgs.
“U.S. Appl. No. 09/943,134 Amendment Under 37 CFR 1.312 mailed Jun. 10, 2005”, 6 pgs.
“U.S. Appl. No. 09/943,134 Response filed Apr. 8, 2003 to Non Final Office Action mailed Jan. 8, 2003”, 15 pgs.
“U.S. Appl. No. 09/945,395 Amendment Under 37 CFR 1.312 mailed Feb. 10, 2004”, 15 pgs.
“U.S. Appl. No. 09/945,395 Amendment Under 37 CFR 1.312 mailed Apr. 17, 2003”, 4 pgs.
“U.S. Appl. No. 09/945,512 Amendment filed Feb. 11, 2004”, 23 pgs.
“U.S. Appl. No. 10/081,818, Response filed Jan. 14, 2005 Non-Final Office Action mailed Oct. 15, 2004”, 8 pgs.
“U.S. Appl. No. 10/081,818, Response filed Mar. 3, 2006 Final Office Action mailed Oct. 5, 2005”, 14 pgs.
“U.S. Appl. No. 10/783,695 Amendment Under 37 CFR 1.312 mailed Jan. 9, 2006”, 10 pgs.
“U.S. Appl. No. 10/789,038 Amendment Under 37 CFR 1.312 mailed Jan. 9, 2006”, 10 pgs.
“U.S. Appl. No. 10/819,550 Amendment Under 37 CFR 1.312 mailed Mar. 31, 2005”, 13 pgs.
“U.S. Appl. No. 10/931,540 Amendment Under 37 CFR 1.312 mailed May 12, 2005”, 17 pgs.
“U.S. Appl. No. 10/931,704, Notice of Allowance mailed Sep. 21, 2007”, NOAR,14 pgs.
“U.S. Appl. No. 11/063,825, Response filed Aug. 31, 2007 to Non-Final Office Action mailed Jun. 1, 2007”, 14 pgs.
“U.S. Appl. No. 11/140,643, Response filed Aug. 31, 2007 to Non-Final Office Action mailed Jun. 4, 2007”, 13 pgs.
Aarik, Jaan, “Atomic layer growth of epitaxial TiO2 thin films from TiCl4 and H2O on alpha -Al2 O3 substrates”, Journal of Crystal Growth, 242(1-2), (2002), 189-198.
Aarik, Jaan, “Influence of substrate temperature on atomic layer growth and properties of HfO2 thin films”, Thin Solid Films, 340(1-2), (1999), 110-116.
Aarik, Jaan, “Phase transformations in hafnium dioxide thin films grown by atomic layer deposition at high temperatures”, Applied Surface Science, 173(1-2), (Mar. 2001), 15-21.
Chen, F., “A study of mixtures of HfO2 and TiO2 as high-k gate dielectrics”, Microelectronic Engineering 72, (2004), 263.
Chen, F., et al., “Hafnium Titanate as a High-K Gate Insulator”, Electrochemical Society Proceedings, vol. 2004-01, (2004), 278-285.
Conley, J. F., “Atomic Layer Deposition of Hafnium Oxide Using Anhydrous Hafnium Nitrate”, Electrochemical and Solid-State Letters, 5(5), (May 2002), C57-C59.
Domagala, R. F., et al., “The Pseudobinary Ti-ZrO2”, J. Am. Ceramic Soc., vol. 56, Paper first presented in 1970, (1973), 584-587.
Forbes, “Hafnium Tantalum Oxynitride High-K Dielectric and Metal Gates”, U.S. Appl. No. 11/515,114, filed Aug. 31, 2005.
Kim, Byoung-Youp, et al., “Comparison study for TiN films deposited from different method: chemical vapor deposition and atomic layer deposition”, Mechanisms of Surface and Microstructure Evolution in Deposited Films and Film Structures Symposium (Materials Research Society Symposium Proceedings vol. 672), (2001), 7.8.1-7.8.6.
Kukli, Kaupo, “Comparison of hafnium oxide films grown by atomic layer deposition from iodide and chloride precursors”, Thin Solid Films, 416, (2002), 72-79.
Leskela, M, “ALD precursor chemistry: Evolution and future challenges”, Journal de Physique IV (Proceedings), 9(8), (Sep. 1999), 837-852.
Nalwa, H. S, “Handbook of Thin Film Materials”, Deposition and Processing of thin Films, vol. 1, San Diego : Academic Press, (2002), 114-119.
Robertson, John, “Band offsets of wide-band-gap oxides and implications for future electronic devices”, Journal of Vacuum Science & Technology B: Microelectronics and Nanometer Structures, 18(3), (May 2000), 1785-1791.
Ruh, Robert, et al., “Phase Relations and Thermal Expansion in the System HfO2-TiO2”, J. Am. Ceramic Soc., 59, (Nov.-Dec. 1976), 495-499.
Sneh, Ofer, “Thin film atomic layer deposition equipment for semiconductor processing”, Thin Solid Films, 402(1-2), (2002), 248-261.
Suntola, T., “Atomic Layer Epitaxy”, Handbook of Crystal Growth, 3; Thin Films of Epitaxy, Part B: Growth Mechanics and Dynamics, Amsterdam, (1994), 601-663.
Wilk, G. D., “High-K gate dielectrics: Current status and materials properties considerations”, Journal of Applied Physics, 89(10), (May 2001), 5243-5275.
Primary Examiner:
Ho, Tu-tu V.
Attorney, Agent or Firm:
Schwegman, Lundberg & Woessner, P.A.
Parent Case Data:

CROSS REFERENCE TO RELATED APPLICATIONS

This application is a continuation of U.S. patent application Ser. No. 10/081,818 filed Feb. 20, 2002, which is a Continuation-in-Part of U.S. patent application Ser. No. 09/943,134 filed on Aug. 30, 2001, now issued as U.S. Pat. No. 7,042,043, both of which are incorporated herein by reference in their entirety.

This application is related to the following commonly assigned U.S. patent applications: “DRAM Cells with Repressed Memory Metal Oxide Tunnel Insulators,” Ser. No. 09/945,395, now issued as U.S. Pat. No. 6,754,108; “Flash Memory with Low Tunnel Barrier Interpoly Insulators,” Ser. No. 09/945,507, now issued as U.S. Pat. No. 7,068,544; “Dynamic Electrically Alterable Programmable Memory with Insulating Metal Oxide Interpoly Insulators,” Ser. No. 09/945,498, now issued as U.S. Pat. No. 6,778,441; “Field Programmable Logic Arrays with Metal Oxide and/or Low Tunnel Barrier Intel-poly Insulators,” Ser. No. 09/945,512, now issued as U.S. Pat. No. 7,087,954; “SRAM Cells with Repressed Floating Gate Memory, Metal Oxide Tunnel Interpoly Insulators,” Ser. No. 09/945,554, now issued as U.S. Pat. No. 6,963,103; “Programmable Memory Address and Decode Devices with Low Tunnel Barrier Interpoly Insulators,” Ser. No. 09/945,500, now issued as U.S. Pat. No. 7,075,829; and “Programmable Array Logic or Memory with P-Channel Devices and Asymmetrical Tunnel Barriers,” Ser. No. 10/028,001, now issued as U.S. Pat. No. 7,132,711; each of which disclosure is herein incorporated by reference.

Claims:
What is claimed is:

1. A floating gate transistor, comprising: a first source/drain region and a second source/drain region separated by a channel; a horizontally oriented first gate formed adjacent a body region that includes the channel; a gate oxide separating the first gate from the channel; a second gate adjacent the first gate; and a graded, asymmetrical low tunnel barrier intergate insulator formed by multiple monolayer deposition separating the second gate from the first gate, the first gate including a polysilicon floating gate having a metal layer formed thereon in contact with the asymmetrical low tunnel barrier intergate insulator, and the second gate includes a polysilicon control gate having a metal layer formed thereon in contact with the asymmetrical low tunnel barrier intergate insulator, wherein the metal layer includes a metal layer that has a different work function than the metal layer formed on the floating gate and the metal layer is formed of the same material as the asymmetrical low tunnel barrier intergate insulator.

2. The floating gate transistor of claim 1, wherein the asymmetrical low tunnel barrier intergate insulator includes aluminum oxide (Al2O3), wherein the aluminum oxide has a number of small compositional ranges such that gradients can be formed by an applied electric field which produce different barrier heights at an interface with the first gate and the second gate.

3. The floating gate transistor of claim 1, wherein the asymmetrical low tunnel barrier intergate insulator includes an asymmetrical transition metal oxide.

4. The floating gate transistor of claim 3, wherein the asymmetrical transition metal oxide includes Ta2O5.

5. The floating gate transistor of claim 3, wherein the asymmetrical transition metal oxide includes TiO2.

6. The floating gate transistor of claim 3, wherein the asymmetrical transition metal oxide includes ZrO2.

7. The floating gate transistor of claim 3, wherein the asymmetrical transition metal oxide includes Nb2O5.

8. The floating gate transistor of claim 1, wherein the asymmetrical low tunnel barrier intergate insulator includes an asymmetrical Perovskite oxide tunnel barrier.

9. The floating gate transistor of claim 8, wherein the asymmetrical Peroyskite oxide tunnel barrier is selected from the group consisting of SrBi2Ta2O3, SrTiO3, PbTiO3, and PbZrO3.

10. The floating gate transistor of claim 1, wherein the floating gate transistor includes an n-channel type floating gate transistor.

11. The floating gate transistor of claim 1, wherein the graded asymmetrical low tunnel barrier intergate insulator includes aluminum oxide having a number of small compositional ranges.

12. The floating gate transistor of claim 1, wherein the asymmetrical low tunnel barrier intergate insulator is continuously graded.

13. A vertical, non volatile memory cell, comprising: a first source/drain region; a body region including a channel region formed on the first source/drain region; a second source/drain region formed on the body region; a floating gate adjacent the channel region and separated therefrom by a gate oxide; a control gate adjacent the floating gate; and a graded, asymmetrical low tunnel barrier intergate insulator separating the floating gate and the control gate, the intergate insulator having a tunneling barrier of less than 2.0 eV and having a number of small compositional ranges such that gradients can be formed which produce different barrier heights at an interface with the floating gate and control gate.

14. The vertical, non volatile memory cell of claim 13, wherein the asymmetrical low tunnel barrier intergate insulator includes an insulator selected from the group consisting of Al2O3, Ta2O5, TiO2, ZrO2, Nb2O5, SrBi2Ta2O3, SrTiO3, PbTiO3, and PbZrO3.