Li, Jiutao (Boise, ID, US)
Mcteer, Allen (Meridian, ID, US)
Herdt, Gregory (Boise, ID, US)
Doan, Trung T. (Boise, ID, US)

Plaque It!

11/710517

11/04/2008

02/26/2007

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Micron Technology, Inc. (Boise, ID, US)

257/762

257/616

H01L29/20

257/762, 257/616

3271591	Symmetrical current controlling device	September, 1966	Ovshinsky
3622319	NONREFLECTING PHOTOMASKS AND METHODS OF MAKING SAME	November, 1971	Sharp
3743847	AMORPHOUS SILICON FILM AS A UV FILTER	July, 1973	Boland
3961314	Structure and method for producing an image	June, 1976	Klose et al.
3966317	Dry process production of archival microform records from hard copy	June, 1976	Wacks et al.
3983542	Method and apparatus for recording information	September, 1976	Ovshinsky
3988720	Recording and retrieving information in an amorphous memory material using a catalytic material	October, 1976	Ovshinsky
4177474	High temperature amorphous semiconductor member and method of making the same	December, 1979	Ovshinsky
4267261	Method for full format imaging	May, 1981	Hallman et al.
4269935	Process of doping silver image in chalcogenide layer	May, 1981	Masters et al.
4312938	Method for making a broadband reflective laser recording and data storage medium with absorptive underlayer	January, 1982	Drexler et al.
4316946	Surface sensitized chalcogenide product and process for making and using the same	February, 1982	Masters et al.
4320191	Pattern-forming process	March, 1982	Yoshikawa et al.
4405710	Ion beam exposure of (g-Ge.sub.x -Se.sub.1-x) inorganic resists	September, 1983	Balasubramanyam et al.
4419421	Ion conductor material	December, 1983	Wichelhaus et al.
4499557	Programmable cell for use in programmable electronic arrays	February, 1985	Holmberg et al.
4597162	Method for making, parallel preprogramming or field programming of electronic matrix arrays	July, 1986	Johnson et al.
4608296	Superconducting films and devices exhibiting AC to DC conversion	August, 1986	Keem et al.
4637895	Gas mixtures for the vapor deposition of semiconductor material	January, 1987	Ovshinsky et al.
4646266	Programmable semiconductor structures and methods for using the same	February, 1987	Ovshinsky et al.
4664939	Vertical semiconductor processor	May, 1987	Ovshinsky
4668968	Integrated circuit compatible thin film field effect transistor and method of making same	May, 1987	Ovshinsky et al.
4670763	Thin film field effect transistor	June, 1987	Ovshinsky et al.
4671618	Liquid crystalline-plastic material having submillisecond switch times and extended memory	June, 1987	Wu et al.
4673957	Integrated circuit compatible thin film field effect transistor and method of making same	June, 1987	Ovshinsky et al.
4678679	Continuous deposition of activated process gases	July, 1987	Ovshinsky
4696758	Gas mixtures for the vapor deposition of semiconductor material	September, 1987	Ovshinsky et al.
4698234	Vapor deposition of semiconductor material	October, 1987	Ovshinsky et al.
4710899	Data storage medium incorporating a transition metal for increased switching speed	December, 1987	Young et al.
4728406	Method for plasma - coating a semiconductor body	March, 1988	Banerjee et al.
4737379	Plasma deposited coatings, and low temperature plasma method of making same	April, 1988	Hudgens et al.
4766471	Thin film electro-optical devices	August, 1988	Ovshinsky et al.
4769338	Thin film field effect transistor and method of making same	September, 1988	Ovshinsky et al.
4775425	P and n-type microcrystalline semiconductor alloy material including band gap widening elements, devices utilizing same	October, 1988	Guha et al.
4788594	Solid state electronic camera including thin film matrix of photosensors	November, 1988	Ovshinsky et al.
4795657	Method of fabricating a programmable array	January, 1989	Formigoni et al.
4800526	Memory element for information storage and retrieval system and associated process	January, 1989	Lewis
4809044	Thin film overvoltage protection devices	February, 1989	Pryor et al.
4818717	Method for making electronic matrix arrays	April, 1989	Johnson et al.
4843443	Thin film field effect transistor and method of making same	June, 1989	Ovshinsky et al.
4845533	Thin film electrical devices with amorphous carbon electrodes and method of making same	July, 1989	Pryor et al.
4847674	High speed interconnect system with refractory non-dogbone contacts and an active electromigration suppression mechanism	July, 1989	Sliwa et al.
4853785	Electronic camera including electronic signal storage cartridge	August, 1989	Ovshinsky et al.
4891330	Method of fabricating n-type and p-type microcrystalline semiconductor alloy material including band gap widening elements	January, 1990	Guha et al.
5128099	Congruent state changeable optical memory material and device	July, 1992	Strand et al.
5159661	Vertically interconnected parallel distributed processor	October, 1992	Ovshinsky et al.
5166758	Electrically erasable phase change memory	November, 1992	Ovshinsky et al.
5177567	Thin-film structure for chalcogenide electrical switching devices and process therefor	January, 1993	Klersy et al.
5219788	Bilayer metallization cap for photolithography	June, 1993	Abernathey et al.
5238862	Method of forming a stacked capacitor with striated electrode	August, 1993	Blalock et al.
5272359	Reversible non-volatile switch based on a TCNQ charge transfer complex	December, 1993	Nagasubramanian et al.
5296716	Electrically erasable, directly overwritable, multibit single cell memory elements and arrays fabricated therefrom	March, 1994	Ovshinsky et al.
5314772	High resolution, multi-layer resist for microlithography and method therefor	May, 1994	Kozicki
5315131	Electrically reprogrammable nonvolatile memory device	May, 1994	Kishimoto et al.
5335219	Homogeneous composition of microcrystalline semiconductor material, semiconductor devices and directly overwritable memory elements fabricated therefrom, and arrays fabricated from the memory elements	August, 1994	Ovshinsky et al.
5341328	Electrically erasable memory elements having reduced switching current requirements and increased write/erase cycle life	August, 1994	Ovshinsky et al.
5350484	Method for the anisotropic etching of metal films in the fabrication of interconnects	September, 1994	Gardner et al.
5359205	Electrically erasable memory elements characterized by reduced current and improved thermal stability	October, 1994	Ovshinsky
5360981	Amorphous silicon memory	November, 1994	Owen et al.
5406509	Electrically erasable, directly overwritable, multibit single cell memory elements and arrays fabricated therefrom	April, 1995	Ovshinsky et al.
5414271	Electrically erasable memory elements having improved set resistance stability	May, 1995	Ovshinsky et al.
5500532	Personal electronic dosimeter	March, 1996	Kozicki et al.
5512328	Method for forming a pattern and forming a thin film used in pattern formation	April, 1996	Yoshimura et al.
5512773	Switching element with memory provided with Schottky tunnelling barrier	April, 1996	Wolf et al.
5534711	Electrically erasable, directly overwritable, multibit single cell memory elements and arrays fabricated therefrom	July, 1996	Ovshinsky et al.
5534712	Electrically erasable memory elements characterized by reduced current and improved thermal stability	July, 1996	Ovshinsky et al.
5536947	Electrically erasable, directly overwritable, multibit single cell memory element and arrays fabricated therefrom	July, 1996	Klersy et al.
5543737	Logical operation circuit employing two-terminal chalcogenide switches	August, 1996	Ovshinsky
5591501	Optical recording medium having a plurality of discrete phase change data recording points	January, 1997	Ovshinsky et al.
5596522	Homogeneous compositions of microcrystalline semiconductor material, semiconductor devices and directly overwritable memory elements fabricated therefrom, and arrays fabricated from the memory elements	January, 1997	Ovshinsky et al.
5687112	Multibit single cell memory element having tapered contact	November, 1997	Ovshinsky
5694054	Integrated drivers for flat panel displays employing chalcogenide logic elements	December, 1997	Ovshinsky et al.
5714768	Second-layer phase change memory array on top of a logic device	February, 1998	Ovshinsky et al.
5726083	Process of fabricating dynamic random access memory device having storage capacitor low in contact resistance and small in leakage current through tantalum oxide film	March, 1998	Takaishi
5751012	Polysilicon pillar diode for use in a non-volatile memory cell	May, 1998	Wolstenholme et al.
5761115	Programmable metallization cell structure and method of making same	June, 1998	Kozicki et al.
5789277	Method of making chalogenide memory device	August, 1998	Zahorik et al.
5814527	Method of making small pores defined by a disposable internal spacer for use in chalcogenide memories	September, 1998	Wolstenholme et al.
5818749	Integrated circuit memory device	October, 1998	Harshfield
5825046	Composite memory material comprising a mixture of phase-change memory material and dielectric material	October, 1998	Czubatyj et al.
5841150	Stack/trench diode for use with a muti-state material in a non-volatile memory cell	November, 1998	Gonzalez et al.
5846889	Infrared transparent selenide glasses	December, 1998	Harbison et al.
5851882	ZPROM manufacture and design and methods for forming thin structures using spacers as an etching mask	December, 1998	Harshfield
5869843	Memory array having a multi-state element and method for forming such array or cells thereof	February, 1999	Harshfield
5896312	Programmable metallization cell structure and method of making same	April, 1999	Kozicki et al.
5912839	Universal memory element and method of programming same	June, 1999	Ovshinsky et al.
5914893	Programmable metallization cell structure and method of making same	June, 1999	Kozicki et al.
5920788	Chalcogenide memory cell with a plurality of chalcogenide electrodes	July, 1999	Reinberg
5933365	Memory element with energy control mechanism	August, 1999	Klersy et al.
5998066	Gray scale mask and depth pattern transfer technique using inorganic chalcogenide glass	December, 1999	Block et al.
6011757	Optical recording media having increased erasability	January, 2000	Ovshinsky
6031287	Contact structure and memory element incorporating the same	February, 2000	Harshfield
6072716	Memory structures and methods of making same	June, 2000	Jacobson et al.
6077729	Memory array having a multi-state element and method for forming such array or cellis thereof	June, 2000	Harshfield
6084796	Programmable metallization cell structure and method of making same	July, 2000	Kozicki et al.
6087674	Memory element with memory material comprising phase-change material and dielectric material	July, 2000	Ovshinsky et al.
6117720	Method of making an integrated circuit electrode having a reduced contact area	September, 2000	Harshfield
6141241	Universal memory element with systems employing same and apparatus and method for reading, writing and programming same	October, 2000	Ovshinsky et al.
6143604	Method for fabricating small-size two-step contacts for word-line strapping on dynamic random access memory (DRAM)	November, 2000	Chiang et al.
6177338	Two step barrier process	January, 2001	Liaw et al.
6236059	Memory cell incorporating a chalcogenide element and method of making same	May, 2001	Wolsteinholme et al.
RE37259	Multibit single cell memory element having tapered contact	July, 2001	Ovshinsky
6297170	Sacrificial multilayer anti-reflective coating for mos gate formation	October, 2001	Gabriel et al.
6300684	Method for fabricating an array of ultra-small pores for chalcogenide memory cells	October, 2001	Gonzalez et al.
6316784	Method of making chalcogenide memory device	November, 2001	Zahorik et al.
6329606	Grid array assembly of circuit boards with singulation grooves	December, 2001	Freyman et al.
6339544	Method to enhance performance of thermal resistor device	January, 2002	Chiang et al.
6348365	PCRAM cell manufacturing	February, 2002	Moore et al.
6350679	Methods of providing an interlevel dielectric layer intermediate different elevation conductive metal layers in the fabrication of integrated circuitry	February, 2002	McDaniel et al.
6376284	Method of fabricating a memory device	April, 2002	Gonzalez et al.
6388324	Self-repairing interconnections for electrical circuits	May, 2002	Kozicki et al.
6391688	Method for fabricating an array of ultra-small pores for chalcogenide memory cells	May, 2002	Gonzalez et al.
6404665	Compositionally modified resistive electrode	June, 2002	Lowery et al.
6414376	Method and apparatus for reducing isolation stress in integrated circuits	July, 2002	Thakur et al.
6418049	Programmable sub-surface aggregating metallization structure and method of making same	July, 2002	Kozicki et al.
6420725	Method and apparatus for forming an integrated circuit electrode having a reduced contact area	July, 2002	Harshfield
6423628	Method of forming integrated circuit structure having low dielectric constant material and having silicon oxynitride caps over closely spaced apart metal lines	July, 2002	Li et al.
6429064	Reduced contact area of sidewall conductor	August, 2002	Wicker
6437383	Dual trench isolation for a phase-change memory cell and method of making same	August, 2002	Xu
6440837	Method of forming a contact structure in a semiconductor device	August, 2002	Harshfield
6462984	Biasing scheme of floating unselected wordlines and bitlines of a diode-based memory array	October, 2002	Xu et al.
6469364	Programmable interconnection system for electrical circuits	October, 2002	Kozicki
6473332	Electrically variable multi-state resistance computing	October, 2002	Ignatiev et al.
6480438	Providing equal cell programming conditions across a large and high density array of phase-change memory cells	November, 2002	Park
6487106	Programmable microelectronic devices and method of forming and programming same	November, 2002	Kozicki
6487113	Programming a phase-change memory with slow quench time	November, 2002	Park et al.
6501111	Three-dimensional (3D) programmable device	December, 2002	Lowery
6507061	Multiple layer phase-change memory	January, 2003	Hudgens et al.
6511862	Modified contact for programmable devices	January, 2003	Hudgens et al.
6511867	Utilizing atomic layer deposition for programmable device	January, 2003	Lowery et al.
6512241	Phase change material memory device	January, 2003	Lai
6514805	Trench sidewall profile for device isolation	February, 2003	Xu et al.
6531373	Method of forming a phase-change memory cell using silicon on insulator low electrode in charcogenide elements	March, 2003	Gill et al.
6534781	Phase-change memory bipolar array utilizing a single shallow trench isolation for creating an individual active area region for two memory array elements and one bipolar base contact	March, 2003	Dennison
6545287	Using selective deposition to form phase-change memory cells	April, 2003	Chiang
6545907	Technique and apparatus for performing write operations to a phase change material memory device	April, 2003	Lowery et al.
6555860	Compositionally modified resistive electrode	April, 2003	Lowery et al.
6563164	Compositionally modified resistive electrode	May, 2003	Lowery et al.
6566700	Carbon-containing interfacial layer for phase-change memory	May, 2003	Xu
6567293	Single level metal memory cell using chalcogenide cladding	May, 2003	Lowery et al.
6569705	Metal structure for a phase-change memory device	May, 2003	Chiang et al.
6570784	Programming a phase-change material memory	May, 2003	Lowery
6576921	Isolating phase change material memory cells	June, 2003	Lowery
6586761	Phase change material memory device	July, 2003	Lowery
6589714	Method for making programmable resistance memory element using silylated photoresist	July, 2003	Maimon et al.
6590807	Method for reading a structural phase-change memory	July, 2003	Lowery
6593176	METHOD FOR FORMING PHASE-CHANGE MEMORY BIPOLAR ARRAY UTILIZING A SINGLE SHALLOW TRENCH ISOLATION FOR CREATING AN INDIVIDUAL ACTIVE AREA REGION FOR TWO MEMORY ARRAY ELEMENTS AND ONE BIPOLAR BASE CONTACT	July, 2003	Dennison
6597009	Reduced contact area of sidewall conductor	July, 2003	Wicker
6605527	Reduced area intersection between electrode and programming element	August, 2003	Dennison et al.
6613604	Method for making small pore for use in programmable resistance memory element	September, 2003	Maimon et al.
6621095	Method to enhance performance of thermal resistor device	September, 2003	Chiang et al.
6625054	Method and apparatus to program a phase change memory	September, 2003	Lowery et al.
6642102	Barrier material encapsulation of programmable material	November, 2003	Xu
6646297	Lower electrode isolation in a double-wide trench	November, 2003	Dennison
6649928	Method to selectively remove one side of a conductive bottom electrode of a phase-change memory cell and structure obtained thereby	November, 2003	Dennison
6667900	Method and apparatus to operate a memory cell	December, 2003	Lowery et al.
6671710	Methods of computing with digital multistate phase change materials	December, 2003	Ovshinsky et al.
6673648	Isolating phase change material memory cells	January, 2004	Lowrey
6673700	Reduced area intersection between electrode and programming element	January, 2004	Dennison et al.
6674115	Multiple layer phrase-change memory	January, 2004	Hudgens et al.
6687153	Programming a phase-change material memory	February, 2004	Lowery
6687427	Optic switch	February, 2004	Ramalingam et al.
6690026	Method of fabricating a three-dimensional array of active media	February, 2004	Peterson
6696355	Method to selectively increase the top resistance of the lower programming electrode in a phase-change memory	February, 2004	Dennison
6707712	Method for reading a structural phase-change memory	March, 2004	Lowery
6714954	Methods of factoring and modular arithmetic	March, 2004	Ovshinsky et al.
20020000666	SELF-REPAIRING INTERCONNECTIONS FOR ELECTRICAL CIRCUITS	January, 2002	Kozicki et al.
20020072188	Non-volatile resistance variable devices and method of forming same, analog memory devices and method of forming same, programmable memory cell and method of forming same, and method of structurally changing a non-volatile device	June, 2002	Gilton
20020106849	Method of forming non-volatile resistance variable devices, method of precluding diffusion of a metal into adjacent chalcogenide material, and non-volatile resistance variable devices	August, 2002	Moore
20020123169	Methods of forming non-volatile resistance variable devices, and non-volatile resistance variable devices	September, 2002	Moore et al.
20020123170	PCRAM cell manufacturing	September, 2002	Moore et al.
20020123248	METHODS OF METAL DOPING A CHALCOGENIDE MATERIAL	September, 2002	Moore et al.
20020127886	Method to manufacture a buried electrode PCRAM cell	September, 2002	Moore et al.
20020132417	Agglomeration elimination for metal sputter deposition of chalcogenides	September, 2002	Li
20020160551	Memory elements and methods for making same	October, 2002	Harshfield
20020163828	Memory device with a self-assembled polymer film and method of making the same	November, 2002	Krieger et al.
20020168820	Microelectronic programmable device and methods of forming and programming the same	November, 2002	Kozicki
20020168852	PCRAM memory cell and method of making same	November, 2002	Kozicki
20020190289	PCRAM memory cell and method of making same	December, 2002	Harshfield et al.
20020190350	Programmable sub-surface aggregating metallization structure and method of making same	December, 2002	Kozicki et al.
20030001229	Chalcogenide comprising device	January, 2003	Moore et al.
20030027416	METHOD OF FORMING INTEGRATED CIRCUITRY, METHOD OF FORMING MEMORY CIRCUITRY, AND METHOD OF FORMING RANDOM ACCESS MEMORY CIRCUITRY	February, 2003	Moore
20030032254	Resistance variable device, analog memory device, and programmable memory cell	February, 2003	Gilton
20030035314	Programmable microelectronic devices and methods of forming and programming same	February, 2003	Kozicki
20030035315	Microelectronic device, structure, and system, including a memory structure having a variable programmable property and method of forming the same	February, 2003	Kozicki
20030038301	Apparatus and method for dual cell common electrode PCRAM memory device	February, 2003	Moore
20030043631	Method of retaining memory state in a programmable conductor RAM	March, 2003	Gilton et al.
20030045049	Method of forming chalcogenide comprising devices	March, 2003	Campbell et al.
20030045054	Method of forming non-volatile resistance variable devices, method of forming a programmable memory cell of memory circuitry, and a non-volatile resistance variable device	March, 2003	Campbell et al.
20030047765	Stoichiometry for chalcogenide glasses useful for memory devices and method of formation	March, 2003	Campbell
20030047772	Agglomeration elimination for metal sputter deposition of chalcogenides	March, 2003	Li
20030047773	Agglomeration elimination for metal sputter deposition of chalcogenides	March, 2003	Li
20030048519	Microelectronic photonic structure and device and method of forming the same	March, 2003	Kozicki
20030048744	Increased data storage in optical data storage and retrieval systems using blue lasers and/or plasmon lenses	March, 2003	Ovshinsky et al.
20030049912	METHOD OF FORMING CHALCOGENIDE COMPRSING DEVICES AND METHOD OF FORMING A PROGRAMMABLE MEMORY CELL OF MEMORY CIRCUITRY	March, 2003	Campbell et al.
20030068861	Integrated circuit device and fabrication using metal-doped chalcogenide materials	April, 2003	Li et al.
20030068862	Integrated circuit device and fabrication using metal-doped chalcogenide materials	April, 2003	Li et al.
20030095426	Complementary bit PCRAM sense amplifier and method of operation	May, 2003	Hush et al.
20030096497	Electrode structure for use in an integrated circuit	May, 2003	Moore et al.
20030107105	Programmable chip-to-substrate interconnect structure and device and method of forming same	June, 2003	Kozicki
20030117831	Programmable conductor random access memory and a method for writing thereto	June, 2003	Hush
20030128612	PCRAM rewrite prevention	July, 2003	Moore et al.
20030137869	Programmable microelectronic device, structure, and system and method of forming the same	July, 2003	Kozicki
20030143782	METHODS OF FORMING GERMANIUM SELENIDE COMPRISING DEVICES AND METHODS OF FORMING SILVER SELENIDE COMPRISING STRUCTURES	July, 2003	Gilton et al.
20030155589	Silver-selenide/chalcogenide glass stack for resistance variable memory	August, 2003	Campbell et al.
20030155606	Method to alter chalcogenide glass for improved switching characteristics	August, 2003	Campbell et al.
20030156447	Programming circuit for a programmable microelectronic device, system including the circuit, and method of forming the same	August, 2003	Kozicki
20030156463	Programmable conductor random access memory and method for sensing same	August, 2003	Casper et al.
20030209728	Microelectronic programmable device and methods of forming and programming the same	November, 2003	Kozicki et al.
20030209971	Programmable structure, an array including the structure, and methods of forming the same	November, 2003	Kozicki et al.
20030210564	Tunable cantilever apparatus and method for making same	November, 2003	Kozicki et al.
20030212724	METHODS OF COMPUTING WITH DIGITAL MULTISTATE PHASE CHANGE MATERIALS	November, 2003	Ovshinsky et al.
20030212725	Methods of factoring and modular arithmetic	November, 2003	Ovshinsky et al.
20040035401	Hydrogen powered scooter	February, 2004	Ramachandran et al.

JP56126916	October, 1981
WO/1997/048032	December, 1997			PROGRAMMABLE METALLIZATION CELL AND METHOD OF MAKING
WO/1999/028914	June, 1999			PROGRAMMABLE SUB-SURFACE AGGREGATING METALLIZATION STRUCTURE AND METHOD OF MAKING SAME
WO/2000/048196	August, 2000			PROGRAMMABLE MICROELECTRONIC DEVICES AND METHODS OF FORMING AND PROGRAMMING SAME
WO/2002/021542	March, 2002			MICROELECTRONIC PROGRAMMABLE DEVICE AND METHODS OF FORMING AND PROGRAMMING THE SAME

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Menz, Douglas M.

Dickstein Shapiro LLP

RELATED APPLICATION

This application is a divisional of U.S. patent application Ser. No. 10/878,060, filed Jun. 29, 2004, now U.S. Pat. No. 7,202,104 which is a divisional of U.S. patent application Ser. No. 10/164,429, filed Jun. 6, 2002, now U.S. Pat. No. 6,890,790 the entirety of each is hereby incorporated by reference. This application is also related to the disclosure of U.S. application Ser. No. 10/164,646, now U.S. Pat. No. 6,825,135 the entirety of which is hereby incorporated by reference.

We claim:

1. A nonvolatile memory cell comprising: a first electrode coupled to a first conductor; a second electrode coupled to a second conductor, where the first conductor and the second conductor provide access to the memory cell; and a memory cell body disposed between the first electrode and the second electrode, where the memory cell body includes a layer of a chalcogenide glass doped uniformly over depth with a metal.

2. The memory cell as defined in claim 1, wherein the metal comprises silver (Ag).

3. The memory cell as defined in claim 1, wherein the metal is selected from the group consisting of copper (Cu) and zinc (Zn).

4. The memory cell as defined in claim 1, wherein the chalcogenide glass comprises germanium selenide (Ge_xSe_1-x).

5. The memory cell as defined in claim 1, wherein x is selected such that the layer of germanium selenide (Ge_xSe_1-x) doped with the metal is amorphous.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention generally relates to memory technology. In particular, present invention relates to the fabrication of metal-doped chalcogenides.

2. Description of the Related Art

Computers and other digital systems use memory to store programs and data. A common form of memory is random access memory (RAM). Many memory devices, such as dynamic random access memory (DRAM) devices and static random access memory (SRAM) devices are volatile memories. A volatile memory loses its data when power is removed. In addition, certain volatile memories such as DRAM devices require period refresh cycles to retain their data even when power is continuously supplied.

In contrast to the potential loss of data encountered in volatile memory devices, nonvolatile memory devices retain data for long periods of time when power is removed. Examples of nonvolatile memory devices include read only memory (ROM), programmable read only memory (PROM), erasable programmable read only memory (EPROM), electrically erasable programmable read only memory (EEPROM), and the like.

U.S. Pat. No. 6,084,796 to Kozicki, et al., entitled “Programmable metallization cell structure and method of making same,” discloses another type of non-volatile memory device known as a programmable conductor memory cell or a programmable metallization cell (PMC). U.S. Pat. No. 6,084,796 is herein incorporated by reference in its entirety. Such memory cells can be integrated into a memory device, which has been referred to as a programmable conductor random access memory (PCRAM). A chalcogenide glass element is doped with metal, preferably silver (Ag). Application of an electric field with a first polarity causes a conductive pathway to grow along the sidewalls or in the sidewalls of the glass element, whereas an electric field of the opposite polarity dissolves the conductive pathway back into the glass element. If the conductive pathway extends between electrodes at opposite ends of the glass element, the resulting short or relatively low resistance can represent a logic state, e.g., a “1” state for the memory cell, whereas the unshorted, relatively high resistance state can represent another logic state, e.g., a “0” state. Additional applications for a programmable metallization cell include use as a variable programmable resistance and a variable programmable capacitance.

One conventional technique for producing the programmable conductor memory cell applies silver (Ag) photodoping to a chalcogenide glass such as germanium selenide (Ge ₃ Se ₇ ). The silver (Ag) photodoping process deposits silver (Ag) over germanium selenide (Ge ₃ Se ₇ ) and exposes the underlying substrate assembly to a relatively intense source of ultraviolet (UV) radiation for an extended period of time, such as 15 minutes. Disadvantageously, the photodoping process is relatively time-consuming and can slow semiconductor fabrication rates. The photodoping process can decrease the overall process rate especially when it is repetitively applied, such as in the fabrication of a multiple layer stack. Further disadvantageously, the extended exposure to intense UV radiation can induce the glass to convert from an amorphous material to a crystallized material, which thereby results in reduced yields.

Another disadvantage to producing memory cells with silver (Ag) photodoping of glasses is that relatively precise control of the amount of silver (Ag) that is photodiffused into the glass is necessary. A sufficient amount of silver (Ag) must be incorporated into the glass backbone and yet, the glass must not crystallize. If too much silver (Ag) is photodiffused into the glass, the glass crystallizes. If too little silver (Ag) were to be photodiffused into the glass, the memory cell would not switch properly.

Another disadvantage to the photodoping process is that the ultraviolet light is attenuated by the silver film as the ultraviolet light penetrates through the silver film. Such attenuation varies exponentially with the thickness of the film. In one example, with 300 nanometers (nm) wavelength ultraviolet radiation, the intensity of the ultraviolet radiation decreases to only about 10% of its initial intensity after penetrating through 650 angstroms (Å) of silver film. This attenuation renders photodoping to be impractical with relatively thick films, and requires relatively precise control of the thicknesses of the silver (Ag) and chalcogenide glass films. In order to form a thick film with a UV photodoping process, the UV photodoping process is disadvantageously applied repetitively to relatively thin films of silver (Ag). In addition, the varying attenuation of the ultraviolet light continues as the silver (Ag) dopes the chalcogenide glass. Further disadvantageously, this attenuation in intensity of the ultraviolet light as the ultraviolet light penetrates material results in a non-uniform depth profile of the doped silver (Ag) in the chalcogenide glass.

SUMMARY OF THE INVENTION

Embodiments of the present invention include systems and methods that overcome the disadvantages of the prior art. The systems and methods described herein allow a chalcogenide glass, such as germanium selenide (Ge _x Se _1-x ), to be doped with a metal such as silver (Ag), copper (Cu), and zinc (Zn), without utilizing an ultraviolet (UV) photodoping step to dope the chalcogenide glass with the metal. Other examples of chalcogenide glasses that can be used include germanium sulfide (Ge _x S _1-x ) and arsenic selenide (As _x Se _1-x ). Advantageously, embodiments of the invention co-sputter the metal and the chalcogenide glass and allow for relatively precise and efficient control of a constituent ratio between the doping metal and the chalcogenide glass. Further advantageously, the systems and methods enable the doping of the chalcogenide glass with a relatively high degree of depth-profile uniformity. Also, the systems and methods allow a metal concentration to be varied in a controlled manner along the thin film depth.

One embodiment according to the present invention is a nonvolatile memory cell including a first electrode, a second electrode, and a memory cell body disposed between the first electrode and the second electrode. The memory cell body includes a layer of germanium selenide (Ge _x Se _1-x ) that is uniformly doped over depth with a metal such as silver (Ag), copper (Cu), or zinc (Zn).

Another embodiment according to the present invention is a deposition system adapted to fabricate a nonvolatile memory cell body in a substrate assembly. The deposition system includes a deposition chamber, a first target, and a second target. The deposition chamber is adapted to hold the substrate assembly. The deposition system is further configured to sputter metal from the first target and to sputter germanium selenide (Ge _x Se _1-x ) from the second target at the same time to co-deposit the metal and the germanium selenide (Ge _x Se _1-x ). In one arrangement, the deposition system sputters silver (Ag) from the first target. In another arrangement, the deposition system sputters copper (Cu) or zinc (Zn) from the first target. The deposition system can further include a control configured to control the deposition rate of the metal and the deposition rate of the germanium selenide such that the nonvolatile memory cell body is deposited at a selected ratio between the metal and the germanium selenide in the cell body.

Another embodiment according to the present invention is a process of fabricating a nonvolatile memory structure in a substrate assembly. The process includes forming a bottom electrode, co-sputtering metal and germanium selenide (Ge _x Se _1-x ), and forming a top electrode. In other embodiments, a metal selenide and germanium; selenium and a mixture of a metal and germanium; or a metal, germanium, and selenium are co-sputtered.

Another embodiment according to the present invention is a process of forming a layer in a substrate assembly. The layer is capable of supporting the growth conductive pathways in the presence of an electric field. The process includes providing elemental silver (Ag) in a first sputtering target, providing germanium selenide (Ge _x Se _1-x ) in a second sputtering target, selecting a first sputtering rate for silver (Ag), selecting a second sputtering rate for germanium selenide (Ge _x Se _1-x ), sputtering the silver (Ag), and sputtering the germanium selenide (Ge _x Se _1-x ) at the same time as sputtering the silver to produce the layer.

Advantageously, the co-sputter deposition of silver (Ag) and germanium selenide (Ge _x Se _1-x ) allows the silver (Ag) to dope the sputtered germanium selenide (Ge _x Se _1-x ) in the layer with a relatively uniform depth profile. In one arrangement, the first sputtering rate is determined by selecting a first sputtering power for silver (Ag), and the second sputtering rate is determined by selecting a second sputtering power for germanium selenide (Ge _x Se _1-x ). The process preferably further includes selecting a ratio between the silver (Ag) and the germanium selenide in the layer, using the ratio to determine the first sputtering rate, and using the ratio to determine the second sputtering rate.

Another embodiment according to the present invention is a process that controls a constituent ratio during production of a memory cell body. The ratio is controlled by selecting a first deposition rate of a metal such as silver (Ag), copper (Cu), or zinc (Zn) selecting a second deposition rate of germanium selenide (Ge _x Se _1-x ), controlling the first deposition rate by selecting a first sputtering power used to deposit the metal, and controlling the second deposition rate by selecting a second sputtering power used to deposit the germanium selenide (Ge _x Se _1-x ).

Another embodiment according to the present invention is a process to configure a deposition system used to fabricate a memory cell body for a nonvolatile memory cell. The process includes receiving an indication of a desired constituent ratio, and calculating a deposition rate for a metal and a deposition rate for germanium selenide (Ge _x Se _1-x ) that provides the desired ratio. The calculated deposition rate for the metal is further related to a sputter power for a metal target, and the calculated deposition rate for germanium selenide (Ge _x Se _1-x ) is related to a sputter power for a germanium selenide (Ge _x Se _1-x ) target. The process configures the deposition system to sputter the metal from the metal target at the calculated sputter power, and configures the deposition system to sputter germanium selenide (Ge _x Se _1-x ) from the germanium selenide (Ge _x Se _1-x ) target with the calculated sputter power. The metal can be silver (Ag), copper (Cu), or zinc (Zn). In another embodiment, the process includes storing a configuration of the deposition chamber, measuring the deposition rate for the metal versus sputter power, measuring the deposition rate for germanium selenide (Ge _x Se _1-x ) versus sputter power, and storing the measured information such that it can be later retrieved by the process to configure the deposition system.

BRIEF DESCRIPTION OF THE DRAWINGS

These and other features of the invention will now be described with reference to the drawings summarized below. These drawings and the associated description are provided to illustrate preferred embodiments of the invention and are not intended to limit the scope of the invention.

FIG. 1 schematically illustrates a co-sputter deposition system according to an embodiment of the present invention.

FIG. 2 is a schematic cross section of a memory cell with a memory cell body formed by co-sputtering a metal and germanium selenide (Ge _x Se _1-x ) glass.

FIG. 3 is a flowchart that generally illustrates a process of co-sputtering metal and germanium selenide (Ge _x Se _1-x ) glass.

FIG. 4 is a flowchart that generally illustrates a process of configuring a deposition system to co-sputter metal and germanium selenide (Ge _x Se _1-x ) glass.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Although this invention will be described in terms of certain preferred embodiments, other embodiments that are apparent to those of ordinary skill in the art, including embodiments which do not provide all of the benefits and features set forth herein, are also within the scope of this invention. Accordingly, the scope of the present invention is defined only by reference to the appended claims.

Embodiments of the present invention allow a chalcogenide glass such as germanium selenide (Ge _x Se _1-x ) to be doped with a metal such as silver (Ag), copper (Cu), or zinc (Zn) without the performance of an ultraviolet (UV) photodoping step. Other examples of chalcogenide glasses that can be used include germanium sulfide (Ge _x S _1-x ) and arsenic selenide (As _x Se _1-x ). The value of x can vary in a wide range. Although the value of x can theoretically range from 0 to 1, the fabrication of a programmable conductor random access memory (PCRAM) should maintain the value of x such that the underlying combination of chalcogenide glass doped with the metal remains in an amorphous state. It will be understood by one of ordinary skill in the art that the value of x can depend on the amount of the metal that dopes the chalcogenide glass. The selection of a value of x will be described later in connection with FIG. 2.

Advantageously, embodiments of the invention co-sputter the metal and the chalcogenide glass. This provides a relatively precise and efficient control of a constituent ratio between the doping metal and the chalcogenide glass. Further advantageously, the doping of the chalcogenide glass with the metal can be produced with a relatively high degree of depth profile uniformity. It will be understood by one of ordinary skill in the art that there are at least two types of uniformity with respect to a doping profile. A first type, a lateral doping profile, varies depending on the deposition system. For example, variations in the projected light intensity of an ultraviolet source across the surface of the deposited film can produce lateral variations in the doping profile. By contrast, the attenuation of the ultraviolet light as the ultraviolet light penetrates through the metal and the chalcogenide glass gives rise to variations in depth profile uniformity.

FIG. 1 schematically illustrates a co-sputter deposition system 100 according to an embodiment of the present invention. The illustrated co-sputter deposition system 100 includes a first inlet 102 adapted to introduce an inert gas, such as argon (Ar). A second inlet 104 allows a vacuum pump to evacuate an interior of the co-sputter deposition system 100 to a relatively low pressure.

A first target 110 provides a source of chalcogenide glass, preferably germanium selenide (Ge _x Se _1-x ). The first target 110 is coupled to a first target electrode 112 , which in turn is coupled to a first power supply 114 . In one arrangement, the first power supply 114 is configured to pulse direct current (DC) to sputter material from .the first target 110 . In one arrangement, the first target 110 is germanium selenide (Ge _x Se _1-x ), e.g., Ge ₃ Se ₇ .

A second target 120 provides the source of the metal that dopes the germanium selenide (Ge _x Se _1-x ). The metal can be silver (Ag), copper (Cu), and zinc (Zn), which will advantageously diffuse relatively quickly into the chalcogenide element. The second target 120 is coupled to a second target electrode 122 , which in turn is coupled to a second power supply 124 . In one arrangement, the second power supply 124 is configured to apply direct current, (DC) to sputter material from the second target 120 .

The co-sputter deposition system 100 sputters chalcogenide glass from the first target 110 and simultaneously sputters the metal from the second target 120 to a substrate 130 to produce a layer 140 of chalcogenide glass doped with the metal. In the illustrated co-sputter deposition system 100 , the substrate 130 rests on an electrode 106 , which is at ground potential. The relative removal rates and thus, deposition rates, of material from the target 110 and the second target 120 approximately determine the doping profile of the layer 140 .

FIG. 2 illustrates one embodiment according to the present invention of a memory cell 200 with an active layer formed by co-sputtering metal and a chalcogenide glass. In one embodiment, the metal is silver (Ag). In other embodiments, the metal is copper (Cu) or zinc (Zn). In one embodiment, the chalcogenide glass is germanium selenide (Ge _x Se _1-x ), e.g., Ge ₃ Se ₇ . The illustrated memory cell 200 includes a first electrode 202 , a memory cell body 204 , an insulator 208 , and a second electrode 210 .

The first electrode 202 is formed on a substrate assembly. The substrate assembly can correspond to a variety of materials including plastic and silicon. Preferably, the first electrode 202 is part of an elongated conductor in a crosspoint array so that the memory cell 200 can be programmed and read. The first electrode 202 can be made from a variety of materials and from combinations of materials such as tungsten (W), nickel (Ni), silver (Ag), and titanium (Ti).

The memory cell body 204 is formed on the first electrode 202 . In the illustrated embodiment, the memory cell body 204 is a co-sputtered layer of silver (Ag) and germanium selenide (Ge _x Se _1-x ). In another embodiment, the memory cell body 203 is a co-sputtered layer of copper (Cu) and germanium selenide (Ge _x Se _1-x ) or a co-sputtered layer of zinc (Zn) and germanium selenide (Ge _x Se _1-x ). A variety of combinations of metal and chalcogenide glass elements can be used to form the memory cell body 204 . In another embodiment, the metal and chalcogenide glass elements are co-sputtered from three separate targets, e.g., a silver target, a germanium target, and a selenium target.

The memory cell body 204 of the memory cell 200 should be formed such that the metal-doped chalcogenide glass in the memory cell body 204 is in an amorphous state. The skilled practitioner will appreciate that where the chalcogenide glass is germanium selenide (Ge _x Se _1-x ), the state of the metal-doped chalcogenide glass, i.e., whether it is amorphous or crystalline, depends on both the value of x and the amount of metal that dopes the chalcogenide glass.

A phase diagram can be used to select a value for x and to silt the amount of metal that is to dope the chalcogenide glass such that the chalcogenide glass remains amorphous. Such a phase diagram can be found in a reference from Mitkova, et al., entitled “Dual Chemical Role of Ag as an Additive in Chalcogenide Glasses,” Physical Review Letters , Vol. 86, no. 19, (Nov. 8, 1999), pp. 3848-3851, (“Mitkova”) which is attached hereto as Appendix 1 and which is hereby incorporated herein by reference in its entirety. FIG. 1 of Mitkova illustrates two glass-forming or amorphous regions for germanium selenide (Ge _x Se _1-x ) doped with silver (Ag). In one example, where x is 30, i.e., 0.30, so that the germanium selenide glass is Ge ₃₀ Se ₇₀ , the amount of silver (Ag) used to dope the germanium selenide should fall within about 0 to 18% or within about 23% to 32% by atomic percentage versus the amount of selenide (Se).

In the illustrated embodiment, the insulator 208 surrounds the memory cell body 204 . The insulator 208 insulates the memory cell body 204 from other memory cells and also prevents the undesired diffusion of metal atoms and ions. The insulator 208 can be formed from a variety of materials such as silicon nitride (Si ₃ N ₄ ).

The second electrode 210 is formed on the memory cell body 204 and on the insulator 208 . In one embodiment, the second electrode 210 also forms part of a line, preferably perpendicular to a lower line as part of a crosspoint array. The second electrode 210 can be formed from a variety of materials such as copper (Cu), zinc (Zn), silver (Ag), and the like. An electric potential applied between the first electrode 202 and the second electrode 210 generates an electric field in the memory cell body 204 , which in turn causes conductive pathways in the memory cell body 204 to grow or shrink in response to the applied electric field.

FIG. 3 illustrates a process 300 of co-sputtering metal and germanium selenide (Ge _x Se _1-x ) glass. The process provides 310 a metal target from which metal is to sputtered onto a substrate assembly. The metal can be silver (Ag), copper (Cu), or zinc (Zn). The process proceeds to provide 320 a germanium selenide (Ge _x Se _1-x ) target from which germanium selenide (Ge _x Se _1-x ) is to sputtered onto the substrate assembly. In one embodiment, the germanium selenide (Ge _x Se _1-x ) target is a germanium selenide (Ge ₃₀ Se ₇₀ ) target.

The process proceeds to select 330 a deposition rate for the metal .In one embodiment the process selects relatively constant deposition rate for the metal. In another embodiment, the process selects a variable deposition rate for the metal that can be used to vary a doping profile of the metal in the resulting metal-doped germanium selenide (Ge _x Se _1-x ) layer. The deposition rate for the metal is approximately related to the removal rate of material from the metal target. In turn, the removal rate of the material from the metal target is approximately related to the sputter power applied to the metal target. This allows sputter power to control the deposition rate for the metal. It will be understood by one of ordinary skill in the art, however, that the deposition rate versus sputter power varies according to the configuration of the deposition system and the material that is sputtered.

The process selects 340 a deposition rate for germanium selenide (Ge _x Se _1-x ). In one embodiment, the deposition rate for germanium selenide (Ge _x Se _1-x ) is relatively constant. In another embodiment, the deposition rate for germanium selenide (Ge _x Se _1-x ) can vary and can be used to vary the doping profile of the metal in the metal-doped germanium selenide (Ge _x Se _1-x ) layer. The deposition rate for the germanium selenide (Ge _x Se _1-x ) is approximately related to the removal rate of material from the germanium selenide (Ge _x Se _1-x ) target and, in turn, approximately related to the sputter power applied to the germanium selenide (Ge _x Se _1-x ) target. This allows the process to select 340 the deposition rate by a selection of sputter power.

The relative deposition rates between the metal and the germanium selenide (Ge _x Se _1-x ) determine the amount of doping of the metal to the germanium selenide. For example, where a silver (Ag) deposition rate is about 17.8% of the total film deposition, the resulting film is doped at about 32 atomic percent of silver (Ag). In another example, where the silver (Ag) deposition rate is about 9% to about 56% of the total film deposition, the resulting film is doped at about 18.3% to about 69.6% silver (Ag) by atomic percentage.

The process sputters 350 the metal and the germanium selenide (Ge _x Se _1-x ) from their respective targets. In one embodiment, the process sputters 350 metal in accordance with a direct current (DC) sputter process, and the process sputters 350 germanium selenide (Ge _x Se _1-x ) in accordance with a pulse DC sputter process. In a pulse DC sputter process, a positive voltage is periodically applied for a short period of time to the target to reduce or eliminate charge build up in the target. It will be understood by one of ordinary skill in the art that the sputter power used to generate a particular desposition rate will vary depending on the configuration of the deposition system. For the purposes of illustration only, one embodiment of the invention uses 30 Watts (W) of DC sputter to sputter silver (Ag) and sputters germanium selenide (Ge ₃₀ Se ₇₀ ) with 575 W of pulse DC sputter to produce a doped film with about 32% silver (Ag) by atomic weight.

FIG. 4 illustrates a process 400 of configuring a deposition system to co-sputter metal and germanium selenide (Ge _x Se _1-x ) glass. In one embodiment, the metal is silver (Ag), copper (Cu), or zinc (Zn) and the germanium selenide (Ge _x Se _1-x ) is germanium selenide (Ge ₃₀ Se ₇₀ ). It will be understood that in other embodiments, a different chalcogenide glass substitutes for the germanium selenide (Ge _x Se _1-x ) glass. For example, germanium sulfide (Ge _x Se _1-x ) or arsenic selenide (As _x Se _1-x ) can also be used. The process selects 410 a desired ratio for the metal to the germanium selenide in the active layer. The ratio can be relatively constant to form a relatively uniformly doped layer of metal-doped chalcogenide glass, or can be variable to allow a metal to dope the chalcogenide glass with a selected doping profile.

The process proceeds to calculate 420 a deposition rate for the metal and a deposition rate for the germanium selenide to produce the desired doping of the metal in the germanium selenide (Ge _x Se _1-x ). A broad variety of methods can be used to calculate 420 the deposition rates. In one embodiment, the process calculates 420 the deposition rates by, for example, referring to a lookup table containing pre-calculated deposition rates for particular doping levels. In another embodiment, the process calculates 420 the deposition rates in real time, and scales calculations as necessary to maintain deposition rates within the capabilities of the applicable deposition system.

The process proceeds to relate 430 the specified deposition rates to sputter power levels. Where the deposition rates of the various materials sputtered versus sputter power for the configuration of the deposition system is available, the process can retrieve the sputter power to be used by reference to, for example, a database. The sputter power levels for a given configuration are related to the deposition rates and can be used to control the doping profile of the deposited film. In one embodiment, the process collects and maintains in a database, the configuration of the deposition system and data of deposition rates versus sputter power for a collection of the materials deposited for later retrieval.

The process proceeds to configure 440 a sputtering tool for co-sputtering. In one embodiment, the process configures the tool for DC sputter of the metal target at the specified power level for the desired deposition rate. In one embodiment, the process configures the tool for pulsed DC sputtering of the germanium selenide (Ge _x Se _1-x ) target at the specified power level for the desired deposition rate.

While illustrated primarily in the context of co-sputtering a metal and germanium selenide (Ge _x Se _1-x ) to produce a ternary mixture of a metal-doped chalcogenide glass, it will be understood that the co-sputtering techniques described herein to fabricate a memory cell body are applicable to other combinations suitable for forming metal-doped chalcogenide glass elements.

One combination includes co-sputtering the metal, germanium (Ge), and selenium (Se) from three separate targets. The metal can correspond to a metal that diffuses relatively quickly into the glass, for example, silver (Ag), copper (Cu), and zinc (Zn). Another combination includes co-sputtering a metal selenide, such as Ag _y1 Se _1-y1 , Cu _y2 Se _1-y2 , or Zn _y3 Se _1-y3 , with germanium (Ge) from two separate targets. Another combination includes co-sputtering a germanium metal mixture, such as Ge _z1 Ag _1-z1 , Cu _z2 Ge _1-z2 , or Zn _z3 Ge _1-z3 , and selenium (Se) from two separate targets. In the illustrated equations, the values of y 1 , y 2 , y 3 , z 1 , z 2 , and z 3 should be maintained such that the deposited material is in an amorphous state. Advantageously, these other combinations can provide the metal-doping of a chalcogenide glass with a relatively high degree of depth-profile uniformity and control.

The chalcogenide glass can also include germanium sulfide (Ge _x S _1-x ) or arsenic selenide (As _x Se _1-x ). Metal-doped germanium sulfide can be formed by co-sputtering metal and germanium sulfide from two separate targets. Another combination includes sputtering a metal sulfide and germanium from two separate targets. Metal-doped arsenic selenide can likewise be formed by co-sputtering metal and arsenic selenide from two separate targets. In another combination, a metal arsenide and selenium are sputtered from two separate targets.

Various embodiments of the present invention have been described above. Although this invention has been described with reference to these specific embodiments, the descriptions are intended to be illustrative of the invention and are not intended to be limiting. Various modifications and applications may occur to those skilled in the art without departing from the true spirit and scope of the invention as defined in the appended claims.