James, Ralph (Andover, MN, US)

Plaque It!

10/813040

11/04/2008

03/29/2004

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Micron Technology, Inc. (Boise, ID, US)

370/516

710/22, 365/63

H04J3/06

370/520, 370/512, 370/503, 711/154, 711/167, 370/249, 370/248

3742253	THREE STATE LOGIC DEVICE WITH APPLICATIONS	June, 1973	Kronies	307/247
4045781	Memory module with selectable byte addressing for digital data processing system	August, 1977	Levy et al.	364/200
4078228	Loop data highway communication system	March, 1978	Miyazaki	370/460
4240143	Hierarchical multi-processor network for memory sharing	December, 1980	Besemer et al.	364/200
4245306	Selection of addressed processor in a multi-processor network	January, 1981	Besemer et al.	364/200
4253144	Multi-processor communication network	February, 1981	Bellamy et al.	364/200
4253146	Module for coupling computer-processors	February, 1981	Bellamy et al.	364/200
4608702	Method for digital clock recovery from Manchester-encoded signals	August, 1986	Hirzel et al.	375/110
4707823	Fiber optic multiplexed data acquisition system	November, 1987	Holdren et al.	370/1
4724520	Modular multiport data hub	February, 1988	Athanas et al.	364/200
4831520	Bus interface circuit for digital data processor	May, 1989	Rubinfeld et al.	364/200
4843263	Clock timing controller for a plurality of LSI chips	June, 1989	Ando	307/480
4891808	Self-synchronizing multiplexer	January, 1990	Williams	370/112
4930128	Method for restart of online computer system and apparatus for carrying out the same	May, 1990	Suzuki et al.	371/12
4953930	CPU socket supporting socket-to-socket optical communications	September, 1990	Ramsey et al.	350/96.11
4982185	System for synchronous measurement in a digital computer network	January, 1991	Holmberg et al.	340/825.21
5241506	Semiconductor memory circuit apparatus	August, 1993	Motegi et al.	365/210
5243703	Apparatus for synchronously generating clock signals in a data processing system	September, 1993	Farmwald et al.	395/325
5251303	System for DMA block data transfer based on linked control blocks	October, 1993	Fogg, Jr. et al.	395/275
5269022	Method and apparatus for booting a computer system by restoring the main memory from a backup memory	December, 1993	Shinjo et al.	395/700
5299293	Protection arrangement for an optical transmitter/receiver device	March, 1994	Mestdagh et al.	398/24
5313590	System having fixedly priorized and grouped by positions I/O lines for interconnecting router elements in plurality of stages within parrallel computer	May, 1994	Taylor	395/325
5317752	Fault-tolerant computer system with auto-restart after power-fall	May, 1994	Jewett et al.	395/750
5319755	Integrated circuit I/O using high performance bus interface	June, 1994	Farmwald et al.	395/325
5327553	Fault-tolerant computer system with /CONFIG filesystem	July, 1994	Jewett et al.	395/575
5355391	High speed bus system	October, 1994	Horowitz et al.	375/36
5432823	Method and circuitry for minimizing clock-data skew in a bus system	July, 1995	Gasbarro et al.	375/356
5432907	Network hub with integrated bridge	July, 1995	Picazo, Jr. et al.	395/200
5442770	Triple port cache memory	August, 1995	Barratt	395/403
5461627	Access protocol for a common channel wireless network	October, 1995	Rypinski	370/95.2
5465229	Single in-line memory module	November, 1995	Bechtolsheim et al.	345/477
5479370	Semiconductor memory with bypass circuit	December, 1995	Furuyama et al.	365/189.12
5497476	Scatter-gather in data processing system	March, 1996	Oldfield et al.	395/439
5502621	Mirrored pin assignment for two sided multi-chip layout	March, 1996	Schumacher et al.	361/760
5544319	Fiber optic memory coupling system with converter transmitting and receiving bus data in parallel fashion and diagnostic data in serial fashion	August, 1996	Acton et al.	395/200.07
5566325	Method and apparatus for adaptive memory access	October, 1996	Bruce, II et al.	395/494
5577220	Method for saving and restoring the state of a CPU executing code in protected mode including estimating the value of the page table base register	November, 1996	Combs et al.	395/416
5581767	Bus structure for multiprocessor system having separated processor section and control/memory section	December, 1996	Katsuki et al.	395/800
5606717	Memory circuitry having bus interface for receiving information in packets and access time registers	February, 1997	Farmwald et al.	395/856
5638334	Integrated circuit I/O using a high performance bus interface	June, 1997	Farmwald et al.	365/230.03
5659798	Method and system for initiating and loading DMA controller registers by using user-level programs	August, 1997	Blumrich et al.	395/846
5687325	Application specific field programmable gate array	November, 1997	Chang	395/284
5706224	Content addressable memory and random access memory partition circuit	January, 1998	Srinivasan et al.	365/49
5715456	Method and apparatus for booting a computer system without pre-installing an operating system	February, 1998	Bennett et al.	395/652
5729709	Memory controller with burst addressing circuit	March, 1998	Harness	395/405
5748616	Data link module for time division multiplexing control systems	May, 1998	Riley	370/242
5818844	Address generation and data path arbitration to and from SRAM to accommodate multiple transmitted packets	October, 1998	Singh et al.	370/463
5819304	Random access memory assembly	October, 1998	Nilsen et al.	711/5
5822255	Semiconductor integrated circuit for supplying a control signal to a plurality of object circuits	October, 1998	Uchida	365/194
5832250	Multi set cache structure having parity RAMs holding parity bits for tag data and for status data utilizing prediction circuitry that predicts and generates the needed parity bits	November, 1998	Whittaker	395/471
5875352	Method and apparatus for multiple channel direct memory access control	February, 1999	Gentry et al.	395/843
5875454	Compressed data cache storage system	February, 1999	Craft et al.	711/113
5928343	Memory module having memory devices containing internal device ID registers and method of initializing same	July, 1999	Farmwald et al.	710/104
5966724	Synchronous memory device with dual page and burst mode operations	October, 1999	Ryan	711/105
5973935	Interdigitated leads-over-chip lead frame for supporting an integrated circuit die	October, 1999	Schoenfeld et al.	361/813
5973951	Single in-line memory module	October, 1999	Bechtolsheim et al.	365/52
5978567	System for distribution of interactive multimedia and linear programs by enabling program webs which include control scripts to define presentation by client transceiver	November, 1999	Rebane et al.	395/200.49
5987196	Semiconductor structure having an optical signal path in a substrate and method for forming the same	November, 1999	Noble	385/14
6014721	Method and system for transferring data between buses having differing ordering policies	January, 2000	Arimilli et al.	710/129
6023726	User configurable prefetch control system for enabling client to prefetch documents from a network server	February, 2000	Saksena	709/219
6029250	Method and apparatus for adaptively adjusting the timing offset between a clock signal and digital signals transmitted coincident with that clock signal, and memory device and system using same	February, 2000	Keeth	713/400
6031241	Capillary discharge extreme ultraviolet lamp source for EUV microlithography and other related applications	February, 2000	Silfvast et al.	250/504R
6033951	Process for fabricating a storage capacitor for semiconductor memory devices	March, 2000	Chao	438/253
6038630	Shared access control device for integrated system with multiple functional units accessing external structures over multiple data buses	March, 2000	Foster et al.	710/132
6061263	Small outline rambus in-line memory module	May, 2000	Boaz et al.	365/51
6061296	Multiple data clock activation with programmable delay for use in multiple CAS latency memory devices	May, 2000	Ternullo, Jr. et al.	365/233
6064706	Apparatus and method of desynchronizing synchronously mapped asynchronous data	May, 2000	Driskill et al.	375/372
6067262	Redundancy analysis for embedded memories with built-in self test and built-in self repair	May, 2000	Irrinki et al.	365/201
6067649	Method and apparatus for a low power self test of a memory subsystem	May, 2000	Goodwin	714/718
6073190	System for dynamic buffer allocation comprising control logic for controlling a first address buffer and a first data buffer as a matched pair	June, 2000	Rooney	710/56
6076139	Multimedia computer architecture with multi-channel concurrent memory access	June, 2000	Welker et al.	711/104
6079008	Multiple thread multiple data predictive coded parallel processing system and method	June, 2000	Clery, III	712/11
6098158	Software-enabled fast boot	August, 2000	Lay et al.	711/162
6100735	Segmented dual delay-locked loop for precise variable-phase clock generation	August, 2000	Lu	327/158
6105075	Scatter gather memory system for a hardware accelerated command interpreter engine	August, 2000	Ghaffari	710/5
6125431	Single-chip microcomputer using adjustable timing to fetch data from an external memory	September, 2000	Kobayashi	711/154
6131149	Apparatus and method for reading data from synchronous memory with skewed clock pulses	October, 2000	Lu et al.	711/167
6134624	High bandwidth cache system	October, 2000	Burns et al.	710/131
6137709	Small outline memory module	October, 2000	Boaz et al.	365/51
6144587	Semiconductor memory device	November, 2000	Yoshida	365/189.05
6167465	System for managing multiple DMA connections between a peripheral device and a memory and performing real-time operations on data carried by a selected DMA connection	December, 2000	Parvin et al.	710/22
6167486	Parallel access virtual channel memory system with cacheable channels	December, 2000	Lee et al.	711/120
6175571	Distributed memory switching hub	January, 2001	Haddock et al.	370/423
6185352	Optical fiber ribbon fan-out cables	February, 2001	Hurley	385/114
6186400	Bar code reader with an integrated scanning component module mountable on printed circuit board	February, 2001	Dvorkis et al.	235/462.45
6191663	Echo reduction on bit-serial, multi-drop bus	February, 2001	Hannah	333/17.3
6201724	Semiconductor memory having improved register array access speed	March, 2001	Ishizaki et al.	365/49
6208180	Core clock correction in a 2/N mode clocking scheme	March, 2001	Fisch et al.	327/141
6219725	Method and apparatus for performing direct memory access transfers involving non-sequentially-addressable memory locations	April, 2001	Diehl et al.	710/26
6233376	Embedded fiber optic circuit boards and integrated circuits	May, 2001	Updegrove	385/14
6243769	Dynamic buffer allocation for a computer system	June, 2001	Rooney	710/56
6243831	Computer system with power loss protection mechanism	June, 2001	Mustafa et al.	714/24
6246618	Semiconductor integrated circuit capable of testing and substituting defective memories and method thereof	June, 2001	Yamamoto et al.	365/200
6247107	Chipset configured to perform data-directed prefetching	June, 2001	Christie	711/216
6249802	Method, system, and computer program product for allocating physical memory in a distributed shared memory network	June, 2001	Richardson et al.	709/200
6256325	Transmission apparatus for half duplex communication using HDLC	July, 2001	Park	370/503
6256692	CardBus interface circuit, and a CardBus PC having the same	July, 2001	Yoda et al.	710/104
6272600	Memory request reordering in a data processing system	August, 2001	Talbot et al.	711/140
6272609	Pipelined memory controller	August, 2001	Jeddeloh	711/169
6278755	Bit synchronization circuit	August, 2001	Baba et al.	375/360
6285349	Correcting non-uniformity in displays	September, 2001	Smith	345/147
6286083	Computer system with adaptive memory arbitration scheme	September, 2001	Chin et al.	711/151
6289068	Delay lock loop with clock phase shifter	September, 2001	Hassoun et al.	375/376
6294937	Method and apparatus for self correcting parallel I/O circuitry	September, 2001	Crafts et al.	327/158
6301637	High performance data paths	October, 2001	Krull et al.	711/112
6324485	Application specific automated test equipment system for testing integrated circuit devices in a native environment	November, 2001	Ellis	702/117
6327642	Parallel access virtual channel memory system	December, 2001	Lee et al.	711/120
6330205	Virtual channel synchronous dynamic random access memory	December, 2001	Shimizu et al.	365/230.096
6347055	Line buffer type semiconductor memory device capable of direct prefetch and restore operations	February, 2002	Motomura	365/189.05
6349363	Multi-section cache with different attributes for each section	February, 2002	Cai et al.	711/129
6356573	Vertical cavity surface emitting laser	March, 2002	Jonsson et al.	372/46
6367074	Operation of a system	April, 2002	Bates et al.	717/11
6370068	Semiconductor memory devices and methods for sampling data therefrom based on a relative position of a memory cell array section containing the data	April, 2002	Rhee	365/196
6373777	Semiconductor memory	April, 2002	Suzuki	365/230.03
6381190	Semiconductor memory device in which use of cache can be selected	April, 2002	Shinkai	365/230.03
6392653	Device for processing acquisition data, in particular image data	May, 2002	Malandain et al.	345/501
6401213	Timing circuit for high speed memory	June, 2002	Jeddeloh	713/401
6405280	Packet-oriented synchronous DRAM interface supporting a plurality of orderings for data block transfers within a burst sequence	June, 2002	Ryan	711/105
6421744	Direct memory access controller and method therefor	July, 2002	Morrison et al.	710/22
6430696	Method and apparatus for high speed data capture utilizing bit-to-bit timing correction, and memory device using same	August, 2002	Keeth	713/503
6434639	System for combining requests associated with one or more memory locations that are collectively associated with a single cache line to furnish a single memory operation	August, 2002	Haghighi	710/39
6434696	Method for quickly booting a computer system	August, 2002	Kang	713/2
6434736	Location based timing scheme in memory design	August, 2002	Schaecher et al.	716/17
6438622	Multiprocessor system including a docking system	August, 2002	Haghighi et al.	710/1
6438668	Method and apparatus for reducing power consumption in a digital processing system	August, 2002	Esfahani et al.	711/165
6449308	High-speed digital distribution system	September, 2002	Knight, Jr. et al.	375/212
6453393	Method and apparatus for interfacing to a computer memory	September, 2002	Holman et al.	711/154
6462978	Method of designing semiconductor integrated circuit device and semiconductor integrated circuit device	October, 2002	Shibata et al.	365/63
6463059	Direct memory access execution engine with indirect addressing of circular queues in addition to direct memory addressing	October, 2002	Movshovich et al.	370/389
6467013	Memory transceiver to couple an additional memory channel to an existing memory channel	October, 2002	Nizar	711/1
6470422	Buffer memory management in a system having multiple execution entities	October, 2002	Cai et al.	711/129
6473828	Virtual channel synchronous dynamic random access memory	October, 2002	Matsui	711/104
6477592	System for I/O interfacing for semiconductor chip utilizing addition of reference element to each data element in first data stream and interpret to recover data elements of second data stream	November, 2002	Chen et al.	710/52
6477614	Method for implementing multiple memory buses on a memory module	November, 2002	Leddige et al.	711/5
6477621	Parallel access virtual channel memory system	November, 2002	Lee et al.	711/120
6479322	Semiconductor device with two stacked chips in one resin body and method of producing	November, 2002	Kawata et al.	438/109
6487556	Method and system for providing an associative datastore within a data processing system	November, 2002	Downs et al.	707/101
6490188	Semiconductor devices having mirrored terminal arrangements, devices including same, and methods of testing such semiconductor devices	December, 2002	Nuxoll et al.	365/63
6493803	Direct memory access controller with channel width configurability support	December, 2002	Pham et al.	711/147
6496909	Method for managing concurrent access to virtual memory data structures	December, 2002	Schimmel	711/163
6501471	Volume rendering	December, 2002	Venkataraman et al.	345/424
6505287	Virtual channel memory access controlling circuit	January, 2003	Uematsu	711/170
6523092	Cache line replacement policy enhancement to avoid memory page thrashing	February, 2003	Fanning	711/134
6523093	Prefetch buffer allocation and filtering system	February, 2003	Bogin et al.	711/137
6526483	Page open hint in transactions	February, 2003	Cho et al.	711/154
6539490	Clock distribution without clock delay or skew	March, 2003	Forbes et al.	713/401
6552564	Technique to reduce reflections and ringing on CMOS interconnections	April, 2003	Forbes et al.	326/30
6564329	System and method for dynamic clock generation	May, 2003	Cheung et al.	713/322
6587912	Method and apparatus for implementing multiple memory buses on a memory module	July, 2003	Leddige et al.	711/5
6590816	Integrated memory and method for testing and repairing the integrated memory	July, 2003	Perner	365/200
6594713	Hub interface unit and application unit interfaces for expanded direct memory access processor	July, 2003	Fuoco et al.	710/31
6594722	Mechanism for managing multiple out-of-order packet streams in a PCI host bridge	July, 2003	Willke, II et al.	710/313
6598154	Precoding branch instructions to reduce branch-penalty in pipelined processors	July, 2003	Vaid et al.	712/237
6615325	Method for switching between modes of operation	September, 2003	Mailloux et al.	711/154
6622188	12C bus expansion apparatus and method therefor	September, 2003	Goodwin et al.	710/101
6622227	Method and apparatus for utilizing write buffers in memory control/interface	September, 2003	Zumkehr et al.	711/167
6628294	Prefetching of virtual-to-physical address translation for display data	September, 2003	Sadowsky et al.	345/568
6629220	Method and apparatus for dynamic arbitration between a first queue and a second queue based on a high priority transaction type	September, 2003	Dyer	711/158
6631440	Method and apparatus for scheduling memory calibrations based on transactions	October, 2003	Jenne et al.	711/105
6636110	Internal clock generating circuit for clock synchronous semiconductor memory device	October, 2003	Ooishi et al.	327/565
6636912	Method and apparatus for mode selection in a computer system	October, 2003	Ajanovic et al.	710/105
6646929	Methods and structure for read data synchronization with minimal latency	November, 2003	Moss et al.	365/194
6658509	Multi-tier point-to-point ring memory interface	December, 2003	Bonella et al.	710/100
6662304	Method and apparatus for bit-to-bit timing correction of a high speed memory bus	December, 2003	Keeth et al.	713/400
6665202	Content addressable memory (CAM) devices that can identify highest priority matches in non-sectored CAM arrays and methods of operating same	December, 2003	Lindahl et al.	365/49
6667895	Integrated circuit device and module with integrated circuits	December, 2003	Jang et al.	365/63
6667926	Memory read/write arbitration method	December, 2003	Chen et al.	365/221
6670833	Multiple VCO phase lock loop architecture	December, 2003	Kurd et al.	327/156
6681292	Distributed read and write caching implementation for optimized input/output applications	January, 2004	Creta et al.	711/119
6697926	Method and apparatus for determining actual write latency and accurately aligning the start of data capture with the arrival of data at a memory device	February, 2004	Johnson et al.	711/167
6715018	Computer including installable and removable cards, optical interconnection between cards, and method of assembling a computer	March, 2004	Farnworth et al.	710/300
6718440	Memory access latency hiding with hint buffer	April, 2004	Maiyuran et al.	711/137
6721195	Reversed memory module socket and motherboard incorporating same	April, 2004	Brunelle et al.	365/63
6721860	Method for bus capacitance reduction	April, 2004	Klein	711/154
6724685	Configuration for data transmission in a semiconductor memory system, and relevant data transmission method	April, 2004	Braun et al.	365/233
6728800	Efficient performance based scheduling mechanism for handling multiple TLB operations	April, 2004	Lee et al.	710/54
6735679	Apparatus and method for optimizing access to memory	May, 2004	Herbst et al.	711/167
6735682	Apparatus and method for address calculation	May, 2004	Segelken et al.	711/220
6742098	Dual-port buffer-to-memory interface	May, 2004	Halbert et al.	711/172
6745275	Feedback system for accomodating different memory module loading	June, 2004	Chang	710/305
6751703	Data storage systems and methods which utilize an on-board cache	June, 2004	Chilton	711/113
6754812	Hardware predication for conditional instruction path branching	June, 2004	Abdallah et al.	712/234
6756661	Semiconductor device, a semiconductor module loaded with said semiconductor device and a method of manufacturing said semiconductor device	June, 2004	Tsuneda et al.	257/673
6760833	Split embedded DRAM processor	July, 2004	Dowling	712/34
6771538	Semiconductor integrated circuit and nonvolatile memory element	August, 2004	Shukuri et al.	365/185.05
6775747	System and method for performing page table walks on speculative software prefetch operations	August, 2004	Venkatraman	711/137
6782435	Device for spatially and temporally reordering for data between a processor, memory and peripherals	August, 2004	Garcia et al.	710/33
6789173	Node controller for performing cache coherence control and memory-shared multiprocessor system	September, 2004	Tanaka et al.	711/147
6792059	Early/on-time/late gate bit synchronizer	September, 2004	Yuan et al.	375/354
6792496	Prefetching data for peripheral component interconnect devices	September, 2004	Aboulenein et al.	710/306
6795899	Memory system with burst length shorter than prefetch length	September, 2004	Dodd et al.	711/137
6799246	Memory interface for reading/writing data from/to a memory	September, 2004	Wise et al.	711/117
6799268	Branch ordering buffer	September, 2004	Boggs et al.	712/228
6804760	Method for determining a type of memory present in a system	October, 2004	Wiliams	711/170
6804764	Write clock and data window tuning based on rank select	October, 2004	LaBerge et al.	711/170
6807630	Method for fast reinitialization wherein a saved system image of an operating system is transferred into a primary memory from a secondary memory	October, 2004	Lay et al.	713/2
6811320	System for connecting a fiber optic cable to an electronic device	November, 2004	Abbott	385/58
6816947	System and method for memory arbitration	November, 2004	Huffman	711/151
6820181	Method and system for controlling memory accesses to memory modules having a memory hub architecture	November, 2004	Jeddeloh et al.	711/169
6821029	High speed serial I/O technology using an optical link	November, 2004	Grung et al.	385/92
6823023	Serial bus communication system	November, 2004	Hannah	375/296
6845409	Data exchange methods for a switch which selectively forms a communication channel between a processing unit and multiple devices	January, 2005	Talagala et al.	710/20
6889304	Memory device supporting a dynamically configurable core organization	May, 2005	Perego et al.	711/170
6901494	Memory control translators	May, 2005	Zumkehr et al.	711/167
6904556	Systems and methods which utilize parity sets	June, 2005	Walton et al.	714/766
6910109	Tracking memory page state	June, 2005	Holman et al.	711/156
6912612	Shared bypass bus structure	June, 2005	Kapur et al.	710/309
6947672	High-speed optical data links	September, 2005	Jiang et al.	398/135
7046060	Method and apparatus compensating for frequency drift in a delay locked loop	May, 2006	Minzoni et al.	327/158
7068085	Method and apparatus for characterizing a delay locked loop	June, 2006	Gomm et al.	327/158
7181584	Dynamic command and/or address mirroring system and method for memory modules	February, 2007	LaBerge	711/167
7187742	Synchronized multi-output digital clock manager	March, 2007	Logue et al.	375/376
20010038611	Apparatus and method to monitor communication system status	November, 2001	Darcie et al.	370/248
20010039612	Apparatus and method for fast booting	November, 2001	Lee	713/2
20020112119	Dual-port buffer-to-memory interface	August, 2002	Halbert et al.	711/115
20020116588	Software management systems and methods for automotive computing devices	August, 2002	Beckert et al.	711/161
20020144064	Controlling cache memory in external chipset using processor	October, 2002	Fanning	711/144
20030005223	System boot time reduction method	January, 2003	Coulson et al.	711/118
20030005344	Synchronizing data with a capture pulse and synchronizer	January, 2003	Bhamidipati et al.	713/400
20030043158	Method and apparatus for reducing inefficiencies in shared memory devices	March, 2003	Wasserman et al.	345/545
20030043426	Optical interconnect in high-speed memory systems	March, 2003	Baker et al.	359/109
20030093630	Techniques for processing out-of -order requests in a processor-based system	May, 2003	Richard et al.	711/154
20030149809	Method and apparatus for timing and event processing in wireless systems	August, 2003	Jensen et al.	710/22
20030156581	Method and apparatus for hublink read return streaming	August, 2003	Osborne	370/389
20030163649	Shared bypass bus structure	August, 2003	Kapur et al.	711/146
20030177320	Memory read/write reordering	September, 2003	Sah et al.	711/158
20030193927	Random access memory architecture and serial interface with continuous packet handling capability	October, 2003	Hronik	370/351
20030217223	Combined command set	November, 2003	Nino, Jr. et al.	711/105
20030227798	REDUCED POWER REGISTERED MEMORY MODULE AND METHOD	December, 2003	Pax	365/189.12
20030229762	Apparatus, method, and system for synchronizing information prefetch between processors and memory controllers	December, 2003	Maiyuran et al.	711/137
20030229770	Memory hub with internal cache and/or memory access prediction	December, 2003	Jeddeloh	711/213
20040022094	Cache usage for concurrent multiple streams	February, 2004	Radhakrishnan et al.	365/200
20040044833	System and method for optimizing interconnections of memory devices in a multichip module	March, 2004	Ryan	711/5
20040107306	Ordering rule controlled command storage	June, 2004	Barth et al.	710/310
20040126115	System having multiple agents on optical and electrical bus	July, 2004	Levy et al.	398/116
20040128449	Method and system to improve prefetching operations	July, 2004	Osborne et al.	711/137
20040144994	Apparatus and methods for optically-coupled memory systems	July, 2004	Lee et al.	257/200
20040160206	Servo motor control system	August, 2004	Komaki et al.	318/569
20040193821	Providing an arrangement of memory devices to enable high-speed data access	September, 2004	Ruhovets et al.	711/167
20040225847	Systems and methods for scheduling memory requests utilizing multi-level arbitration	November, 2004	Wastlick et al.	711/158
20040236885	Arrangement and method for system of locally deployed module units, and contact unit for connection of such a module unit	November, 2004	Fredriksson et al.	710/100
20040251936	Clock synchronizing apparatus and method using frequency dependent variable delay	December, 2004	Gomm	327/141
20050015426	Communicating data over a communication link	January, 2005	Woodruff et al.	709/200
20050044327	Asynchronous, independent and multiple process shared memory system in an adaptive computing architecture	February, 2005	Howard et al.	711/147
20050071542	Prefetch mechanism for use in a system including a host connected to a plurality of memory modules via a serial memory interconnect	March, 2005	Weber et al.	711/105
20050105350	Memory channel test fixture and method	May, 2005	Zimmerman	365/201
20050122153	Centralizing the lock point of a synchronous circuit	June, 2005	Lin	327/291
20050149603	Queuing of conflicted remotely received transactions	July, 2005	DeSota et al.	709/200
20050162882	METHOD FOR INITIALIZING A SYSTEM INCLUDING A HOST AND PLURALITY OF MEMORY MODULES CONNECTED VIA A SERIAL MEMORY INTERCONNECT	July, 2005	Reeves et al.	365/63
20050166006	System including a host connected serially in a chain to one or more memory modules that include a cache	July, 2005	Talbot et al.	711/105
20060022724	Method and apparatus for fail-safe resynchronization with minimum latency	February, 2006	Zerbe et al.	327/141
20060218318	Method and system for synchronizing communications links in a hub-based memory system	September, 2006	James	710/58
20060271746	Arbitration system and method for memory responses in a hub-based memory system	November, 2006	Meyer et al.	711/148

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Ngo, Ricky

Yuen, Kan

Dorsey & Whitney LLP

The invention claimed is:

1. A memory hub, comprising: a downstream reception interface operable in an initialization mode to adjust a phase of a generated receive clock signal relative to applied test data signals and to generate an inversion signal once a final phase of the generated receive clock is determined, and operable in an enablement mode responsive to receiving an enablement command to generate an enablement signal and to place the downstream reception interface in the normal mode of operation; a downstream transmission interface operable in the initialization mode to apply test data signals on an output and operable to adjust the value of the test data signals responsive to the inversion signal from the downstream reception interface, and operable in the enablement mode responsive to the enablement signal from the downstream reception interface to provide the enablement command on the output and to place the downstream transmission interface into the normal mode of operation; an upstream reception interface operable in the initialization mode to adjust a phase of the generated receive clock signal relative to applied test data signals and to generate an inversion signal once a final phase of the generated receive clock is determined, and operable in an enablement mode responsive to receiving an enablement command to generate an enablement signal and to place the upstream reception interface into the normal mode of operation; and an upstream transmission interface operable in the initialization mode to apply test data signals on an output and operable to adjust the value of the test data signals responsive to the inversion signal from the upstream reception interface, and operable in the enablement mode responsive to the enablement signal from the upstream reception interface to provide the enablement command on the output and to place the upstream transmission interface into the normal mode of operation.

2. The memory hub of claim 1 wherein the enablement command comprises a No Operation command.

3. The memory hub of claim 1 wherein the downstream and upstream transmission interfaces adjust the value of the corresponding test data signals responsive to the inversion signal by inverting the test data signals.

4. The memory hub of claim 1 further comprising local hub circuitry coupled to the interfaces, the local control circuitry operable process memory requests during the normal mode of operation and to develop corresponding memory signals on a memory bus output.

5. The memory hub of claim 4, wherein the memory signals comprise address, data, and control signals.

6. The memory hub of claim 1 wherein the reception interfaces include optical interfaces to receive data words from an optical communications link.

7. The memory hub of claim 6 wherein the downstream reception interface and the upstream transmission interface are configured to be coupled to the same optical communications link, and wherein the downstream transmission interface and the upstream reception interface are configured to be coupled to the same optical communications link.

8. The memory hub of claim 7 wherein the optical communications link comprises an optical fiber.

9. A memory module, comprising: a plurality of memory devices; and a memory hub, comprising: a downstream reception interface operable in an initialization mode to adjust a phase of a generated receive clock signal relative to applied test data signals and to generate an inversion signal once a final phase of the generated receive clock signal is determined, and operable in an enablement mode responsive to receiving an enablement command to generate an enablement signal and to place the downstream reception interface in the normal mode of operation; a downstream transmission interface operable in the initialization mode to apply test data signals on an output and operable to adjust the value of the test data signals responsive to the inversion signal from the downstream reception interface, and operable in the enablement mode responsive to the enablement signal from the downstream reception interface to provide the enablement command on the output and to place the downstream transmission interface into the normal mode of operation; an upstream reception interface operable in the initialization mode to adjust a phase of the generated receive clock signal relative to applied test data signals and to generate an inversion signal once a final phase of the generated receive clock is determined, and operable in an enablement mode responsive to receiving an enablement command to generate an enablement signal and to place the upstream reception interface into the normal mode of operation; an upstream transmission interface operable in the initialization mode to apply test data signals on an output and operable to adjust the value of the test data signals responsive to the inversion signal from the upstream reception interface, and operable in the enablement mode responsive to the enablement signal from the upstream reception interface to provide the enablement command on the output and to place the upstream transmission interface into the normal mode of operation; and local hub circuitry coupled to the interfaces and to the memory devices.

10. The memory module of claim 9 wherein the enablement command comprises a No Operation command.

11. The memory module of claim 9 wherein the downstream and upstream transmission interfaces adjust the value of the corresponding test data signals responsive to the inversion signal by inverting the test data signals.

12. The memory module of claim 9 wherein the memory signals comprise address, data, and control signals.

13. The memory module of claim 9 wherein the memory devices comprise SDRAMs.

14. The memory module of claim 9 wherein the reception interfaces include optical interfaces to receive data words from an optical communications link.

15. The memory module of claim 14 wherein the downstream reception interface and the upstream transmission interface are configured to be coupled to the same optical communications link, and wherein the downstream transmission interface and the upstream reception interface are configured to be coupled to the same optical communications link.

16. The memory module of claim 15 wherein the optical communications link comprises an optical fiber.

17. A memory system, comprising: a plurality of memory modules coupled in series, each module being coupled to adjacent modules through respective downstream and upstream high-speed communications links, each memory module comprising: a plurality of memory devices; and a memory hub, comprising: a downstream reception interface operable in an initialization mode to adjust a phase of a generated receive clock signal relative to applied test data signals and to generate an inversion signal once a final phase of the generated receive clock signal is determined, and operable in an enablement mode responsive to receiving an enablement command to generate an enablement signal and to place the downstream reception interface in the normal mode of operation; a downstream transmission interface operable in the initialization mode to apply test data signals on an output and operable to adjust the value of the test data signals responsive to the inversion signal from the downstream reception interface, and operable in the enablement mode responsive to the enablement signal from the downstream reception interface to provide the enablement command on the output and to place the downstream transmission interface into the normal mode of operation; an upstream reception interface operable in the initialization mode to adjust a phase of the generated receive clock signal relative to applied test data signals and to generate an inversion signal once a final phase of the generated receive clock signal is determined, and operable in an enablement mode responsive to receiving an enablement command to generate an enablement signal and to place the upstream reception interface into the normal mode of operation; an upstream transmission interface operable in the initialization mode to apply test data signals on an output and operable to adjust the value of the test data signals responsive to the inversion signal from the upstream reception interface, and operable in the enablement mode responsive to the enablement signal from the upstream reception interface to provide the enablement command on the output and to place the upstream transmission interface into the normal mode of operation; and local hub circuitry coupled to the interfaces and to the memory devices; and a system controller coupled to a first one of the memory modules through respective downstream and upstream high-speed communications links.

18. The memory system of claim 17 wherein the system controller further comprises: a downstream transmission interface coupled to the downstream high-speed communications link, the interface operable in the initialization mode to apply test data signals on an output and operable to adjust the value of the test data signals responsive to an inversion signal, and operable in the enablement mode responsive to an enablement signal to provide an enablement command on the output and to place the downstream transmission interface into the normal mode of operation; and an upstream reception interface coupled to the upstream high-speed communications link, the interface operable in the initialization mode to adjust a phase of a generated receive clock signal relative to applied test data signals and to generate the inversion signal once a final phase of the generated receive clock signal is determined, and operable in an enablement mode responsive to receiving an enablement command to generate an enablement signal and to place the upstream reception interface into the normal mode of operation, and further operable responsive to receiving the enablement command to generate a ready signal indicating all the memory modules have been synchronized.

19. The memory system of claim 17 wherein the enablement command comprises a No Operation command.

20. The memory system of claim 17 wherein the downstream and upstream transmission interfaces adjust the value of the corresponding test data signals responsive to the inversion signal by inverting the test data signals.

21. The memory system of claim 17 wherein the memory signals comprise address, data, and control signals.

22. The memory system of claim 17 wherein the memory devices comprise SDRAMs.

23. The memory system of claim 17 wherein the reception interfaces include optical interfaces to receive data words from an optical communications link.

24. The memory system of claim 23 wherein in each memory module the downstream reception interface and the upstream transmission interface are coupled to the same optical communications link, and wherein the downstream transmission interface and the upstream reception interface are coupled to the same optical communications link.

25. The memory system of claim 24 wherein the optical communications link comprises an optical fiber.

26. A computer system, comprising: a processor; a system controller coupled to the processor through respective downstream and upstream high-speed communications links; a memory system, comprising: a plurality of memory modules coupled in series, each module being coupled to adjacent modules through respective downstream and upstream high-speed communications links, and a first one of the modules being coupled to the processor through respective downstream and upstream high-speed communications links, each memory module comprising: a plurality of memory devices; and a memory hub, comprising: a downstream reception interface operable in an initialization mode to adjust a phase of a generated receive clock signal relative to applied test data signals and to generate an inversion signal once a final phase of the generated receive clock signal is determined, and operable in an enablement mode responsive to receiving an enablement command to generate an enablement signal and to place the downstream reception interface in the normal mode of operation; a downstream transmission interface operable in the initialization mode to apply test data signals on an output and operable to adjust the value of the test data signals responsive to the inversion signal from the downstream reception interface, and operable in the enablement mode responsive to the enablement signal from the downstream reception interface to provide the enablement command on the output and to place the downstream transmission interface into the normal mode of operation; an upstream reception interface operable in the initialization mode to adjust a phase of the generated receive clock signal relative to applied test data signals and to generate an inversion signal once a final phase of the generated receive clock signal is determined, and operable in an enablement mode responsive to receiving an enablement command to generate an enablement signal and to place the upstream reception interface into the normal mode of operation; an upstream transmission interface operable in the initialization mode to apply test data signals on an output and operable to adjust the value of the test data signals responsive to the inversion signal from the upstream reception interface, and operable in the enablement mode responsive to the enablement signal from the upstream reception interface to provide the enablement command on the output and to place the upstream transmission interface into the normal mode of operation; and local hub circuitry coupled to the interfaces and to the memory devices.

27. The computer system of claim 26 wherein the system controller further comprises: a downstream transmission interface coupled to the downstream high-speed communications link, the downstream transmission interface operable in the initialization mode to apply test data signals on an output and operable to adjust the value of the test data signals responsive to an inversion signal, and operable in the enablement mode responsive to an enablement signal to provide an enablement command on the output and to place the downstream transmission interface into the normal mode of operation; and an upstream reception interface coupled to the upstream high-speed communications link, the upstream reception interface operable in the initialization mode to adjust a phase of a generated receive clock signal relative to applied test data signals and to generate the inversion signal once a final phase of the generated receive clock signal is determined, and operable in an enablement mode responsive to receiving an enablement command to generate an enablement signal and to place the upstream reception interface into the normal mode of operation, and further operable responsive to receiving the enablement command to generate a ready signal indicating all the memory modules have been synchronized.

28. The memory system of claim 26 wherein the enablement command comprises a No Operation command.

29. The computer system of claim 26 wherein the memory devices comprise SDRAMs.

30. The computer system of claim 26 wherein each of the high-speed links comprises an optical communications link.

31. The computer system of claim 26 wherein the processor comprises a central processing unit (CPU).

TECHNICAL FIELD

This invention relates to computer systems, and, more particularly, to a computer system including a system memory having a memory hub architecture.

BACKGROUND OF THE INVENTION

Computer systems use memory devices, such as dynamic random access memory (“DRAM”) devices, to store data that are accessed by a processor. These memory devices are normally used as system memory in a computer system. In a typical computer system, the processor communicates with the system memory through a processor bus and a memory controller. The processor issues a memory request, which includes a memory command, such as a read command, and an address designating the location from which data or instructions are to be read. The memory controller uses the command and address to generate appropriate command signals as well as row and column addresses, which are applied to the system memory. In response to the commands and addresses, data are transferred between the system memory and the processor. The memory controller is often part of a system controller, which also includes bus bridge circuitry for coupling the processor bus to an expansion bus, such as a PCI bus.

Although the operating speed of memory devices has continuously increased, this increase in operating speed has not kept pace with increases in the operating speed of processors. Even slower has been the increase in operating speed of memory controllers coupling processors to memory devices. The relatively slow speed of memory controllers and memory devices limits the data bandwidth between the processor and the memory devices.

In addition to the limited bandwidth between processors and memory devices, the performance of computer systems is also limited by latency problems that increase the time required to read data from system memory devices. More specifically, when a memory device read command is coupled to a system memory device, such as a synchronous DRAM (“SDRAM”) device, the read data are output from the SDRAM device only after a delay of several clock periods. Therefore, although SDRAM devices can synchronously output burst data at a high data rate, the delay in initially providing the data can significantly slow the operating speed of a computer system using such SDRAM devices.

One approach to alleviating the memory latency problem is to use multiple memory devices coupled to the processor through a memory hub. In a memory hub architecture, a system controller or memory controller is coupled over a high speed link to several memory modules. Typically, the memory modules are coupled in a point-to-point or daisy chain architecture such that the memory modules are connected one to another in series. Thus, the memory controller is coupled to a first memory module over a first high speed link, with the first memory module connected to a second memory module through a second high speed link, and the second memory module coupled to a third memory module through a third high speed link, and so on in a daisy chain fashion.

Each memory module includes a memory hub that is coupled to the corresponding high speed links and a number of memory devices on the module, with the memory hubs efficiently routing memory requests and memory responses between the controller and the memory devices over the high speed links. Computer systems employing this architecture can have a higher bandwidth because a processor can access one memory device while another memory device is responding to a prior memory access. For example, the processor can output write data to one of the memory devices in the system while another memory device in the system is preparing to provide read data to the processor. Moreover, this architecture also provides for easy expansion of the system memory without concern for degradation in signal quality as more memory modules are added, such as occurs in conventional multi drop bus architectures.

Signals are transferred over the high speed links at very high rates, with the links being optical, radio frequency, or other suitable high speed communications media. As the data transfer rate increases, the duration for which each signal being transferred over the high speed link is valid decreases by a corresponding amount, as will be understood by one skilled in the art. More specifically, the data window or “data eye” for each of the signals decreases as the data transfer rate increases. As understood by those skilled in the art, the data eye for each of the signals defines the actual duration for which each signal is valid after timing skew, jitter, duty cycle variation, and other types of unwanted signal distortion are considered. Signal distortion can arise from a variety of sources, such as different loading on the lines of the link and the physical lengths of such lines.

In a conventional system memory, to synchronize memory devices coupled to a memory controller the controller enters an initialization or synchronization mode of operation and applies a test data pattern to the memory devices. Typically, the controller thereafter adjusts the phase of the data strobe signal relative to the signals forming the test data pattern and determines limits for phase shifts of the data strobe signal that allow the memory device to successfully capture the data signals. A phase shift within the determined limits is then selected for use during normal operation of the controller and memory device. In the conventional system memory, each memory device is coupled to the controller over a common memory bus. Conversely, in a memory hub system having a daisy-chain configuration not every memory hub is coupled directly to the controller. The controller does not directly communicate with each memory hub in a memory hub system having more than one memory hub, and therefore the controller cannot synchronize the memory hubs in the same way as in a conventional system memory.

There is a need for a system and method of synchronizing memory hubs in a system memory having a memory hub architecture.

SUMMARY OF THE INVENTION

According to one aspect of the present invention, a method is disclosed for synchronizing communications links in a memory hub system. The memory hub system includes a system controller and a plurality of memory hubs coupled in series, with pairs of downstream and upstream links being coupled between adjacent modules and the controller. The method includes synchronizing each upstream and downstream link. In a clockwise order starting with the downstream link coupled between the controller and the first memory module, the next adjacent clockwise link is signaled that the prior clockwise link has been synchronized. The method then detects through the upstream link coupled between the controller and the first memory module when all links have been synchronized. In a clockwise order starting with the downstream link coupled between the controller and the first memory module, each link is enabled. The method then detects through the upstream link coupled between the controller and the first memory module when all links have been enabled.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram of a computer system including a system memory having a high-bandwidth memory hub architecture according to one example of the present invention.

FIG. 2 is a block diagram illustrating in more detail the memory hubs contained in the memory modules in the system memory of FIG. 1 according to one example of the present invention.

FIG. 3 is a functional diagram illustrating the operation of the system controller and the memory modules of FIG. 2 during an initialization stage of a synchronization process according to one embodiment of the present invention.

FIG. 4 is a functional diagram illustrating the operation of the system controller and memory modules of FIG. 2 during an enablement stage of a synchronization process according to one embodiment of the present invention.

DETAILED DESCRIPTION OF THE INVENTION

A computer system 100 according to one example of the present invention is shown in FIG. 1. The computer system 100 includes a system memory 102 having a memory hub architecture that executes an initialization or synchronization process to synchronize a plurality of memory hubs 140 contained in a plurality of memory modules 130, as will be explained in more detail below. In the following description, certain details are set forth to provide a sufficient understanding of the present invention. One skilled in the art will understand, however, that the invention may be practiced without these particular details. In other instances, well-known circuits, control signals, timing protocols, and/or software operations have not been shown in detail or omitted entirely in order to avoid unnecessarily obscuring the present invention.

The computer system 100 includes a processor 104 for performing various computing functions, such as executing specific software to perform specific calculations or tasks. The processor 104 is typically a central processing unit (“CPU”) having a processor bus 106 that normally includes an address bus, a control bus, and a data bus. The processor bus 106 is typically coupled to a cache memory 108, which is usually static random access memory (“SRAM”). Finally, the processor bus 106 is coupled to a system controller 110, which is also sometimes referred to as a “North Bridge” or “memory controller.”

The system controller 110 serves as a communications path to the processor 104 for the memory modules 130 and for a variety of other components. More specifically, the system controller 110 includes a graphics port that is typically coupled to a graphics controller 112, which is, in turn, coupled to a video terminal 114. The system controller 110 is also coupled to one or more input devices 118, such as a keyboard or a mouse, to allow an operator to interface with the computer system 100. Typically, the computer system 100 also includes one or more output devices 120, such as a printer, coupled to the processor 104 through the system controller 110. One or more data storage devices 124 are also typically coupled to the processor 104 through the system controller 110 to allow the processor 104 to store data or retrieve data from internal or external storage media (not shown). Examples of typical storage devices 124 include hard and floppy disks, tape cassettes, and compact disk read-only memories (CD-ROMs).

The system controller 110 is coupled to the system memory 102 including the memory modules 130a,b . . . n, and operates to apply commands to control and access data in the memory modules. The system controller 110 also initiates a synchronization mode of operation of the controller and memory modules 130, as will be explained in more detail below. The memory modules 130 are coupled in a point-to-point or daisy chain architecture through respective high speed links 134 coupled between the modules and the system controller 110. The high-speed links 134 may be optical, RF, or electrical communications paths, or may be some other suitable type of communications paths, as will be appreciated by those skilled in the art. In the event the high-speed links 134 are implemented as optical communications paths, each optical communication path may be in the form of one or more optical fibers, for example. In such a system, the system controller 110 and the memory modules 130 will each include an optical input/output port or separate input and output ports coupled to the corresponding optical communications paths. Although the memory modules 130 are shown coupled to the system controller 110 in a daisy architecture, other topologies that may be used, such as a ring topology, will be apparent to those skilled in the art.

Each of the memory modules 130 includes the memory hub 140 for communicating over the corresponding high-speed links 134 and for controlling access to six memory devices 148, which are synchronous dynamic random access memory (“SDRAM”) devices in the example of FIG. 1. The memory hubs 140 each include input and output interfaces or ports that are coupled to the corresponding high-speed links 134, with the nature and number of ports depending on the characteristics of the high-speed links. A fewer or greater number of memory devices 148 may be used, and memory devices other than SDRAM devices may also be used. The memory hub 140 is coupled to each of the system memory devices 148 through a bus system 150, which normally includes a control bus, an address bus, and a data bus.

FIG. 2 is a block diagram illustrating in more detail the memory hubs in the memory modules 130a and 130b and link interface components in the system controller 110. In the memory module 130a, the memory hub 140 includes a link interface 200 that is connected to the high-speed link 134 coupled to the system controller 110. The link interface 200 includes a downstream physical reception port 202 that receives downstream memory requests from the system controller 110 over a downstream high-speed link 204, and includes an upstream physical transmission port 206 that provides upstream memory responses to the system controller over an upstream high-speed link 208. The downstream and upstream high-speed links 204, 208 collectively form the corresponding high-speed link 134.

The system controller 110 includes a downstream physical transmission port 210 coupled to the downstream high-speed link 204 to provide memory requests to the memory module 130a, and also includes an upstream physical reception port 212 coupled to the upstream high-speed link 208 to receive memory responses from the memory module 130a. The ports 202, 206, 210, 212 and other ports to be discussed below are designated “physical” interfaces or ports since these ports are in what is commonly termed the “physical layer” of a communications system. In this case, the physical layer corresponds to components providing the actual physical connection and communications between the system controller 110 and system memory 102 (FIG. 1), as will be understood by those skilled in the art.

The nature of the physical reception ports 202, 212 and physical transmission ports 206, 210 will depend upon the characteristics of the high-speed links 204, 208. For example, in the event the high-speed links 204, 208 are implemented using optical communications paths, the reception ports 202, 212 will convert optical signals received through the optical communications path into electrical signals and the transmission ports will convert electrical signals into optical signals that are then transmitted over the corresponding optical communications path.

In operation, the physical reception port 202 captures the downstream memory requests and provides the captured memory request to local hub circuitry 214, which includes control logic for processing the request and accessing the memory devices 148 over the bus system 150 to provide the corresponding data when the request packet is directed to the memory module 130a. The local hub circuitry 214 also provides the captured downstream memory request to a downstream physical transmission port 216. The downstream physical transmission port 216, in turn, provides the memory request over the corresponding downstream high-speed link 204 to a downstream physical reception port 202 in the adjacent downstream memory module 130b. The port 202 in module 130b operates in the same way as the corresponding port in the module 130a, namely to capture the memory request and provide the request to local hub circuitry 214, which processes the request and provides the request to a downstream physical transmission port 216. The port 216 in the module 130b then operates in the same way as the corresponding port in module 130a to provide the memory request over the corresponding downstream high-speed link 204 to the next downstream memory module 130c (not shown in FIG. 2).

The memory hub 140 in the module 130a further includes an upstream physical reception port 218 that receives memory responses over the corresponding upstream high-speed link 208 from an upstream physical transmission port 206 in the module 130b. The reception port 218 captures the received memory responses and provides them to the local hub circuitry 214, which stores the responses and provides the responses to the upstream physical transmission port 206, or the responses may be directed to the upstream physical transmission on the bypass bus, if the transmission port is not processing hub local responses. The upstream physical transmission port 206, in turn, provides the response over the upstream high-speed link 208 to the upstream physical reception port 212 in the system controller 212. Each of the memory modules 130 includes a corresponding downstream physical reception port 202, upstream physical transmission port 206, downstream physical transmission port 216, and upstream physical reception port 218. Moreover, these ports 202, 206, 216, 218 in each module 130 operate in the same way as just described for the corresponding ports in the module 130a.

During a synchronization mode of operation, the system controller 110 and the ports 202, 206, 216, and 218 operate to synchronize each of the downstream high-speed links 204 and upstream high-speed links 208, as will now be described in more detail with reference to FIGS. 3 and 4. Briefly, the synchronization process includes two stages, an initialization stage and an enablement stage. In the initialization stage, the transmission-reception port pairs associated with each high-speed link 204, 208 are synchronized, and the system controller 110 is notified when all such pairs have been synchronized. When the system controller 110 is notified the initialization stage has been completed, the enablement stage commences and the reception and transmission ports in the controller 110 and modules 130 are sequentially enabled to start receiving and transmitting functional operations. A transmission-reception port pair is the pair of ports associated with a particular high-speed link 204, 208, and thus, for example, the ports 210 and port 202 in module 130a are a transmission-reception port pair, as are the port 216 in module 130a and the port 202 in module 130b, and so on. The link 204 or 208 and the corresponding transmission-reception port pair may be collectively referred to simply as a “link” in the following description.

FIG. 3 is a functional diagram illustrating the operation of the system controller 110 and the memory modules 130a and 130b during the initialization stage of operation. In the example of FIG. 3, the system memory 102 is assumed to include only the two memory modules 130a and 130b for ease of explanation, and from this example description one skilled in the art will readily understand the operation in the initialization stage when the system memory 102 includes additional memory modules. In FIG. 3, the ports 210 and 212 in the system controller 110 and ports 202, 206, 216, 218 in the modules 130a, 130b have been designated using new identifiers to simplify the description of the initialization stage of operation. More specifically, the transmission port 210 and reception port 212 in the system controller 110 have been designated TXP-SC and RXP-SC, respectively, where the “SC” indicates the ports are contained in the controller and “TX” indicates a transmission port and “RX” a reception port. The downstream physical reception port 202 in modules 130a and 130b have been designated DRXP-A and DRXP-B, respectively, where the “A” and “B” indicate the ports are contained in the modules 130a and 130b, respectively, and the “U” indicates an upstream port. Similarly, the upstream physical transmission ports 206 in the modules 130a and 130b are designated UTXP-A and UTXP-B, respectively. The downstream physical transmission port 216 in module 130a is designated DTXP-A where the “D” indicates a downstream port. The upstream physical reception port 218 in module 130a is designated URXP-A. Note that since the module 130b is the last module in the example of FIG. 3, the ports 216, 218 in this module are not utilized and are thus not shown in FIG. 3.

To start the synchronization process, the system controller 110 and memory modules 130a, 130b are placed in an initialization mode of operation. This may occur, for example, upon power up of the computer system 100 (FIG. 1). In the initialization mode, each transmission port TXP-SC, DTXP-A, UTXP-B, UTXP-A and reception port DRXP-A, DRXP-B, URXP-A, RXP-SC pair execute an initialization routine to determine a desired phase shift of a generated receive clock signal relative to test data being sent to the reception port. Thus, the TXP-SC-DRXP-A ports execute an initialization routine, as do the DTXP-A-DRXP-B 202 ports, the UTXP-B-URXP-A ports, and the UTXP-A-RXP-SC ports.

The specific initialization routine executed by each pair may vary. In one embodiment, each transmission port TXP-SC, DTXP-A, UTXP-B, UTXP-A applies test data TD to the corresponding reception port DRXP-A, DRXP-B, URXP-A, RXP-SC. The test data may have a variety of different values, and could, for example, be a pseudo random bit pattern. The reception port DRXP-A, DRXP-B, URXP-A, RXP-SC captures the test data responsive to a generated receive clock, and then determines whether the test data was successfully captured. The reception port DRXP-A, DRXP-B, URXP-A, RXP-SC adjusts the phase of the generated receive clock signal relative to the test data and once again determines whether the test data was successfully captured. In this way, the reception port DRXP-A, DRXP-B, URXP-A, RXP-SC “paints” a data eye for the test data by determining limits for the phase shift of the generated receive clock signal that allow the test data to be successfully captured. Once all phase shifts for the generated receive clock signal have been used, the reception port DRXP-A, DRXP-B, URXP-A, RXP-SC selects one of the phase shifts for use during normal operation of the system memory 102.

Because multiple high-speed links 134 must be synchronized, the controller 110 must be able to determine when all links have been successfully synchronized. Accordingly, during the initialization stage of operation, once the RXP-SC port has painted the corresponding data eye and selected the phase of the generated receive clock signal to be used during normal operation, the RXP-SC port applies an invert signal INV to the TXP-SC port. In response to the INV signal, the TXP-SC port inverts the test data being sent to the DRXP-A port, meaning that the bit-wise complement of each test data word being transmitted is now provided by the TXP-SC port. For example, if a 15-bit pseudo random sequence “11101011001000” is applied for each bit of a test data word, the TXP-SC port would provide the complement of this sequence, namely “00010100110111.” This inverted test data is indicated as TD* in FIG. 3.

When the DRXP-A port receives inverted test data TD*, this indicates that the RXP-SC port has been synchronized. Once the DRXP-A port has painted the corresponding data eye and selected the phase of the generated receive clock signal to be used during normal operation (i.e., has been synchronized), the DRXP-A port applies an invert signal INV to the DTXP-A port. In response to the INV signal, the DTXP-A port provides inverted test data TD* to the DRXP-B port, indicating the DRXP-A port has been synchronized. Once the DRXP-B port has been synchronized, the port applies an invert signal INV to the UTXP-B port which, in turn, applies inverted test data TD* to the URXP-A port. The URXP-A port the operates in the same way, and once synchronized applies an invert signal INV to the UTXP-A port, which then applies inverted test data TD* to the RXP-SC port.

When the RXP-SC port receives the inverted test data TD*, the system controller 110 determines that all the transmission-reception port pairs have been synchronized, and the thus all the ports are ready to be placed into a normal mode of operation to allow normal operation of the computer system 100. Accordingly, at this point the controller 110 and system memory 102 enter the enablement stage of the synchronization process, as will now be described in more detail. The term “enablement” is used to indicate that the ports are placed in a normal mode of operation to transfer or receive functional commands in the system memory 102, such as read or write commands from the system controller 110.

FIG. 4 is a functional diagram illustrating the operation of the system controller 110 and memory modules 130 of FIG. 2 during the enablement stage of the synchronization process according to one embodiment of the present invention. As previously mentioned, once the RXP-SC port receives the inverted test data TD* the system controller 110 determines that all the transmission-reception port pairs have been synchronized. More specifically, when the RXP-SC port receives the TD* data, the port applies an active enable signal EN to the TXP-SC port. In response to the enable signal, the TXP-SC port is enabled as indicated by the looped arrow with the EN designation in FIG. 4. Once enabled, the TXP-SC port starts sending no operation or “NOP” commands to the DRXP-A port. A NOP command is a valid command used during normal operation of a memory system but which causes a receiving module to perform no action, as will be understood by those skilled in the art.

Upon receiving the NOP commands from the TXP-SC port, the DRXP-A is enabled and also applies an active enable signal EN to the DTXP-A port. In response to the enable signal, the DTXP-A port is enabled and, in turn, starts sending NOP commands to the DRXP-B port. The DRXP-B port is enabled responsive to the NOP commands, and also provides an active enable signal EN to active the UTXP-B port. Once activated, the UTXP-B port starts sending NOP commands to the URXP-A port, and this port is enabled responsive to the NOP commands. The URXP-A port thereafter applies an active enable signal EN to the UTXP-A port to active this port, which, in turn, starts sending NOP commands to the RXP-SC port in the system controller 110. Upon receiving the NOP commands, the RXP-SC port generates a ready signal RDY, indicating that the synchronization process is now complete and signaling to the controller 110 that normal functional commands such as read and write commands may now be applied to the memory modules 130.

The initialization stage of the synchronization process synchronizes each of the links 204, 208 and the associated transmission-reception port pair. The system controller 110 is notified when all the transmission-reception port pairs have been synchronized. At this point in time, all the ports in the controller 110 and modules 130 may be enabled to allow functional commands to be processed by the system memory 102. The ports may not simply be randomly enabled, however, or erroneous operation of the system memory could result. For example, if the TXP-SC port were simply enabled once the DRXP-A port was synchronized, the controller 110 could then output a functional command through the TXP-SC port. If one of the downstream ports were not enabled, however, then this functional command may not be applied to all memory hubs 140 as desired. For example, if the DTXP-A port was not yet enabled to transmit functional commands (i.e., was still synchronizing the DRXP-B port), then the functional command would not be applied to module 130b as desired. The present synchronization process eliminates this possibility by sequentially enabling the ports in a clockwise manner starting with the TXP-SC port and ending with the RXP-SC port in the controller 110. In this way, downstream links are sequentially enabled starting from the controller 110 and progressing downstream, and upstream links are sequentially enabled starting with the module 130 furthest downstream and ending with the controller.

One skilled in the art will understand suitable circuitry for forming the components of the memory hubs 140, and will understand that the components may be implemented using either digital or analog circuitry, or a combination of both, and also, where appropriate, may be realized through software executing on suitable processing circuitry. Moreover, in the above description the ports are discussed as applying the INV and EN signals to adjacent ports during the synchronization process. These signals may be applied to the adjacent ports through the local hub circuitry 214 or directly as described, as will be appreciate by those skilled in the art. Similarly, some of functionality of the ports may be performed by the local hub circuitry 214. The division of the functionality among one or more components in the hubs 140 is not important so long as the components operate in combination to perform the described functions, as will also be appreciated by those skilled in the art.

In the preceding description, certain details were set forth to provide a sufficient understanding of the present invention. One skilled in the art will appreciate, however, that the invention may be practiced without these particular details. Furthermore, one skilled in the art will appreciate that the example embodiments described above do not limit the scope of the present invention, and will also understand that various equivalent embodiments or combinations of the disclosed example embodiments are within the scope of the present invention illustrative examples set forth above are intended only to further illustrate certain details of the various embodiments, and should not be interpreted as limiting the scope of the present invention. Also, in the description above the operation of well known components has not been shown or described in detail to avoid unnecessarily obscuring the present invention. Finally, the invention is to be limited only by the appended claims, and is not limited to the described examples or embodiments of the invention.