Klein, Dean A. (Eagle, ID, US)

Plaque It!

11/269403

11/04/2008

11/07/2005

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Micron Technology, Inc. (Boise, ID, US)

714/773

714/754, 714/765

H03M13/00; G11C29/00

714/773, 714/754, 714/765

4334295	Memory device	June, 1982	Nagami	365/222
4433211	Privacy communication system employing time/frequency transformation	February, 1984	McCalmont et al.	380/36
4598402	System for treatment of single bit error in buffer storage unit	July, 1986	Matsumoto et al.	371/38
4706249	Semiconductor memory device having error detection/correction function	November, 1987	Nakagawa et al.	371/38
4710934	Random access memory with error correction capability	December, 1987	Traynor	371/38
4766573	Semiconductor memory device with error correcting circuit	August, 1988	Takemae	365/222
4780875	Semiconductor memory with reduced size ECC circuit	October, 1988	Sakai	371/38
4858236	Method for error correction in memory system	August, 1989	Ogasawara	371/38
4862463	Error correcting code for 8-bit-per-chip memory with reduced redundancy	August, 1989	Chen	371/38
4918692	Automated error detection for multiple block memory array chip and correction thereof	April, 1990	Hidaka et al.	371/2.2
4937830	Semiconductor memory device having function of checking and correcting error of read-out data	June, 1990	Kawashima et al.	371/40.1
4958325	Low noise semiconductor memory	September, 1990	Nakagome et al.	365/206
5056089	Memory device	October, 1991	Furuta et al.	371/3
5127014	Dram on-chip error correction/detection	June, 1992	Raynham	371/37.3
5172339	Semiconductor memory device having error checking and correcting circuit and operating method therefor	December, 1992	Noguchi et al.	365/201
5278796	Temperature-dependent DRAM refresh circuit	January, 1994	Tillinghast et al.	365/211
5291498	Error detecting method and apparatus for computer memory having multi-bit output memory circuits	March, 1994	Jackson et al.	371/40.1
5307356	Interlocked on-chip ECC system	April, 1994	Fifield	371/40.1
5313425	Semiconductor memory device having an improved error correction capability	May, 1994	Lee et al.	365/201
5313464	Fault tolerant memory using bus bit aligned Reed-Solomon error correction code symbols	May, 1994	Reiff	371/2.1
5313475	ECC function with self-contained high performance partial write or read/modify/write and parity look-ahead interface scheme	May, 1994	Cromer et al.	371/40.1
5313624	DRAM multiplexer	May, 1994	Harriman et al.	714/6
5321661	Self-refreshing memory with on-chip timer test circuit	June, 1994	Iwakiri et al.	365/222
5335201	Method for providing synchronous refresh cycles in self-refreshing interruptable DRAMs	August, 1994	Walther et al.	365/222
5369651	Multiplexed byte enable bus for partial word writes to ECC protected memory	November, 1994	Marisetty	371/40.1
5418796	Synergistic multiple bit error correction for memory of array chips	May, 1995	Price et al.	371/39.1
5428630	System and method for verifying the integrity of data written to a memory	June, 1995	Weng et al.	371/40.1
5432802	Information processing device having electrically erasable programmable read only memory with error check and correction circuit	July, 1995	Tsuboi	371/40.1
5446695	Memory device with programmable self-refreshing and testing methods therefore	August, 1995	Douse et al.	365/222
5448578	Electrically erasable and programmable read only memory with an error check and correction circuit	September, 1995	Kim	371/40.4
5450424	Semiconductor memory device with error checking and correcting function	September, 1995	Okugaki et al.	371/40.1
5455801	Circuit having a control array of memory cells and a current source and a method for generating a self-refresh timing signal	October, 1995	Blodgett et al.	365/222
5459742	Solid state disk memory using storage devices with defects	October, 1995	Cassidy et al.	371/40.1
5481552	Method and structure for providing error correction code for 8-byte data words on SIMM cards	January, 1996	Aldereguia et al.	371/40.1
5509132	Semiconductor memory device having an SRAM as a cache memory integrated on the same chip and operating method thereof	April, 1996	Matsuda et al.	395/403
5513135	Synchronous memory packaged in single/dual in-line memory module and method of fabrication	April, 1996	Dell et al.	365/52
5515333	Semiconductor memory	May, 1996	Fujita et al.	365/229
5588112	DMA controller for memory scrubbing	December, 1996	Dearth et al.	395/182.07
5600662	Error correction method and apparatus for headers	February, 1997	Zook	371/40.1
5604703	Semiconductor memory device with error check-correction function permitting reduced read-out time	February, 1997	Nagashima	365/200
5623506	Method and structure for providing error correction code within a system having SIMMs	April, 1997	Dell et al.	371/40.1
5629898	Dynamic memory device, a memory module, and a method of refreshing a dynamic memory device	May, 1997	Idei et al.	365/222
5631914	Error correcting apparatus	May, 1997	Kashida et al.	371/37.4
5703823	Memory device with programmable self-refreshing and testing methods therefore	December, 1997	Douse et al.	365/222
5706225	Memory apparatus with dynamic memory cells having different capacitor values	January, 1998	Buchenrieder et al.	365/102
5712861	Error correcting method and decoder with improved reliability	January, 1998	Inoue et al.	714/752
5732092	Method of refreshing flash memory data in flash disk card	March, 1998	Shinohara	371/40.2
5740188	Error checking and correcting for burst DRAM devices	April, 1998	Olarig	371/40.11
5754753	Multiple-bit error correction in computer main memory	May, 1998	Smelser	395/182.06
5761222	Memory device having error detection and correction function, and methods for reading, writing and erasing the memory device	June, 1998	Baldi	371/40.18
5765185	EEPROM array with flash-like core having ECC or a write cache or interruptible load cycles	June, 1998	Lambrache et al.	711/103
5784328	Memory system including an on-chip temperature sensor for regulating the refresh rate of a DRAM array	July, 1998	Irrinki et al.	365/222
5784391	Distributed memory system with ECC and method of operation	July, 1998	Konigsburg	371/40.18
5808952	Adaptive auto refresh	September, 1998	Fung et al.	365/222
5841418	Dual displays having independent resolutions and refresh rates	November, 1998	Bril et al.	345/3
5864569	Method and apparatus for performing error correction on data read from a multistate memory	January, 1999	Roohparvar	371/40.18
5878059	Method and apparatus for pipelining an error detection algorithm on an n-bit word stored in memory	March, 1999	Maclellan	371/40.13
5896404	Programmable burst length DRAM	April, 1999	Kellogg et al.	371/40.11
5912906	Method and apparatus for recovering from correctable ECC errors	June, 1999	Wu et al.	371/40.11
5953278	Data sequencing and registering in a four bit pre-fetch SDRAM	September, 1999	McAdams et al.	365/219
5961660	Method and apparatus for optimizing ECC memory performance	October, 1999	Capps, Jr. et al.	714/763
5963103	Temperature sensitive oscillator circuit	October, 1999	Blodgett	331/75
6009547	ECC in memory arrays having subsequent insertion of content	December, 1999	Jaquette et al.	714/758
6009548	Error correcting code retrofit method and apparatus for multiple memory configurations	December, 1999	Chen et al.	714/762
6018817	Error correcting code retrofit method and apparatus for multiple memory configurations	January, 2000	Chen et al.	714/762
6041001	Method of increasing data reliability of a flash memory device without compromising compatibility	March, 2000	Estakhri	365/200
6041430	Error detection and correction code for data and check code fields	March, 2000	Yamauchi	714/752
6085283	Data selecting memory device and selected data transfer device	July, 2000	Toda	711/104
6085334	Method and apparatus for testing an integrated memory device	July, 2000	Giles et al.	714/7
6092231	Circuit and method for rapid checking of error correction codes using cyclic redundancy check	July, 2000	Sze	714/758
6101614	Method and apparatus for automatically scrubbing ECC errors in memory via hardware	August, 2000	Gonzales et al.	714/6
6125467	Method and apparatus for partial word read through ECC block	September, 2000	Dixon	714/763
6134167	Reducing power consumption in computer memory	October, 2000	Atkinson	365/222
6178537	Method and apparatus for performing error correction on data read from a multistate memory	January, 2001	Roohparvar	714/773
6199139	Refresh period control apparatus and method, and computer	March, 2001	Katayama et al.	711/106
6212118	Semiconductor memory	April, 2001	Fujita	365/222
6212631	Method and apparatus for automatic L2 cache ECC configuration in a computer system	April, 2001	Springer et al.	713/1
6216246	Methods to make DRAM fully compatible with SRAM using error correction code (ECC) mechanism	April, 2001	Shau	714/763
6216247	32-bit mode for a 64-bit ECC capable memory subsystem	April, 2001	Creta et al.	714/763
6219807	Semiconductor memory device having an ECC circuit	April, 2001	Ebihara et al.	714/720
6223309	Method and apparatus for ECC logic test	April, 2001	Dixon et al.	714/703
6233717	Multi-bit memory device having error check and correction circuit and method for checking and correcting data errors therein	May, 2001	Choi	714/805
6262925	Semiconductor memory device with improved error correction	July, 2001	Yamasaki	365/200
6279072	Reconfigurable memory with selectable error correction storage	August, 2001	Williams et al.	711/105
6310825	Data writing method for semiconductor memory device	October, 2001	Furuyama	365/233
6324119	Data input circuit of semiconductor memory device	November, 2001	Kim	365/233
6349068	Semiconductor memory device capable of reducing power consumption in self-refresh operation	February, 2002	Takemae et al.	365/222
6349390	On-board scrubbing of soft errors memory module	February, 2002	Dell et al.	714/6
6353910	Method and apparatus for implementing error correction coding (ECC) in a dynamic random access memory utilizing vertical ECC storage	March, 2002	Carnevale et al.	714/763
6397290	Reconfigurable memory with selectable error correction storage	May, 2002	Williams et al.	711/105
6397357	Method of testing detection and correction capabilities of ECC memory controller	May, 2002	Cooper	714/703
6397365	Memory error correction using redundant sliced memory and standard ECC mechanisms	May, 2002	Brewer et al.	714/766
6438066	Synchronous semiconductor memory device allowing control of operation mode in accordance with operation conditions of a system	August, 2002	Ooishi et al.	365/233
6442644	Memory system having synchronous-link DRAM (SLDRAM) devices and controller	August, 2002	Gustavson et al.	711/105
6457153	Storage device and storage subsystem for efficiently writing error correcting code	September, 2002	Yamamoto et al.	714/763
6484246	High-speed random access semiconductor memory device	November, 2002	Tsuchida et al.	711/169
6510537	Semiconductor memory device with an on-chip error correction circuit and a method for correcting a data error therein	January, 2003	Lee	714/763
6526537	Storage for generating ECC and adding ECC to data	February, 2003	Kishino	714/763
6549460	Memory device and memory card	April, 2003	Nozoe et al.	365/185.09
6556497	Refresh controller and address remapping circuit and method for dual mode full/reduced density DRAMs	April, 2003	Cowles et al.	365/222
6557072	Predictive temperature compensation for memory devices systems and method	April, 2003	Osborn	711/106
6560155	System and method for power saving memory refresh for dynamic random access memory devices after an extended interval	May, 2003	Hush	365/222
6584543	Reconfigurable memory with selectable error correction storage	June, 2003	Williams et al.	711/105
6591394	Three-dimensional memory array and method for storing data bits and ECC bits therein	July, 2003	Lee et al.	714/766
6594796	Simultaneous processing for error detection and P-parity and Q-parity ECC encoding	July, 2003	Chiang	714/800
6601211	Write reduction in flash memory systems through ECC usage	July, 2003	Norman	714/773
6603694	Dynamic memory refresh circuitry	August, 2003	Frankowsky et al.	365/222
6609236	Semiconductor IC device having a memory and a logic circuit implemented with a single chip	August, 2003	Watanabe et al.	716/8
6614698	Method and apparatus for synchronous data transfers in a memory device with selectable data or address paths	September, 2003	Ryan et al.	365/189.04
6618281	Content addressable memory (CAM) with error checking and correction (ECC) capability	September, 2003	Gordon	365/49
6618319	Synchronous semiconductor memory device allowing control of operation mode in accordance with operation conditions of a system	September, 2003	Ooishi et al.	365/233
6628558	Proportional to temperature voltage generator	September, 2003	Fiscus	365/222
6636444	Semiconductor memory device having improved data transfer rate without providing a register for holding write data	October, 2003	Uchida et al.	365/189.05
6636446	Semiconductor memory device having write latency operation and method thereof	October, 2003	Lee et al.	365/194
6646942	Method and circuit for adjusting a self-refresh rate to maintain dynamic data at low supply voltages	November, 2003	Janzen	365/222
6662333	Shared error correction for memory design	December, 2003	Zhang et al.	714/767
6665231	Semiconductor device having pipelined dynamic memory	December, 2003	Mizuno et al.	365/233
6678860	Integrated circuit memory devices having error checking and correction circuits therein and methods of operating same	January, 2004	Lee	714/763
6697926	Method and apparatus for determining actual write latency and accurately aligning the start of data capture with the arrival of data at a memory device	February, 2004	Johnson et al.	711/167
6697992	Data storing method of dynamic RAM and semiconductor memory device	February, 2004	Ito et al.	714/763
6701480	System and method for providing error check and correction in memory systems	March, 2004	Karpuszka et al.	714/764
6704230	Error detection and correction method and apparatus in a magnetoresistive random access memory	March, 2004	DeBrosse et al.	365/201
6715104	Memory access system	March, 2004	Imbert de Tremiolles et al.	714/25
6715116	Memory data verify operation	March, 2004	Lester et al.	714/718
6735726	Method of deciding error rate and semiconductor integrated circuit device	May, 2004	Muranaka et al.	714/708
6751143	Method and system for low power refresh of dynamic random access memories	June, 2004	Morgan et al.	365/222
6754858	SDRAM address error detection method and apparatus	June, 2004	Borkenhagen et al.	714/720
6775190	Semiconductor memory device with detection circuit	August, 2004	Setogawa	365/193
6778457	Variable refresh control for a memory	August, 2004	Burgan	365/222
6781908	Memory having variable refresh control and method therefor	August, 2004	Pelley et al.	365/222
6788616	Semiconductor memory device	September, 2004	Takahashi	365/233
6789209	Semiconductor integrated circuit device	September, 2004	Suzuki et al.	713/401
6792567	System and method for correcting soft errors in random access memory devices	September, 2004	Laurent	714/763
6795362	Power controlling method for semiconductor storage device and semiconductor storage device employing same	September, 2004	Nakai et al.	365/222
6807108	Semiconductor memory device having select circuit	October, 2004	Maruyama et al.	365/189.05
6810449	Protocol for communication with dynamic memory	October, 2004	Barth et al.	710/61
6819624	Latency time circuit for an S-DRAM	November, 2004	Acharya et al.	365/233
6834022	Partial array self-refresh	December, 2004	Derner et al.	365/222
6934199	Memory device and method having low-power, high write latency mode and high-power, low write latency mode and/or independently selectable write latency	August, 2005	Johnson et al.	365/194
6940773	Method and system for manufacturing DRAMs with reduced self-refresh current requirements	September, 2005	Poechmueller	365/222
6965537	Memory system and method using ECC to achieve low power refresh	November, 2005	Klein et al.	365/222
7027337	Memory device and method having low-power, high write latency mode and high-power, low write latency mode and/or independently selectable write latency	April, 2006	Johnson et al.	365/194
7095669	Refresh for dynamic cells with weak retention	August, 2006	Oh	365/222
7096407	Technique for implementing chipkill in a memory system	August, 2006	Olarig	714/768
7117420	Construction of an optimized SEC-DED code and logic for soft errors in semiconductor memories	October, 2006	Yeung et al.	714/763
7171605	Check bit free error correction for sleep mode data retention	January, 2007	White	714/763
20010023496	Storage device and storage subsystem for efficiently writing error correcting code	September, 2001	Yamamoto et al.	714/763
20010029592	Memory sub-system error cleansing	October, 2001	Walker et al.	714/42
20010044917	Memory data verify operation	November, 2001	Lester et al.	714/718
20010052090	Storage device having an error correction function	December, 2001	Mio	714/42
20010052102	Method and apparatus for performing error correction on data read from a multistate memory	December, 2001	Roohparvar	714/773
20020013924	Semiconductor memory device having ECC type error recovery circuit	January, 2002	Yamasoto	714/763
20020029316	Reconfigurable memory with selectable error correction storage	March, 2002	Williams et al.	711/105
20020144210	SDRAM address error detection method and apparatus	October, 2002	Borkenhagen et al.	714/805
20020152444	Multi-cycle symbol level error correction and memory system	October, 2002	Chen et al.	714/785
20020162069	System and method for correcting soft errors in random access memory devices	October, 2002	Laurent	714/763
20020184592	Semiconductor memory device	December, 2002	Koga et al.	714/763
20030009721	Method and system for background ECC scrubbing for a memory array	January, 2003	Hsu et al.	714/773
20030070054	Reconfigurable memory with selectable error correction storage	April, 2003	Williams et al.	711/173
20030093744	Error correcting memory and method of operating same	May, 2003	Leung et al.	714/763
20030097608	System and method for scrubbing errors in very large memories	May, 2003	Rodeheffer et al.	714/7
20030101405	Semiconductor memory device	May, 2003	Shibata	714/763
20030149855	Unbuffered memory system	August, 2003	Shibata et al.	711/200
20030167437	Cache entry error-correcting code (ECC) based at least on cache entry data and memory address	September, 2003	DeSota et al.	714/763
20030191888	Method and system for dynamically operating memory in a power-saving error correction mode	October, 2003	Klein	711/105
20040008562	Semiconductor memory device	January, 2004	Ito et al.	365/223
20040064646	Multi-port memory controller having independent ECC encoders	April, 2004	Emerson et al.	711/131
20040083334	Method and apparatus for managing the integrity of data in non-volatile memory system	April, 2004	Chang et al.	711/103
20040098654	FIFO memory with ECC function	May, 2004	Cheng et al.	714/758
20040117723	Error correction scheme for memory	June, 2004	Foss	714/805
20040225944	Systems and methods for processing an error correction code word for storage in memory components	November, 2004	Brueggen	714/758
20050099868	Refresh for dynamic cells with weak retention	May, 2005	Oh	365/222
20080092016	Memory system and method using partial ECC to achieve low power refresh and fast access to data	April, 2008	Pawlowski	714/764
20080109705	Memory system and method using ECC with flag bit to identify modified data	May, 2008	Pawlowski et al.	714/767

Stojko, J. et al., “Error-Correction Code”, IBM Technical Disclosure Bulletin, vol. 10, No. 10, Mar. 1968.

Torres, Joseph D.

Dorsey & Whitney LLP

CROSS-REFERENCE TO RELATED APPLICATION

This application is a divisional of pending U.S. patent application Ser. No. 10/839,942, filed May 6, 2004.

I claim:

1. A memory controller, comprising: a refresh shadow counter that is operable to output a row address; a least one inverter coupled to receive at least one of bit of the row address from the refresh shadow counter, the at least one inverter being operable to invert the at least one bit of the row address from the refresh counter to provide at least one inverted bit; a failing address comparator storing row addresses corresponding to rows of memory cells in a memory device that may contain at least one operational memory cell that is prone to error, the failing address comparator being coupled to the refresh shadow counter and to an output of the inverter to receive the row address from the refresh shadow counter and the at least one inverted bit, the failing address comparator being operable to substitute the at least one inverted bit for at least one corresponding bit in the row address from the refresh shadow counter to provide a comparison row address and to compare the comparison row address to the stored row address and to generate an indicating signal responsive to a predetermined relationship between the comparison row address and one of the stored row addresses; and a memory control circuit coupled to receive the indicating signal from the failing address comparator, the memory control circuit being operable to output the stored row address having the predetermined relationship with the comparison row address, the memory control circuit further being operable to output refresh command signals responsive to the indicating signal.

2. The memory controller of claim 1, further comprising: an ECC generator coupled to receive write data and to generate respective ECC syndrome bits corresponding to the write data; and an ECC checker coupled to receive read data along with corresponding stored ECC syndrome bits, the ECC checker being operable to detect if the read data are in error based on the ECC syndrome bits corresponding to the read data, the ECC checker being operable to output an error signal responsive to detecting a read data error.

3. The memory controller of claim 1, further comprising a refresh timer coupled to the memory control circuit, the refresh time being operable to periodically generate a trigger signal that causes the memory control circuit to output command signals corresponding to an auto-refresh command.

TECHNICAL FIELD

This invention relates to dynamic random access memory (“DRAM”) devices and controllers for such memory device, and, more particularly, to a method and system for controlling the operation of a memory controller, a memory module or a DRAM to manage the rate at which data bits stored in the DRAM are lost during refresh.

BACKGROUND OF THE INVENTION

As the use of electronic devices, such as personal computers, continue to increase, it is becoming ever more important to make such devices portable. The usefulness of portable electronic devices, such as notebook computers, is limited by the limited length of time batteries are capable of powering the device before needing to be recharged. This problem has been addressed by attempts to increase battery life and attempts to reduce the rate at which such electronic devices consume power.

Various techniques have been used to reduce power consumption in electronic devices, the nature of which often depends upon the type of power consuming electronic circuits that are in the device. For example, electronic devices, such a notebook computers, typically include dynamic random access memory (“DRAM”) devices that consume a substantial amount of power. As the data storage capacity and operating speeds of DRAM devices continues to increase, the power consumed by such devices has continued to increase in a corresponding manner.

In general, the power consumed by a DRAM increases with both the capacity and the operating speed of the DRAM devices. The power consumed by DRAM devices is also affected by their operating mode. A DRAM, for example, will generally consume a relatively large amount of power when the memory cells of the DRAM are being refreshed. As is well-known in the art, DRAM memory cells, each of which essentially consists of a capacitor, must be periodically refreshed to retain data stored in the DRAM device. Refresh is typically performed by essentially reading data bits from the memory cells in each row of a memory cell array and then writing those same data bits back to the same cells in the row. A relatively large amount of power is consumed when refreshing a DRAM because rows of memory cells in a memory cell array are being actuated in the rapid sequence. Each time a row of memory cells is actuated, a pair of digit lines for each memory cell are switched to complementary voltages and then equilibrated. As a result, DRAM refreshes tends to be particularly power-hungry operations. Further, since refreshing memory cells must be accomplished even when the DRAM is not being used and is thus inactive, the amount of power consumed by refresh is a critical determinant of the amount of power consumed by the DRAM over an extended period. Thus many attempts to reduce power consumption in DRAM devices have focused on reducing the rate at which power is consumed during refresh.

Refresh power can, of course, be reduced by reducing the rate at which the memory cells in a DRAM are being refreshed. However, reducing the refresh rate increases the risk of data stored in the DRAM memory cells being lost. More specifically, since, as mentioned above, DRAM memory cells are essentially capacitors, charge inherently leaks from the memory cell capacitors, which can change the value of a data bit stored in the memory cell over time. However, current leaks from capacitors at varying rates. Some capacitors are essentially short-circuited and are thus incapable of storing charge indicative of a data bit. These defective memory cells can be detected during production testing, and can then be repaired by substituting non-defective memory cells using conventional redundancy circuitry. On the other hand, current leaks from most DRAM memory cells at much slower rates that span a wide range. A DRAM refresh rate is chosen to ensure that all but a few memory cells can store data bits without data loss. This refresh rate is typically once every 64 ms. The memory cells that cannot reliably retain data bits at this refresh rate are detected during production testing and replaced by redundant memory cells. However, the rate of current leakage from DRAM memory cells can change after production testing, both as a matter of time and from subsequent production steps, such as in packaging DRAM chips. Current leakage, and hence the rate of data loss, can also be effected by environmental factors, such as the temperature of DRAM devices. Therefore, despite production testing, a few memory cells will typically be unable to retain stored data bits at normal refresh rates.

One technique that has been used to reduce prevent data errors during refresh is to generate an error correcting code “ECC” from each item of stored data, and then store the ECC along with the data. A computer system 10 employing typical ECC techniques is shown in FIG. 1. The computer system 10 includes a central processor unit (“CPU”) 14 coupled to a system controller 16 through a processor bus 18 . The system controller 16 is coupled to input/output (“I/O”) devices (not shown) through a peripheral bus 20 and to an I/O controller 24 through an expansion bus 26 . The I/O controller 24 is also connected to various peripheral devices (not shown) through an I/O bus 28 .

The system controller 16 includes a memory controller 30 that is coupled to several memory modules 32 a - c through an address bus 36 , a control bus 38 , a syndrome bus 40 , and a data bus 42 . Each of the memory modules 32 a - c includes several DRAM devices (not shown) that store data and an ECC. The data are coupled through the data bus 42 to and from the memory controller 30 and locations in the DRAM devices mounted on the modules 32 a - c . The locations in the DRAM devices to which data are written and data are read are designated by addresses coupled to the memory modules 32 a - c on the address bus 36 . The operation of the DRAM devices in the memory modules 32 a - c are controlled by control signals coupled to the memory modules 32 a - c on the control bus 38 .

In operation, when data are to be written to the DRAM devices in the memory modules 32 a - c , the memory controller 30 generates an ECC, and then couples the ECC and the write data to the memory modules 32 a - c through the syndrome bus 40 and the data bus 42 , respectively, along with control signals coupled through the control bus 38 and a memory address coupled through the address bus 36 . When the store data are to be read from the DRAM devices in the memory modules 32 a - c , the memory controller 30 applies to the memory modules 32 a - c control signals through the control bus 38 and a memory address 36 through the address bus. Read data and the corresponding syndrome are then coupled from the memory modules 32 a - c to the memory controller 30 through the data bus 42 and syndrome bus 40 , respectively. The memory controller 30 then uses the ECC to determine if any bits of the read data are in error, and, if not too many bits are in error, to correct the read data.

One example of a conventional memory controller 50 is shown in FIG. 2. The operation of the memory controller 50 is controlled by a memory control state machine 54 , which outputs control signals on the control bus 38 . The state machine 54 also outputs a control signal to an address multiplexer 56 that outputs an address on the address bus 36 . The most significant or upper bits of an address are coupled to a first port the multiplexer 56 on an upper address bus 60 , and the least significant or lower bits of an address are coupled to a second port of the multiplexer 56 on a lower address bus 62 . The upper and lower address buses 60 , 62 , respectively are coupled to an address bus 18 A portion of the processor bus 18 (FIG. 1).

A data bus portion 18 D of the processor bus 18 on which write data are coupled is connected to a buffer/transceiver 70 and to an ECC generator 72 . A data bus portion 18 D′ on which read data are coupled is connected to an ECC check/correct circuit 74 . In practice, both data bus portions 18 D and 18 D′ comprise a common portion of the processor bus 18 , but they are illustrated as being separate in FIG. 2 for purposes of clarity. The ECC generator 72 generates an ECC from the write data on bus 18 D, and couples the syndrome to the buffer transceiver through an internal ECC syndrome bus 74 . The ECC check/correct circuit 76 receives read data from the buffer transceiver 70 through an internal read bus 78 and a syndrome through an internal ECC syndrome bus 80 . The buffer/transceiver 70 applies the syndrome received from the ECC generator 72 to the memory modules 32 a - c (FIG. 1) through the syndrome bus 40 . The buffer/transceiver 70 couples the syndrome to the memory modules 32 a - c along with the write data, which are coupled through the data bus 42 . The buffer/transceiver 70 also couples read data from the data bus 42 and a syndrome from the syndrome bus 40 to the ECC check/correct circuit 76 . The ECC check/correct circuit 76 then determines whether or not any of the bits of the read data are in error. If the ECC's check/correct circuit 76 determines that any of the bits of the read data are in error, it corrects those bits as long as a sufficiently low number of bits are in error that they can be corrected. As is well-known in the art, the number of bits in the syndrome determines the number of bits of data that can be corrected. The uncorrected read data, if no error was detected, or the corrected read data, if an error was detected, are then coupled through the data bus 18 D′. In the event a correctable error was found, the ECC check/correct circuit 76 generates a read error R_ERROR signal, which is coupled to the memory control state machine 54 . If, however, too many bits of the read data were in error to be corrected, the ECC check/correct circuit 76 generates a fatal error F_ERROR signal, which is coupled to the CPU 14 (FIG. 1).

The memory controller 50 also includes a refresh timer 84 that schedules a refresh of the DRAM devices in the memory modules 32 a - c at a suitable rate, such as once every 64 ms. The refresh timer 84 periodically outputs a refresh trigger signal on line 88 that causes the memory control state machine 54 to issue an auto refresh command on the control bus 38 .

The use of ECCs in the memory controller 50 shown in FIG. 2 can significantly improve the reliability of data stored in the DRAM devices in the memory modules 32 a - c . Furthermore, the refresh timer 84 can cause the DRAMs to be refreshed at a slower refresh rate since resulting data bit errors can be corrected. The use of a slower refresh rate can provide the significant advantage of reducing the power consumed by the DRAM. However, the use of ECCs requires that a significant portion of the DRAM storage capacity be used to store the ECCs, thus effectively reducing the storage capacity of the DRAM. Further, the use of ECCs can reduce the rate at the DRAM can be refreshed because the ECC must be used to check and possibly correct each item of data read from the DRAM during refresh. Furthermore, the need to perform ECC processing on read data all during refresh can consume a significant amount of power. Also, if the ECCs are not used during normal operation, it is necessary to refresh the DRAM array at the normal refresh rate while checking the entire array for data errors and correcting any errors that are found before switching to the normal operating mode.

There is therefore a need for a method and system that eliminates or corrects data storage errors produced during refresh of a DRAM either without the use of ECCs or without the need to repetitively correct data errors with ECCs.

SUMMARY OF THE INVENTION

A system and method for refreshing rows of dynamic random access memory cells avoids data loss even though some of the memory cells are operational but prone to errors during refresh. The system and method refreshes the rows of memory cells that do not contain any error-prone memory cells at a first rate, and they refresh the rows of memory cells that contain at least one error-prone memory cell at a second rate that is higher than the first rate. The rows containing an error-prone memory cell are preferably refreshed at a more rapid rate by detecting when a row of memory cells is refreshed that has a row address that is offset from the row containing an error-prone memory cell by a predetermined quantity of rows, such as half. After detecting the row of memory cells is being refreshed, the row containing at least one error-prone memory cell is refreshed. The rows of memory cells containing at least one error-prone memory cell are detected by writing data to the memory cells in the dynamic random access memory. Following a refresh of the memory cells, the data stored in the memory cells are read to detect data read errors. These data read errors may be detected by storing error correcting codes along with the data, which are then read and processed to identify and correct the read data errors.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram of a conventional computer system.

FIG. 2 is a block diagram of a conventional memory controller that may be used in the computer system of FIG. 1.

FIG. 3 is a block diagram of a computer system according to one embodiment of the invention.

FIG. 4 is a block diagram of a memory controller according to one embodiment of the invention that may be used in the computer system of FIG. 3.

FIG. 5 is a flow chart showing a procedure for transferring error-prone row addresses from a memory module to the memory controller of FIG. 4 and for storing the error-prone row addresses in the memory controller.

FIG. 6 is a flow chart showing a procedure identifying error-prone row addresses and for storing information about the error-prone row addresses in a memory module.

FIG. 7 is a schematic diagram illustrating the manner in which the memory controller of FIG. 3 may insert extra refreshes of rows containing at least one error-prone memory cell.

FIG. 8 is a block diagram of a computer system according to another embodiment of the invention.

FIG. 9 is a block diagram of a computer system according to still another embodiment of the invention.

DETAILED DESCRIPTION

One embodiment of a computer system 100 according to one embodiment of the invention is shown in FIG. 3. The computer system 100 uses many of the same components that are used in the conventional computer system 10 of FIG. 1. Therefore, in the interest of brevity, these components have been provided with the same reference numerals, and an explanation of their operation will not be repeated. The computer system 100 of FIG. 3 differs from the computer system 10 of FIG. 1 by including memory modules 102 a - c that each include a non-volatile memory 110 a - c , respectively (only 110 a is shown in FIG. 3). The non-volatile memories 110 a - c store row addresses identifying rows containing one or more memory cells in the DRAM devices in the respective modules 102 a - c that are prone to errors because they discharge at a relatively high rate. The computer system 100 also differs from the computer system 10 of FIG. 1 by including circuitry that detects and identifies these error-prone memory cells and subsequently takes protective action. More specifically, as described in greater detail below, a memory controller 120 in the computer system 100 uses ECC techniques to determine which memory cells are error-prone during refresh. Once these error-prone memory cells have been identified, the memory controller 120 inserts additional refreshes for the rows containing these memory cells. As a result, this more rapid refresh is performed only on the rows containing memory cells that need to be refreshed at a more rapid rate so that power is not wasted refreshing memory cells that do not need to be refreshed at a more rapid rate.

One embodiment of the memory controller 120 that is used in the computer system 100 is shown in FIG. 4. The memory controller 120 uses many of the same components that are used in the conventional memory controller 50 of FIG. 2. Again, in the interest of brevity, these components have been provided with the same reference numerals, and an explanation of their operation will not be repeated except to the extent that they perform different or additional functions in the memory controller 120 . In addition to the components included in the memory controller 50 , the memory controller 120 includes a failing address register and comparator unit (“FARC”) 124 that stores the row addresses containing error-prone memory cells requiring refreshes at a more rapid rate. The FARC 124 is coupled to the raw write data bus 18 D to receive from the CPU 14 (FIG. 3) the row addresses that are stored in the non-volatile memories 110 a - c (FIG. 3). At power-up of the computer system 100 , the CPU 14 performs a process 130 to either transfer the row addresses from the non-volatile memories 110 a - c to the FARC 124 as shown in the flow-chart of FIG. 5 or to test the DRAMs in the memory modules 102 a - c to determine which rows contain at least one error-prone memory cell and then program the non-volatile memories 110 a - c and the FARC, as shown in the flow-chart of FIG. 6.

With reference, first, to FIG. 5, the process 130 is entered during power-on at step 134 . The non-volatile memories 110 a - c are then read at 136 by the CPU 14 coupling read addresses to the non-volatile memories 110 a - c and the I/O controller coupling control signals to the non-volatile memories 110 a - c through line 137 . The FARC 124 is then initialized at 140 before continuing at 142 by the CPU 14 coupling the row addresses through the raw write data bus 18 D and the data bus 126 .

In the event row addresses have not yet been stored in the non-volatile memories 110 a - c , the memory controller 120 may determine which rows contain error-prone memory cells and program the non-volatile memories 110 a - c with the addresses of such rows. The non-volatile memories 110 a - c are initially programmed by the CPU 14 writing data to the DRAMs in the memory modules 110 a - c and then reading the stored data from the DRAMs after the DRAMs have been refreshed over a period. Any errors that have arisen as a result of excessive discharge of memory cells during the refresh are detected by the ECC check/correct circuit 76 . As the DRAMs are read, the row addresses coupled to the DRAMs through the address bus 18 A are stored in address holding registers 128 and coupled to the FARC 124 . If the read data are in error, the ECC check/correct circuit 76 outputs an R_ERROR that is coupled through line 148 to the memory control state machine 54 . The memory control state machine 54 then processes the R_ERROR signal using the process 150 shown in FIG. 6. The process is initiated by the memory control state machine 54 upon receipt of the R_ERROR signal at step 154 . The address holding register 128 is then read at 156 , and a determination is made at 160 whether the row responsible for the R_ERROR signal being generated is a new row in which an error-prone memory cells previously not been detected. If an error-prone memory cells was previously detected, the row address being output from the read address holding register 128 has already been recorded for extra refreshes. The process 150 can therefore progress direction to the final continue step 162 without the need for further action.

If an error-prone memory cells had previously not been detected in the current row, the row address being output from the address holding register 128 is transferred to the FARC 124 at step 164 . This is accomplished by the memory control state machine 54 outputting a “FAIL” signal on line 132 that causes the FARC 124 to store the current row address, which is output from the address holding registers 128 on bus 138 . The address is also appended at step 168 to the non-volatile memory 110 in the memory module 102 a - c containing the DRAM having the error-prone memory cell. This is accomplished by coupling data identifying the row addresses containing error-prone memory cells to the raw write data bus 18 D. The data identifying the row addresses are then coupled to the memory modules 102 a - c for storage in the non-volatile memories 110 a - c.

Once either the process 130 of FIG. 5 or the process 150 of FIG. 6 has been completed for all rows, the row addresses identifying rows containing one or more error-prone memory cells have been stored in the FARC 124 . The memory controller 120 is then ready to insert extra refreshes of such rows. As is well known in the art, when an auto-refresh command is issued to a DRAM, an internal refresh counter in the DRAM generates row addresses that are used to select the rows being refreshed. However, since these row addresses are not coupled from the DRAMs to the memory controller 120 , the address of each row being refreshed must be determined in the memory controller 120 . This is accomplished by using a refresh shadow counter 170 to generate refresh row addresses in the same that the refresh counter in the DRAMs generate such addresses. Furthermore, for the memory controller 120 , the addresses that are used for refreshing the memory cells in the DRAMs are generated by the memory controller 120 . When the memory control state machine 54 issues an auto-refresh command to a DRAM, it outputs a trigger signal on line 174 that resets the refresh shadow counter 170 and the refresh timer 84 and causes the refresh shadow counter 170 to begin outputting incrementally increasing row addresses. These incrementally increasing row addresses are coupled to the DRAMs via the address bus 18 A, and they are also coupled to the FARC 124 via bus 176 . However, the most significant bit (“MSB”) of the row address is applied to an inverter 178 so that the FARC 124 receives a row address that is offset from the current row address by one-half the number of rows in the DRAMs. This offset row address is compared to the addresses of the rows containing error-prone memory cell(s) that are stored in the FARC 124 . In the event of a match, the FARC 124 outputs a HIT signal on line 180 .

The memory control state machine 54 responds to the HIT signal by inserting an extra refresh of the row identified by the offset address. For this purpose, the address bus 18 A receives all but the most significant bit of the row address from the refresh shadow counter 170 and the most significant bit from the FARC 124 on line 182 . As a result, the row identified by the offset is refreshed twice as often as other rows, i.e., once when the address is output from the refresh shadow counter 170 and once when the row address offset from the address by one-half the number of rows is output from the refresh shadow counter 170 .

The manner in which extra refreshes of rows occurs will be apparent with reference to FIG. 7, which shows the output of the refresh shadow counter 170 (FIG. 4) on the left hand side and the addresses of the rows actually being refreshed on the right hand side. Every 64 ms, the refresh shadow counter 170 outputs row addresses that increment from “0000000000000” to “1111111111111.” For purposes of illustration, assume that row “0000000000010” contains one or more error-prone memory cells. This row will be refreshed in normal course when the refresh shadow counter 170 outputs “0000000000010” on the third count of the counter 170 . When the refresh shadow counter 170 has counted three counts past one-half of the rows, it outputs count “1000000000010.” However, the MSB is inverted by the inverter 178 so that the FARC 124 receives a count of “0000000000010.” Since this count corresponds to an address for a row containing one or more error-prone memory cells, a refresh of row “0000000000010” is inserted between row “1000000000010” and row “1000000000011,” as shown on the right hand side of FIG. 7.

Although the memory controller 120 refreshes rows containing one or more error-prone memory cells twice as often as other rows, it may alternatively refresh rows containing error-prone memory cells more frequently. This can be accomplished by inverting the MSB and the next to MSB (“NTMSB”) of the row address coupled from the refresh shadow counter 170 to the FARC 124 . A row would then be refreshed when the refresh shadow counter 170 outputs its address, when the refresh shadow counter 170 outputs its address with the NTMSB inverted, when the refresh shadow counter 170 outputs its address with the MSB inverted, and when the refresh shadow counter 170 outputs its address with both the MSB and the NTMSB inverted. Other variations will be apparent to one skilled in the art.

A computer system 190 according to another embodiment of the invention is shown in FIG. 8. In this embodiment, the computer system 190 includes the conventional memory controller 30 of FIG. 1 coupled to memory modules 194 a - c . Each of the memory modules 194 a - c includes several DRAMs 196 , although only one DRAM is shown in FIG. 8. The DRAM 196 includes the FARC 124 , which is coupled to a refresh counter 198 through inverting circuitry 200 . The FARC 124 is initialized with data stored in a non-volatile memory 202 that identifies the addresses of the rows containing one or more error-prone memory cells. The non-volatile memory 202 is initially programmed in the same manner that the non-volatile memory was programmed, as explained above, using ECC circuitry 204 . The inverting circuitry 200 inverts appropriate bits of refresh addresses generated by the refresh counter 198 to schedule extra refreshes of rows containing one or more error-prone memory cells. The DRAM 196 also includes a memory control state machine 210 that controls the operation of the above-described components.

A computer system 220 according to another embodiment of the invention is shown in FIG. 9. This embodiment includes several memory modules 224 a - c coupled to a memory controller 230 . The memory modules 224 a - c each include the ECC generator 72 and ECC check/correct circuit 76 of FIGS. 2 and 3 as well as the other components that are used to determine which rows contain one or more error-prone memory cells. The computer system 220 does not include a syndrome bus 40 , of course, since the ECC syndromes are generated in the memory modules 224 a - c . However, once the memory modules 224 a - c have determined the address of rows containing one or more error-prone memory cells, it programs a non-volatile memory device 234 in each of the memory modules 224 a - c with those addresses. DRAMs 238 each include the FARC 124 , the refresh counter 198 , the inverting circuitry 200 , and the memory control state machine 210 of FIG. 8 to schedule extra refreshed of rows containing one or more error-prone memory cell, as previously explained.

Although the component of the various embodiments have been explained as being in either a memory controller, a memory module or a DRAM, it will be understood that there is substantial flexibility in the location of many components. For example, the FARC 124 may be either in the memory controller as shown in FIG. 4, the DRAMs as shown in FIGS. 8 and 9, or in the memory modules separate from the DRAMs. Furthermore, although the present invention has been described with reference to the disclosed embodiments, persons skilled in the art will recognize that changes may be made in form and detail without departing from the spirit and scope of the invention.