|
Match
|
Document |
Document Title |
|
|
7402498 |
Methods of forming trench isolation regions
The invention includes methods of forming trench isolation regions. In one implementation, a masking material is formed over a semiconductor substrate. The masking material comprises at least one...
|
|
|
7402489 |
Capacitor compatible with high dielectric constant materials having a low contact resistance layer and the method for forming same
A storage cell capacitor and a method for forming the storage cell capacitor having a storage node electrode including a barrier layer interposed between a conductive plug and an oxidation...
|
|
|
7402453 |
Microelectronic imaging units and methods of manufacturing microelectronic imaging units
Methods for manufacturing microelectronic imaging units and microelectronic imaging units that are formed using such methods are disclosed herein. In one embodiment, a method includes coupling a...
|
|
|
7402451 |
Optimized transistor for imager device
An imager device that has mitigated dark current leakage and punch-through protection. The transistor associated with the photoconversion device is formed with a single (i.e, one-sided) active area...
|
|
|
7402379 |
Resist exposure system and method of forming a pattern on a resist
A resist exposure system and a method of forming a pattern on a resist are provided and include an exposure source, a photoresist composition, and a mask positioned therebetween. The resist...
|
|
|
7402259 |
Chemical-mechanical polishing methods
A chemical-mechanical polishing (CMP) method includes applying a solid abrasive material to a substrate, polishing the substrate, flocculating at least a portion of the abrasive material, and...
|
|
|
7402094 |
Fixed-abrasive chemical-mechanical planarization of titanium nitride
Planarizing solutions, and their methods of use, for removing titanium nitride from the surface of a substrate using a fixed-abrasive planarizing pad. The planarizing solutions take the form of an...
|
|
|
7401267 |
Program failure recovery
Methods and apparatus are provided. A method of operating a memory device includes detecting a programming failure at a first location of a memory array, preserving data within the memory device...
|
|
|
7401010 |
Methods of forming radiation-patterning tools; carrier waves and computer readable media
The invention includes a method for placement of sidelobe inhibitors on a radiation-patterning tool. Elements of the tool are represented by design features in a modeling domain. The modeling...
|
|
|
7400549 |
Memory block reallocation in a flash memory device
A non-volatile memory device has the pages of a certain memory block reallocated to other blocks in order to increase decrease disturb and increase reliability. Each of the reallocation blocks that...
|
|
|
7400544 |
Actively driven VREF for input buffer noise immunity
A memory device including a circuit for actively driving a reference voltage in a memory device is disclosed. A circuit integrated in a memory device and coupled to an external voltage source...
|
|
|
7400539 |
Memory device having terminals for transferring multiple types of data
A device includes a number of terminals for transferring input data and output data to and from a memory array. The memory device includes an auxiliary circuit for receiving input auxiliary...
|
|
|
7400533 |
Mimicking program verify drain resistance in a memory device
A selected word line is biased with a program verify voltage. A predetermined quantity of unselected word lines that are between the selected word line and the bit line are biased with a modified V...
|
|
|
7400532 |
Programming method to reduce gate coupling interference for non-volatile memory
A non-volatile memory device and programming process is described that compensates for coupling effects on threshold gate voltages of adjacent floating gate or non-conductive floating node memory...
|
|
|
7400389 |
Method and apparatus for testing image sensors
Methods and apparatuses for testing image sensors are disclosed. Desirable apparatuses of the present invention include image sensor testing devices comprising a digital light projection system...
|
|
|
7400350 |
System and method for collecting images of a monitored device
A system and method for collecting images of monitored devices, such as utility meters for electricity, gas and water, captures a digital image of a monitored device and produces a difference...
|
|
|
7400124 |
Apparatus and methods for regulated voltage
An electronic system according to various aspects of the present invention includes a memory and a supply regulation circuit having a regulated output to provide a selected voltage level. In one...
|
|
|
7400043 |
Semiconductor constructions
The invention includes a method of forming a metal-containing film over a surface of a semiconductor substrate. The surface is exposed to a supercritical fluid. The supercritical fluid has H 2 , at...
|
|
|
7400032 |
Module assembly for stacked BGA packages
Ball grid array packages that can be stacked to form highly dense components and the method for stacking ball grid arrays are disclosed. The ball grid array packages comprise flexible or rigid...
|
|
|
7400012 |
Scalable Flash/NV structures and devices with extended endurance
Devices and methods are provided with respect to a gate stack for a nonvolatile structure. According to one aspect, a gate stack is provided. One embodiment of the gate stack includes a tunnel...
|
|
|
7400004 |
Isolation structures for preventing photons and carriers from reaching active areas and methods of formation
Regions of an integrated circuit are isolated by a structure that includes at least one isolating trench on the periphery of an active area. The trench is deep, extending at least about 0.5 μm...
|
|
|
7399714 |
Method of forming a structure over a semiconductor substrate
The invention includes a method of forming a structure over a semiconductor substrate. A silicon dioxide containing layer is formed across at least some of the substrate. Nitrogen is formed within...
|
|
|
7399671 |
Disposable pillars for contact formation
Sacrificial plugs for forming contacts in integrated circuits, as well as methods of forming connections in integrated circuit arrays are disclosed. Various pattern transfer and etching steps can...
|
|
|
7399666 |
Atomic layer deposition of Zr3N4/ZrO2 films as gate dielectrics
The use of atomic layer deposition (ALD) to form a dielectric layer of zirconium nitride (Zr 3 N 4 ) and zirconium oxide (ZrO 2 ) and a method of fabricating such a dielectric layer produces a...
|
|
|
7399657 |
Ball grid array packages with thermally conductive containers
Ball grid array packages for semiconductor die include a thermally conductive container and a substrate that substantially enclose a semiconductor die. The die is positioned with respect to the...
|
|
|
7399499 |
Methods of gas delivery for deposition processes and methods of depositing material on a substrate
Methods for depositing material onto workpieces, methods of controlling the delivery of gases in deposition processes, and apparatus for depositing materials onto workpieces. One embodiment of a...
|
|
|
7399424 |
Compositions for dissolution of low-k dielectric films, and methods of use
An improved composition and method for cleaning the surface of a semiconductor wafer are provided. The composition can be used to selectively remove a low-k dielectric material such as silicon...
|
|
|
7398595 |
Method for forming a storage cell capacitor compatible with high dielectric constant materials
An integrated circuit structure includes a digit line and an electrode adapted to be part of a storage cell capacitor and includes a barrier layer interposed between a conductive plug and an...
|
|
|
7398412 |
Measure controlled delay with duty cycle control
The disclosed embodiments relate to circuits that produce synchronized output signals. More specifically, there is provided a synchronization circuit adapted to receive an input signal, the...
|
|
|
7398358 |
Method and apparatus for high performance branching in pipelined microsystems
A pipelined processor includes a branch acceleration technique which is based on an improved branch cache. The improved branch cache minimizes or eliminates delays caused by branch instructions,...
|
|
|
7398342 |
Active termination control
A method and apparatus are provided for active termination control in a memory by a module register providing an active termination control signal to the memory. The memory turns on active...
|
|
|
7397712 |
Pre-emphasis for strobe signals in memory device
Some embodiments of the invention include a memory device having a number of data terminals for transferring data signals and a number of strobe terminals for transferring strobe signals...
|
|
|
7397711 |
Distributed write data drivers for burst access memories
An address strobe latches a first address. A burst cycle increments the address internally with additional address strobes. A new memory address is only required at the beginning of each burst...
|
|
|
7397689 |
Resistive memory device
A system having a memory cell. In certain embodiments, the memory cell includes a resistive memory element, an access transistor having a gate, a first terminal, and a second terminal, and a...
|
|
|
7397509 |
High dynamic range imager with a rolling shutter
A high dynamic range imager operates pixels utilizing at least a short integration period and a long integration period. The pixel reading circuits of the imager are adapted to process pixel...
|
|
|
7397503 |
Systems and methods for reducing artifacts caused by illuminant flicker
Methods for reducing artifacts caused by illuminant flicker are provided. One such method comprises: providing pixel circuits; and operating the pixel circuits in a bi-directional mode during which...
|
|
|
7397479 |
Programmable multiple texture combine circuit for a graphics processing system and method for use thereof
The present invention is directed toward a texture combine circuit for generating fragment graphics data for a pixel in a graphics processing system. The texture combine circuit includes at least...
|
|
|
7397477 |
Memory system having multiple address allocation formats and method for use thereof
A system and method for decoding memory addresses for accessing a memory system having a plurality of blocks of memory for storing data at addressable memory locations. Memory addresses are decoded...
|
|
|
7397129 |
Interposers with flexible solder pad elements
Various embodiments of an interposer for mounting a semiconductor die, as well as methods for forming the interposer, are disclosed. The interposer includes flexible solder pad elements that are...
|
|
|
7397075 |
Method and apparatus providing CMOS imager device pixel with transistor having lower threshold voltage than other imager device transistors
A transistor of a pixel cell for use in a CMOS imager with a low threshold voltage of about 0.3 V to less than about 0.7 V is disclosed. The transistor is provided with high dosage source and drain...
|
|
|
7397066 |
Microelectronic imagers with curved image sensors and methods for manufacturing microelectronic imagers
Microelectronic imagers with curved image sensors and methods for manufacturing curved image sensors. In one embodiment, a microelectronic imager device includes an imager die having a substrate, a...
|
|
|
7396781 |
Method and apparatus for adjusting feature size and position
Variations in the pitch of features formed using pitch multiplication are minimized by separately forming at least two sets of spacers. Mandrels are formed and the positions of their sidewalls are...
|
|
|
7396779 |
Electronic apparatus, silicon-on-insulator integrated circuits, and fabrication methods
An electronic apparatus includes an insulative substrate containing an aluminum-based glass and a layer containing a semiconductive material over the substrate. The insulative substrate can include...
|
|
|
7396774 |
Methods for forming an enriched metal oxide surface
Methods of forming a metal oxide surface that is enriched with metal oxide in its higher oxidation state are provided. A metal oxide surface that is enriched with metal oxide in its higher...
|
|
|
7396720 |
High coupling memory cell
A first dielectric layer is formed over a substrate. A single layer first conductive layer that acts as a floating gate is formed over the first dielectric layer. A trough is formed in the first...
|
|
|
7396702 |
Module assembly and method for stacked BGA packages
Ball grid array packages that can be stacked to form highly dense components and the method for stacking ball grid arrays are disclosed. The ball grid array packages comprise flexible or rigid...
|
|
|
7396699 |
Method of forming non-volatile resistance variable devices and method of forming a programmable memory cell of memory circuitry
A first conductive electrode material is formed on a substrate. Chalcogenide comprising material is formed thereover. The chalcogenide material comprises A x Se y . A silver comprising layer is...
|
|
|
7396570 |
Plasma enhanced chemical vapor deposition method of forming titanium silicide comprising layers
Chemical vapor deposition methods of forming titanium silicide including layers on substrates are disclosed. TiCl 4 and at least one silane are first fed to the chamber at or above a first...
|
|
|
7396447 |
Through-hole conductors for semiconductor substrates and system for making same
A method, structure and system for forming a through-hole conductor in a semiconductor substrate includes forming a hole having an inner surface from a first side of the semiconductor substrate to...
|
|
|
7395409 |
Split embedded DRAM processor
A processing architecture includes a first CPU core portion coupled to a second embedded dynamic random access memory (DRAM) portion. These architectural components jointly implement a single...
|