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7450425 Non-volatile memory cell read failure reduction  
The present disclosure includes various method, device, and system embodiments for reducing non-volatile memory cell read failures. One such method embodiment includes performing a first read...
7450422 NAND architecture memory devices and operation  
Non-volatile memory devices utilizing a modified NAND architecture where ends of the NAND string of memory cells are selectively coupled to different bit lines may facilitate increased memory...
7450410 High speed data bus  
The invention comprises data processing systems and components thereof. Such systems may include a memory controller, a plurality of memory devices, a data bus coupling the memory controller with...
7449953 Input buffer design using common-mode feedback (CMFB)  
An input buffer includes a first stage for receiving an input signal and having a first pair of complementary output signals, the first stage including an input circuit for receiving the input...
7449941 Master bias current generating circuit with decreased sensitivity to silicon process variation  
A master bias current generating circuit includes a current source, a first reference leg, and a second reference leg. The first reference leg includes a first transistor having a first size...
7449939 Bias generator with feedback control  
A bias generator for initializing a voltage controlled delay line by providing the voltage controlled delay line with a control signal having an initial voltage and monitoring the variable delay...
7449910 Test system for semiconductor components having conductive spring contacts  
An interconnect for testing a semiconductor component includes a substrate, and interconnect contacts on the substrate configured to electrically engage component contacts on a semiconductor...
7449766 Methods of forming a contact opening in a semiconductor assembly using a disposable hard mask  
Methods to form contact openings and allow the formation of self-aligned contacts for use in the manufacture of semiconductor devices are described. During formation of a multi-layered resist, a...
7449736 Pixel with transfer gate with no isolation edge  
A pixel and imager device, and method of forming the same, where the pixel has a transfer transistor gate associated with a photoconversion device and is isolated in a substrate by shallow trench...
7449410 Methods of forming CoSi2, methods of forming field effect transistors, and methods of forming conductive contacts  
The invention included to methods of forming CoSi 2 , methods of forming field effect transistors, and methods of forming conductive contacts. In one implementation, a method of forming CoSi 2 ...
7449391 Methods of forming plurality of capacitor devices  
The invention includes semiconductor constructions, and also includes methods of forming pluralities of capacitor devices. An exemplary method of the invention includes forming conductive storage...
7449390 Methods of forming memory  
Methods of forming memory are described. According to one arrangement, a method of forming memory includes forming a plurality of word lines over a substrate, the word lines having insulating...
7449368 Technique for attaching die to leads  
A semiconductor die assembly comprising a semiconductor die with bond pads, a plurality of leads which extend across the semiconductor die and terminates over their respective bond pads, and an...
7448038 Method for using filtering to load balance a loop of parallel processing elements  
One aspect of the present invention relates to a method for balancing the load of a parallel processing system having a plurality of parallel processing elements arranged in a loop, wherein each...
7447974 Memory controller method and system compensating for memory cell data losses  
A computer system includes a memory controller coupled to a memory module containing several DRAMs. The memory module also includes a non-volatile memory storing row addresses identifying rows...
7447973 Memory controller method and system compensating for memory cell data losses  
A computer system includes a memory controller coupled to a memory module containing several DRAMs. The memory module also includes a non-volatile memory storing row addresses identifying rows...
7447847 Memory device trims  
Methods and apparatus are provided. A memory device has a memory array, base trim circuitry adapted to store base control parameter values common to the memory array, and a reference trim circuit...
7447720 Method for finding global extrema of a set of bytes distributed across an array of parallel processing elements  
A method for finding an extrema for an n-dimensional array having a plurality of processing elements, the method includes determining within each of the processing elements a dimensional extrema...
7447240 Method and system for synchronizing communications links in a hub-based memory system  
A method is disclosed for synchronizing communications links in a memory hub system. The system includes a system controller and a plurality of memory hubs coupled in series, with pairs of...
7447106 Delay stage-interweaved analog DLL/PLL  
A methodology is disclosed that enables the delay stages of an analog delay locked loop (DLL) or phase locked loop (PLL) to be programmed according to the operating condition, which may depend on...
7447085 Multilevel driver  
The present disclosure includes various method, device, and system embodiments for multilevel driving of rowlines and/or wordlines. One such method embodiment includes supplying a first power...
7446855 Methods and apparatuses for configuring radiation in microlithographic processing of workpieces using an adjustment structure  
Methods and apparatuses for configuring radiation used in microlithographic processing of workpieces are disclosed herein. One particular embodiment of such a method comprises directing a radiation...
7446812 Wide dynamic range operations for imaging  
Embodiments provide a method and apparatus that achieve wide dynamic range operation of an image sensor. In an array of pixel cells, first charge is accumulated in a first subset of pixel cells...
7446807 Imager pixel with capacitance for boosting reset voltage  
A pixel cell in which a capacitance is coupled between a storage node and a row select transistor and another capacitance is coupled between a storage node and a voltage supply or ground source...
7446610 Low voltage CMOS differential amplifier  
A low voltage CMOS differential amplifier is provided. More specifically, in one embodiment, a device comprising a differential pair is provided. A self-biased transistor and a component are...
7446580 System and method to improve the efficiency of synchronous mirror delays and delay locked loops  
A phase detection system for use with a synchronous mirror delay or a delay-locked loop in order to reduce the number of delay stages required, and therefore increase the efficiency, is disclosed....
7446415 Method for filling electrically different features  
Methods of electroless filling electrically different features such as contact openings to form interconnects and conductive contacts, and semiconductor devices, dies, and systems that incorporate...
7446393 Co-sputter deposition of metal-doped chalcogenides  
The present invention is related to methods and apparatus that allow a chalcogenide glass such as germanium selenide (Ge x Se 1-x ) to be doped with a metal such as silver, copper, or zinc without...
7446385 Methods of fabricating optical packages, systems comprising the same, and their uses  
Methods and apparatuses for forming optical packages, and intermediate structures resulting from the same are disclosed, which provide an optical element over a device. The optical element is...
7446372 DRAM tunneling access transistor  
In one embodiment, a first transistor is comprised of a first p+ source region doped in an n-well in the substrate and a first n+ drain region doped on one side at the top of the pillar. A second...
7446368 Deposition of metal oxide and/or low asymmetrical tunnel barrier interpoly insulators  
Structures and methods for programmable array type logic and/or memory devices with asymmetrical low tunnel barrier intergate insulators are provided. The programmable array type logic and/or...
7446363 Capacitor including a percentage of amorphous dielectric material and a percentage of crystalline dielectric material  
The invention comprises integrated circuitry and to methods of forming capacitors. In one implementation, integrated circuitry includes a capacitor having a first capacitor electrode, a second...
7446357 Split trunk pixel layout  
A pixel array architecture having multiple pixel cells arranged in a split trunk pixel layout and sharing common pixel cell components. The array architecture increases the fill factor, and in...
7446351 Transistor structures and transistors with a germanium-containing channel  
A transistor structure includes a first undoped, silicon-containing channel layer, a buried germanium channel, and a second undoped, silicon-containing channel layer. The first and second channel...
7446277 Method for sorting integrated circuit devices  
A method for sorting integrated circuit (IC) devices of the type having a substantially unique identification (ID) code, such as a fuse ID, including automatically reading the ID code of each of...
7446028 Multi-component integrated circuit contacts  
An integrated circuit connection is describe that includes a first, securing member and a second, connection member. The first member, in an embodiment, is a spike that has a portion of its body...
7445996 Low resistance peripheral contacts while maintaining DRAM array integrity  
A process and apparatus directed to forming low resistance contacts in both the memory cell array and peripheral logic circuitry areas of a semiconductor device, for example, a DRAM memory device,...
7445991 Methods of forming a plurality of capacitors  
The invention includes methods of forming a plurality of capacitors. In one implementation, a plurality of capacitor electrode openings is formed over a substrate. Individual of the capacitor...
7445990 Methods of forming a plurality of capacitors  
A plurality of capacitor electrode openings is formed within capacitor electrode-forming material. A first set of the openings is formed to a depth which is greater within the capacitor...
7445973 Transistor surround gate structure with silicon-on-insulator isolation for memory cells, memory arrays, memory devices and systems and methods of forming same  
A transistor surround gate structure and a method of forming thereof on a semiconductor assembly are described. The transistor surround gate structure is formed on a partial silicon-on-insulator in...
7445951 Trench photosensor for a CMOS imager  
A trench photosensor for use in a CMOS imager having an improved charge capacity. The trench photosensor may be either a photogate or photodiode structure. The trench shape of the photosensor...
7444934 Supercritical fluid-assisted direct write for printing integrated circuits  
High resolution patterns provided on a surface of a semiconductor substrate and methods of direct printing of such high resolution patterns are disclosed. The high resolution patterns may have...
7444579 Non-systematic coded error correction  
Improved memory devices, circuitry, and data methods are described that facilitate the detection and correction of data in memory systems or devices by encoding the data bits of a memory row or...
7444559 Generation of memory test patterns for DLL calibration  
A system and method to generate memory test patterns for the calibration of a delay locked loop (DLL) using pseudo random bit sequences (PRBS) generated through a pair of liner feedback shift...
7444550 System and method for communicating a software-generated pulse waveform between two servers in a network  
A method of monitoring a status condition of a first server with a second server in a server network, and also providing synchronization and messaging between the two servers, the method including:...
7444537 System and method for communicating a software-generated pulse waveform between two servers in a network  
A method of monitoring a status condition of a first server with a second server in a server network, and also providing synchronization and messaging between the two servers, the method including:...
7444458 Method for assigning addresses to memory devices  
A memory system having a memory controller and several separate memory devices connected to the controller by a system bus. The memory devices each included an array of memory cells, addressing...
7444030 Image encoding with dynamic buffer-capacity-level-based compression adjustment  
Methods, systems, and computer programs for encoding images are described. In one aspect, quantized frequency domain vectors are sequentially generated from a sequence of blocks of the image. Each...
7443761 Loop filtering for fast PLL locking  
Methods, circuits, devices, and systems are provided for phase locked loop (PLL) locking. A method of locking a PLL includes locking a delay locked loop (DLL) path while applying a control voltage...
7443750 Switched capacitor DRAM sense amplifier with immunity to mismatch and offsets  
A switched capacitor sense amplifier includes capacitively coupled input, feedback, and reset paths to provide immunity to the mismatches in transistor characteristics and offsets. The sense...
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