Matches 101 - 150 out of 17621 < 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 >
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7443749 Switched capacitor DRAM sense amplifier with immunity to mismatch and offsets  
A switched capacitor sense amplifier includes capacitively coupled input, feedback, and reset paths to provide immunity to the mismatches in transistor characteristics and offsets. The sense...
7443743 Method and system for improved efficiency of synchronous mirror delays and delay locked loops  
A plurality of improved memory systems employing a phase detection system in conjunction with either a synchronous mirror delay or a delay-locked loop, and related methods of operation, are...
7443715 SRAM cells with repressed floating gate memory, low tunnel barrier interpoly insulators  
Structures and methods are provided for SRAM cells having a novel, non-volatile floating gate transistor, e.g. a non-volatile memory component, within the cell which can be programmed to provide...
7443437 Image sensor with a gated storage node linked to transfer gate  
A CMOS imaging system with increased charge storage of pixels yet decreased physical size, kTC noise and active area. A storage node is connected to the transfer gate and provides a storage node...
7443427 Wide dynamic range linear-and-log active pixel  
A pixel circuit having an improved dynamic range is disclosed. When incoming light detected by the photodiode is strong, the accumulated (integrated) charge on a signal capacitor becomes large. To...
7443219 Phase interpolation apparatus, systems, and methods  
A phase interpolator circuit may comprise a multiplexer circuit (MUX) coupled to a plurality of clock signals at MUX inputs and may provide a first clock signal and a second clock signal at MUX...
7443216 Trimmable delay locked loop circuitry with improved initialization characteristics  
Disclosed herein is improved delay locked loop (DLL) initialization circuitry that alters the measurement used to initialize the variable delay line's delay (e.g., entry point or exit point) by...
7443038 Flip-chip image sensor packages  
The present invention provides flip-chip packaging for optically interactive devices such as image sensors and methods of assembly. In a first embodiment of the invention, conductive traces are...
7443032 Memory device with chemical vapor deposition of titanium for titanium silicide contacts  
A titanium layer is formed on a substrate with chemical vapor deposition (CVD). First, a seed layer is formed on the substrate by combining a first precursor with a reducing agent by CVD. Then, the...
7443022 Board-on-chip packages  
The invention encompasses a board-on-chip package comprising an insulative substrate having circuitry thereon and an opening therethrough. A semiconductive-material-comprising die is adhered to the...
7443009 N well implants to separate blocks in a flash memory device  
A semiconductor memory device that has an isolated area formed from one conductivity and formed in part by a buried layer of a second conductivity that is implanted in a substrate. The walls of the...
7443006 Photon amplification of image sensors  
A pixel cell having a substrate, photo-conversion device, and at least one dielectric layer over the photo-conversion device. The at least one dielectric layer includes one or more rare earth...
7442979 Reduced cell-to-cell shorting for memory arrays  
Bottom electrodes of memory cell capacitors are recessed to prevent electrical shorts between neighboring memory cells. A partially fabricated memory cell capacitor has a bottom electrode...
7442977 Gated field effect devices  
This invention includes gated field effect devices, and methods of forming gated field effect devices. In one implementation, a gated field effect device includes a pair of source/drain regions...
7442976 DRAM cells with vertical transistors  
The invention includes a semiconductor structure having U-shaped transistors formed by etching a semiconductor substrate. In an embodiment, the source/drain regions of the transistors are provided...
7442970 Active photosensitive structure with buried depletion layer  
An imager pixel has a photosensitive JFET structure having a channel region located above a buried charge accumulation region. The channel region has a resistance characteristic that changes...
7442910 High dynamic range cascaded integration pixel cell  
A cascaded imaging storage system for a pixel is disclosed for improving intrascene dynamic range. Charges accumulated in a first capacitor spill over into a second capacitor when a charge storage...
7442655 Selective oxidation methods and transistor fabrication methods  
The invention includes selective oxidation methods and transistor fabrication methods. In one implementation, a selective oxidation method includes positioning a substrate within a chamber. The...
7442643 Methods of forming conductive elements using organometallic layers and flowable, curable conductive materials  
A conductive element is formed on a substrate by forming an organometallic layer on at least a portion of a surface of the substrate, heating a portion of the organometallic layer, and removing an...
7442633 Decoupling capacitor for high frequency noise immunity  
Systems and methods are provided for an on-chip decoupling device and method. One aspect of the present subject matter is a capacitor. One embodiment of the capacitor includes a substrate, a high K...
7442608 Methods of fabricating a semiconductor device using angled implantation  
Methods of fabricating structures, such as memory cell structures by exposing at least one edge portion of an intermediate nitride layer arranged between a polysilicon layer and a tungsten layer...
7442600 Methods of forming threshold voltage implant regions  
The invention includes methods of forming channel region implants for two transistor devices simultaneously, in which a mask is utilized to block a larger percentage of a channel region location of...
7442578 Underfill compounds including electrically charged filler elements, microelectronic devices having underfill compounds including electrically charged filler elements, and methods of underfilling micoelectronic devices  
Underfill compounds including electrically charged filler elements, microelectronic devices having underfill compounds including electrically charged filler elements, and methods of disposing...
7442472 Methods of forming reticles  
The invention includes reticle constructions and methods of forming reticle constructions. In a particular aspect, a method of forming a reticle includes provision of a reticle substrate having a...
7442319 Poly etch without separate oxide decap  
The use of an ammonium hydroxide spike to a hot tetra methyl ammonium hydroxide (TMAH) solution to form an insitu poly oxide decapping step in a polysilicon (poly) etch process, results in a single...
7441949 System and method for providing temperature data from a memory device having a temperature sensor  
A circuit and method for providing temperature data indicative of a temperature measured by a temperature sensor. The circuit is coupled to the temperature sensor and configured to identify for a...
7441172 DVI link with parallel test data  
An embodiment includes encoding parallel digital data into encoded and parallel digital data in an encoder and generating parallel test data in a pseudo-random binary sequence generator circuit....
7440860 Sequential unique marking  
The present invention comprises a method of sequential unique marking comprising providing a multi-die handling device with a plurality of semiconductor devices therein, reading an ID code on the...
7440344 Level shifter for low voltage operation  
A voltage level translator boosts the gate voltage of a transistor, and increases the gate to source voltage, to allow operation over a wider range of supply voltages. The P/N ratio of transistors...
7440339 Stacked columnar 1T-nMTj MRAM structure and its method of formation and operation  
This invention relates to an MRAM array architecture which incorporates certain advantages from both cross-point and 1T-1MTJ architectures during reading operations. The fast read-time and higher...
7440336 Memory device having terminals for transferring multiple types of data  
A memory device having a number of terminals for transferring input data and output data to and from a memory array. The memory device includes an auxiliary circuit for receiving input auxiliary...
7440332 Low power multiple bit sense amplifier  
A sense amplifier for multiple level flash memory cells is comprised of a voltage ramp generator that generates a ramp voltage signal. Reference sense amplifiers compare an input reference current...
7440321 Multiple select gate architecture with select gates of different lengths  
A portion of a memory array has a string of two or more non-volatile memory cells, a first select gate coupled in series with one non-volatile memory cell of the string of two or more non-volatile...
7440317 One transistor SOI non-volatile random access memory cell  
One aspect of the present subject matter relates to a memory cell, or more specifically, to a one-transistor SOI non-volatile memory cell. In various embodiments, the memory cell includes a...
7440310 Memory cell with trenched gated thyristor  
One aspect of this disclosure relates to a method for operating a memory cell. According to various embodiments, the method includes charging a storage node of the memory cell, including forward...
7440255 Capacitor constructions and methods of forming  
A capacitor construction includes a first electrode and a layer between the first electrode and a surface supporting the capacitor construction. The capacitor construction can exhibit a lower RC...
7440012 Method and apparatus for optimizing image sensor noise and dynamic range  
A method and apparatus for optimizing the voltage supply of an image sensor pixel array to minimize pixel noise and maximize dynamic range is disclosed. The voltage supply is adjusted in response...
7439752 Methods of providing semiconductor components within sockets  
The invention includes methods of utilizing removable mechanical precising mechanisms and/or optical-based precising mechanisms to align chips within sockets. The sockets can be configured so that...
7439598 Microelectronic imaging units  
Methods for manufacturing microelectronic imaging units and microelectronic imaging units that are formed using such methods are disclosed herein. In one embodiment, a method includes coupling a...
7439594 Stacked non-volatile memory with silicon carbide-based amorphous silicon thin film transistors  
A stacked non-volatile memory device uses amorphous silicon based thin film transistors stacked vertically. Each layer of transistors or cells is formed from a deposited a-Si channel region layer...
7439576 Ultra-thin body vertical tunneling transistor  
A vertical tunneling, ultra-thin body transistor is formed on a substrate out of a vertical oxide pillar having active regions of opposing conductivity on opposite ends of the pillar. In one...
7439564 Methods of forming capacitor constructions  
The invention includes constructions having two dielectric layers over a conductively-doped semiconductive material. One of the dielectric layers contains aluminum oxide, and the other contains a...
7439479 Photonic crystal-based filter for use in an image sensor  
The invention, in various exemplary embodiments, incorporates a photonic crystal filter into an image sensor. The photonic crystal filter comprises a substrate and a plurality of pillars forming a...
7439450 Plating buss and a method of use thereof  
The present invention relates generally to a plating buss design and method for minimizing short circuit problems in PCB panel singulation. More particularly, the invention encompasses a serpentine...
7439338 Beta-diketiminate ligand sources and metal-containing compounds thereof, and systems and methods including same  
The present invention provides metal-containing compounds that include at least one β-diketiminate ligand, and methods of making and using the same. In certain embodiments, the metal-containing...
7439195 Systems and methods for forming metal oxides using metal compounds containing aminosilane ligands  
A method of forming (and an apparatus for forming) a metal oxide layer on a substrate, particularly a semiconductor substrate or substrate assembly, using a vapor deposition process and one or more...
7439194 Lanthanide doped TiOx dielectric films by plasma oxidation  
A dielectric film containing lanthanide doped TiO x and a method of fabricating such a dielectric film produce a reliable gate dielectric having an equivalent oxide thickness thinner than...
7439169 Integrated circuit and methods of redistributing bondpad locations  
Integrated circuits and methods of redistributing bondpad locations are disclosed. In one implementation, a method of redistributing a bondpad location of an integrated circuit includes providing...
7439158 Strained semiconductor by full wafer bonding  
One aspect of this disclosure relates to a method for forming a wafer with a strained semiconductor. In various embodiments of the method, a predetermined contour is formed in one of a...
7439157 Isolation trenches for memory devices  
A method includes removing a portion of a substrate to define an isolation trench; forming a first dielectric layer on exposed surfaces of the substrate in the trench; forming a second dielectric...
Matches 101 - 150 out of 17621 < 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 >