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7439155 Isolation techniques for reducing dark current in CMOS image sensors  
Isolation methods and devices for isolating regions of a semiconductor device. The isolation method and structure include forming an isolating trench in an active area and filling the trench with a...
7439152 Methods of forming a plurality of capacitors  
The invention includes methods of forming a plurality of capacitors. In one implementation, a plurality of capacitor electrode openings is formed over a substrate. Individual of the capacitor...
7439140 Formation of standard voltage threshold and low voltage threshold MOSFET devices  
Wells are formed in a substrate where standard Vt and low Vt devices of both a first and second type are to be fabricated. Wells defining the locations of first type standard Vt devices are masked,...
7439138 Method of forming integrated circuitry  
The invention includes methods of forming integrated circuitry, methods of forming memory circuitry, and methods of forming field effect transistors. In one implementation, conductive metal...
7439136 Method of forming a layer comprising epitaxial silicon  
The invention includes methods of forming epitaxial silicon-comprising material and methods of forming vertical transistors. In one implementation, a method of forming epitaxial silicon-comprising...
7438632 Method and apparatus for cleaning a web-based chemical mechanical planarization system  
A method and apparatus for cleaning a web-based chemical-mechanical planarization (CMP) system. Specifically, a fluid spray bar is coupled to a frame assembly which may be mounted on a CMP system....
7438626 Apparatus and method for removing material from microfeature workpieces  
Machines and systems for removing materials from microfeature workpieces using fixed-abrasive mediums. One embodiment of a method for removing material from a microfeature workpiece comprises...
7437729 Method for load balancing a loop of parallel processing elements  
A method for balancing the load of a parallel processing system having a plurality of parallel processing elements arranged in a loop, wherein each processing element has a local number of tasks...
7437726 Method for rounding values for a plurality of parallel processing elements  
A method for calculating a local mean number of tasks for each processing element (PE r ) in a parallel processing system, wherein each processing element (PE r ) has a local number of tasks...
7437647 Mode entry circuit and method  
An apparatus and method for generating an active mode activation signal in response to an input signal having a voltage exceeding the greater of two reference voltages by a voltage margin.
7437632 Circuits and methods for repairing defects in memory devices  
A memory device has a number of memory segments connected to a supply source through a supply control circuit. If one of the memory segments is defective, the supply control circuit isolates the...
7437630 Testing a multibank memory module  
A method and system for testing a memory module that has at least a first and second memory bank. The first and second memory banks have a plurality of integrated circuit (IC) devices for storing...
7437625 Memory with element redundancy  
A memory device to perform an erase operation algorithm that specifically deals with different types of defects in a memory array. The memory array of one embodiment of the present invention has...
7437579 System and method for selective memory module power management  
A memory module includes a memory hub that monitors utilization of the memory module and directs devices of the memory module to a reduced power state when the module is not being used at a desired...
7436708 NAND memory device column charging  
Embodiments of NAND Flash memory devices and methods recognize that effective column coupling capacitance can be reduced by maintaining a sourced voltage on adjacent columns of an array....
7436705 Multiple level cell memory device with single bit per cell, re-mappable memory block  
A non-volatile memory device has a plurality of memory cells that are organized into memory blocks. Each block can operate in either a multiple level cell mode or a single bit per cell mode. One...
7436442 Low light sensor signal to noise improvement  
A number of different elements are added together in a staggered way to avoid the total loss of resolution caused by the binning process. The circuit for doing this includes a variable gain. In a...
7436267 Microstrip line dielectric overlay  
A printed circuit board has a dielectric constant different from the dielectric constant of free space, with at least two microstrip lines routed adjacent to one another on a surface of the printed...
7436231 Low power and low timing jitter phase-lock loop and method  
A phase-lock loop generates an output clock signal from an input clock signal. The output clock signal is coupled through a clock tree and is fed back to a phase detector, which compares the phase...
7436202 Method and apparatus for calibrating driver impedance  
The present invention provides a method and apparatus is provided for calibrating a driver impedance in an integrated circuit device. The method includes providing a signal from a synchronous...
7436067 Methods for forming conductive structures and structures regarding same  
A method for forming a metal/metal oxide structure that includes forming metal oxide regions, e.g., ruthenium oxide regions, at grain boundaries of a metal layer, e.g., platinum. Preferably, the...
7436020 Flash memory with metal-insulator-metal tunneling program and erase  
The flash memory cell comprises a sense transistor that has a pair of source/drain lines and a control gate. A coupling metal-insulator-metal capacitor is created between the control gate and a...
7436018 Discrete trap non-volatile multi-functional memory device  
A multiple layer tunnel insulator is fabricated between a substrate and a discrete trap layer. The properties of the multiple layers determines the volatility of the memory device. The composition...
7435913 Slanted vias for electrical circuits on circuit boards and other substrates  
Circuit boards, microelectronic devices, and other apparatuses having slanted vias are disclosed herein. In one embodiment, an apparatus for interconnecting electronic components includes a...
7435688 Semiconductor processing methods of transferring patterns from patterned photoresists to materials, and structures comprising silicon nitride  
The invention includes a semiconductor processing method. A first material comprising silicon and nitrogen is formed. A second material is formed over the first material, and the second material...
7435641 Low leakage MIM capacitor  
Capacitor structures for use in integrated circuits and methods of their manufacture. The capacitor structures include a bottom electrode, a top electrode and a dielectric layer interposed between...
7435636 Fabrication of self-aligned gallium arsenide MOSFETs using damascene gate methods  
A method for fabricating a gallium arsenide MOSFET device is presented. A dummy gate is formed over a gallium arsenide substrate. Source-drain extensions are implanted into the substrate adjacent...
7435620 Low temperature methods of forming back side redistribution layers in association with through wafer interconnects  
Low temperature processed back side redistribution lines (RDLs) are disclosed. Low temperature processed back side RDLs may be electrically connected to the active surface devices of a...
7435536 Method to align mask patterns  
Alignment tolerances between narrow mask lines, for forming interconnects in the array region of an integrated circuit, and wider mask lines, for forming interconnects in the periphery of the...
7435324 Noncontact localized electrochemical deposition of metal thin films  
A method of selectively electroplating metal features on a semiconductor substrate having a conductive surface. An electrode assembly that includes a plurality of adjacent, mutually spaced and...
7434152 Multiple-level data compression read mode for memory testing  
Memory devices having a normal mode of operation and a test mode of operation are useful in quality programs. The test mode of operation includes a data compression test mode having more than one...
7434081 System and method for read synchronization of memory modules  
A memory module includes several memory devices coupled to a memory hub. The memory hub includes several link interfaces coupled to respective processors, several memory controller coupled to...
7433751 Sorting a group of integrated circuit devices for those devices requiring special testing  
A method for sorting integrated circuit (IC) devices of the type having a fuse identification (ID) into those devices requiring enhanced reliability testing and those requiring standard testing...
7433585 System and method of lens placement  
A lens-placement system in accordance with the invention includes an imaging system having an imaging camera to capture an image of at least a portion of an image sensor module that is located in a...
7433250 Sense amplifier circuit  
An equalization circuit may include a first sense amplifier having an input, the input being electrically isolated from an input to a second sense amplifier. An equalizer may be connected to the...
7433249 Apparatus with equalizing voltage generation circuit and methods of use  
A memory device includes an equalization voltage generator. The equalization voltage generator includes an oscillator and a charge pump to produce a first voltage, which may be used as an...
7433248 System and method for enhanced mode register definitions  
Apparatus and methods for increasing a number of selectable options for an operating mode. A number of selectable options for an operating mode is increased by programming a first register with...
7433237 Memory utilizing oxide nanolaminates  
One transistor embodiment includes a first source/drain region, a second source/drain region, and a channel region therebetween. A gate is separated from the channel region by a gate insulator. The...
7433231 Multiple select gates with non-volatile memory cells  
Multiple select gates in association with non-volatile memory cells are described. Various embodiments include multiple select gate structure, process, and operation and their applicability for...
7433227 Resistance variable memory device with sputtered metal-chalcogenide region and method of fabrication  
A chalcogenide-based programmable conductor memory device and method of forming the device, wherein a chalcogenide glass region is provided with a plurality of alternating tin chalcogenide and...
7432968 CMOS image sensor with reduced 1/f noise  
A CMOS image sensor includes a plurality of pixel circuits. Each pixel circuit includes a plurality of transistors. The image sensor includes a controller for controlling operation of the plurality...
7432774 Microstrip line dielectric overlay  
A printed circuit board has a dielectric constant different from the dielectric constant of free space, with at least two microstrip lines routed adjacent to one another on a surface of the printed...
7432604 Semiconductor component and system having thinned, encapsulated dice  
A semiconductor component includes a thinned semiconductor die having protective polymer layers on up to six surfaces. The component also includes contact bumps on the die embedded in a circuit...
7432600 System having semiconductor component with multiple stacked dice  
A system includes a semiconductor component having a base die and a secondary die flip chip mounted to the base die. The base die includes a set of stacking contacts for flip chip mounting the...
7432593 Semiconductor package assembly and method for electrically isolating modules  
A semiconductor package assembly and method for electrically isolating modules, having a capacitor within the semiconductor package assembly. The package assembly and method are suitable for...
7432562 SRAM devices, and electronic systems comprising SRAM devices  
The invention includes SRAM constructions comprising at least one transistor device having an active region extending into a crystalline layer comprising Si/Ge. A majority of the active region...
7432548 Silicon lanthanide oxynitride films  
Electronic apparatus and methods of forming the electronic apparatus include a silicon lanthanide oxynitride film on a substrate for use in a variety of electronic systems. The silicon lanthanide...
7432546 Apparatus having a memory device with floating gate layer grain boundaries with oxidized portions  
The present invention provides a flash memory integrated circuit and a method for fabricating the same. The method includes etching a gate stack that includes an initial oxide layer directly in...
7432540 Dual conversion gain gate and capacitor combination  
A pixel cell array architecture having a dual conversion gain. A dual conversion gain element is coupled between a floating diffusion region and a respective storage capacitor. The dual conversion...
7432491 Pixel with spatially varying sensor positions  
An image sensor including a substrate, at least one metal layer, and a plurality of pixels arranged in array. Each pixel includes a sense element disposed in the substrate and at least one metal...
Matches 151 - 200 out of 17621 < 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 >