Matches 201 - 250 out of 17621 < 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 >
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7432214 Compositions for dissolution of low-k dielectric film, and methods of use  
An improved composition and method for cleaning the surface of a semiconductor wafer are provided. The composition can be used to selectively remove a low-k dielectric material such as silicon...
7432212 Methods of processing a semiconductor substrate  
The invention includes methods of processing semiconductor substrates. In one implementation, a semiconductor substrate is provided which has an outer surface. Such surface has a peripheral region...
7432197 Methods of patterning photoresist, and methods of forming semiconductor constructions  
The invention includes semiconductor constructions containing optically saturable absorption layers. An optically saturable absorption layer can be between photoresist and a topography, with the...
7432166 Methods of forming a nitrogen enriched region  
The invention encompasses a method of incorporating nitrogen into a silicon-oxide-containing layer. The silicon-oxide-containing layer is exposed to a nitrogen-containing plasma to introduce...
7432152 Methods of forming HSG layers and devices  
A polysilicon film is formed with enhanced selectivity by flowing chlorine during the formation of the film. The chlorine acts as an etchant to insulative areas adjacent polysilicon structures on...
7432148 Shallow trench isolation by atomic-level silicon reconstruction  
Methods of forming an improved shallow trench isolation (STI) region are disclosed. Several exemplary techniques are proposed for treating STI sidewalls to improve the silicon (Si) surface at the...
7432121 Isolation process and structure for CMOS imagers  
A barrier implanted region of a first conductivity type formed in lieu of an isolation region of a pixel sensor cell that provides physical and electrical isolation of photosensitive elements of...
7432025 Methods of forming reticles  
The invention includes reticle constructions and methods of forming reticle constructions. In a particular aspect, a method of forming a reticle includes provision of a reticle substrate having a...
7431966 Atomic layer deposition method of depositing an oxide on a substrate  
The invention includes atomic layer deposition methods of depositing an oxide on a substrate. In one implementation, a substrate is positioned within a deposition chamber. A first species is...
7431773 Atomic layer deposition apparatus and method  
An atomic layer deposition method includes positioning a semiconductor substrate within an atomic layer deposition chamber. A first deposition precursor is fed to the chamber under first vacuum...
7431225 Methods of operating a liquid vaporizer  
The present invention is generally directed to a vaporizer with positive liquid shut-off. In one illustrative embodiment, the vaporizer is comprised of a body, a liquid inlet and a carrier gas...
7430742 Method for load balancing a line of parallel processing elements  
A method for balancing the load of a parallel processing system having parallel processing elements (PEs) linked serially in a line with first and second ends, wherein each of the PEs has a local...
7430002 Digital imaging system and method for adjusting image-capturing parameters using image comparisons  
A digital imaging system and method for manually adjusting the image-capturing parameters of a digital imaging device of the system utilizes a comparative image scheme that allows users to adjust...
7429767 High performance multi-level non-volatile memory device  
Non-volatile memory devices and arrays are described that utilize band engineered gate-stacks and multiple charge trapping layers allowing a multiple trapping site gate-insulator stack memory cell...
7429763 Memory with strained semiconductor by wafer bonding with misorientation  
One aspect of the present invention relates to a method for forming a strained semiconductor structure. In various embodiments, at least two strong bonding regions are defined for a desired bond...
7429541 Method of forming trench isolation in the fabrication of integrated circuitry  
This invention includes methods of depositing a silicon dioxide comprising layer in the fabrication of integrated circuitry, and to methods of forming trench isolation in the fabrication of...
7429536 Methods for forming arrays of small, closely spaced features  
Methods of forming arrays of small, densely spaced holes or pillars for use in integrated circuits are disclosed. Various pattern transfer and etching steps can be used, in combination with...
7429535 Use of a plasma source to form a layer during the formation of a semiconductor device  
A method used to form a semiconductor device having a capacitor comprises placing a semiconductor wafer assembly into a chamber of a plasma source, the wafer assembly comprising a layer of...
7429515 Low-temperature grown high quality ultra-thin CoTiO3 gate dielectrics  
A gate oxide and method of fabricating a gate oxide that produces a more reliable and thinner equivalent oxide thickness than conventional SiO 2 gate oxides are provided. Gate oxides formed from...
7429514 Use of selective oxidation to form asymmetrical oxide features during the manufacture of a semiconductor device  
A sidewall oxidation process for use during the formation of a transistor such as a flash memory cell allows for improved control of a gate oxide profile. The method comprises doping transistor...
7429494 Microelectronic imagers with optical devices having integral reference features and methods for manufacturing such microelectronic imagers  
Microelectronic imager assemblies with optical devices having integral reference features and methods for assembling such microelectronic imagers is disclosed herein. In one embodiment, the imager...
7428714 Line width error check  
A method of checking for errors in line width in an integrated circuit includes identifying with a marker any lines having a line width greater than a minimum line width, and associating a line...
7428687 Memory controller method and system compensating for memory cell data losses  
A computer system includes a memory controller coupled to a memory module containing several DRAMs. The memory module also includes a non-volatile memory storing row addresses identifying rows...
7428672 Apparatus and methods for testing memory devices  
Each match line of a memory device such as a content addressable memory (CAM) device and a related part of a priority encoder can be separately tested. In test mode, all match lines are first...
7428644 System and method for selective memory module power management  
A memory module includes a memory hub that monitors utilization of the memory module and directs devices of the memory module to a reduced power state when the module is not being used at a desired...
7428373 Delivery of solid chemical precursors  
Systems and methods are provided for delivering solid precursors. In certain embodiments of the present application, a flow monitor, pressure sensor, or temperature sensor is used to measure and...
7428284 Phase detector and method providing rapid locking of delay-lock loops  
A delay-lock loop includes a dual mode phase detector. The dual mode phase detector includes a single edge phase detector that generates output signals indicative of the phase relationship between...
7428181 Semiconductor device with self refresh test mode  
A semiconductor device includes a memory array that has dynamic memory cells. In a self refresh test mode, a self refresh test mode controller monitors and/or controls various blocks and internal...
7428173 Low power NROM memory devices  
A buried bipolar junction is provided in a charge trapping transistor memory device. During a write operation electrons are injected into a surface depletion region of the memory cell transistors....
7428103 Gapless microlens array and method of fabrication  
A microlens array with reduced or no empty space between individual microlenses and a method for forming the same. The microlens array is formed by patterning a first set of microlens precursors in...
7427869 Resilient contact probe apparatus  
Carriers comprising a carrier body having a plurality of openings holding a plurality of resilient contact probes are disclosed. A number of different embodiments for the resilient contact probes...
7427837 Rear plate for plasma display panel with barrier ribs having specific width characteristics  
Disclosed is a rear plate of a plasma display panel. In the rear plate, barrier ribs are formed by etching a baked barrier rib layer, so that the completed barrier ribs have no deformation and the...
7427811 Semiconductor substrate  
A semiconductor wafer having a high degree of thinness and exhibiting an enhanced strength state. A layer of tenacious reinforcement material is disposed over a back side of the wafer while in a...
7427798 Photonic crystal-based lens elements for use in an image sensor  
The invention, in various exemplary embodiments, incorporates a photonic crystal lens element into an image sensor. The photonic crystal lens element comprises a substrate and a plurality of...
7427793 Sacrificial self-aligned interconnect structure  
A sacrificial, self-aligned polysilicon interconnect structure is formed in a region of insulating material to the side of an active region location and underlying a semiconductor device of a...
7427770 Memory array for increased bit density  
A memory array having a plurality of resistance variable memory units and method for forming the same are provided. Each memory unit includes a first electrode, a resistance variable material over...
7427737 Pixel with differential readout  
An imager in which two adjacent pixels share row and reset lines and a row selection circuitry while the output transistors of the two pixels are configured as a differential amplifier. In...
7427736 Method and apparatus for providing a rolling double reset timing for global storage in image sensors  
An apparatus for and a method of operating an array of pixels of an image sensor, where each pixel includes at least a photosensor, an associated storage device and a floating diffusion region and...
7427735 Method and apparatus for setting black level in an imager using both optically black and tied pixels  
An imaging pixel array includes an active area of pixels, organized into rows and columns of pixels. The array also includes a plurality of dark pixel columns adjacent to the active area of pixels...
7427570 Porous organosilicate layers, and vapor deposition systems and methods for preparing same  
The present invention provides porous organosilicate layers, and vapor deposition systems and methods for preparing such layers on substrates. The porous organosilicate layers are useful, for...
7427536 High density stepped, non-planar nitride read only memory  
A non-planar, stepped NROM array is comprised of cells formed in trenches and on pillars that are etched into a substrate. Each cell has a plurality of charge storage regions in its nitride layer...
7427535 Semiconductor/printed circuit board assembly, and computer system  
A method of forming a computer system and a printed circuit board assembly, are provided comprising first and second semiconductor dies and an intermediate substrate. The intermediate substrate is...
7427514 Passivated magneto-resistive bit structure and passivation method therefor  
A passivated magneto-resistive bit structure is disclosed in which surfaces subjects to oxidation or corrosion are protected. In one embodiment, a bit structure is encapsulated by means of an etch...
7427425 Reactors with isolated gas connectors and methods for depositing materials onto micro-device workpieces  
Reactors having gas distributors for depositing materials onto micro-device workpieces, systems that include such reactors, and methods for depositing materials onto micro-device workpieces. In one...
7426148 Method and apparatus for identifying short circuits in an integrated circuit device  
The disclosed embodiments relate to a method and apparatus for identifying short circuits in an integrated circuit device. The method may comprise the acts of programming a first memory cell...
7425847 Input buffer with optimal biasing and method thereof  
A method and circuit of a biased input buffer is described to maximize the quality in the output signals. The input buffer includes a first stage for receiving differential input signals and...
7425839 Systems and methods for testing packaged microelectronic devices  
Systems and methods for testing packaged microelectronic devices are disclosed herein. One such system for testing a packaged microelectronic device includes a test socket configured to receive the...
7425758 Metal core foldover package structures  
Chip-scale packages and assemblies thereof and methods of fabricating such packages including Chip-On-Board, Board-On-Chip, and vertically stacked Package-On-Package modules are disclosed. The...
7425742 NAND flash cell structure  
NAND architecture Flash memory strings, memory arrays, and memory devices are described that utilize continuous channel enhancement and depletion mode floating gate memory cells. Depletion mode...
7425507 Semiconductor substrates including vias of nonuniform cross section, methods of forming and associated structures  
Methods for forming a via and a conductive path are disclosed. The methods include forming a via within a wafer with cyclic etch/polymer phases, followed by an augmented etch phase. The resulting...
Matches 201 - 250 out of 17621 < 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 >