Matches 351 - 400 out of 17621 < 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 >
Match Document Document Title
7413928 Die-wafer package and method of fabricating same  
A die-wafer package includes a singulated semiconductor die having a first plurality of bond pads on a first surface and a second plurality of bond pads on a second opposing surface thereof. Each...
7413500 Methods for planarizing workpieces, e.g., microelectronic workpieces  
This disclosure provides methods and apparatus for predictably changing the thickness of a microfeature workpiece. One implementation provides a planarizing method in which a first workpiece is...
7413480 Silicon pillars for vertical transistors  
In order to form a more stable silicon pillar which can be used for the formation of vertical transistors in DRAM cells, a multi-step masking process is used. In a preferred embodiment, an oxide...
7413342 DRAM temperature measurement system  
A converter comprising a comparator having a first input operable to receive a first signal, a second input operable to receive a second signal, and an output, a switch for sinking a portion of the...
7412634 On-chip sampling circuit and method  
Through addressing circuitry, a sampling circuit can choose a unique internal node/signal on an encapsulated/packaged chip to be output to one or more drivers. The chosen signals available at the...
7412574 System and method for arbitration of memory responses in a hub-based memory system  
A memory hub module includes a decoder that receives memory requests determines a memory request identifier associated with each memory request. A packet memory receives memory request identifiers...
7412571 Memory arbitration system and method having an arbitration packet protocol  
A memory hub and method for transmitting a read response on a data path of a memory hub interposed between a transmitting memory hub and a receiving memory hub. An arbitration packet including data...
7412566 Memory hub and access method having internal prefetch buffers  
A memory module includes a memory hub coupled to several memory devices. The memory hub includes history logic that predicts on the basis of read memory requests which addresses in the memory...
7411857 Power savings in active standby mode  
Apparatus for reducing the power consumed by a memory device selectively activates a power saving mode in which operation of a delay compensation circuit may be suspended during an active power...
7411848 Independent polling for multi-page programming  
A method of testing, polling and trimming memory pages in different memory banks simultaneously is presented, using a cache memory located in each one of the memory banks. The cache memory is at...
7411832 Programming a non-volatile memory device  
A non-volatile memory device that changes the programming step voltage between the source side of the array and the drain side of the array. After the initial programming pulse, a verify operation...
7411823 In-service reconfigurable DRAM and flash memory device  
A memory cell that has both a DRAM cell and a non-volatile memory cell. The non-volatile memory cell might include a flash memory or an NROM cell. The memory cell is comprised of a vertical...
7411812 Memory architecture and method of manufacture and operation thereof  
An architecture, and its method of formation and operation, containing a high density memory array of semi-volatile or non-volatile memory elements, including, but not limited to, programmable...
7411807 System and method for optically interconnecting memory devices  
A memory device includes a semiconductor substrate in which memory circuitry has been fabricated. An address converter and a control signal converter are coupled to an address decoder and control...
7411621 Apparatus and method for eliminating artifacts in active pixel sensor (APS) imagers  
An active pixel sensor (APS) that includes circuitry to eliminate artifacts in digital images. The APS includes a comparator for comparing a signal level from a pixel to an adjusted saturation...
7411566 System and method for a portable terminal having a dual display module structure  
A portable terminal has the dual display module structure in which a plurality of panels provided in the portable terminal are combined with clear conjunction to display a distortionless large...
7411304 Semiconductor interconnect having conductive spring contacts  
An interconnect for testing a semiconductor component includes a substrate, and interconnect contacts on the substrate configured to electrically engage component contacts on a semiconductor...
7411300 Agglomeration control using early transition metal alloys  
Structures and methods of fabricating portions of integrated circuit devices to reduce agglomeration tendencies of high surface-energy metals used in interconnects and contacts. Early transition...
7411297 Microfeature devices and methods for manufacturing microfeature devices  
Microfeature devices, microfeature workpieces, and methods for manufacturing microfeature devices and microfeature workpieces are disclosed herein. The microfeature workpieces have an integrated...
7411286 Methods for stacking wire-bonded integrated circuit dice on flip-chip bonded integrated circuit dice  
An inventive electronic device, such as a multi-chip module (MCM), a Single In-line Memory Module (SIMM), or a Dual In-line Memory Module (DIMM), includes a base, such as a printed circuit board,...
7411262 Self-aligned, low-resistance, efficient memory array  
The present invention seeks to reduce the amount of current required for a write operation by using a process for forming the read conductor within a recessed write conductor, the write conductor...
7411255 Dopant barrier for doped glass in memory devices  
A semiconductor device has a diffusion barrier formed between a doped glass layer and surface structures formed on a substrate. The diffusion barrier includes alumina and optionally a nitride, and...
7411254 Semiconductor substrate  
The invention includes methods of forming conductive metal silicides by reaction of metal with silicon. In one implementation, such a method includes providing a semiconductor substrate comprising...
7411237 Lanthanum hafnium oxide dielectrics  
Dielectric layers containing a lanthanum hafnium oxide layer, where the lanthanum hafnium oxide layer is arranged as a structure of one or more monolayers, provide an insulating layer in a variety...
7410918 Systems and methods for forming metal oxides using alcohols  
A method of forming (and an apparatus for forming) a metal oxide layer on a substrate, particularly a semiconductor substrate or substrate assembly, using a vapor deposition process, one or more...
7410917 Atomic layer deposited Zr-Sn-Ti-O films using TiI4  
Various structures having a dielectric film containing Zr—Sn—Ti—O formed by atomic layer deposition using a TiI 4 precursor and a method of fabricating structures having such a dielectric...
7410911 Method for stabilizing high pressure oxidation of a semiconductor device  
A method and apparatus for preventing N 2 O from becoming super critical during a high pressure oxidation stage within a high pressure oxidation furnace are disclosed. The method and apparatus...
7410910 Lanthanum aluminum oxynitride dielectric films  
Electronic apparatus and methods of forming the electronic apparatus include a lanthanum aluminum oxynitride film on a substrate for use in a variety of electronic systems. The lanthanum aluminum...
7410903 Methods of patterning substrates  
The invention includes a template comprising one or both of CdS and CdSe adhered to a base in a desired pattern. The base can be any transparent or translucent material, and the desired pattern can...
7410898 Methods of fabricating interconnects for semiconductor components  
In one aspect, the invention encompasses a method of fabricating an interconnect for a semiconductor component. A semiconductor substrate is provided, and an opening is formed which extends...
7410867 Vertical transistor with horizontal gate layers  
Vertical body transistors with adjacent horizontal gate layers are used to form a memory array in a high density flash electrically erasable and programmable read only memory (EEPROM) or a logic...
7410863 Methods of forming and using memory cell structures  
A method of filling vias for a PCRAM cell with a metal is described. A PCRAM intermediate structure including a substrate, a first conductor, and an insulator through which a via extends has a...
7410856 Methods of forming vertical transistors  
A vertical transistor forming method includes forming a first pillar above a first source/drain and between second and third pillars, providing a first recess between the first and second pillars...
7410748 Method of etching materials patterned with a single layer 193nm resist  
A technique for etching with a single layered patterned photomask at wavelengths of 193 nanometers or less. Specifically, a method for etching a bottom anti-reflectant coating layer that utilizes a...
7410668 Methods, systems, and apparatus for uniform chemical-vapor depositions  
Integrated circuits, the key components in thousands of electronic and computer products, are generally built layer by layer on a silicon substrate. One common technique for forming layers is...
7409762 Method for fabricating an interconnect for semiconductor components  
A method for fabricating an interconnect for testing a semiconductor component includes the steps of providing a substrate, and forming interconnect contacts on the substrate configured to...
7409529 Method and apparatus for a shift register based interconnection for a massively parallel processor array  
A system and method for using wider data paths within Processing Elements (PEs) of a Massively Parallel Array (MPP) to speed the computational performance of the PEs and the MPP array while still...
7409493 Top/bottom symmetrical protection scheme for flash  
A synchronous flash memory includes an array of non-volatile memory cells. The memory device has a package configuration that is compatible with an SDRAM. The memory device can comprise an array of...
7408828 System and method for reducing power consumption during extended refresh periods of dynamic random access memory devices  
A dynamic random access memory (“DRAM”) device is operable in either a normal refresh mode or a static refresh mode, such as a self-refresh mode. A cell plate voltage selector couples a voltage...
7408825 Apparatus and method for repairing a semiconductor memory  
An apparatus and method for repairing a semiconductor memory device includes a first memory cell array, a first redundant cell array and a repair circuit configured to nonvolatilely store a first...
7408822 Alignment of memory read data and clocking  
Circuits and methods are provided for aligning data read from a memory with an output clock signal when the memory is operated at very high clock frequencies. To align data and clock signals when...
7408814 Method and apparatus for filtering output data  
Apparatus and methods for filtering spurious output transitions with an adaptive filtering circuit which tracks the memory architecture and form factors with a reduced speed penalty. The filtering...
7408813 Block erase for volatile memory  
A system and method for erasing a block of data in a plurality of memory cells includes clamping one of a digit line and an I/O line in a sensing circuit of a memory device to a fixed logic level....
7408810 Minimizing effects of program disturb in a memory device  
A selected word line that is coupled to cells for programming is biased with an initial programming voltage. The unselected wordlines that are adjacent to the selected word line are biased at an...
7408808 User configurable commands for flash memory  
A memory device includes a plurality of memory dies, each having an assigned address. A register on each die is reset on power-up. Boot data is loaded as part of the initialization routine. If the...
7408807 NAND string wordline delay reduction  
An improved NAND Flash memory and word line selection method has been described, that takes advantage of the asymmetric nature of the word line to word line capacitive coupling to reduce word line...
7408805 Reducing delays in word line selection  
Delays in selecting word lines of a NAND memory device are reduced by respectively connecting conductive straps to word lines of a subset of the word lines of the memory device.
7408577 Biasing scheme for large format CMOS active pixel sensors  
An image sensor includes circuitry compensating for voltage drops in a V SS line. The image sensor includes a plurality of photoreceptors arranged in a pixel array having a number of column lines,...
7408496 Method, apparatus and system sharing an operational amplifier between two stages of pipelined ADC and/or two channels of signal processing circuitry  
A mechanism for discharging parasitic capacitance at an input of an operational amplifier, which is shared between two stages of a pipelined analog-to-digital converter and/or two channels of...
7408394 Measure control delay and method having latching circuit integral with delay circuit  
A measure control delay includes a measuring delay line and a signal generating delay line, each of which include a plurality of series-connected delay units. A digital signal is applied to an...
Matches 351 - 400 out of 17621 < 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 >