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Match Document Document Title
7473960 Non-volatile two-transistor programmable logic cell and array layout  
A two-transistor non-volatile memory cell is formed in a semiconductor body. A memory-transistor well is disposed within the semiconductor body. A switch-transistor well is disposed within the...
7473959 Non-volatile semiconductor memory devices and methods of fabricating the same  
Nonvolatile memory devices and related methods of fabricating nonvolatile memory devices are disclosed. A nonvolatile memory device includes a tunnel insulation film on a semiconductor substrate, a...
7473958 Electronic memory component with protection against light attack  
In order to further develop an electronic memory component ( 100 or 100′ ), comprising at least one memory cell matrix ( 10 ) which is embedded in and/or let into at least one doped receiving...
7473957 Floating gate non-volatile memory  
A floating non-volatile memory has a substrate and source and drain regions disposed in a surface region of the substrate and spaced apart from each other with a channel forming semiconductor...
7470949 Bidirectional nonvolatile memory cell having charge trapping layer in trench and an array of such memory cells, and method of manufacturing  
A nonvolatile memory cell has a charge trapping layer for the storage of charges thereon. The cell is a bidirectional cell in a substrate of a first conductivity. The cell has two spaced apart...
7470947 Semiconductor memory and fabrication method for the same  
A semiconductor memory includes memory cell transistors comprising a tunnel insulating film, a floating gate electrode, a first insulating film, a control gate electrode, and a first metal salicide...
7470587 Flash memory device and method of manufacturing the same  
A flash memory device includes trenches that are formed at regions on a semiconductor substrate spaced apart from one another at predetermined distances, buried floating gates buried into the...
7462906 Flash memory process with high voltage LDMOS embedded  
A method of embedding the forming of peripheral devices such as HV-LDMOS into the forming of flash memory is presented. A layered structure is formed with a first insulating layer formed on a...
7462905 Nonvolatile semiconductor memory device, semiconductor device and method of manufacturing nonvolatile semiconductor memory device  
A nonvolatile semiconductor memory device includes a semiconductor substrate, a first floating gate formed on a main surface of the semiconductor substrate, a second floating gate formed on the...
7462904 Non-volatile memory devices and methods of forming the same  
A non-volatile memory device includes an upwardly protruding fin disposed on a substrate and a control gate electrode crossing the fin. A floating gate is interposed between the control gate...
7460396 Semiconductor device  
In a data program/erase device of a nonvolatile memory cell, data are re-written by means of an FN tunnel current of an entire channel surface. In a buried n-well of a semiconductor substrate in a...
7459741 Semiconductor memory device  
A semiconductor memory device excellent in data holding characteristics even when a cell area is reduced is disclosed. According to one aspect of the present invention, a semiconductor memory...
7459740 Integrated DRAM-NVRAM multi-level memory  
An integrated DRAM-NVRAM, multi-level memory cell is comprised of a vertical DRAM device with a shared vertical gate floating plate device. The floating plate device provides enhanced charge...
7457159 Integrated DRAM-NVRAM multi-level memory  
An integrated DRAM-NVRAM, multi-level memory cell is comprised of a vertical DRAM device with a shared vertical gate floating plate device. The floating plate device provides enhanced charge...
7456467 Process for manufacturing a byte selection transistor for a matrix of non volatile memory cells and corresponding structure  
A process for manufacturing a matrix of non volatile memory cells includes forming a floating gate transistor and a cell selection transistor in a first active area, and a byte selection transistor...
7456466 NAND flash memory device and method of manufacturing the same  
A NAND flash memory device and method of manufacturing the same is disclosed. Source and drain select transistor gates are recessed lower than an active region of a semiconductor substrate. A valid...
7453117 Non-volatile semiconductor memory device  
To achieve a high-speed and reliable read operation. A unit cell is constituted by a select gate 3 provided in a first region and on a substrate 1 with an insulating film 2 interposed...
7450423 Methods of operating non-volatile memory cells having an oxide/nitride multilayer insulating structure  
A method of operating a memory cell by applying a positive voltage to the gate sufficient to cause hole tunneling from the gate toward the charge storage layer is disclosed. The method is applied...
7449747 Semiconductor memory device  
Flash memory is rapidly decreasing in price. There is a demand for a new memory system that permits size reduction and suits multiple-value memory. A flash memory of AND type suitable for...
7449745 Nonvolatile semiconductor memory device having element isolating region of trench type  
Disclosure is semiconductor device of a selective gate region, comprising a semiconductor layer, a first insulating film formed on the semiconductor layer, a first electrode layer formed on the...
7449744 Non-volatile electrically alterable memory cell and use thereof in multi-function memory array  
A multi-function memory array that includes a DRAM distributed in several DRAM sectors, a Flash EEPROM distributed in several Flash EEPROM sectors, a data bus interconnecting the DRAM sectors and...
7449742 Memory device with active layer of dendrimeric material  
The present memory device includes first and second electrodes, a passive layer between the first and second electrodes; and an active layer between the first and second electrodes, the active...
7446370 Non-volatile memory  
A non-volatile memory is provided, including a substrate, a control gate, a floating gate, and a select gate. A source region and a drain region are disposed in the substrate. The control gate is...
7442988 Semiconductor devices and methods of fabricating the same  
Disclosed is a semiconductor device and method of fabricating the same. The device is disposed on a substrate, including a fin constructed with first and second sidewalls, a first gate line formed...
7442987 Non-volatile memory devices including divided charge storage structures  
A semiconductor memory device includes a substrate having first and second source/drain regions therein and a channel region therebetween. The device also includes first and second charge storage...
7442986 Nonvolatile semiconductor memory device with tapered sidewall gate and method of manufacturing the same  
In a split gate type nonvolatile memory cell in which a MOS transistor for a nonvolatile memory using a charge storing film and a MOS transistor for selecting it are adjacently formed, the charge...
7442985 Semiconductor memory device having memory cell section and peripheral circuit section and method of manufacturing the same  
An element isolating region for separating an element region of a semiconductor layer is formed in a peripheral circuit section of a semiconductor memory device, and a first conductive layer is...
7442984 Semiconductor memory device and manufacturing method thereof  
An active region is provided which includes a plurality of active region columns extending in a first direction and a plurality of active region rows extending in a second direction substantially...
7439574 Silicon/oxide/nitride/silicon nonvolatile memory with vertical channels  
Provided are a silicon/oxide/nitride/oxide/silicon (SONOS) memory, a fabricating method thereof, and a memory programming method. The SONOS memory includes a substrate; a first insulating layer...
7439573 Semiconductor device including transistor with composite gate structure and transistor with single gate structure, and method for manufacturing the same  
A semiconductor device comprises a first transistor having a composite gate structure containing a lamination of a first polycrystalline silicon film, an interlayer insulating film, and a second...
7439572 Stacked gate memory cell with erase to gate, array, and method of manufacturing  
A stacked gate nonvolatile memory floating gate device has a control gate. Programming of the cell in the array is accomplished by hot channel electron injecton from the drain to the floating gate....
7439571 Method for fabricating metal gate structures  
Methods of forming a microelectronic structure are described. Those methods comprise providing a substrate comprising source/drain and gate regions, wherein the gate region comprises a metal layer...
7436707 Flash memory cell structure and operating method thereof  
A flash memory cell structure has a substrate, a select gate, a first-type doped region, a shallow second-type doped region, a deep second-type doped region, and a doped source region. The...
7432547 Non-volatile memory device with improved data retention and method therefor  
A semiconductor device ( 30 ) comprises an underlying insulating layer ( 34 ), an overlying insulating layer ( 42 ) and a charge storage layer ( 36 ) between the insulating layers ( 34, 42 ). The...
7429766 Split gate type nonvolatile memory device  
In a split gate type nonvolatile memory device, a supplementary layer pattern is disposed on a source region of a semiconductor substrate. Since the source region is vertically extended by virtue...
7427544 Semiconductor device and method of manufacturing the same  
A semiconductor device includes an element isolation insulating film provided in a semiconductor substrate between first and second element regions, a gate electrode running over the element...
7425742 NAND flash cell structure  
NAND architecture Flash memory strings, memory arrays, and memory devices are described that utilize continuous channel enhancement and depletion mode floating gate memory cells. Depletion mode...
7425741 EEPROM structure with improved data retention utilizing biased metal plate and conductive layer exclusion  
A biased conductive plate is provided over an NVM cell structure to overcome data retention charge loss due to the presence of dielectric films that are conductive at higher temperatures. The...
7425482 Non-volatile memory device and method for fabricating the same  
A non-volatile memory device and a method for fabricating the same are provided. The method includes: forming a plurality of gate structures on a substrate, each gate structure including a first...
7423903 Single-gate non-volatile memory and operation method thereof  
A single-gate non-volatile memory and an operation method thereof, wherein a transistor and a capacitor structure are embedded in a semiconductor substrate; the transistor comprises: a first...
7423312 Apparatus and method for a memory array with shallow trench isolation regions between bit lines for increased process margins  
The present invention provides an apparatus and method for a non-volatile memory comprising at least one array of memory cells with shallow trench isolation (STI) regions between bit lines for...
RE40486 Self-aligned non-volatile memory cell  
Disclosed is a self-aligned non-volatile memory cell including a small sidewall spacer electrically coupled and being located next to a main floating gate region. Both the small sidewall spacer and...
7420243 Non-volatile memory device with buried control gate and method of fabricating the same  
In a non-volatile memory device with a buried control gate, the effective channel length of the control gate is increased to restrain punchthrough, and a region for storing charge is increased for...
7420242 Stacked bit line dual word line nonvolatile memory  
An arrangement of nonvolatile memory devices, having at least one memory device level stacked level by level above a semiconductor substrate, each memory level comprising an oxide layer...
7420241 Semiconductor memory device and method of manufacturing the same  
A semiconductor memory device includes a memory cell which includes a first gate insulation film provided on the semiconductor substrate; a floating gate electrode provided on the first gate...
7420240 Method to remove an oxide seam along gate stack edge, when nitride space formation begins with an oxide liner surrounding gate stack  
An exposed top end of a vertical oxide spacer is removed, and a nitride layer is deposited in an amount sufficient to replace the removed portion prior to exposing a memory device to a self align...
7419865 Methods of forming memory circuitry  
The invention includes methods of forming memory circuitry. In one implementation, a semiconductor substrate includes a pair of word lines having a bit node received therebetween. A bit node...
7417893 Integrated DRAM-NVRAM multi-level memory  
An integrated DRAM-NVRAM, multi-level memory cell is comprised of a vertical DRAM device with a shared vertical gate floating plate device. The floating plate device provides enhanced charge...
7417281 Semiconductor device with a selection gate and a peripheral gate  
A semiconductor device comprises a memory cell array portion and peripheral circuit portion, wherein a first insulation film including elements as main components other than nitrogen fills between...
7417280 Method and apparatus for a flash memory device comprising a source local interconnect  
A method for forming a flash memory device having a local interconnect connecting source regions of a plurality of transistors within a sector allows for a highly selective wet etch of a dielectric...
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