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Match Document Document Title
7468549 Method for producing a package for an electronic circuit and a substrate for a package  
The invention relates a substrate for a package for an electronic circuit and methods for packaging an electronic circuit with a substrate. The substrate comprises at least one conduction region...
7468525 Test structures for development of metal-insulator-metal (MIM) devices  
In the present electronic test structure comprising, a conductor is provided, overlying a substrate. An electronic device overlies a portion of the conductor and includes a first electrode...
7467360 LSI design support apparatus and LSI design support method  
An LSI design support apparatus includes a data acquisition section and an equal processing section. The data acquisition section acquires first position data concerning positions of a plurality of...
7466157 Contactless interfacing of test signals with a device under test  
An interface device receives test data from a tester. A signal representing the test data is transmitted to a device under test through electromagnetically coupled structures on the interface...
7456449 Semiconductor apparatus, LED print head, and printer  
A semiconductor apparatus has a substrate to which is attached a thin semiconductor film including at least one semiconductor device. An interconnecting line links the semiconductor film with...
7456033 Method of evaluating semiconductor device  
The present invention provides a semiconductor device having an active region bent at right angles, wherein an interval between patterns for the active region and a gate is set larger than an arc...
7455939 Method of improving grating test pattern for lithography monitoring and controlling  
A method of making a process monitor grating pattern for use in a lithographic imaging system comprises determining minimum resolvable pitch of a plurality of spaced, adjacent line elements, and...
7453272 Electrical open/short contact alignment structure for active region vs. gate region  
A method is disclosed for measuring alignment of polysilicon shapes relative to a silicon area wherein the presence of an electrical coupling is used to determine the presence of bias or...
7449909 System and method for testing one or more dies on a semiconductor wafer  
A testing system or method compares read data from one or more dies in a semiconductor wafer with the original data written onto the one or more dies. The testing system includes one or more write...
7449716 Bond quality indication by bump structure on substrate  
A bump structure on a substrate including at least one first electrode, at least one first bump, at least one second bump is provided. The first electrode is disposed on the substrate. The first...
7439586 Liquid crystal display device and fabricating method thereof  
A base thin film transistor (TFT) substrate includes a substrate, array areas on the substrate; at least one dummy area on the substrate and between the array areas; an insulating film on the...
7439538 Multi-purpose poly edge test structure  
A test structure in accordance with the present invention allows for testing of both V bd TDDB, and leakage current between adjacent gate features. The test structure comprises a plurality of...
7439122 Method of manufacturing semiconductor device having improved RESURF Trench isolation and method of evaluating manufacturing method  
A p impurity region ( 3 ) defines a RESURF isolation region in an n − semiconductor layer ( 2 ). A trench isolation structure ( 8 a ) and the p impurity region ( 3 ) together define a trench...
7439083 Technique for compensating for substrate shrinkage during manufacture of an electronic assembly  
Substrate shrinkage that occurs during manufacture of an electronic assembly is compensated for by the incorporation of a horizontal line, having a plurality of vertical graduations, across a...
7436199 Stack-type semiconductor package sockets and stack-type semiconductor package test systems  
A stack-type semiconductor package socket may include: a first package connection portion for connection with leads of a lowermost package of a stack-type semiconductor package; a second package...
7435991 Micromechanical sensor  
A micromechanical sensor and a method for manufacturing same are described. A secure diaphragm restraint, independent of fluctuations in the cavern etching process due to the process technology,...
7435990 Arrangement for testing semiconductor chips while incorporated on a semiconductor wafer  
An arrangement that will provide multiple communication paths for the simultaneously testing of a plurality of un-diced chips on a semiconductor wafer that will simultaneously permit each such...
7427774 Targets for measurements in semiconductor devices  
Targets or test structures used for measurements in semiconductor devices having long lines exceeding design rule limitations are divided into segments. In one embodiment, the segments have...
7423288 Technique for evaluating a fabrication of a die and wafer  
The fabrication of the wafer may be analyzed starting from when the wafer is in a partially fabricated state. The value of a specified performance parameter may be determined at a plurality of...
7423287 System and method for measuring residual stress  
The invention comprises devices and methods for determining residual stress in MEMS devices such as interferometric modulators. In one example, a device measuring residual stress of a deposited...
7423286 Laser transfer article and method of making  
The present invention is directed to methods for transferring pre-formed electronic devices, such as transistors, resistors, capacitors, diodes, semiconductors, inductors, conductors, and...
7423282 Memory structure and method of manufacture  
A solid state electrolyte memory structure includes a solid state electrolyte layer, a metal layer on the solid state electrolyte layer, and an etch stop layer on the metal layer.
7420206 Interposer, semiconductor chip mounted sub-board, and semiconductor package  
A semiconductor device can be manufactured with a high non-defect ratio, making it possible to easily guarantee the KGD (Known-Good-Die) of semiconductor chips, when configuring one packaged...
7419299 Methods of sensing temperature of an electronic device workpiece  
The present invention includes electronic device workpieces, methods of semiconductor processing and methods of sensing temperature of an electronic device workpiece. In one aspect, the invention...
7418643 Integrated circuit having electrically isolatable test circuitry  
Special test circuitry in an IC for wafer level testing selectively connects the specialized test circuitry to the functional circuitry during wafer test. Following wafer test the special test...
7418283 Adiabatic quantum computation with superconducting qubits  
A method for quantum computing using a quantum system comprising a plurality of qubits is provided. The system can be in any one of at least two configurations at any given time including one...
7416819 Test mask for optical and electron optical systems  
A test mask 1 for microscopy is disclosed, which is formed on a substrate of quartz. The test mask 1 comprises a multiplicity of sub-masks 4 , which are implemented such that each sub-mask 4 ...
7411294 Display device having misalignment detection pattern for detecting misalignment between conductive layer and insulating layer  
A display device includes a display panel, and the circuit substrate is separately formed and positioned different from the array substrate of the display panel and connected to the display panel....
7411210 Semiconductor probe with resistive tip having metal shield thereon  
A semiconductor probe with a resistive tip and a method of fabricating the semiconductor probe. The resistive tip doped with a first impurity includes a resistive region formed at a peak thereof...
7410837 Method of manufacturing mounting substrate  
A method for manufacturing a mounting substrate on which a semiconductor chip is mounted includes: forming a wiring section by electrolytic plating on a first face of a supporting substrate which...
7408189 Method of testing FPC bonding yield and FPC having testing pads thereon  
A flexible printed circuit (FPC) having testing pads thereon is provided. The FPC comprises a plurality of bonding pads and a plurality of testing pads, wherein each of the testing pads is disposed...
7405423 Random number generating device  
The objective is to provide a random number generating device having a smaller circuit size and a smaller value of output bias. The random number generating device includes a pair of first and...
7400157 Composite wiring structure having a wiring block and an insulating layer with electrical connections to probes  
A method of designing and manufacturing a probe card assembly includes prefabricating one or more elements of the probe card assembly to one or more predefined designs. Thereafter, design data...
7399990 Wafer-level package having test terminal  
A wafer-level package includes a semiconductor wafer having at least one semiconductor chip circuit forming region each including a semiconductor chip circuit each provided with test chip terminals...
7397260 Structure and method for monitoring stress-induced degradation of conductive interconnects  
A microelectronic element such as a chip or microelectronic wiring substrate is provided which includes a plurality of conductive interconnects for improved resistance to thermal stress. At least...
7394164 Semiconductor device having bumps in a same row for staggered probing  
A semiconductor device has a plurality of bumps in a same row for staggered probing. The bumps in a same row are disposed on a chip and include a plurality of regular bumps and a plurality of...
7393754 Tape carrier type semiconductor device and method of producing the same  
A tape carrier type semiconductor device comprising: a long flexible insulating tape; and a plurality of semiconductor devices sequentially arranged on one surface of the tape, wherein each...
7393619 Method and lithographic structure for measuring lengths of lines and spaces  
There is a structure and method for measuring the lengths of lines and spaces in semiconductor process. In an example embodiment, a lithographic structure ( 400 ) comprises, a frame ( 450 ). The...
7393471 Anisotropic conductive sheet, its manufacturing method, and its application  
An anisotropically conductive sheet which does not contaminate an object of connection, does not adhere to the object of connection even when it is left to stand for a long period of time in a...
7391226 Contact resistance test structure and methods of using same  
The present invention is directed to a contact resistance test structure and methods of using same. In one illustrative embodiment, the method includes forming a test structure comprised of two...
7390427 Hydrofluoroether as a heat-transfer fluid  
The present invention provides an apparatus comprising a device and a mechanism for heat transfer comprising a hydrofluoroether heat-transfer fluid wherein the heat transfer fluid is represented by...
7388385 Wafer dicing system  
A wafer is formed with metal traces that extend a distance across the wafer on opposite sides of a saw street. The resistances of the metal traces, which can each be formed from one or more layers...
7388224 Structure for determining thermal cycle reliability  
A device and method for evaluating reliability of a semiconductor chip structure built by a manufacturing process includes a test structure built in accordance with a manufacturing process. The...
7381986 Arrangement for testing semiconductor chips while incorporated on a semiconductor wafer  
An arrangement that will provide multiple communication paths for the simultaneously testing of a plurality of un-diced chips on a semiconductor wafer that will simultaneously permit each such...
7375371 Structure and method for thermally stressing or testing a semiconductor device  
A structure is provided which includes at least one semiconductor device and a diffusion heater in a continuous active semiconductor area of a substrate. One or more semiconductor devices are...
7372072 Semiconductor wafer with test structure  
The invention relates to a semiconductor wafer ( 1 ) having a plurality of first sawing regions ( 201 - 211 ) running parallel to one another in a first direction (X) and a plurality of second...
7370257 Test vehicle data analysis  
A system and method for collecting and analyzing integrated circuit test vehicle test data by identifying various blocks of circuitry through at least two different intersecting test paths. In one...
7368749 Method of detecting misalignment of ion implantation area  
A method of detecting misalignment of ion implantation areas comprises forming at least one standard pattern consisting of a first area and a second area for use in measuring resistance, implanting...
7368748 Test pixel and test pixel array for evaluating pixel quality in CMOS image sensor  
A test pixel for use in a CMOS image sensor is employed to evaluate a pixel quality by modulating a contact chain. The test pixel for use the CMOS image sensor including: a test pixel active area...
7368208 Measuring phase errors on phase shift masks  
Methods and apparatus for producing a semiconductor. A production reticle having a pattern that includes circuit features, phase shift target structures and overlay target structures is provided....
Matches 1 - 50 out of 995 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 >