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Match Document Document Title
7473997 Method for forming robust solder interconnect structures by reducing effects of seed layer underetching  
A method for forming an interconnect structure for a semiconductor device includes defining a via in a passivation layer so as expose a top metal layer in the semiconductor device. A seed layer is...
7473580 Temporary chip attach using injection molded solder  
An improved method for performing an improved Temporary Chip Attach utilizing an Injection Molded Solder (IMS) process to allow efficient testing of die for creating a Known Good Die Bank. The IMS...
7470997 Wirebond pad for semiconductor chip or wafer  
In the present invention, copper interconnection with metal caps is extended to the post-passivation interconnection process. Metal caps may be aluminum. A gold pad may be formed on the metal caps...
7470996 Packaging method  
A packaging method includes ultrasonically bonding a semiconductor device and a substrate together via bumps that include gold as a main component thereof. A contact surface of a primary bump on a...
7468559 Semiconductor integrated circuit package having electrically disconnected solder balls for mounting  
Integrated circuit packages that connect solder balls between solder ball pads of a die and substrate pads of a printed circuit board (PCB). The solder balls are electrically disconnected from any...
7462942 Die pillar structures and a method of their formation  
A die, comprising a substrate and one or more pillar structures formed over the substrate in a pattern and the method of forming the die.
7462941 Power grid layout techniques on integrated circuits  
Techniques are provided for reducing the power supply voltage drop introduced by routing conductive traces on an integrated circuit. Techniques for reducing variations in the power supply voltages...
7462933 Ball grid array package enhanced with a thermal and electrical connector  
Electrically, mechanically, and thermally enhanced ball grid array (BGA) packages are described. A substrate has a surface, wherein the surface has an opening therein. A stiffener has a surface...
7459796 BGA-type multilayer circuit wiring board  
Provided is a BGA-type multilayer circuit wiring board which is mounted on a printed wiring board directly via a solder ball with the electrode pad for solder ball connection formed thereon and in...
7456502 Wiring board with connection electrode formed in opening and semiconductor device using the same  
The invention provides a wiring board ( 2,15 ) to which a semiconductor chip ( 3 ) is to be bonded while directing a surface of the semiconductor chip toward the wiring board. The wiring board...
7453155 Method for fabricating a flip chip package  
A flip chip packaging method is disclosed. First, a substrate is provided, in which the substrate comprises a plurality of integrated circuit (IC) package substrate units therein and the surface of...
7449785 Solder bump on a semiconductor substrate  
A solder bump on a semiconductor substrate is provided. The solder bump comprises a semiconductor substrate having a top copper pad thereon, a protective layer on the semiconductor substrate and at...
7449364 Device and method for including passive components in a chip scale package  
The invention provides a method and device for building one or more passive components into a chip scale package. The method includes the steps of selecting a passive component having a terminal...
7446405 Wafer level chip scale package (WLCSP) with high reliability against thermal stress  
A wafer level chip scale package includes a semiconductor chip having a plurality of pads; a lower insulation layer having a high Young's modulus of 1˜5 GPa formed on the semiconductor chip to...
7446384 CMOS image sensor module with wafers  
The present invention relates to an image sensor module and a manufacturing method thereof, especially to a wafer level chip size package (WL-CSP) realized by directly contacting an image sensor...
7446028 Multi-component integrated circuit contacts  
An integrated circuit connection is describe that includes a first, securing member and a second, connection member. The first member, in an embodiment, is a spike that has a portion of its body...
7443041 Packaging of a microchip device  
A method of packaging a microchip device, an interposer for packaging, and a packaged microchip device. An interposer is placed on microchip devices. The interposer includes an aperture which...
7443040 Aluminum cap with electroless nickel/immersion gold  
A resulting solder bump structure comprising the following steps. A structure having a metal bond pad formed thereover is provided. A patterned cover layer is formed over the structure. The...
7443036 Manufacturing method of semiconductor device  
The manufacturing method of the semiconductor device of the present invention has a step forming solder balls on the circuit face of a mother chip, a step making flip chip bonding of the daughter...
7436074 Chip package without core and stacked chip package structure thereof  
A chip package without a core, including a patterned circuit layer, a chip, a solder mask, a molding compound and multiple outer terminals, is provided. The patterned circuit layer has a first...
7436073 Junction structure for a terminal pad and solder, and semiconductor device having the same  
A junction structure, and a semiconductor device including the same, for a junction of a terminal pad and solder, including an underlying base on which said terminal pad is formed; a nickel layer...
7436063 Packaging substrate and semiconductor device  
A packaging substrate according to the present invention is a packaging substrate to which a semiconductor chip having a plurality of connection metal bodies on a surface thereof is bonded with the...
7435619 Method of fabricating a 3-D package stacking system  
The present invention provides a system for 3D package stacking system, comprising providing a substrate, attaching a ball grid array package, in an inverted position, to the substrate, forming a...
7432604 Semiconductor component and system having thinned, encapsulated dice  
A semiconductor component includes a thinned semiconductor die having protective polymer layers on up to six surfaces. The component also includes contact bumps on the die embedded in a circuit...
7432555 Testable electrostatic discharge protection circuits  
A semiconductor die has a bonding pad for a MOSFET such as a power MOSFET and a separate bonding pad for ESD protection circuitry. Connecting the bonding pads together makes the ESD protection...
7429797 Electronic device and carrier substrate  
Consistent with an example embodiment, an electronic device comprises a semiconductor device, particularly an integrated circuit, and a carrier substrate with conductive layers on the first side...
7429704 Electronic component, electro-optical device, and electronic apparatus  
Provided is an electronic component including a pad provided on an active surface of a rectangular chip substrate, a resin protrusion provided along sides of the chip substrate, and a conductive...
7420285 Semiconductor device and method of manufacturing the same, circuit board, and electronic instrument  
A semiconductor device comprising: a semiconductor element having a plurality of electrodes; a passivation film formed on the semiconductor element in a region avoiding at least a part of each of...
7420284 Semiconductor device and manufacturing method thereof  
A semiconductor device includes a semiconductor chip formed with connection terminals, an elastic structure interposed between a main surface of the chip and a wiring substrate formed with wirings...
7420283 Integration type semiconductor device and method for manufacturing the same  
A semiconductor device includes: a plurality of power MOS cells on a semiconductor substrate; a plurality of lead wires connecting to a source and a drain of each power MOS cell through a contact...
7420280 Reduced stress under bump metallization structure  
An improved under bump structure for use in semiconductor devices is described. The under bump structure includes a passivation layer having a plurality of vias. The vias are positioned such that a...
7417326 Semiconductor device and manufacturing method of the same  
A semiconductor device includes a plurality of electrode layers provided at designated positions of a semiconductor substrate, an organic insulation film formed on the semiconductor substrate by...
7417325 Semiconductor component having thinned die with conductive vias configured as conductive pin terminal contacts  
A semiconductor component includes a thinned semiconductor die having protective polymer layers on up to six surfaces. The component also includes contact bumps on the die embedded in a circuit...
7417324 Semiconductor device and method for manufacturing the same  
A semiconductor device is composed of a semiconductor chip, aluminum pads formed on the semiconductor chip, alloy ball bumps, which are formed on the aluminum pads, containing gold and Pd, and gold...
7414301 Printed circuit board with soldering lands  
The present invention provides a printed circuit board having an area of non-resist portion, where each non-resist portion expands gradually toward the back end of a land array in the dipping...
7408260 Microelectronic assemblies having compliant layers  
A microelectronic assembly includes a microelectronic element such as a semiconductor chip or wafer having a first surface and contacts accessible at the first surface, a compliant layer overlying...
7407877 Self-coplanarity bumping shape for flip-chip  
A stud bump structure for electrical interconnection between a pair of members includes a base portion, and a stem portion. The base portion is affixed to a pad or trace in one of the pair of...
7407833 Process for fabricating chip package structure  
A chip package structure comprising a carrier, a chip and an underfill layer is disclosed. The carrier has a plurality of bumps disposed thereon. The chip has an active surface. The chip is...
7405486 Circuit device  
In stack packaging, an IC chip in an upper layer and an IC chip in a lower layer are insulated from each other by use of an insulating adhesive and the like. Thus, if an analog IC chip is stacked...
7405484 Semiconductor device containing stacked semiconductor chips and manufacturing method thereof  
An adhesive film is formed on an electrode film, and a coating film is formed thereon. Nickel, chrome, molybdenum, tungsten, aluminum or an alloy of them is used as a constituent material of the...
7397129 Interposers with flexible solder pad elements  
Various embodiments of an interposer for mounting a semiconductor die, as well as methods for forming the interposer, are disclosed. The interposer includes flexible solder pad elements that are...
7397127 Bonding and probing pad structures  
A pad structure includes a first metal-containing layer formed over a substrate. A first passivation layer is formed over the first metal-containing layer. The first passivation layer has a first...
7397121 Semiconductor chip with post-passivation scheme formed over passivation layer  
The invention provides a semiconductor chip comprising an interconnecting structure over said passivation layer. The interconnecting structure comprises a first contact pad connected to a second...
7397117 Chip package with die and substrate  
A thin film semiconductor die circuit package is provided utilizing low dielectric constant (k) polymer material for the insulating layers of the metal interconnect structure. Five embodiments...
7394164 Semiconductor device having bumps in a same row for staggered probing  
A semiconductor device has a plurality of bumps in a same row for staggered probing. The bumps in a same row are disposed on a chip and include a plurality of regular bumps and a plurality of...
7394161 Chip structure with pads having bumps or wirebonded wires formed thereover or used to be tested thereto  
A chip structure comprising a semiconductor substrate, a plurality of dielectric layers, a plurality of circuit layers, a passivation layer, a metal layer and at least a bump. The semiconductor...
7394160 Printed wires arrangement for in-line memory (IMM) module  
An inline memory module (IMM) architecture may include: a printed circuit board (PCB); a first array of memory devices on a first side of the PCB; a second array of memory devices on a second side...
7394148 Module having stacked chip scale semiconductor packages  
Stacked CSP (chip scale package) modules include a molded first (“top”) chip scale package having a molding side and a substrate side, and a second (“bottom”) package affixed to the...
7393719 Increased stand-off height integrated circuit assemblies, systems, and methods  
Disclosed are integrated circuit assemblies with increased stand-off height and methods and systems for their manufacture. Methods of the invention provide for assembling a semiconductor device by...
7391114 Electrode pad section for external connection  
A pad section serving as an electrode for external connection of a semiconductor device includes a first pad metal ( 61 ) formed in the top layer, a second pad metal ( 62 ) formed under the first...
Matches 1 - 50 out of 1330 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 >