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Match Document Document Title
7439580 Top drain MOSgated device and process of manufacture therefor  
A trench type top drain MOSgated device has a drain electrode on the die top and a source electrode on the die bottom surface. The device is turned on by a control voltage connected between a drain...
7413981 Pitch doubled circuit layout  
In one embodiment of the present invention, a method for connecting a plurality of bit lines to sense circuitry includes providing a plurality of bit lines extending from a memory array in a first...
7410892 Methods of fabricating integrated circuit devices having self-aligned contact structures  
An integrated circuit device, e.g., a memory device, includes a substrate, a first insulation layer on the substrate, and a contact pad disposed in the first insulation layer in direct contact with...
7375019 Image sensor and method for fabricating the same  
An image sensor and a method for fabricating the same are disclosed, to improve a contact quality between a contact plug and a source diffusion layer. The image sensor includes a photodiode in an...
7365396 SOI SRAM products with reduced floating body effect  
A memory device is formed on a semiconductor-on-insulator (SOI) structure, the SOI structure including a substrate, an insulating layer on the substrate, and a semiconductor film on the insulating...
7348263 Manufacturing method for electronic component, electronic component, and electronic equipment  
A manufacturing method for electronic device, includes: preparing a first substrate having a plurality of first regions; preparing a second substrate having a plurality of second regions; facing...
7332401 Method of fabricating an electrode structure for use in an integrated circuit  
An electrode structure includes a first layer of conductive material and a dielectric layer formed on a surface of the first layer. An opening is formed in the dielectric layer to expose a portion...
7326977 Low noise field effect transistor  
An FET (field effect transistor) having source, drain and channel regions of a conductivity type in a semiconductor body of opposite conductivity type. The channel region is located at the lower...
7323389 Method of forming a FINFET structure  
A semiconductor device ( 10 ) such as a FinFET transistor of small dimensions is formed in a process that permits substantially uniform ion implanting ( 32 ) of a source ( 14 ) electrode and a...
7314794 Low-cost high-performance planar back-gate CMOS  
A method of fabricating a high-performance planar back-gate CMOS structure having superior short-channel characteristics and reduced capacitance using processing steps that are not too lengthy or...
7301193 Structure and method for low Vss resistance and reduced DIBL in a floating gate memory cell  
According to one exemplary embodiment, a floating gate memory cell comprises a stacked gate structure situated on a substrate and situated over a channel region in the substrate. The floating gate...
7256119 Semiconductor device having trench structures and method  
In one embodiment, a pair of sidewall passivated trench contacts is formed in a substrate to provide electrical contact to a sub-surface feature. A doped region is diffused between the pair of...
7211865 Silicided body contact SOI device  
A semiconductor device includes a dielectric layer, a semiconductor layer provided above the dielectric layer, a gate dielectric layer provided above the semiconductor layer, a gate electrode...
7202155 Method for manufacturing wiring and method for manufacturing semiconductor device  
The present invention provides a method for manufacturing a wiring and a method for manufacturing a semiconductor device, which do not require a photolithography step in connecting a pattern of an...
7183193 Integrated device technology using a buried power buss for major device and circuit advantages  
A method for providing an improved integrated circuit device is disclosed. The method comprises the steps of providing active and passive areas in the substrate, providing a plurality of slots in...
7166515 Implanted hidden interconnections in a semiconductor device for preventing reverse engineering  
A camouflaged interconnection for interconnecting two spaced-apart regions of a common conductivity type in an integrated circuit or device and a method of forming same. The camouflaged...
7164188 Buried conductor patterns formed by surface transformation of empty spaces in solid state materials  
A plurality of buried conductors and/or buried plate patterns formed within a monocrystalline substrate is disclosed. A plurality of empty-spaced buried patterns are formed by drilling holes in the...
7122463 Manufacturing method of semiconductor device  
When the occurrence of the bowing is controlled through the etching conditions, a change in etching conditions causes the bowing. Another problem is a requirement of the larger-sized apparatus for...
7118998 Method of forming a conductive structure  
A conductive structure provides a conductive path from a first region in a semiconductor material to a second spaced apart region in the semiconductor material by forming a plurality of trenches...
7115999 Semiconductor device and method of manufacturing the same  
A semiconductor device has an active element structure formed on a semiconductor substrate. The active element has a connection region formed on a surface of the semiconductor substrate. An...
7112856 Semiconductor device having a merged region and method of fabrication  
A semiconductor device includes an insulated gate electrode pattern formed on a well region. The semiconductor device further includes a sidewall spacer formed on sidewalls of the gate electrode...
7101791 Method for forming conductive line of semiconductor device  
A method for conductive line of semiconductor device is disclosed. A cobalt silicide layer is formed on an impurity junction region exposed through a contact hole. The cobalt silicide layer...
7098113 Method and system for providing a power lateral PNP transistor using a buried power buss  
A power lateral PNP device is disclosed which includes an epitaxial layer; a first and second collector region embedded in the epitaxial layer; an emitter region between the first and second...
7087491 Method and system for vertical DMOS with slots  
A method for providing a high power, low resistance, high efficient vertical DMOS device is disclosed. The method comprises providing a semiconductor substrate with a source body structure thereon....
7074678 Method for fabricating a buried bit line for a semiconductor memory  
In a method for fabricating a buried bit line for a semiconductor memory, the buried bit line is produced as a diffusion region using a dopant source including polysilicon that has previously been...
7060610 Method for forming contact in semiconductor device  
The present invention relates to a method for forming a contact in a semiconductor device. The method includes the steps of: forming a P-type source/drain junction in a substrate; forming an...
7049169 Method of fabricating a semiconductor device  
According to the present invention, by applying a basic surface-processing agent to a film underlying a resist, the excessive photoacid present at the interface between the resist and the front-end...
7037804 Wafer bonding using a flexible bladder press for three dimensional (3D) vertical stack integration  
A three-dimensional (3-D) integrated chip system is provided with a first wafer including one or more integrated circuit (IC) devices; a second wafer including one or more integrated circuit (IC)...
7005380 Simultaneous formation of device and backside contacts on wafers having a buried insulator layer  
A semiconductor device manufacturing method is provided where a device structure is formed on top of a wafer that comprises a backside semiconductor substrate, a buried insulator layer and a top...
6995072 Method of making sacrificial self-aligned interconnection structure  
A sacrificial, self-aligned polysilicon interconnect structure is formed in a region of insulating material to the side of an active region location and underlying a semiconductor device of a...
6995049 Method for forming semiconductor device  
In a method for forming a silicon-on-insulator FET having a contact that provides a fixed potential to a substrate, the substrate-biasing between the SOI transistor and the silicon substrate is...
6987052 Method for making enhanced substrate contact for a semiconductor device  
A method of forming a semiconductor structure in a semiconductor wafer includes the steps of forming an epitaxial layer on at least a portion of a semiconductor substrate of a first conductivity...
6979868 Bypass circuits for reducing plasma damage  
The present invention provides a method for reducing-plasma damage to a gate oxide of a metal-oxide semiconductor (MOS) transistor positioned on a substrate of a MOS semiconductor wafer. The method...
6975016 Wafer bonding using a flexible bladder press and thinned wafers for three-dimensional (3D) wafer-to-wafer vertical stack integration, and application thereof  
A three-dimensional (3-D) integrated chip system is provided with a first wafer including one or more integrated circuit (IC) devices; a second wafer including one or more integrated circuit (IC)...
6974751 Semiconductor device and method for producing the same  
A semiconductor device includes a SiC substrate and an ohmic electrode, a semiconductor member including a SiC member and a SiGe member being formed between the SiC substrate and the ohmic...
6969676 Method of adjusting etch selectivity by adapting aspect ratios in a multi-level etch process  
The present invention discloses a technique for controlling a local etch rate in forming multi-level contact openings, for example, in forming substrate contact openings and transistor contact...
6963100 Semiconductor device having gate electrode in which depletion layer can be generated  
Performance for a gate insulation film of an insulated gate transistor is enhanced. A depletion layer is generated in a region of a gate electrode 12 which is provided in contact with a gate...
6955972 Methods of fabricating integrated circuit devices having trench isolation structures  
Methods of fabricating integrated circuit devices include forming a trench in a face of an integrated circuit substrate. The trench has a trench sidewall and a trench floor. The method further...
6943411 Semiconductor device including a low resistance wiring layer  
A semiconductor device can include a low resistance wiring layer ( 13 ) formed in, and extending along a base material. A number of element regions ( 14 ) are formed separate from one another, each...
6930357 Active SOI structure with a body contact through an insulator  
A silicon on insulator shaped structure formed to reduce floating body effect comprises a T-shaped active structure and a body contact for back bias. Etching a T-shape through two layers of oxide...
6930040 Method of forming a contact on a silicon-on-insulator wafer  
In a method of the present invention, an intermediate structure having a top surface is provided. An isolation trench is formed is the intermediate structure. Isolation material is deposited over...
6930010 Method of forming a conductive structure in a semiconductor material  
A conductive structure provides a conductive path from a first region in a semiconductor material to a second spaced apart region in the semiconductor material by forming one or more trenches...
6917083 Local ground and VCC connection in an SRAM cell  
A retrograde well region, having a buried layer of high conductivity, is formed in a semiconductor substrate. A trench structure is selectively etched in the semiconductor substrate down to a...
6894393 Buried power bus utilized as a sinker for high current, high power semiconductor devices and a method for providing the same  
A method and system for providing a sinker on a semiconductor device is described. The method and system includes providing a substrate region and providing a buried layer and an epitaxial (EPI)...
6885054 Threshold voltage stabilizer, method of manufacturing and integrated circuit employing the same  
The present invention provides a threshold voltage stabilizer for use with a MOS transistor having a body effect associated therewith. In one embodiment, the threshold voltage stabilizer, includes...
6881621 Method of fabricating SOI substrate having an etch stop layer, and method of fabricating SOI integrated circuit using the same  
A method of fabricating a SOI substrate includes sequentially forming a first semiconductor layer, which may be either a porous semiconductor layer or a bubble layer, a second semiconductor layer...
6872653 Manufacturing method of semiconductor device  
After deposition of a conductor film made of titanium tungsten over a main surface of a semiconductor substrate formed with grooves, an initial conductor film made of aluminium is further...
6844224 Substrate contact in SOI and method therefor  
A doped area is formed in the silicon substrate layer of a silicon-on-insulator stack including a silicon substrate, an insulator layer and an silicon active layer, by implanting a species through...
6828649 Semiconductor device having an interconnect that electrically connects a conductive material and a doped layer, and a method of manufacture therefor  
The present invention provides a semiconductor device, a method of manufacture therefor, and an integrated circuit including the same. In one advantageous embodiment, the semiconductor device...
6828199 Monos device having buried metal silicide bit line  
A MONOS device and method for making the device has a charge trapping dielectric layer, such as an oxide-nitride-oxide (ONO) layer, formed on a substrate. A recess is created through the ONO layer...
Matches 1 - 50 out of 481 1 2 3 4 5 6 7 8 9 10 >