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7468313 Engineering strain in thick strained-SOI substrates  
A semiconductor fabrication process preferably used with a semiconductor on insulator (SOI) wafer. The wafer's active layer is biaxially strained and has first and second regions. The second region...
7462537 Fabricating method of an non-volatile memory  
A method of fabricating a non-volatile memory is provided. A substrate having a trench therein for forming a trench device is provided. Then, a doped metal silicide layer is formed on the substrate...
7456068 Forming ultra-shallow junctions  
A method to form an ultra-shallow junction is described. In one embodiment, a replacement gate process is utilized to enable the overlap of a gate electrode over the regions of a semiconductor...
7453120 Semiconductor structure  
A method for fabricating a semiconductor structure is described. A substrate is provided, having thereon a gate structure and a spacer on the sidewall of the gate structure and having therein an...
7432167 Method of fabricating a strained silicon channel metal oxide semiconductor transistor  
The present invention provides a method of fabricating strained silicon channel MOS transistor, comprising providing a substrate, forming at least a gate structure on the substrate, forming a mask...
7432146 Semiconductor device and manufacturing method thereof  
To make it possible to obtain a sharp impurity profile without presenting a disadvantage such as an increase in parasitic resistance or the like using a laser annealing method to thereby meet...
7432136 Transistors with controllable threshold voltages, and various methods of making and operating same  
In one illustrative embodiment, the method comprises providing an SOI substrate comprised of an active layer, a buried insulation layer and a bulk substrate, the active layer being doped with a...
7416931 Methods for fabricating a stress enhanced MOS circuit  
Methods are provided for fabricating a stress enhanced MOS circuit. One method comprises the steps of depositing a stressed material overlying a semiconductor substrate and patterning the stressed...
7414277 Memory cell having combination raised source and drain and method of fabricating same  
A memory device and a method of fabrication are provided. The memory device includes a semiconductor substrate and a charge trapping dielectric stack disposed over the semiconductor substrate. A...
7413946 Formation of standard voltage threshold and low voltage threshold MOSFET devices  
Wells are formed in a substrate where standard Vt and low Vt devices of both a first and second type are to be fabricated. Wells defining the locations of first type standard Vt devices are masked,...
7410876 Methodology to reduce SOI floating-body effect  
A method for making a semiconductor device, comprising (a) providing a structure comprising a gate electrode ( 207 ) disposed on a substrate ( 203 ); (b) creating first ( 213 ) and second ( 214 )...
7410875 Semiconductor structure and fabrication thereof  
A method for fabricating a semiconductor structure is described. A substrate is provided, having thereon a gate structure and a spacer on the sidewall of the gate structure and having therein an...
7402484 Methods for forming a field effect transistor  
Methods for forming a field effect transistor are disclosed. An illustrated method comprises: forming a gate electrode on a substrate; and forming a nitride layer on at least a part of the gate...
7402479 CMOS image sensor and fabricating method thereof  
A fabricating method of a CMOS image sensor includes the steps of: forming a transfer gate on a semiconductor substrate where a device isolation layer is formed; forming a first n-type ion...
7390711 MOS transistor and manufacturing method thereof  
A MOS transistor including a gate insulation layer and a gate electrode layer on a channel region of a semiconductor substrate. A gate spacer layer is formed on a sidewall of the electrode layer...
7381623 Pre-epitaxial disposable spacer integration scheme with very low temperature selective epitaxy for enhanced device performance  
The embodiments of the invention provide a method, etc. for a pre-epitaxial disposable spacer integration scheme with very low temperature selective epitaxy for enhanced device performance. More...
7368358 Method for producing field effect device that includes epitaxially growing SiGe source/drain regions laterally from a silicon body  
A structure, and method of fabrication, for high performance field effect devices is disclosed. The MOS structures include a crystalline Si body of one conductivity type, a strained SiGe layer...
7365010 Semiconductor device having carbon-containing metal silicide layer and method of fabricating the same  
Methods of fabricating semiconductor devices having a carbon-containing metal silicide layer and semiconductor devices fabricated by the methods are provided. A representative method includes the...
7364959 Method for manufacturing a MOS transistor  
A method for manufacturing a MOS transistor integrated into a chip of semi-conductive material comprising a first and a second active region which extend from the inside of the chip to a surface of...
7361973 Embedded stressed nitride liners for CMOS performance improvement  
The present invention provides a semiconducting device including a gate region positioned on a mesa portion of a substrate; and a nitride liner positioned on the gate region and recessed surfaces...
7358551 Structure and method for improved stress and yield in pFETs with embedded SiGe source/drain regions  
The present invention provides a technique for forming a CMOS structure including at least one pFET that has a stressed channel which avoids the problems mentioned in the prior art. Specifically,...
7358168 Ion implantation method for forming a shallow junction  
A shallow junction that previously would require the use of a low-energy ion implanter can be directly formed by high-energy or middle-energy ion implanters such that the manufacturer need not...
7355214 Field effect transistor and fabrication thereof, semiconductor device and fabrication thereof, logic circuit including the semiconductor device, and semiconductor substrate  
A method for forming a Field Effect Transistor (FET) within a strain effect semiconductor layer is disclosed, whereby the source and drain of the FET are formed only in the strain effect silicon...
7354835 Method of fabricating CMOS transistor and CMOS transistor fabricated thereby  
In a method of fabricating a CMOS transistor, and a CMOS transistor fabricated according to the method, the characteristics of first and second conductivity type MOS transistors are both...
7354833 Method for improving threshold voltage stability of a MOS device  
This invention provides a method for improving threshold voltage stability of at least one metal-oxide-semiconductor (MOS) device. In one embodiment of the invention, at least one well is formed on...
7354819 Method of manufacturing CMOS with silicide contacts  
A semiconductor device is disclosed, which comprises a silicon substrate, a complementary MISFET circuit, an insulation film formed on the silicon substrate, a first contact hole formed in the...
7351627 Method of manufacturing semiconductor device using gate-through ion implantation  
Disclosed herein is a method of manufacturing a semiconductor device via gate-through ion implantation, comprising forming a gate stack on a semiconductor substrate and performing ion implantation...
7348248 CMOS transistor with high drive current and low sheet resistance  
A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a gate dielectric over a substrate, a gate electrode over the gate dielectric, a slim...
7348233 Methods for fabricating a CMOS device including silicide contacts  
Methods are provided for fabricating a CMOS device having a silicon substrate including a first N-type region and a second P-type region. The method includes the steps of forming a first gate...
7348232 Highly activated carbon selective epitaxial process for CMOS  
In accordance with the invention there is a method of forming a semiconductor device comprising forming a gate over a substrate, forming a source region and a drain region by doping a first portion...
7348230 Manufacturing method of semiconductor device  
A method of manufacture of a semiconductor device includes forming a gate insulating film and a gate electrode made of polycrystalline silicon over a semiconductor substrate; implanting ions into...
7345329 Method for reduced N+ diffusion in strained Si on SiGe substrate  
The first source and drain regions are formed in an upper surface of a SiGe substrate. The first source and drain regions containing an N type impurity. Vacancy concentration in the first source...
7344984 Technique for enhancing stress transfer into channel regions of NMOS and PMOS transistors  
A method and a semiconductor device are provided in which respective contact layers having a specific intrinsic stress may be directly formed on respective metal silicide regions without undue...
7344933 Method of forming device having a raised extension region  
A method is disclosed of forming an extension region for a transistor having a gate structure overlying a compound semiconductor layer. An anneal is used either before or after deep source/drain...
7344929 Method for manufacturing an integrated circuit using a capping layer having a degree of reflectivity  
The present invention provides a method for manufacturing a semiconductor device and a method for manufacturing an integrated circuit. The method for manufacturing the semiconductor device, among...
7342289 Strained silicon MOS devices  
A structure to improve carrier mobility of a MOS device in an integrated circuit. The structure comprises a semiconductor substrate, containing a source region and a drain region; a conductive gate...
7339234 Semiconductor device and fabrication process thereof, and application thereof  
An LDMOS transistor includes a gate insulation film formed on a semiconductor substrate, a gate electrode formed on the gate insulation film, a drain well of a first conductivity type formed in the...
7339215 Transistor device containing carbon doped silicon in a recess next to MDD to create strain in channel  
A method ( 100 ) of forming a transistor includes forming a gate structure ( 106, 108 ) over a semiconductor body and forming recesses ( 112 ) substantially aligned to the gate structure in the...
7335563 Rotated field effect transistors and method of manufacture  
An apparatus and method for manufacturing rotated field effect transistors. The method comprises providing a substrate including a first gate structure and a second gate structure, which are not...
7329596 Method for tuning epitaxial growth by interfacial doping and structure including same  
A method that allows for uniform, simultaneous epitaxial growth of a semiconductor material on dissimilarly doped semiconductor surfaces (n-type and p-type) that does not impart substrate thinning...
7329570 Method for manufacturing a semiconductor device  
An exemplary method of manufacturing a semiconductor device according to an embodiment of the present invention includes forming a P-well and an N-well for high voltage (HV) devices and a first...
7326644 Semiconductor device and method of fabricating the same  
A method of fabricating a semiconductor device, includes (a) forming an oxide film entirely over a silicon substrate on which a MOS transistor is fabricated, (b) carrying out first...
7326622 Method of manufacturing semiconductor MOS transistor device  
A method of manufacturing a metal-oxide-semiconductor (MOS) transistor device is disclosed. A semiconductor substrate having a main surface is prepared. A gate dielectric layer is formed on the...
7326601 Methods for fabrication of a stressed MOS device  
Methods for fabricating a stressed MOS device is provided. One method comprises the steps of providing a monocrystalline semiconductor substrate having a surface and a channel abutting the surface....
7321151 Semiconductor device and method of fabricating the same  
An extension region is formed by ion implantation under masking by a gate electrode, and then a substance having a diffusion suppressive function over an impurity contained in a source-and-drain is...
7320939 Semiconductor device fabricated by a method of reducing the contact resistance of the connection regions  
A semiconductor device, fabricated by a method, having a semiconductor structure with a silicon region which forms at least one connection region in and/or on a surface of a substrate is disclosed....
7320907 Method for controlling lattice defects at junction and method for forming LDD or S/D regions of CMOS device  
A method for controlling lattice defects at a junction is described, which is used in accompany with an ion implantation step for forming a junction in a substrate and a subsequent annealing step....
7319061 Method for fabricating electronic device  
In a method for fabricating an electronic device including a transistor with a drain extension structure, a correspondence between a size of a gate electrode of the transistor and ion implantation...
7316960 Strain enhanced ultra shallow junction formation  
Provided is a method of manufacturing a microelectronic device. In one example where the device includes a semiconductor substrate with a gate feature and a shallow junction, the method includes...
7315063 CMOS transistor and method of manufacturing the same  
A CMOS transistor structure and related method of manufacture are disclosed in which a first conductivity type MOS transistor comprises an enhancer and a second conductivity type MOS transistor...
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