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US20080104334 |
Method and system for managing access to a data element in a multithreaded environment
A method for managing access to a data element involves storing a first copy of the data element in a cache location, obtaining a request to modify the data element, where the request to modify the...
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US20080104333 |
TRACKING OF HIGHER-LEVEL CACHE CONTENTS IN A LOWER-LEVEL CACHE
A cache memory system is provided which includes a higher-level cache, a lower-level cache, and a bus coupling the higher-level cache and the lower-level cache together. Also included is a...
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US20080104332 |
CACHE MEMORY SYSTEM AND METHOD FOR PROVIDING TRANSACTIONAL MEMORY
A method for providing a transactional memory is described. A cache coherency protocol is enforced upon a cache memory including cache lines, wherein each line is in one of a modified state, an...
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US20080104331 |
MEMORY CONTROL SYSTEMS WITH DIRECTORY CACHES AND METHODS FOR OPERATION THEREOF
A memory control system is provided with a directory cache and a memory controller. The directory cache has a plurality of directory cache entries configured to store information regarding copies...
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US20080104330 |
SYSTEM AND METHOD FOR REPORTING CACHE COHERENCY STATE RETAINED WITHIN A CACHE HIERARCHY OF A PROCESSING NODE
A coherency state of a coherency granule is determined for each of a plurality of caches of a processor of a multiple-processor system to generate a plurality of coherency states in response to...
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US20080104329 |
CACHE AND METHOD FOR CACHE BYPASS FUNCTIONALITY
A cache is provided for operatively coupling a processor with a main memory. The cache includes a cache memory and a cache controller operatively coupled with the cache memory. The cache controller...
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US20080104328 |
DATA TRANSFER DEVICE, DATA TRANSFER METHOD, AND COMPUTER DEVICE
A local-memory side data transfer unit increments the number of addresses, reads out data from a local memory, and stores the data into a cache memory of a remote-memory side data transfer unit....
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US20080104327 |
Systems and Method for Improved Data Retrieval from Memory on Behalf of Bus Masters
Systems and methods are disclosed herein for retrieving data from memory in a computer system. In one example, a memory controller is coupled to a system bus in a computer system that includes bus...
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US20080104326 |
Facilitating store reordering through cacheline marking
One embodiment of the present invention provides a system that facilitates store reordering through cacheline marking. During operation, the system receives a memory operation which is directed to...
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US20080104325 |
Temporally relevant data placement
A method and apparatus for placement of temporary relevant data are disclosed. In one embodiment, the apparatus comprising one or more memories through which a producer provides data for access by...
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US20080104324 |
DYNAMICALLY SCALABLE CACHE ARCHITECTURE
A technique for managing power consumption of a cache memory system dynamically adjusts the size of the cache memory system according to an energy level of an energy storage device. In at least one...
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US20080104323 |
METHOD FOR IDENTIFYING, TRACKING, AND STORING HOT CACHE LINES IN AN SMP ENVIRONMENT
The invention is directed to the identifying, tracking, and storing of hot cache lines in an SMP environment. A method in accordance with an embodiment of the present invention includes: accessing,...
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US20080104322 |
Method and system for filling cache memory for cache memory initialization
Embodiments of the present invention relate to the filling of cache memory for cache memory initialization. In one embodiment, cache architecture dependent data is loaded into cacheable memory. The...
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US20080104321 |
FAST WRITE OPERATIONS TO A MIRRORED VOLUME IN A VOLUME MANAGER
In one embodiment, a method is provided comprising: receiving, at a virtualizer, a write command from an initiator in a storage area network, wherein the storage area network includes the initiator...
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US20080104320 |
CHIPSET AND NORTHBRIDGE WITH RAID ACCESS
A Northbridge providing RAID access is coupled among a central processing unit, a system memory, and a Southbridge. Furthermore, the Northbridge further couples to a RAID through a Southbridge. The...
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US20080104319 |
Dynamic database memory management policies
A database engine is provided with memory management policies to dynamically configure an area of memory called a buffer pool into which data pages are held during processing. The data pages are...
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US20080104318 |
Worm Proving Storage System
A method for operating a storage system configured to provide a Write Once and Read Many (WORM) function includes receiving a first command at a storage subsystem from a host. At least a portion of...
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US20080104317 |
SYSTEM AND COMPUTER PROGRAM PRODUCT FOR SYNCHRONIZING DIRECT ACCESS STORAGE VOLUMES
A system and computer program product for synchronizing direct access storage volumes designated as managed by storage management software with direct access storage volumes available to a computer...
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US20080104316 |
Emulating Volume Having Selected Storage Capacity
A volume having a selected storage capacity is emulated within a computer configuration by (a) representing to an operating system of the computer configuration the presence of the volume having...
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US20080104315 |
Techniques For Improving Hard Disk Drive Efficiency
A host operating system (OS) can function as a task under a disk drive operating system. The host OS and the disk drive operating system can be run on a single processor. The processor is able to...
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US20080104314 |
MEMORY DEVICE WITH EMULATED CHARACTERISTICS
A memory subsystem is provided including an interface circuit adapted for communication with a system and a majority of address or control signals of a first number of memory circuits. The...
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US20080104313 |
Multiple-Buffer Queueing of Data Packets with High Throughput Rate
The present invention is a method and apparatus to buffer data. A buffer memory of a first type stores data associated with a connection identifier corresponding to a channel in a network. The data...
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US20080104312 |
STATES ENCODING IN MULTI-BIT FLASH CELLS FOR OPTIMIZING ERROR RATE
Memory cells are programmed and read, at least M=3 data bits per cell, according to a valid nonserial physical bit ordering with reference to a logical bit ordering. The logical bit ordering is...
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US20080104311 |
NAND FLASH MEMORY SYSTEM ARCHITECTURE
A data storage device includes a NAND flash memory, an executable interface and a controller for receiving, from a host, via the executable interface, an instruction to access the NAND flash memory...
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US20080104310 |
Erase history-based flash writing method
A method for writing into a flash memory device includes calculating a physical block for writing data thereto, checking whether the calculated physical block has been erased since a last power-up...
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US20080104309 |
Flash memory device with multi-level cells and method of writing data therein
In one aspect, a method of writing data in a flash memory system is provided. The flash memory system forms an address mapping pattern according to a log block mapping scheme. The method includes...
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US20080104308 |
System with flash memory device and data recovery method thereof
A method is for recovering a block mapping table in a system including a flash memory device, where the block mapping table utilizes address mapping in accordance with a wear-leveling scheme. The...
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US20080104307 |
Multi-sector to single-sector request mapping
One embodiment relates to a method of performing a multi-sector memory request for data to be communicated with a memory device. The multi-sector memory request is received. The multi-sector memory...
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US20080104306 |
INFORMATION STORAGE MEDIUM ON WHICH DRIVE DATA IS RECORDED, AND METHOD OF RECORDING INFORMATION ON THE INFORMATION STORAGE MEDIUM
An information storage medium includes a drive zone having a plurality of physical clusters or ECC blocks. When new drive data is recorded in the drive zone, the new drive data is recorded in a...
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US20080104305 |
Media processing device and control method for a media processing device
A media processing device has a media drive for writing data on one side of recording media, a label printer for printing on the other side of the media M, media stackers for storing the media, and...
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US20080104304 |
Storage interfacing method and apparatus
A storage interfacing method and apparatus for a mobile terminal are disclosed. The storage interfacing method utilizes a plurality of storage devices. The method includes identifying the storage...
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US20080104303 |
Low latency event communication system and method
A low latency event communication system comprises a computer system having an Advanced Configuration and Power Interface (ACPI) namespace table with a Peripheral Component Interconnect (PCI)...
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US20080104302 |
System and method for effectively performing a signal conversion procedure
A system and method for effectively utilizing a converter device to perform a signal conversion procedure includes an input detector module that references an input table to validate input values...
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US20080104301 |
METHOD AND SYSTEM FOR COUPLING A LAPTOP OR OTHER PORTABLE OR HAND-HELD DEVICE TO A DOCKING SYSTEM USING AN ETHERNET INTERFACE
Methods and systems for coupling a laptop or other portable or hand-held device to a docking system using an Ethernet Interface are disclosed and may comprise interfacing a portable computing...
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US20080104300 |
Docking station having auxiliary power management for use with portable medical equipment
When portable diagnostic medical equipment is placed into a dock, or docking station, the batteries of the docking station are used in a hierarchical manner to insure that the batteries in the...
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US20080104299 |
Business card sized storage device
A business card sized storage device comprises: a housing having an upper and lower covers, from whose edges extend downward to form a sidewall, respectively, and in turn establish an internal...
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US20080104298 |
Expandable Express Card Capable of Isolating Noise and Method for Combining Functionalities of the Express Card with a Non-Host Device
An express card includes a plurality of detection pins, a plurality of power pins, a plurality of Universal Serial Bus (USB) interface pins, a plurality of Peripheral Component Interconnect Express...
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US20080104297 |
EXPANSION CARD APPARATUS
An expansion card apparatus for expanding a motherboard which complies with a first signal transmission standard with an expansion card which complies with a second signal transmission standard,...
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US20080104296 |
INTERRUPT HANDLING USING SIMULTANEOUS MULTI-THREADING
Disclosed are a method, information processing system, and computer readable medium for managing interrupts. The method includes placing at least one physical processor of an information processing...
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US20080104295 |
METHOD AND APPARATUS FOR TRANSFERRING DATA TO VIRTUAL DEVICES BEHIND A BUS EXPANDER
A method, apparatus, and computer instructions for transferring data from a master to a set of applications executing on a slave. Data is received from a master at a device driver in the slave. The...
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US20080104294 |
Method for operation of a bus system
The disclosure relates to a method for operating a bus system, in which a plurality of subscribers communicate with one another over the same bus line and all subscribers are assigned a subscriber...
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US20080104293 |
Memory controller connection to RAM using buffer interface
Provided are memory control apparatus and methods for controlling data transfer between a memory controller and at least two logical memory busses connected to memory, comprising a memory...
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US20080104292 |
ELECTRONIC NETWORK
An electronic network is disclosed. One embodiment includes a plurality of network devices, a bus for transferring data between the network devices and a bus master for controlling the transfer of...
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US20080104291 |
FLASH DRIVE MEMORY APPARATUS AND METHOD
A memory apparatus includes a non-volatile computer memory, a USB mass storage controller connected to the non-volatile computer memory, the USB mass storage controller including a daisy chain...
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US20080104290 |
SYSTEM, METHOD AND STORAGE MEDIUM FOR PROVIDING A HIGH SPEED TEST INTERFACE TO A MEMORY SUBSYSTEM
A buffer device for testing a memory subsystem. The buffer device includes a parallel bus port adapted for connection to a slow speed bus and a serial bus port adapted for connection to a high...
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US20080104289 |
AUDIO INTERFACE FOR CONTROLLING A MOTION SIGNAL
The present description relates to the interfacing of a computer with a motion platform using a USB audio-class computer peripheral. The computer peripheral receives a digital audio-format signal...
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US20080104288 |
ELECTRONIC DEVICE, COMPUTER SYSTEM COMPRISING THE SAME AND CONTROL METHOD THEREOF
A computer system includes a central processing unit (CPU) including at least one compensation port, a register setting part to set a control value corresponding to a predetermined specification of...
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US20080104287 |
INFORMATION TERMINAL, INFORMATION PROCESSING SYSTEM, AND METHODS OF CONTROLLING THE SAME
An information terminal disclosed herein includes a data storage in which data is stored; an internal controller which accesses the data storage by a request from inside the information terminal;...
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US20080104286 |
DATA TRANSFER APPARATUS AND DATA TRANSFER METHOD
According to one embodiment, a data transfer apparatus includes a first device, a transfer unit which controls data transfer between a second device to be connected to the first device and to be...
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US20080104285 |
METHOD AND SYSTEM FOR MONITORING DEVICE PORT
A device port monitoring system is disclosed by embodiments of the present invention, and the system includes an indicator status tracking module coupled with each distributed device respectively....
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