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<title>freepatentsonline.com</title>
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<title>freepatentsonline.com: Static information storage and retrieval</title>
<link>http://www.freepatentsonline.com/result.html?query_txt=ccl/365%20and%20isd/04/24/2008&amp;usapp=on</link>
<description>USPTO Class 365 Static information storage and retrieval</description>
<language>en-us</language>
<lastBuildDate>Wed Apr 30 17:03:08 EDT 2008</lastBuildDate>

<item>
<title><![CDATA[SENSING A SIGNAL IN A TWO-TERMINAL MEMORY ARRAY HAVING LEAKAGE CURRENT]]></title>
<link>http://www.freepatentsonline.com/20080094876.html</link>
<description><![CDATA[A two-terminal memory array includes a plurality of first and second conductive traces. An address unit operatively applies a select voltage across a selected pair of the first and second conductive traces and applies a non-select voltage potential to unselected traces. A total current flowing in the selected first conductive trace and a leakage current flowing through unselected second conductive traces are sensed by a sense unit in a one cycle or a two cycle pre-read operation. The total and leakage currents can be combined with a reference signal to derive a data signal indicative of one of a plurality of conductivity profiles that represent stored data. The conductivity profiles can be stored in a resistive state memory element that is electrically in series with the selected first and second conductive traces.]]></description>
<pubDate>April 24, 2008</pubDate>
</item>

<item>
<title><![CDATA[FASTER INITIALIZATION OF DRAM MEMORY]]></title>
<link>http://www.freepatentsonline.com/20080094877.html</link>
<description><![CDATA[A method of initializing dynamic random access memory (DRAM) comprises allocating one or more rows of a plurality of cells in the DRAM; signaling an initialization request to initialize the allocated one or more rows; and simultaneously initializing all cells in each of the one or more allocated rows upon accessing each of the one or more allocated rows.]]></description>
<pubDate>April 24, 2008</pubDate>
</item>

<item>
<title><![CDATA[Semiconductor Device]]></title>
<link>http://www.freepatentsonline.com/20080094922.html</link>
<description><![CDATA[A column circuit that amplifies signals read from a sense amplifier array SAA to local input/output lines LIO in sub-amplifiers SAMP to transfer the amplified signals to main input/output lines MIO is provided. A current control circuit IC that can set one of two kinds of currents according to read enable signals RD 1 , RD 2  is provided in each sub-amplifier SAMP. The read enable signals RD 1 , RD 2  are generated at timings corresponding to the number of cycles in burst read operation under control of the timing controller. Current in the current control circuit IC is set to be large by the RD 1  in burst read operation cycle just after activation of a memory bank, while current in the current control circuit IC is set to be small by the RD 2  in the next and subsequent burst read cycles. Accordingly, expansion of an operation margin or reduction of power consumption can be realized in a semiconductor device including a semiconductor memory such as a DRAM.]]></description>
<pubDate>April 24, 2008</pubDate>
</item>

<item>
<title><![CDATA[TWO-CYCLE SENSING IN A TWO-TERMINAL MEMORY ARRAY HAVING LEAKAGE CURRENT]]></title>
<link>http://www.freepatentsonline.com/20080094929.html</link>
<description><![CDATA[A two-terminal memory array includes a plurality of first and second conductive traces. An address unit operatively applies a select voltage across a selected pair of the first and second conductive traces and applies a non-select voltage potential to unselected traces. A total current flowing in the selected first conductive trace and a leakage current flowing through unselected second conductive traces are sensed by a sense unit in a one cycle or a two cycle pre-read operation. The total and leakage currents can be combined with a reference signal to derive a data signal indicative of one of a plurality of conductivity profiles that represent stored data. The conductivity profiles can be stored in a resistive state memory element that is electrically in series with the selected first and second conductive traces.]]></description>
<pubDate>April 24, 2008</pubDate>
</item>

<item>
<title><![CDATA[METHODS OF OPERATING A BISTABLE RESISTANCE RANDOM ACCESS MEMORY WITH MULTIPLE MEMORY LAYERS AND MULTILEVEL MEMORY STATES]]></title>
<link>http://www.freepatentsonline.com/20080094875.html</link>
<description><![CDATA[A method is described for operating a bistable resistance random access memory having two memory layer stacks that are aligned in series is disclosed. The bistable resistance random access memory comprises two memory layer stacks per memory cell, the bistable resistance random access memory operates in four logic states, a logic “00” state, a logic “01” state, a logic “10” state and a logic “11” state. The relationship between the four different logic states can be represented mathematically by the two variables n and f and a resistance R. The logic “0” state is represented by a mathematical expression (1+f)R. The logic “1” state is represented by a mathematical expression (n+f)R. The logic “2” state is represented by a mathematical expression (1+nf)R. The logic “3” state is represented by a mathematical expression n(1+f)R.]]></description>
<pubDate>April 24, 2008</pubDate>
</item>

<item>
<title><![CDATA[Multiple-read resistance-variable memory cell structure and method of sensing a resistance thereof]]></title>
<link>http://www.freepatentsonline.com/20080094874.html</link>
<description><![CDATA[Disclosed herein is a multiple read-port nonvolatile memory cell structure, and related method of sensing a resistance state of memory cell, for high-speed and high-bandwidth applications. It provides about a 2× bandwidth gain over conventional cells during the read cycle in embodiments where two read ports are constructed. For example, where conventional arrays include only one read wordline and one read bitline for each memory cell in an array, an array constructed as disclosed herein includes at least two read wordlines and at least two read bitlines for each memory cell. It is still comparable in cell size with a typical 1T1RV cell because the cell pitch is limited by backend size and under-metal layer connection layout.]]></description>
<pubDate>April 24, 2008</pubDate>
</item>

<item>
<title><![CDATA[MEMORY DEVICE HAVING SELECTIVELY DECOUPLEABLE MEMORY PORTIONS AND METHOD THEREOF]]></title>
<link>http://www.freepatentsonline.com/20080094924.html</link>
<description><![CDATA[In response to determining a bit cell of a bit cell array of a memory device is a defective bit cell, a portion of the bit cell array including the defective bit cell is decoupled from a power source of the memory device. The portion can be decoupled via a fuse, a transistor, and the like.]]></description>
<pubDate>April 24, 2008</pubDate>
</item>

<item>
<title><![CDATA[SEMICONDUCTOR INTEGRATED CIRCUIT]]></title>
<link>http://www.freepatentsonline.com/20080094889.html</link>
<description><![CDATA[The present invention provides an integrated circuit capable of reducing a leak current and reliably holding data therein in a standby mode. A potential higher than a potential of a second source line is supplied to a first source line. A potential lower than a potential of a first ground line is supplied to a second ground line. A virtual source line and a virtual ground line are respectively connected to the second source line and the first ground line by switches in an operation mode and float thereby in the standby mode. Substrates of MOS transistors are respectively connected to the second source line and the first ground line by switches in the operation mode and connected to the first source line and the second ground line thereby in the standby mode. A gate circuit transmits an output signal of a data non-holding circuit to a data holding circuit in the operation mode and fixes an input signal of the data holding circuit in the standby mode.]]></description>
<pubDate>April 24, 2008</pubDate>
</item>

<item>
<title><![CDATA[Bistable Resistance Random Access Memory Structures with Multiple Memory Layers and Multilevel Memory States]]></title>
<link>http://www.freepatentsonline.com/20080094885.html</link>
<description><![CDATA[A bistable resistance random access memory comprises a plurality of memory cells where each memory cell having multiple memory layer stack. Each memory layer stack includes a conductive layer overlying a programmable resistance random access memory layer. A first memory layer stack overlies a second memory layer stack, and the second memory stack overlies a third memory layer stack. The first memory layer stack has a first conductive layer overlies a first programmable resistance random access memory layer. The second memory layer stack has a second conductive layer overlies a second programmable resistance random access memory layer. The second programmable resistance random access memory layer has a memory area that is larger than a memory area of the first programmable resistance random access memory layer.]]></description>
<pubDate>April 24, 2008</pubDate>
</item>

<item>
<title><![CDATA[Non-volatile memory device capable of reducing threshold voltage distribution]]></title>
<link>http://www.freepatentsonline.com/20080094923.html</link>
<description><![CDATA[A method for programming a flash memory device which includes a plurality of memory cells arranged in rows and columns. The method includes programming selected memory cells from among the plurality of memory cells according to loaded data bits. Data bits are read from the programmed selected memory cells. It is determined whether each of the programmed memory cells has been successfully programmed based on the results of the reading step. The programming of memory cells that have been determined to have been successfully programmed are inhibited. The programming, reading, determining and inhibiting steps are repeated until each of the selected memory cells has been determined to have been successfully programmed. A memory cell that has been previously determined to have been successfully programmed and inhibited is uninhibited and subsequently re-programmed when it is determined that the previously inhibited memory cell is no longer successfully programmed.]]></description>
<pubDate>April 24, 2008</pubDate>
</item>

<item>
<title><![CDATA[NON-VOLATILE MEMORY DEVICE]]></title>
<link>http://www.freepatentsonline.com/20080094882.html</link>
<description><![CDATA[A non-volatile memory device according to one embodiment comprises a plurality of memory cells each comprising a magneto resistive element and a selection transistor; wherein at least some of the memory cells are arranged into a two dimensional array; a first interconnect line extending in a first direction of the memory array and functioning as a gate electrode of a selection transistor included in each memory cell; a second interconnect line extending in the first direction of the memory array; a third interconnect line extending in a second direction; wherein the magneto resistive element of at least some of the memory cells is sandwiched between the second and third interconnect lines, wherein the second interconnect line extends at least partially along all magneto resistive elements in a particular one of the memory cells.]]></description>
<pubDate>April 24, 2008</pubDate>
</item>

<item>
<title><![CDATA[Magneto-Resistance Element And Magnetic Random Access Memory]]></title>
<link>http://www.freepatentsonline.com/20080094880.html</link>
<description><![CDATA[A magneto-resistance element includes a free layer, a fixed layer and a non-magnetic layer interposed between the free layer and the fixed layer. The free layer has a first magnetic layer, a second magnetic layer, a third magnetic layer, a first non-magnetic layer interposed between the first magnetic layer and the second magnetic layer, and a second non-magnetic layer interposed between the second magnetic layer and the third magnetic layer. The first magnetic layer, the second magnetic layer and the third magnetic layer are coupled such that spontaneous magnetizations have a helical structure.]]></description>
<pubDate>April 24, 2008</pubDate>
</item>

<item>
<title><![CDATA[Portable device for storing private information such as medical, financial or emergency information]]></title>
<link>http://www.freepatentsonline.com/20080094926.html</link>
<description><![CDATA[A portable housing capable of being carried by a certain person includes a circuit. The circuit includes a memory for storing private data concerning that certain person, a circuit operable to effectuate storage of the private data in the memory in a secure manner, and a processing unit operable to control access to the memory for purposes of reading private data concerning the certain person from the memory and storing private data concerning the certain person to the memory. The conditions under which access to the memory for read and write operations with respect to the private data is permitted are governed by parameters that are specified by the certain person to whom the stored private data concerns. A biometric sensor may also be included to capture identification information useful in implementing the operations for controlling access to the memory.]]></description>
<pubDate>April 24, 2008</pubDate>
</item>

<item>
<title><![CDATA[RING OSCILLATOR ROW CIRCUIT FOR EVALUATING MEMORY CELL PERFORMANCE]]></title>
<link>http://www.freepatentsonline.com/20080094878.html</link>
<description><![CDATA[A ring oscillator row circuit for evaluating memory cell performance provides for circuit delay and performance measurements in an actual memory circuit environment. A ring oscillator is implemented with a row of memory cells and has outputs connected to one or more bitlines along with other memory cells that are substantially identical to the ring oscillator cells. Logic may be included for providing a fully functional memory array, so that the cells other than the ring oscillator cells can be used for storage when the ring oscillator row wordlines are disabled. One or both power supply rails of individual cross-coupled inverter stages forming static memory cells used in the ring oscillator circuit may be isolated from each other in order to introduce a voltage asymmetry so that circuit asymmetry effects on delay can be evaluated.]]></description>
<pubDate>April 24, 2008</pubDate>
</item>

<item>
<title><![CDATA[MAGNETIC TUNNEL JUNCTION DEVICES AND MAGNETIC RANDOM ACCESS MEMORY]]></title>
<link>http://www.freepatentsonline.com/20080094888.html</link>
<description><![CDATA[A magnetic random access memory (MRAM) is disclosed. The MRAM includes a first electrode, an antiferromagnetic layer formed over the first electrode, a pinned layer formed over the antiferromagnetic layer, a barrier layer formed over the pinned layer, a composite free layer formed over the barrier layer, and a second electrode formed over the composite free layer. The composite free layer includes a first magnetic layer, a spacer layer and a second magnetic layer sequentially stacked over the barrier layer and the spacer layer allows parallel coupling between the first and second magnetic layers. A magnetic tunnel junction (MTJ) device suitable for a memory unit of a magnetic memory device is also provided.]]></description>
<pubDate>April 24, 2008</pubDate>
</item>

<item>
<title><![CDATA[Semiconductor memory having data line separation switch]]></title>
<link>http://www.freepatentsonline.com/20080094928.html</link>
<description><![CDATA[A semiconductor memory comprises a data line separation switch circuit, which controls connection and separation of digit lines DT/DB connected to a memory cell and sense amplifier, and a control circuit, which performs a control of switching the data line separation switch circuit from turning-on to turning-off according to the level of the amplification output of the sense amplifier at the sense operation time. Detecting the output level of the sense amplifier so as to separate the sense amplifier from the digit lines makes it difficult for an error read to occur, and at the same time, adjusting a timing of the data line separation switch is made unnecessary.]]></description>
<pubDate>April 24, 2008</pubDate>
</item>

<item>
<title><![CDATA[Soft Error Robust Static Random Access Memory Cells]]></title>
<link>http://www.freepatentsonline.com/20080094925.html</link>
<description><![CDATA[A Static Random Access Memory (SRAM) cell is provided with an improved robustness to radiation induced soft errors. The SRAM cell comprises the following elements. First and second storage nodes are configured to store complementary voltages. Access transistors are configured to selectively couple the first and second storage nodes to a corresponding bit line. Drive transistors are configured to selectively couple one of the first and second storage nodes to ground. Load transistors are configured to selectively couple the other one of the first and second storage nodes to a power supply. At least one stabilizer transistor is configured to provide a corresponding redundant storage node and limit feedback between the first and second storage nodes. The redundant storage node is capable of restoring the first or second storage nodes in case of a soft error.]]></description>
<pubDate>April 24, 2008</pubDate>
</item>

<item>
<title><![CDATA[TEMPERATURE COMPENSATION OF SELECT GATES IN NON-VOLATILE MEMORY]]></title>
<link>http://www.freepatentsonline.com/20080094930.html</link>
<description><![CDATA[Reading and verify operations are performed on non-volatile storage elements using temperature-compensated read voltages for unselected word lines, and/or for select gates such as drain or source side select gates of a NAND string. In one approach, while a read or verify voltage is applied to a selected word line, temperature-compensated read voltages are applied to unselected word lines and select gates. Word lines which directly neighbor the selected word line can receive a voltage which is not temperature compensated, or which is temperature-compensated to a reduced degree. The read or verify voltage applied to the selected word line can also be temperature-compensated. The temperature compensation may also account for word line position.]]></description>
<pubDate>April 24, 2008</pubDate>
</item>

<item>
<title><![CDATA[Magnetic memory]]></title>
<link>http://www.freepatentsonline.com/20080094883.html</link>
<description><![CDATA[To provide a magnetic memory capable of reducing the amount of write current, even when the element size is 0.7 μm or less. Each of storage areas has a transistor for read/write control, which is connected electrically to either one of the fixed layer and the free layer of each magneto-resistance effect element, a wiring that is electrically connected to the other one of the fixed layer and the free layer of each magneto-resistance effect element, and a magnetic yoke that surrounds the wiring and provides a magnetic field to the free layer, and the number of the transistors within each storage area is one.]]></description>
<pubDate>April 24, 2008</pubDate>
</item>

<item>
<title><![CDATA[Semiconductor device using magnetic domain wall movement and method of manufacturing the same]]></title>
<link>http://www.freepatentsonline.com/20080094887.html</link>
<description><![CDATA[A semiconductor device using a magnetic domain wall movement and a method of manufacturing the semiconductor device are provided. The semiconductor device includes a magnetic layer that is formed on a substrate and has a plurality of magnetic domains, and a unit that supplies energy to move a magnetic domain wall in the magnetic layer. The magnetic layer is formed parallel to the substrate, and includes a plurality of prominences and a plurality of depressions alternately formed along a lengthwise direction thereof. The magnetic layer has a stepped form that secures a reliable movement of the magnetic domain wall in units of one bit.]]></description>
<pubDate>April 24, 2008</pubDate>
</item>

<item>
<title><![CDATA[Hybrid Memory Cell for Spin-Polarized Electron Current Induced Switching and Writing/Reading Process Using Such Memory Cell]]></title>
<link>http://www.freepatentsonline.com/20080094881.html</link>
<description><![CDATA[A magnetoresistive hybrid memory cell includes first and second stacked structures. The first stacked structure includes a magnetic tunnel junction including first and second magnetic regions stacked in a parallel, overlying relationship separated by a layer of non-magnetic material, wherein the first magnetic region has a fixed first magnetic moment vector and the second magnetic region has a free second magnetic moment vector that is switchable between the same and opposite directions with respect to the fixed first magnetic moment vector. The second stacked structure is at least partly arranged in a lateral relationship with respect to the first stacked structure and includes a third magnetic region having a fixed third magnetic moment vector and the second magnetic region. The first and second structures are arranged between at least two electrodes in electrical contact therewith.]]></description>
<pubDate>April 24, 2008</pubDate>
</item>

<item>
<title><![CDATA[Semiconductor memory device layout comprising high impurity well tap areas for supplying well voltages to NWELLS and PWELLS]]></title>
<link>http://www.freepatentsonline.com/20080094869.html</link>
<description><![CDATA[A semiconductor device includes a plurality of memory cells, and an error-correction circuit. Its write operation is performed by a late-write method, and ECC processing is executed in parallel with writing to shorten a cycle time. Moreover, when a memory cell is power-supplied through a well tap, the same address is not assigned while the memory cell is power-supplied through the well tap.]]></description>
<pubDate>April 24, 2008</pubDate>
</item>

<item>
<title><![CDATA[Sequential and video access for non-volatile memory arrays]]></title>
<link>http://www.freepatentsonline.com/20080094871.html</link>
<description><![CDATA[An array of non-volatile memory cells arranged in logical columns and logical rows, and associated circuitry to enable reading or writing one or more memory cells on a row in parallel. In some embodiments, the array of memory cells may include a phase change material. In some embodiments, the circuitry may include a write driver, a read driver, a sense amplifier, and circuitry to isolate the memory cells from the sense amplifier with extended refresh. In some embodiments, the circuitry may further include shift registers and one or more arithmetic logic units to provide a video memory.]]></description>
<pubDate>April 24, 2008</pubDate>
</item>

<item>
<title><![CDATA[Flash memory device with word line discharge unit and data read method thereof]]></title>
<link>http://www.freepatentsonline.com/20080094927.html</link>
<description><![CDATA[Exemplary embodiments of the present invention provide a flash memory device which includes a memory cell array. A decoder circuit is connected to the memory cell array via a plurality of select lines and a plurality of word lines. The detector circuit supplies voltages for a read operation to the plurality of select lines and the plurality of word lines during the read operation. A word line discharge unit is connected to the memory cell array via the plurality of word lines. The word line discharge unit discharges a voltage level of a selected word line during the read operation.]]></description>
<pubDate>April 24, 2008</pubDate>
</item>

<item>
<title><![CDATA[Reference cell scheme for MRAM]]></title>
<link>http://www.freepatentsonline.com/20080094884.html</link>
<description><![CDATA[An MRAM reference cell sub-array provides a mid-point reference current to sense amplifiers. The MRAM reference cell sub-array has MRAM cells arranged in rows and columns. Bit lines are associated with each column of the sub-array. A coupling connects the bit lines of pairs of the columns together at a location proximally to the sense amplifiers. The MRAM cells of a first of the pair of columns are programmed to a first magneto-resistive state and the MRAM cells of a second of the pair of columns are programmed to a second magneto-resistive state. When one row of data MRAM cells is selected for reading, a row of paired MRAM reference cells are placed in parallel to generate the mid-point reference current for sensing. The MRAM reference sub-array may be programmed electrically or aided by a magnetic field. A method for verifying programming of the MRAM reference sub-array is discussed.]]></description>
<pubDate>April 24, 2008</pubDate>
</item>

<item>
<title><![CDATA[Semiconductor memory device]]></title>
<link>http://www.freepatentsonline.com/20080094879.html</link>
<description><![CDATA[A storage node voltage control circuit is added to a memory cell including two load transistors, two drive transistors and two access transistors. The storage node voltage control circuit performs control so that in writing data into the memory cell, a voltage at one of the two storage nodes holding a low logic level is raised without changing voltages at respective sources of the load transistors.]]></description>
<pubDate>April 24, 2008</pubDate>
</item>

<item>
<title><![CDATA[Memory device performing partial refresh operation and method thereof]]></title>
<link>http://www.freepatentsonline.com/20080094931.html</link>
<description><![CDATA[The present invention provides a memory device which comprises a memory cell array having a plurality of memory blocks; a memory controller for controlling a refresh operation with respect to the memory blocks; a refresh check bit storing part for storing refresh check bits corresponding to the memory blocks, respectively; a block select control part for setting refresh check bits of memory blocks to be refreshed to a check state according to a control of the memory controller; a using check bit storing part for storing using check bits corresponding to the memory blocks, respectively; a using check control part for setting refresh check bits of memory blocks access-requested to a check state according to a control of the memory controller; and a partial refresh control part for controlling such that memory blocks corresponding to checked using check bits or refresh check bits according to a control of the memory controller.]]></description>
<pubDate>April 24, 2008</pubDate>
</item>

<item>
<title><![CDATA[TEMPERATURE COMPENSATION OF VOLTAGES OF UNSELECTED WORD LINES IN NON-VOLATILE MEMORY BASED ON WORD LINE POSITION]]></title>
<link>http://www.freepatentsonline.com/20080094908.html</link>
<description><![CDATA[Reading and verify operations are performed on non-volatile storage elements using temperature-compensated read voltages for unselected word lines, and/or for select gates such as drain or source side select gates of a NAND string. In one approach, while a read or verify voltage is applied to a selected word line, temperature-compensated read voltages are applied to unselected word lines and select gates. Word lines which directly neighbor the selected word line can receive a voltage which is not temperature compensated, or which is temperature-compensated to a reduced degree. The read or verify voltage applied to the selected word line can also be temperature-compensated. The temperature compensation may also account for word line position.]]></description>
<pubDate>April 24, 2008</pubDate>
</item>

<item>
<title><![CDATA[Noise resistant small signal sensing circuit for a memory device]]></title>
<link>http://www.freepatentsonline.com/20080094919.html</link>
<description><![CDATA[Apparatus and method for data sensing circuitry that uses averaging to sense small differences in signal levels representing data states. The apparatus periodically switches the coupling of input terminals and output terminals of an integrator circuit from a first configuration to a second configuration, where the second configuration changes the polarity of the integrator circuit from the first configuration. The output signals of the integrator circuit are periodically compared, and based on the comparison, output signals having a voltage representative of a value are generated. The values of the output signals are then averaged over time to determine the data state.]]></description>
<pubDate>April 24, 2008</pubDate>
</item>

<item>
<title><![CDATA[Parallel Threshold Voltage Margin Search for MLC Memory Application]]></title>
<link>http://www.freepatentsonline.com/20080094891.html</link>
<description><![CDATA[A method for determining read voltage margins in a memory array compares as-read sum codes generated from data read from the memory array with expected sum codes generated from the loaded data. The read voltage (Vt) is stepped and the as-read sum codes are compared to the expected sum codes to determine the Vt range(s) that provides matching sum codes. Multiple read voltage margins (i.e. the read voltage margins between multiple programming levels of the MLC memory array) are determined in a parallel fashion as Vt is stepped across its range.]]></description>
<pubDate>April 24, 2008</pubDate>
</item>

<item>
<title><![CDATA[FLASH MEMORY DEVICE AND PROGRAM METHOD THEREOF]]></title>
<link>http://www.freepatentsonline.com/20080094910.html</link>
<description><![CDATA[A method of programming a plurality of memory cells in a flash memory device from a first state to a second state includes verifying the plurality of memory cells using a verify voltage having a level increased according to an increase in a program loop number; and programming the plurality of memory cells using a program voltage having an increment decreased according to an increase in the program loop number, wherein the verifying and programming steps constitute a program loop, the program loop being terminated at a point in time when a level of the verify voltage reaches to a voltage range of the second state.]]></description>
<pubDate>April 24, 2008</pubDate>
</item>

<item>
<title><![CDATA[Semiconductor memory device]]></title>
<link>http://www.freepatentsonline.com/20080094870.html</link>
<description><![CDATA[A semiconductor memory device includes a memory cell array and peripheral control circuits. In each of the peripheral control circuits, a plurality of transistors are arranged at a substantially constant transistor pitch in a first direction which is the row direction or the column direction of the memory cell array. In the memory cell array, a memory cell length in the first direction is substantially n times the transistor pitch, wherein n is an integer.]]></description>
<pubDate>April 24, 2008</pubDate>
</item>

<item>
<title><![CDATA[Semiconductor memory device and methods thereof]]></title>
<link>http://www.freepatentsonline.com/20080094932.html</link>
<description><![CDATA[A semiconductor memory device and methods thereof are provided. The example semiconductor memory device may include an internal address generating circuit operating in accordance with a first addressing protocol during normal operation and operating in accordance with a second addressing protocol during a test operation, the first addressing protocol associated with a first number of clock cycles for transferring a memory address and the second addressing protocol associated with a second number of clock cycles for transferring a memory address, the first number of clock cycles being greater than the second number of clock cycles. An example method may for achieving an single pumped address (SPA) mode in a semiconductor memory device configured for a double pumped address (DPA) mode may include receiving a first external address, generating a first internal address corresponding to the received first external address, receiving a second external address, generating a second internal address corresponding to the received second external address and delaying the generation of the first internal address to reduce a clock cycle interval between the generated first and second internal addresses.]]></description>
<pubDate>April 24, 2008</pubDate>
</item>

<item>
<title><![CDATA[Non Volatile Memory RAD-hard (NVM-rh) System]]></title>
<link>http://www.freepatentsonline.com/20080094896.html</link>
<description><![CDATA[The embodiments of the invention provide an apparatus, method, etc. for a non volatile memory RAD-hard (NVM-rh) system. More specifically, an IC permanent non-volatile storage element comprises an integrated semiconductor stable reference component, wherein the component is resistant to external radiation. The storage element further comprises e-fuse structures in the component and a sensing circuit coupled to the e-fuse structures. The sensing circuit is adapted to update an external device at a specified time interval to reduce incidence of soft errors and errors due to power failure. Moreover, the sensing circuit is adapted to cease updating the external device to program the e-fuse structures; and, continue updating the external device after programming the e-fuse structures.]]></description>
<pubDate>April 24, 2008</pubDate>
</item>

<item>
<title><![CDATA[Memory read control circuit and control method thereof]]></title>
<link>http://www.freepatentsonline.com/20080094918.html</link>
<description><![CDATA[A control circuit to which a read requirement signal for data read of a memory and a burst length information signal for the read requirement are input controls a pull-up circuit so as to pull-up a data strobe signal if the read requirement signal is active. A mask signal is made to an unmask state if the data strobe signal is transferred from H-level to L-level. The mask signal is made to an unmask state if a repetition of the predetermined transfer of the data strobe signal is detected based on the burst length information signal. A postamble in the data strobe signal starts by the repetition of the transfer, and after the end of the postamble period, the data strobe signal is pulled-up to H-level.]]></description>
<pubDate>April 24, 2008</pubDate>
</item>

<item>
<title><![CDATA[Non-volatile semiconductor memory device and method for recovering data in non-volatile semiconductor memory device]]></title>
<link>http://www.freepatentsonline.com/20080094897.html</link>
<description><![CDATA[A method and device for recovering data in a non-volatile semiconductor memory device that may include controlling a reference current by the non-volatile semiconductor memory device, reading data of at least one memory cell based on the controlled reference current, storing the read data in a buffer memory, and writing the data stored in the buffer memory to the at least one memory cell.]]></description>
<pubDate>April 24, 2008</pubDate>
</item>

<item>
<title><![CDATA[FLASH MEMORY DEVICE OPERATING AT MULTIPLE SPEEDS]]></title>
<link>http://www.freepatentsonline.com/20080094904.html</link>
<description><![CDATA[A method of operating a flash memory device includes a first operating mode and a second operating mode having different operating speeds. Each one of the first and second operating modes includes a bit line set-up interval and at least one additional interval. The flash memory is divided into first and second mats connected to respective first and second R/W circuits. During the bit line set-up interval of the second operating mode, the flash memory controls operation of both the first and second R/W circuits in a time division approach to stagger respective peak current intervals for the first and second mats.]]></description>
<pubDate>April 24, 2008</pubDate>
</item>

<item>
<title><![CDATA[MEMORY DEVICE FOR CONTROLLING CURRENT DURING PROGRAMMING OF MEMORY CELLS]]></title>
<link>http://www.freepatentsonline.com/20080094916.html</link>
<description><![CDATA[Improved circuitry and methods for programming memory cells of a memory device are disclosed. The improved circuitry and methods operate to isolate the memory cells from potentially damaging electrical energy that can be imposed during a precharge phase that precedes programming of the memory cells. Additionally, the improved circuitry and methods can operate to ensure that programming of the memory cells is performed in a controlled manner using only a program current. The improved circuitry and methods are particularly useful for programming non-volatile memory cells. In one embodiment, the memory device pertains to a semiconductor memory product, such as a semiconductor memory chip or a portable memory card.]]></description>
<pubDate>April 24, 2008</pubDate>
</item>

<item>
<title><![CDATA[LOW POWER MULTIPLE BIT SENSE AMPLIFIER]]></title>
<link>http://www.freepatentsonline.com/20080094909.html</link>
<description><![CDATA[A sense amplifier for multiple level flash memory cells is comprised of a voltage ramp generator that generates a ramp voltage signal. Reference sense amplifiers compare an input reference current to a ramp current generated from the ramp voltage signal. When the ramp voltage signal is greater than the reference current, an output latch signal is toggled. A sense amplifier compares an input bit line current to a threshold and outputs a logical low when the bit line current goes over the threshold. The sense amplifier output is latched into one of three digital latches at a time determined by the latch signals. An encoder encodes the data from the three digital latches into two bits of output data.]]></description>
<pubDate>April 24, 2008</pubDate>
</item>

<item>
<title><![CDATA[Method and Apparatus for Non-Volatile Multi-Bit Memory]]></title>
<link>http://www.freepatentsonline.com/20080094873.html</link>
<description><![CDATA[A memory device that selectably exhibits first and second logic levels. A first conductive material has a first surface with a first memory layer formed thereon, and a second conductive material has a second surface with a second memory layer formed thereon. A connective conductive layer joins the first and second memory layers and places the same in electrical contact. The structure is designed so that the first memory layer has a cross-sectional area less than that of the second memory layer.]]></description>
<pubDate>April 24, 2008</pubDate>
</item>

<item>
<title><![CDATA[FLASH MEMORIES WITH ADAPTIVE REFERENCE VOLTAGES]]></title>
<link>http://www.freepatentsonline.com/20080094907.html</link>
<description><![CDATA[Cells of a flash memory are read by determining respective adaptive reference voltages for the cells and comparing the cells' threshold voltages to their respective reference voltages. The adaptive reference voltages are determined either from analog measurements of the threshold voltages of the cells' neighbors or from preliminary estimates of the cells' threshold voltages based on comparisons of the cells' threshold voltages with integral or fractional reference voltages common to all the cells. Cells of a flash memory also are read by comparing the cells' threshold voltages to integral reference voltages, comparing the threshold voltages of cells that share a common bit pattern to a fractional reference voltage, and adjusting the reference voltages in accordance with the comparisons.]]></description>
<pubDate>April 24, 2008</pubDate>
</item>

<item>
<title><![CDATA[METHOD FOR CONTROLLING CURRENT DURING PROGRAMMING OF MEMORY CELLS]]></title>
<link>http://www.freepatentsonline.com/20080094915.html</link>
<description><![CDATA[Improved circuitry and methods for programming memory cells of a memory device are disclosed. The improved circuitry and methods operate to isolate the memory cells from potentially damaging electrical energy that can be imposed during a precharge phase that precedes programming of the memory cells. Additionally, the improved circuitry and methods can operate to ensure that programming of the memory cells is performed in a controlled manner using only a program current. The improved circuitry and methods are particularly useful for programming non-volatile memory cells. In one embodiment, the memory device pertains to a semiconductor memory product, such as a semiconductor memory chip or a portable memory card.]]></description>
<pubDate>April 24, 2008</pubDate>
</item>

<item>
<title><![CDATA[NON-VOLATILE SEMICONDUCTOR STORAGE DEVICE]]></title>
<link>http://www.freepatentsonline.com/20080094898.html</link>
<description><![CDATA[A memory cell array includes a plurality of non-volatile semiconductor memory elements, each memory element storing data in a non-volatile manner. A shift register stores data read from the semiconductor memory element and sequentially transfers the data outside, the shift register also stores data transferred from outside and stores the data in the semiconductor memory element. A syndrome generation circuit is connected to an output terminal of the shift register, the syndrome generation circuit generating syndrome of data output from the output terminal. An error-correction circuit uses the data and the syndrome to correct an error of the data.]]></description>
<pubDate>April 24, 2008</pubDate>
</item>

<item>
<title><![CDATA[Low-power dram and method for driving the same]]></title>
<link>http://www.freepatentsonline.com/20080094933.html</link>
<description><![CDATA[A dynamic random access memory includes: an address latch configured to latch a row address in response to a row address strobe (RAS) signal and latch a column address in response to a column address strobe (CAS) signal; a row decoder configured to decode the row address; an enabler configured to decode a part of most significant bits (MSB) of the column address to locally enable a part of one page area corresponding to the row address; and a column decoder configured to decode the column address.]]></description>
<pubDate>April 24, 2008</pubDate>
</item>

<item>
<title><![CDATA[VOLTAGE REGULATOR FOR THE PROGRAMMING CIRCUIT OF A MEMORY CELL]]></title>
<link>http://www.freepatentsonline.com/20080094906.html</link>
<description><![CDATA[A voltage regulator connected to a memory cell is configured by identifying at least a first and a second operation regions of the cell and associating the first and second operation regions with respective first and second operation conditions of the memory cell. An operative condition of the memory cell involved in a programming operation is detected, and at least a configuration signal of the regulator according to said detected operative condition is generated, this configuration signal taking a first and a second value associated with the first and second operation conditions.]]></description>
<pubDate>April 24, 2008</pubDate>
</item>

<item>
<title><![CDATA[NONVOLATILE SEMICONDUCTOR MEMORY]]></title>
<link>http://www.freepatentsonline.com/20080094900.html</link>
<description><![CDATA[A nonvolatile semiconductor memory according to an example of the present invention includes first and second word lines extending in a first direction and having the same row address, a first block including the first word line and having a first block address, a second block including the second word line and having a second block address, first and second signal lines extending in a second direction crossing the first direction, a first transfer transistor connected between the first word line and the first signal line, a second transfer transistor connected between the second word line and the second signal line, and a transfer voltage selector to output a transfer voltage to the first and second signal lines.]]></description>
<pubDate>April 24, 2008</pubDate>
</item>

<item>
<title><![CDATA[Flash memory devices and methods of operating the same]]></title>
<link>http://www.freepatentsonline.com/20080094902.html</link>
<description><![CDATA[A memory cell array includes a NAND string formed of a plurality of memory cells coupled in series between a string selection transistor and a ground selection transistor. The string selection transistor controls an electrical connection between the NAND string and a bit line based on a string selection voltage in a read operation. A row selection circuit is coupled to the memory cell array through a string selection line, ground selection line and a plurality of word lines. The row selection circuit selects a word line which is coupled to the read memory cell among the plurality of word lines based on a row address signal and a read voltage in a read operation. A voltage generation circuit generates the string selection voltage and the read voltage.]]></description>
<pubDate>April 24, 2008</pubDate>
</item>

<item>
<title><![CDATA[Nonvolatile memory system and associated programming methods]]></title>
<link>http://www.freepatentsonline.com/20080094893.html</link>
<description><![CDATA[A nonvolatile memory system includes a host system, a memory controller, and a flash memory chip including multi-level flash memory cells. The memory controller includes a backup memory adapted to store a backup copy of previously programmed data from the multi-level flash memory cells when further programming of the multi-level flash memory cells fails. The backup copy of the previously programmed data is used to detect and correct any errors in the previously programmed data before reprogramming the previously programmed data to different multi-level memory cells in the nonvolatile memory system.]]></description>
<pubDate>April 24, 2008</pubDate>
</item>

<item>
<title><![CDATA[METHODS OF RESTORING DATA IN FLASH MEMORY DEVICES AND RELATED FLASH MEMORY DEVICE MEMORY SYSTEMS]]></title>
<link>http://www.freepatentsonline.com/20080094914.html</link>
<description><![CDATA[Methods for setting a read voltage in a memory system which comprises a flash memory device and a memory controller for controlling the flash memory device, comprise sequentially varying a distribution read voltage to read page data from the flash memory device; constituting a distribution table having a data bit number and a distribution read voltage, the data bit number indicating an erase state among the page data respectively read from the flash memory device and the distribution read voltage corresponding to the read page data; detecting distribution read voltages corresponding to data bit numbers each indicating maximum points of possible cell states of a memory cell, based on the distribution table; and defining new read voltages based on the detected distribution read voltages.]]></description>
<pubDate>April 24, 2008</pubDate>
</item>

<item>
<title><![CDATA[Semiconductor storage device]]></title>
<link>http://www.freepatentsonline.com/20080094921.html</link>
<description><![CDATA[A semiconductor storage device according to the present invention comprises a plurality of memory cells each provided with an access transistor in which a source is connected to a bit line and a gate is connected to a word line and a capacitor in which a storage electrode is connected to a drain of the access transistor, the plurality of memory cells being placed in a matrix shape in column and row directions, a sense amplifier circuit connected to the source of the access transistor via the bit line, a bit-line precharge voltage generating circuit for generating a bit-line precharge voltage lower than a sense amplifier supply voltage to be supplied to the sense amplifier circuit and supplying the generated bit-line precharge voltage to the bit line, and a cell plate voltage generating circuit for generating a cell plate voltage set to be lower than the bit-line precharge voltage and supplying the generated cell plate voltage to a plate electrode of the capacitor.]]></description>
<pubDate>April 24, 2008</pubDate>
</item>

<item>
<title><![CDATA[NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE]]></title>
<link>http://www.freepatentsonline.com/20080094899.html</link>
<description><![CDATA[A non-volatile semiconductor memory device, allocates data contained in an ECC frame as a first data group to be stored in a first memory cell group composed of a plurality of first memory cells selected by a first word line and a second data group to be stored in a second memory cell group composed of a plurality of second memory cells selected by a second word line.]]></description>
<pubDate>April 24, 2008</pubDate>
</item>

<item>
<title><![CDATA[Non-Volatile Memory With Improved Program-Verify Operations]]></title>
<link>http://www.freepatentsonline.com/20080094911.html</link>
<description><![CDATA[In programming a non-volatile memory involving alternately applying a programming pulse and verifying the programming, time is saved in the program verify portion when, depending on the states of the memory cells, a portion of the verify operation is recognized to be superfluous and skipped. Preferably, in a program verify operation relative to a demarcation threshold level for demarcating between two memory states, the verify operation includes a sequence of two verify sub-cycles, the first sub-cycle performing a verify relative to a first threshold level at a predetermined margin below the demarcation threshold level and the second sub-cycle performing a verify relative to a second threshold level which is identical to the demarcation threshold level. Unlike conventional cases, the second sub-cycle is not performed until any one memory cell of the group has been verified to pass the first threshold.]]></description>
<pubDate>April 24, 2008</pubDate>
</item>

<item>
<title><![CDATA[Memory card having an information display function using an external light source]]></title>
<link>http://www.freepatentsonline.com/20080093532.html</link>
<description><![CDATA[A memory card including a first memory responsible for the main memory of the memory card, a memory control unit adapted to control the operation of the first memory, a photoelectric voltage generating unit adapted to generate a voltage corresponding to light irradiated externally via photoelectric conversion, a display unit having a second memory adapted to store information set in advance and adapted to display the information set in advance, and a display control unit adapted to control the operation of the display unit. The method of displaying information includes generating a voltage corresponding to light irradiated externally via photoelectric conversion and displaying information set in advance via a display unit of the memory card using the voltage by photoelectric conversion.]]></description>
<pubDate>April 24, 2008</pubDate>
</item>

<item>
<title><![CDATA[SEMICONDUCTOR MEMORY DEVICE AND DATA WRITE AND READ METHOD THEREOF]]></title>
<link>http://www.freepatentsonline.com/20080094890.html</link>
<description><![CDATA[A semiconductor memory device includes a memory cell array including a plurality of memory banks, an address input portion which receives a row address and a column address through address pins during a normal mode operation and which receives the row address, the column address and write data through the address pins during a test mode operation, an address decoder which accesses one of the plurality of memory banks during the normal mode operation and at least two of the plurality of memory banks during the test mode operation in response to the row address and the column address, a data input portion which inputs write data applied through data pins to the memory cell array during the normal mode operation and which inputs write data output from the address input portion to the memory cell array during the test mode operation, and a data output portion which outputs read data output from the memory cell array to the data pins during the normal mode operation and the test mode operation.]]></description>
<pubDate>April 24, 2008</pubDate>
</item>

<item>
<title><![CDATA[NONVOLATILE SEMICONDUCTOR MEMORY AND MEMORY SYSTEM]]></title>
<link>http://www.freepatentsonline.com/20080094894.html</link>
<description><![CDATA[A nonvolatile semiconductor memory includes a plurality of memory cells each configured to store M bits of data, where M is an integer greater than 1. In addition, the memory includes a selection circuit configured to select a first or second mode according to an instruction from outside of the nonvolatile semiconductor memory, and a program circuit configured to program M bits of data into each memory cell in the first mode, and N bits of data into each memory cell in the second mode, where N is an integer less than M. A selection pin may receive a voltage as the instruction from outside the memory indicating the first or second mode. Further, each of the memory cells may be assigned N different page addresses in the first mode and M different page addresses in the second mode.]]></description>
<pubDate>April 24, 2008</pubDate>
</item>

<item>
<title><![CDATA[MEMORY DEVICE FOR PROTECTING MEMORY CELLS DURING PROGRAMMING]]></title>
<link>http://www.freepatentsonline.com/20080094913.html</link>
<description><![CDATA[Improved circuitry and methods for programming memory cells of a memory device are disclosed. The improved circuitry and methods operate to protect the memory cells from potentially damaging electrical energy that can be imposed during programming of the memory cells. Additionally, the improved circuitry and methods operate to detect when programming of the memory cells has been achieved. The improved circuitry and methods are particularly useful for programming non-volatile memory cells. In one embodiment, the memory device pertains to a semiconductor memory product, such as a semiconductor memory chip or a portable memory card.]]></description>
<pubDate>April 24, 2008</pubDate>
</item>

<item>
<title><![CDATA[Nonvolatile Memory]]></title>
<link>http://www.freepatentsonline.com/20080094905.html</link>
<description><![CDATA[A nonvolatile memory includes circuits each having first control transistors, memory transistors, second control transistors and memory transistors repeatedly connected in series in sequence. Inversion layers are formed in the direction intersecting the serial direction with turning on of the control transistors. A selection circuit selects a connection of the inversion layer placed under the first control transistor and its corresponding read/write circuit. The control transistors placed on both sides adjacent to the memory transistor are turned on to perform reading. The first control transistors placed on both sides of the second control transistor as viewed from side to side are turned on to perform writing into the other of the right and left memory transistors via one of the right and left memory transistors. The selection circuit connects the read/write circuit and the inversion layer in such a manner that the same read/write circuit is used in reading and writing for the same memory transistor.]]></description>
<pubDate>April 24, 2008</pubDate>
</item>

<item>
<title><![CDATA[MEMORY AND LOW OFFSET CLAMP BIAS CIRCUIT THEREOF]]></title>
<link>http://www.freepatentsonline.com/20080094920.html</link>
<description><![CDATA[A memory and a low offset clamp bias circuit thereof are provided. The low offset clamp bias circuit is adapted for any existing memory and is used for reducing the variation of a drain side voltage V d  supplied to a memory cell in a memory cell array area through the feedback mechanism formed by a clamp bias modulator and a constant voltage generator. Thereby, the accuracy in reading, writing, or erasing data in the memory can be improved.]]></description>
<pubDate>April 24, 2008</pubDate>
</item>

<item>
<title><![CDATA[Flash memory device capable of preventing coupling effect and program method thereof]]></title>
<link>http://www.freepatentsonline.com/20080094901.html</link>
<description><![CDATA[The present invention provides a flash memory device that comprises a word line; even page cells that are physically adjacent and connected to the word line; and odd page cells that are physically adjacent and connected to the word line, wherein at a program operation, page data is programmed in either one of the even page cells or the odd page cells.]]></description>
<pubDate>April 24, 2008</pubDate>
</item>

<item>
<title><![CDATA[NAND FLASH MEMORY]]></title>
<link>http://www.freepatentsonline.com/20080094903.html</link>
<description><![CDATA[A NAND flash memory, in a read operation, a p-type semiconductor substrate is set at a ground potential, a bit line is charged to a first voltage, a source line, a n-type well and a p-type well are charged to a second voltage, which lies between a ground potential and a first voltage, and in a block not selected by said row decoder, said drain-side select gate line and said source-side select gate line are charged to a third voltage, which is higher than said ground potential and is equal to or lower than said second voltage.]]></description>
<pubDate>April 24, 2008</pubDate>
</item>

<item>
<title><![CDATA[METHOD FOR PROTECTING MEMORY CELLS DURING PROGRAMMING]]></title>
<link>http://www.freepatentsonline.com/20080094892.html</link>
<description><![CDATA[Improved circuitry and methods for programming memory cells of a memory device are disclosed. The improved circuitry and methods operate to protect the memory cells from potentially damaging electrical energy that can be imposed during programming of the memory cells. Additionally, the improved circuitry and methods operate to detect when programming of the memory cells has been achieved. The improved circuitry and methods are particularly useful for programming non-volatile memory cells. In one embodiment, the memory device pertains to a semiconductor memory product, such as a semiconductor memory chip or a portable memory card.]]></description>
<pubDate>April 24, 2008</pubDate>
</item>

<item>
<title><![CDATA[Method of operating a semiconductor memory device having a recessed control gate electrode]]></title>
<link>http://www.freepatentsonline.com/20080094917.html</link>
<description><![CDATA[A semiconductor memory device may include a semiconductor substrate, a control gate electrode recessed in the semiconductor substrate, a storage node layer between the control gate electrode and the semiconductor substrate, a tunneling insulating layer between the storage node layer and the semiconductor substrate, a blocking insulating layer between the storage node layer and the control gate electrode, and first and second channel regions surrounding the control gate electrode and separated by a pair of opposing separating insulating layers. A method of operating the semiconductor memory device may include programming data in the storage node layer by charge tunneling through the blocking insulating layer, thus achieving relatively high reliability and efficiency.]]></description>
<pubDate>April 24, 2008</pubDate>
</item>

<item>
<title><![CDATA[SELECTIVE SLOW PROGRAMMING CONVERGENCE IN A FLASH MEMORY DEVICE]]></title>
<link>http://www.freepatentsonline.com/20080094912.html</link>
<description><![CDATA[A plurality of memory cells are programmed with incrementally increased programming pulses applied to word lines to which the memory cells are coupled. After each pulse, a verify operation determines the threshold voltage for each cell. When the threshold voltage reaches a pre-verify threshold, only the bit line connected to that particular cell is biased with an intermediate voltage that slows down the change in the V t  of the cell. The other cells continue to be programmed at their normal pace. As the V t  for each cell reaches the pre-verify level, it is biased with the intermediate voltage. All of the bit lines are biased with an inhibit voltage as their threshold voltages reach the verify voltage threshold.]]></description>
<pubDate>April 24, 2008</pubDate>
</item>

<item>
<title><![CDATA[Method for forming organic layer pattern, organic layer pattern prepared by the same and organic memory devices comprising the pattern]]></title>
<link>http://www.freepatentsonline.com/20080094872.html</link>
<description><![CDATA[Disclosed are a method for forming an organic layer pattern which is characterized by forming a thin layer by coating a coating solution including a polyimide-based polymer having a heteroaromatic pendant group including a heteroatom in its polyimide major chain, a photoinitiator and a crosslinking agent on a substrate and drying the substrate, and exposing and developing the thin layer, an organic layer pattern prepared by the method, and an organic memory device comprising the pattern. According to example embodiments, a high-resolution micropattern may be formed without undergoing any expensive process, e.g., photoresist, leading to simplification of the preparation process and cost reduction.]]></description>
<pubDate>April 24, 2008</pubDate>
</item>

<item>
<title><![CDATA[NON-UNIFORM SWITCHING BASED NON-VOLATILE MAGNETIC BASED MEMORY]]></title>
<link>http://www.freepatentsonline.com/20080094886.html</link>
<description><![CDATA[One embodiment of the present invention includes a non-uniform switching based non-volatile magnetic memory element including a fixed layer, a barrier layer formed on top of the fixed layer, a first free layer formed on top of the barrier layer, a non-uniform switching layer (NSL) formed on top of the first free layer, and a second free layer formed on top of the non-uniform switching layer, wherein switching current is applied, in a direction that is substantially perpendicular to the fixed, barrier, first free, non-uniform and the second free layers causing switching between states of the first, second free and non-uniform layers with substantially reduced switching current.]]></description>
<pubDate>April 24, 2008</pubDate>
</item>

<item>
<title><![CDATA[NAND type non-volatile memory device and method of forming the same]]></title>
<link>http://www.freepatentsonline.com/20080093678.html</link>
<description><![CDATA[A NAND type non-volatile memory device and a method for forming the same. Well bias lines are disposed substantially parallel to other wiring lines at equal intervals. Active regions that are electrically connected to the well bias line are disposed substantially parallel to other active regions at the same equal intervals. As a result, continuity and repeatability in patterns may be maintained and pattern defects may be minimized or prevented.]]></description>
<pubDate>April 24, 2008</pubDate>
</item>

<item>
<title><![CDATA[Non-volatile memory device and method of fabricating the same]]></title>
<link>http://www.freepatentsonline.com/20080094895.html</link>
<description><![CDATA[A non-volatile memory device, and method of forming the same, increases or maximizes the performance of an ultramicro-structured device. In one embodiment, a non-volatile memory device comprises a first word line and a second word line insulated from each other and positioned to intersect each other with a vacant space therebetween; a bit line in the vacant space between one of the first word line and the second word line and positioned in parallel with one of the first word line and the second word line, the bit line constructed and arranged to be deflected toward one of the first word line and the second word line by an electric field induced between the first word line and the second word line; and a trap site between the bit line and one of the first word line and the second word line intersecting the bit line, the trap site being insulated from the one of the first word line and the second word line intersecting the bit line and spaced apart from the bit line by a portion of the vacant space, the trap site configured to trap a predetermined electric charge to electrostatically fix the bit line in a deflected position in the direction of the one of the word lines.]]></description>
<pubDate>April 24, 2008</pubDate>
</item>

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