freepatentsonline.com 141 131 http://www.freepatentsonline.com/index.html http://www.freepatentsonline.com/images/logo.gif freepatentsonline.com: Static information storage and retrieval http://www.freepatentsonline.com/result.html?query_txt=ccl/365%20and%20isd/11/05/2009&usapp=on USPTO Class 365 Static information storage and retrieval en-us Thu, 05 Nov 2009 03:35:38 EST <![CDATA[SEMICONDUCTOR DEVICE AND OPERATING METHOD THEREOF]]> http://www.freepatentsonline.com/y2009/0273992.html Thu, 05 Nov 2009 08:00:00 EST <![CDATA[APPARATUS FOR REMOVING CROSSTALK IN SEMICONDUCTOR MEMORY DEVICE]]> http://www.freepatentsonline.com/y2009/0273995.html Thu, 05 Nov 2009 08:00:00 EST <![CDATA[BITCELL CURRENT SENSE DEVICE AND METHOD THEREOF]]> http://www.freepatentsonline.com/y2009/0273998.html Thu, 05 Nov 2009 08:00:00 EST <![CDATA[SEMICONDUCTOR DEVICE]]> http://www.freepatentsonline.com/y2009/0273961.html Thu, 05 Nov 2009 08:00:00 EST <![CDATA[FOUR-TERMINAL MULTIPLE-TIME PROGRAMMABLE MEMORY BITCELL AND ARRAY ARCHITECTURE]]> http://www.freepatentsonline.com/y2009/0273962.html Thu, 05 Nov 2009 08:00:00 EST <![CDATA[METHOD AND APPARATUS FOR IMPLEMENTING SELF-REFERENCING READ OPERATION FOR PCRAM DEVICES]]> http://www.freepatentsonline.com/y2009/0273968.html Thu, 05 Nov 2009 08:00:00 EST <![CDATA[CAPACITIVE DIVIDER SENSING OF MEMORY CELLS]]> http://www.freepatentsonline.com/y2009/0273969.html Thu, 05 Nov 2009 08:00:00 EST <![CDATA[SEMICONDUCTOR MEMORY DEVICE, OPERATING METHOD THEREOF, AND COMPRESSION TEST METHOD THEREOF]]> http://www.freepatentsonline.com/y2009/0273991.html Thu, 05 Nov 2009 08:00:00 EST <![CDATA[Integrated Circuit, Memory Cell Array, Memory Module, and Method of Operating an Integrated Circuit]]> http://www.freepatentsonline.com/y2009/0273966.html Thu, 05 Nov 2009 08:00:00 EST <![CDATA[MEMORY DEVICE INCLUDING A PROGRAMMABLE RESISTANCE ELEMENT]]> http://www.freepatentsonline.com/y2009/0273970.html Thu, 05 Nov 2009 08:00:00 EST <![CDATA[SEMICONDUCTOR DEVICE HAVING MULTIPLE I/O MODES]]> http://www.freepatentsonline.com/y2009/0273985.html Thu, 05 Nov 2009 08:00:00 EST <![CDATA[SEMICONDUCTOR MEMORY DEVICE AND OPERATION METHOD THEREOF]]> http://www.freepatentsonline.com/y2009/0273993.html Thu, 05 Nov 2009 08:00:00 EST <![CDATA[DUAL MODE ACCESSING SIGNAL CONTROL APPARATUS AND DUAL MODE TIMING SIGNAL GENERATING APPARATUS]]> http://www.freepatentsonline.com/y2009/0273994.html Thu, 05 Nov 2009 08:00:00 EST <![CDATA[Controlling Apparatus and Controlling Method for Controlling a Pre-Charge Activity on a SRAM Array]]> http://www.freepatentsonline.com/y2009/0273997.html Thu, 05 Nov 2009 08:00:00 EST <![CDATA[SYSTEM AND METHOD OF COMMAND BASED AND CURRENT LIMIT CONTROLLED MEMORY DEVICE POWER UP]]> http://www.freepatentsonline.com/y2009/0274000.html Thu, 05 Nov 2009 08:00:00 EST <![CDATA[METHOD AND INTEGRATED CIRCUIT FOR DETERMINING THE STATE OF A RESISTIVITY CHANGING MEMORY CELL]]> http://www.freepatentsonline.com/y2009/0273967.html Thu, 05 Nov 2009 08:00:00 EST <![CDATA[DATA OUTPUT CIRCUIT OF SEMICONDUCTOR MEMORY APPARATUS]]> http://www.freepatentsonline.com/y2009/0273987.html Thu, 05 Nov 2009 08:00:00 EST <![CDATA[Memory testing system and memory module thereof]]> http://www.freepatentsonline.com/y2009/0273996.html Thu, 05 Nov 2009 08:00:00 EST <![CDATA[NAND ARCHITECTURE MEMORY WITH VOLTAGE SENSING]]> http://www.freepatentsonline.com/y2009/0273980.html Thu, 05 Nov 2009 08:00:00 EST <![CDATA[CONTINUOUSLY DRIVING NON-VOLATILE MEMORY ELEMENT]]> http://www.freepatentsonline.com/y2009/0273971.html Thu, 05 Nov 2009 08:00:00 EST <![CDATA[Nonvolatile Memory, Verify Method Therefor, and Semiconductor Device Using the Nonvolatile Memory]]> http://www.freepatentsonline.com/y2009/0273974.html Thu, 05 Nov 2009 08:00:00 EST <![CDATA[MULTILAYERED NONVOLATILE MEMORY WITH ADAPTIVE CONTROL]]> http://www.freepatentsonline.com/y2009/0273977.html Thu, 05 Nov 2009 08:00:00 EST <![CDATA[SEMICONDUCTOR MEMORY DEVICE, SEMICONDUCTOR DEVICE, AND DATA WRITE METHOD]]> http://www.freepatentsonline.com/y2009/0273982.html Thu, 05 Nov 2009 08:00:00 EST <![CDATA[NONVOLATILE MEMORY DEVICE AND PROGRAMMING METHOD]]> http://www.freepatentsonline.com/y2009/0273983.html Thu, 05 Nov 2009 08:00:00 EST <![CDATA[Non-Volatile Memory With Redundancy Data Buffered in Remote Buffer Circuits]]> http://www.freepatentsonline.com/y2009/0273986.html Thu, 05 Nov 2009 08:00:00 EST <![CDATA[CIRCUIT AND METHODS TO IMPROVE THE OPERATION OF SOI DEVICES]]> http://www.freepatentsonline.com/y2009/0273988.html Thu, 05 Nov 2009 08:00:00 EST <![CDATA[SYSTEM FOR PROVIDING ON-DIE TERMINATION OF A CONTROL SIGNAL BUS]]> http://www.freepatentsonline.com/y2009/0273960.html Thu, 05 Nov 2009 08:00:00 EST <![CDATA[MULTI-LEVEL CELL ACCESS BUFFER WITH DUAL FUNCTION]]> http://www.freepatentsonline.com/y2009/0273973.html Thu, 05 Nov 2009 08:00:00 EST <![CDATA[NON-VOLATILE MULTILEVEL MEMORY CELLS WITH DATA READ OF REFERENCE CELLS]]> http://www.freepatentsonline.com/y2009/0273975.html Thu, 05 Nov 2009 08:00:00 EST <![CDATA[SEMICONDUCTOR MEMORY DEVICE WHICH INCLUDES MEMORY CELL HAVING CHARGE ACCUMULATION LAYER AND CONTROL GATE]]> http://www.freepatentsonline.com/y2009/0273976.html Thu, 05 Nov 2009 08:00:00 EST <![CDATA[PROGRAMMING METHOD TO REDUCE WORD LINE TO WORD LINE BREAKDOWN FOR NAND FLASH]]> http://www.freepatentsonline.com/y2009/0273979.html Thu, 05 Nov 2009 08:00:00 EST <![CDATA[BIASING SYSTEM AND METHOD]]> http://www.freepatentsonline.com/y2009/0273984.html Thu, 05 Nov 2009 08:00:00 EST <![CDATA[SEMICONDUCTOR INTEGRATED CIRCUIT AND METHOD OF PROCESSING ADDRESS AND COMMAND SIGNALS THEREOF]]> http://www.freepatentsonline.com/y2009/0274002.html Thu, 05 Nov 2009 08:00:00 EST <![CDATA[SEMICONDUCTOR INTEGRATED CIRCUIT]]> http://www.freepatentsonline.com/y2009/0273870.html Thu, 05 Nov 2009 08:00:00 EST <![CDATA[NAND FLASH MEMORY]]> http://www.freepatentsonline.com/y2009/0273978.html Thu, 05 Nov 2009 08:00:00 EST <![CDATA[Methods and apparatuses for programming flash memory using modulated pulses]]> http://www.freepatentsonline.com/y2009/0273981.html Thu, 05 Nov 2009 08:00:00 EST <![CDATA[Synchronous Command Base Write Recovery Time Auto Precharge Control]]> http://www.freepatentsonline.com/y2009/0273989.html Thu, 05 Nov 2009 08:00:00 EST <![CDATA[SEMICONDUCTOR DEVICE]]> http://www.freepatentsonline.com/y2009/0273990.html Thu, 05 Nov 2009 08:00:00 EST <![CDATA[SENSE AMPLIFIER AND DATA SENSING METHOD THEREOF]]> http://www.freepatentsonline.com/y2009/0273999.html Thu, 05 Nov 2009 08:00:00 EST <![CDATA[SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR OPERATING THE SAME]]> http://www.freepatentsonline.com/y2009/0274001.html Thu, 05 Nov 2009 08:00:00 EST <![CDATA[NONVOLATILE SEMICONDUCTOR MEMORY DEVICE]]> http://www.freepatentsonline.com/y2009/0273964.html Thu, 05 Nov 2009 08:00:00 EST <![CDATA[MAGNETIC MEMORY DEVICE AND METHOD OF FABRICATING THE SAME]]> http://www.freepatentsonline.com/y2009/0273045.html Thu, 05 Nov 2009 08:00:00 EST <![CDATA[Nonvolatile Memory Device]]> http://www.freepatentsonline.com/y2009/0273965.html Thu, 05 Nov 2009 08:00:00 EST <![CDATA[MAGNETIC LOGIC ELEMENT WITH TOROIDAL MULTIPLE MAGNETIC FILMS AND A METHOD OF LOGIC TREATMENT USING THE SAME]]> http://www.freepatentsonline.com/y2009/0273972.html Thu, 05 Nov 2009 08:00:00 EST <![CDATA[MEMORY CONTROLLER-ADAPTIVE 1T/2T TIMING CONTROL]]> http://www.freepatentsonline.com/y2009/0276597.html Thu, 05 Nov 2009 08:00:00 EST <![CDATA[SEMICONDUCTOR STORAGE DEVICE, SEMICONDUCTOR STORAGE DEVICE MANUFACTURING METHOD AND PACKAGE RESIN FORMING METHOD]]> http://www.freepatentsonline.com/y2009/0273963.html Thu, 05 Nov 2009 08:00:00 EST <![CDATA[SURFACE TREATMENT TO IMPROVE RESISTIVE-SWITCHING CHARACTERISTICS]]> http://www.freepatentsonline.com/y2009/0272961.html Thu, 05 Nov 2009 08:00:00 EST