<?xml version="1.0" encoding="UTF-8"?>

<rss version="2.0">

<channel>
<image>
<title>freepatentsonline.com</title>
<width>141</width>
<height>131</height>
<link>http://www.freepatentsonline.com/index.html</link>
<url>http://www.freepatentsonline.com/images/logo.gif</url>
</image>

<title>freepatentsonline.com: Electrical computers and digital processing systems: processing architectures and instruction processing (e.g., processors)</title>
<link>http://www.freepatentsonline.com/result.html?query_txt=ccl/712%20and%20isd/04/24/2008&amp;usapp=on</link>
<description>USPTO Class 712 Electrical computers and digital processing systems: processing architectures and instruction processing (e.g., processors)</description>
<language>en-us</language>
<lastBuildDate>Wed Apr 30 17:03:31 EDT 2008</lastBuildDate>

<item>
<title><![CDATA[Apparatus and methods for stabilization of processors, operating systems and other hardware and/or software configurations]]></title>
<link>http://www.freepatentsonline.com/20080098205.html</link>
<description><![CDATA[Apparatus and methods for converting a processor, having a plurality of states and being operative to execute software operations stored in a memory device, into a self-stabilizing processor, comprising providing self-stabilizing watchdog hardware that, with given timing, interacts with the processor, in accordance with an interaction sequence that includes at least one trigger that sets the processor to a known state from among a set of at least one known states. Also described are applications for stabilization of operating systems and other hardware or software configurations, apparatus and methods for ensuring eventual invariance of software executed by a processor, and apparatus and methods for enforcing fixed software configurations.]]></description>
<pubDate>April 24, 2008</pubDate>
</item>

<item>
<title><![CDATA[Analyzing diagnostic data generated by multiple threads within an instruction stream]]></title>
<link>http://www.freepatentsonline.com/20080098207.html</link>
<description><![CDATA[A diagnostic method for outputting diagnostic data relating to processing of instruction streams stemming from a computer program, at least some of said instructions streams comprising multiple threads is disclosed. The method comprises the steps of: (i) receiving diagnostic data; (ii) reordering said received diagnostic data in dependence upon reordering data, said reordering data comprising data relating to said computer program; and (iii) outputting said reordered diagnostic data. In general, the instructions streams are processed by a plurality of processing units arranged to process at least some of said instructions in parallel, said diagnostic data being received from said plurality of processing units.]]></description>
<pubDate>April 24, 2008</pubDate>
</item>

<item>
<title><![CDATA[Method And Apparatus For Improving The Efficiency Of A Processor Instruction Pipeline]]></title>
<link>http://www.freepatentsonline.com/20080098204.html</link>
<description><![CDATA[A system and method are disclosed which may include providing a processor instruction pipeline having a main line and a branch line; executing at least one wait cycle for at least one wait instruction in said pipeline; and advancing at least selected instructions, that are initially located subsequent to at least one wait instruction in said pipeline, through the pipeline during the at least one wait cycle.]]></description>
<pubDate>April 24, 2008</pubDate>
</item>

<item>
<title><![CDATA[APPARATUS, METHOD, SYSTEM AND EXECUTABLE MODULE FOR CONFIGURATION AND OPERATION OF ADAPTIVE INTEGRATED CIRCUITRY HAVINGF FIXED, APPLICATION SPECIFIC COMPUTATIONAL ELEMENTS]]></title>
<link>http://www.freepatentsonline.com/20080098203.html</link>
<description><![CDATA[The present invention concerns configuration of a new category of integrated circuitry for adaptive computing. The various embodiments provide an executable information module for an adaptive computing engine (ACE) integrated circuit and may include configuration information, operand data, and may also include routing and power control information. The ACE IC comprises a plurality of heterogeneous computational elements coupled to an interconnection network. The plurality of heterogeneous computational elements include corresponding computational elements having fixed and differing architectures, such as fixed architectures for different functions such as memory, addition, multiplication, complex multiplication, subtraction, configuration, reconfiguration, control, input, output, and field programmability. In response to configuration information, the interconnection network is operative to configure the plurality of heterogeneous computational elements for a plurality of different functional modes.]]></description>
<pubDate>April 24, 2008</pubDate>
</item>

<item>
<title><![CDATA[TWO DIMENSIONAL ADDRESSING OF A MATRIX-VECTOR REGISTER ARRAY]]></title>
<link>http://www.freepatentsonline.com/20080098200.html</link>
<description><![CDATA[A processor for processing matrix data. The processor includes M independent vector register files which are adapted to collectively store a matrix of L data elements. Each data element has B binary bits. The matrix has N rows and M columns, and L=N*M. Each column has K subcolumns. N≧2, M≧2, K≧2, and B≧1. Each row and each subcolumn is addressable. The processor does not duplicatively store the L data elements. The matrix includes a set of arrays such that each array is a row or subcolumn of the matrix. The processor may execute an instruction that performs an operation on a first array of the set of arrays, such that the operation is performed with selectivity with respect to the data elements of the first array.]]></description>
<pubDate>April 24, 2008</pubDate>
</item>

<item>
<title><![CDATA[Analyzing and transforming a computer program for executing on asymmetric multiprocessing systems]]></title>
<link>http://www.freepatentsonline.com/20080098208.html</link>
<description><![CDATA[A method is disclosed for transforming a portion of a computer program comprising a list of sequential instructions comprising control code and data processing code and a program separation indicator indicating a point where said sequential instructions may be divided to form separate sections that are capable of being separately executed and that each comprise different data processing code. The m method comprises the steps of: (i) analysing said portion of said program to determine if said sequential instructions can be divided at said point indicated by said program separation indicator and in response to determining that it can: (iia) providing data communication between said separate sections indicated by said program separation indicator, such that said separate sections can be decoupled from each other, such that at least one of said sections is capable of being separately executed by an execution mechanism that is separate from an execution mechanism executing another of said separate sections, said at least one of said sections being capable of generating data and communicating said data to at least one other of said separate sections; and in response to determining it can not: (iib) not performing step (iia). If step (iia) is not performed then a warning may be output, or the program may be amended so it can be separated at that point, or the program separation indicator may be removed and the sections that were to be separated merged.]]></description>
<pubDate>April 24, 2008</pubDate>
</item>

<item>
<title><![CDATA[Coupling a general purpose processor to an application specific instruction set processor]]></title>
<link>http://www.freepatentsonline.com/20080098202.html</link>
<description><![CDATA[Provides methods, systems and apparatus for coupling a general purpose processor (GPP) to an application specific instruction set processor (ASIP) in such a manner that the GPP can include execute instructions that do not normally comprise part of its instruction set architecture (ISA). The GPP is coupled to the ASIP via a coprocessor port such that instructions issued by the GPP to the port are conveyed to a novel pre-decoder module of the ASIP. The pre-decoder module translates the GPP instruction into operation codes for ASIP instructions to be executed in the ASIP or to an address in the ASIP instruction memory that identifies a start address for a plurality of ASIP instructions defining a complex application specific function. Once the ASIP has executed the instructions it shares the result of the execution with the GPP. In this way, the GPP takes advantage of the ASIP in its ability to more quickly execute an application specific program/procedure.]]></description>
<pubDate>April 24, 2008</pubDate>
</item>

<item>
<title><![CDATA[Plotting Device And Plotting Method]]></title>
<link>http://www.freepatentsonline.com/20080098206.html</link>
<description><![CDATA[A reference address generator receives UV coordinate values from a shader, converts the value into a reference address for referring to a texture, and refers to a texture map or an instruction map stored in a texture memory based upon the reference address. The value referred to by the texture map is supplied to an interpolation unit, and the value referred to by the instruction map is written into an instruction buffer. The interpolation unit performs a texture mapping process so as to generate color values corresponding to the UV coordinate values of the pixels and supply the color values to the shader via a data path. An instruction decoder reads out an instruction code retained in the instruction buffer, decodes the instruction code, and supplies a control signal for executing the decoded instruction to the shader.]]></description>
<pubDate>April 24, 2008</pubDate>
</item>

<item>
<title><![CDATA[PARALLEL DATA PROCESSING APPARATUS]]></title>
<link>http://www.freepatentsonline.com/20080098201.html</link>
<description><![CDATA[A data processing apparatus includes a plurality of processing elements arranged in a single instruction multiple data array. The apparatus is operable to process multiple instructions streams in parallel with one another.]]></description>
<pubDate>April 24, 2008</pubDate>
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</channel>
</rss>
