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Networked test system

April 24, 2008

An automatic test system that can be configured to perform any of a number of test processes. The test system contains multiple functional modules that are interconnected by a network. By using software to configure data flow between functional modules, combinations of modules can be made, thereby creating virtual instruments. As test requirements change, the test system can be reconfigured to contain other virtual instruments, eliminating or reducing the need to add instruments to meet changing test requirements. To ensure adequate performance of the test system, a proposed configuration may be simulated, and if a virtual instrument does not provide a required level of performance, the test system may be reconfigured.

Mechanism for concurrent testing of multiple embedded arrays

April 24, 2008

In one embodiment, an apparatus and method for concurrent testing of multiple embedded arrays is disclosed. In one embodiment, the apparatus comprises a built-in self test (BIST) engine coupled to a plurality of arrays having different sizes to generate test packets targeted to an array with the most entries among the plurality of arrays, a plurality of address space control logic each associated with an array of the plurality of arrays, the address space control logic to adjust a broadcast address of the test packets to match an address space of its associated array, and an array width independent concurrent response evaluator (AWIC-RE) coupled to the plurality of arrays. In addition, the AWIC-RE includes a plurality of response collectors each associated with an array of the plurality of arrays, the response collector to collect test data from its associated array and serially shift the test data out, and a response evaluator to receive the test data response streams from the plurality of response collectors and to compress the serial response streams after each read. Other embodiments are also described.

SYSTEM AND PROGRAM PRODUCT FOR ERROR RECOVERY WHILE DECODING CACHED COMPRESSED DATA

April 24, 2008

A system and program for decoding cached compressed data. Compressed data is received and decoded. An error is detected while decoding a first location in the compressed data. A reentry data set is accessed having a pointer to a second location in the compressed data following the first location and decoding information that enables decoding to start from the second location. The second location in the compressed data is accessed and the decoding information in the accessed reentry data set is used to continue decoding the compressed data from the second location.

HIGH SPEED ERROR CORRECTING SYSTEM

April 24, 2008

Disclosed is an error correcting system, which comprises: a demodulator, for receiving and demodulating data from the optical disc to generate input data; a data buffer, for storing the input data; an on the fly ECC decoder, for performing a PI error correction to the input data before the input data from the demodulator stored by the buffer; an ECC decoder, for performing an error correction on the input data in the data buffer to generate an error correction information and correcting the input data to transform it to corrected data; an non-linear EDC check device, for performing a non linear error detection on the input data to generate a first EDC result stored by the EDC memory; an EDC corrector, for adjusting the first EDC result according to the error correction information; wherein the ECC decoder first performs a PO error correction on the input data.

Multiplier product generation based on encoded data from addressable location

April 24, 2008

For one disclosed embodiment, an apparatus comprises first circuitry to output encoded data from an addressable location based at least in part on an address corresponding to a first number, wherein the encoded data is based at least in part on data that corresponds to the first number and that is encoded for partial product reduction, and second circuitry to generate a product based at least in part on the encoded data and on data corresponding to a second number. Other embodiments are also disclosed.

USING CLOCK GATING OR SIGNAL GATING TO PARTITION A DEVICE FOR FAULT ISOLATION AND DIAGNOSTIC DATA COLLECTION

April 24, 2008

In one aspect, an electronic device that has been partitioned into segments by using clock gating or signal gating is tested. One of the segments that is a source of a failure is identified. Diagnostic procedures are applied to the identified segment to determine a cause of the failure.

FORWARD DECISION AIDED NONLINEAR VITERBI DETECTOR

April 24, 2008

A system, apparatus, and method are provided for a nonlinear Viterbi detector that may be used in an iterative decoding system or any other system with multiple, interconnected detectors. At least one of the Viterbi detectors may estimate the digital information sequence in a received signal based on the signal itself and an estimate of the signal from another of the Viterbi detectors. The at least one Viterbi detector may calculate branch metrics for a subset of the branches in an associated trellis diagram by selecting branches that correspond to the output of the other Viterbi detector. Thus, the area and complexity of the at least one Viterbi detector may be reduced approximately two-fold or more.

USING SAM IN ERROR CORRECTING CODE ENCODER AND DECODER IMPLEMENTATIONS

April 24, 2008

SAM is a very attractive memory option for systems due to its higher speed and reduced area when compared to RAM. However it is generally not used in implementations of FECCs due to its limitation to sequential accesses. According to the present invention, Forward Error Correcting Code encoder and decoder structures are shown to allow the use of SAM in their memory designs. Thus SAM is utilized in FECC implementations to achieve better area efficiency for the same amount of memory as well as higher throughput for the hardware implementations.

Semiconductor IC and testing method thereof

April 24, 2008

According to the present invention, the outputs of the last scanning flip-flop circuits 12 included in scan chains 111 are compiled and compressed in an output compression circuit 112, a sum of the outputs from the scan chains 111 and an expected value written in an expected value storage circuit 113 from the outside are compared with each other in an expected value decision circuit 114, the sum being outputted from the output compression circuit 112, a pass/fail decision result obtained by the comparison can be outputted from an output terminal 116 of the expected value decision circuit 114 to the outside, and the decision result can be stored regardless of the reset of a system.

HIGH DENSITY HIGH RELIABILITY MEMORY MODULE WITH POWER GATING AND A FAULT TOLERANT ADDRESS AND COMMAND BUS

April 24, 2008

A high density high reliability memory module with power gating and a fault tolerant address and command bus. The memory module includes a rectangular printed circuit board having a first side and a second side, a length of between 149 and 153 millimeters and first and second ends having a width smaller than said length. The memory module also includes a first plurality of connector locations on the first side extending along a first edge of said board that extends the length of the board and a second plurality of connector locations on the second side extending on said first edge of said board. The memory module further includes a buffer device in communication with the circuit board for accessing up to four ranks of memory devices mounted on the first side and second side of the circuit board. In addition, a power savings means is included for causing all or a portion of the buffer device to be in an inactive mode in response to current activity at the memory module. The memory module also includes a locating key having its center positioned on said first edge and located between 82 mm and 86 mm from said first end of said card and located between 66 and 70 mm from said second end of said card.

N-dimensional iterative ECC method and apparatus with combined erasure - error information and re-read

April 24, 2008

In an iterative error correction method and apparatus for correcting errors in digital data read from a storage medium, re-reads are combined with the error correction procedure in a single error recovery procedure. The data read from the storage medium are represented as a multi-dimensional data structure, and the error recovery procedure is undertaken for each dimension of the data structure. In each dimension, an erasure map is generated that contains errors in the initial read of the data for that dimension, and the errors in the erasure map are deducted as they are corrected in subsequent re-reads. After a predetermined number of re-reads, or when no further errors exist, the error recovery procedure is ended.

Method For Determining Time to Failure of Submicron Metal Interconnects

April 24, 2008

The present disclosure is related to a method for determining time to failure characteristics of a microelectronics device. A test structure, being a parallel connection of a plurality of such on-chip interconnects, is provided. Measurements are performed on the test structure under test conditions for current density and temperature. The test structure is arranged such that failure of one of the on-chip interconnects within the parallel connection changes the test conditions for at least one of the other individual on-chip interconnects of the parallel connection. From these measurements, time to failure characteristics are determined, whereby the change in the test conditions is compensated for.

METHOD AND APPARATUS FOR ENCODING AND DECODING DATA

April 24, 2008

A method and apparatus for turbo coding and decoding is provided herein. During operation, a concatenated transport block (CTB) of length X is received and a forward error correction (FEC) block size K I is determined from a group of available non-contiguous FEC block sizes between K min and K max , and wherein K min ≦K I

SEMICONDUCTOR INTEGRATED CIRCUIT

April 24, 2008

The present invention provides a data transmission method capable of suppressing degradation in data rate while improving a bit error rate of transmission data, and transmitters and receivers employed in the data transmission method. On the transmitting side, a CRC bit is added to an input information bit sequence in block units. The information bit sequence subsequent to the addition of the CRC bit is modulated and transmitted to the receiving side. On the receiving side, the information bit sequence is received and demodulated. A CRC check for the post-demodulation information bit sequence is performed. When the above result of CRC check is found to be negative-acknowledged, a NACK signal is transmitted to the transmitting side. On the transmitting side, when the NACK signal transmitted from the receiving side is received after modulation/transmission of the information bit sequence, the information bit sequence subsequent to the addition of the CRC bit is systematically encoded to generate a first parity bit sequence. The first parity bit sequence is modulated and transmitted to the receiving side. On the receiving side, the first parity bit sequence is received and demodulated. The post-demodulation information bit sequence is subjected to error correction decoding using the demodulated first parity bit sequence.

Test apparatus and method for testing booting and shutdown process of computer system

April 24, 2008

A test apparatus for testing a booting and shutdown process of a computer system provided. The test apparatus includes a power control unit and a test control unit. The power control unit is for receiving AC power, and selectively outputting the AC power to a power supply end of the computer system. The test control unit outputs a power control signal to the power control unit, for controlling the power control unit to output the AC power to the power supply end. The test control unit then tests the booting and shutdown process of the computer system. The test control unit receives a test result data transferred from the computer system and determines whether the booting and shutdown process is correct.

SYSTEMS, METHODS, APPARATUS, AND COMPUTER PROGRAM PRODUCTS FOR PROVIDING FORWARD ERROR CORRECTION WITH LOW LATENCY

April 24, 2008

Systems, methods, apparatus and computer program products for providing forward error correction with low latency to live streams in networks are provided, including outputting source data at a rate less than the rate of a source stream, building a buffer, FEC decoding the source data; and outputting the packets at a rate equal to the rate of the source stream.

Performing diagnostic operations upon an asymmetric multiprocessor apparatus

April 24, 2008

An asymmetric multiprocessor apparatus 2 is provided in which respective slave diagnostic units 20, 22, 24 are associated with corresponding execution mechanisms 6, 8, 10 . A master diagnostic unit 26 tracks the migration of thread execution between the different execution mechanisms 6, 8, 10 so that the execution of a given thread can be followed by the diagnostic mechanisms 20, 22, 24, 26 and this information provided to the programmer. The execution mechanisms 6, 8, 10 can be diverse such as a general purpose processor 6 , a DMA unit 12 , a coprocessor, an VLIW processor, a digital signal processor 8 and a hardware accelerator 10 . The asymmetric multiprocessor apparatus 2 will also typically include an asymmetric memory hierarchy such as including two or more of a global memory, a shared memory 16 , a private memory 18 and a cache memory 14.

Irregular Systematic with Serial Concatenated Parity Codes

April 24, 2008

Systems and techniques for transmitting an Irregular Systematic with Serially Concatenated Parity (Ir-S-SCP) are described. The techniques include generating an outer code comprising a plurality of bits using systematic bits as input, repeating the plurality of bits of the outer code a pre-determined number of times to generate at least a first set of repeated bits and a second set of repeated bits, serializing the generated sets of repeated bits, wherein each generated set is serialized in parallel with another generated set, interleaving the generated sets of repeated bits, generating an inner code, the inner code generated in part based on the interleaved sets, puncturing the inner code to output parity bits, wherein the puncturing is non-uniform and the puncturing is based at least in part on an incremental redundancy scheme, and transmitting the parity bits, wherein the transmitted parity bits and the systematic bits comprise the Ir-S-SCP code.

System and Method for Verification and Generation of Timing Exceptions

April 24, 2008

The invention relates to a method for verifying one or more exceptions in a logic circuit comprising the steps of: a first step of providing an initial representation of a logic circuit; a second step of indicating at least one exception for the logic circuit; a third step of introducing one or more potential malfunctions of the logic circuit related to the one or more exceptions into the representation of the logic circuit to produce a modified representation of the logic circuit; a fourth step of determining whether functional behaviour of the modified representation of the logic circuit differs from functional behaviour of the first representation of the logic circuit; and a fifth step of reporting a result relating to the difference in the functional behaviour of the modified representation of the logic circuit from the functional behaviour of the initial representation of the logic circuit.

COMPUTER READABLE STORAGE MEDIUM FOR MIGRATABLE SERVICES

April 24, 2008

A migration framework provides for the migration of services in a cluster. A migratable target contains a list of servers in the cluster capable of hosting a migratable service. A migration manager can migrate the service between servers in the migratable target, and can activate an instance of the service on the selected host server. The migration manager ensures that only one active instance of the service exists in the cluster. A service stub can serve a user request on servers in the migration target, such as by order of preference, until the user request is served on the server hosting the active instance. A lease manager can assign a lease period to determine how long a server hosts an active instance.

Methods and apparatus for handling processing errors in a multi-processing system

April 24, 2008

Methods and apparatus are provided for: monitoring processor tasks and associated processor loads therefor that are allocated to be performed by respective sub-processing units associated with a main processing unit; detecting whether a processing error has occurred in a given one of the sub-processing units; re-allocating all of the processor tasks of the given sub-processing unit to one or more participating sub-processing units, including other sub-processing units associated with the main processing unit, based on the processor loads of the processor tasks of the given sub-processing unit and the processor loads of the participating sub-processing units; and at least one of: (i) shutting down, and (ii) re-booting the given sub-processing unit.

DATA TRANSMISSION APPARATUS AND METHOD

April 24, 2008

Provided are a data transmission apparatus and method which apply an appropriate coding rate according to significance of bits or bit groups included in uncompressed data and retransmit all or part of the data when a transmission error occurs in the data while the data is being transmitted over a wireless network. The data transmission apparatus includes a mode termination unit which determines a retransmission mode for an initial transmission packet which has a transmission error; a packet generation unit which generates a retransmission packet, which includes at least part of the initial transmission packet, according to the determined retransmission mode; and a communication unit which transmits the retransmission packet through a communication channel.

OUTER CODING METHODS FOR BROADCAST/MULTICAST CONTENT AND RELATED APPARATUS

April 24, 2008

Transmission techniques are provided that improve service continuity and reduce interruptions in delivery of content that can be caused by techniques that occur when the User Equipment (UE) moves from one cell to the other, or when the delivery of content changes from Point-to-Point (PTP) connection to a Point-to-Multipoint (PTM) connection in the same serving cell, and vice-versa. Such transmission techniques enable seamless delivery of content across cell borders and/or between different transmission schemes such as Point-to-Multipoint (PTM) and Point-to-Point (PTP). Mechanisms for adjusting different streams and for recovering content from each data block during such transitions are also provided so that data is not lost during a transition. In addition, mechanisms for realigning data during decoding at a receiving terminal are also provided.

METHOD, SYSTEM, AND PROGRAM FOR ERROR HANDLING IN A DUAL ADAPTOR SYSTEM WHERE ONE ADAPTOR IS A MASTER

April 24, 2008

Provided is a method, system, and program for processing Input/Output (I/O) requests to a storage network including at least one storage device and at least two adaptors, wherein each adaptor is capable of communicating I/O requests to the at least one storage device. An error is detected in a system including a first adaptor, wherein the first adaptor is capable of communicating on the network after the error is detected. In response to detecting the error, a master switch timer is started that is less than a system timeout period if the first adaptor is the master. An error recovery procedure in the system including the first adaptor would be initiated after the system timeout period has expired. An operation is initiated to designate another adaptor in the storage network as the master if the first adaptor is the master in response to detecting an expiration of the master switch timer.

PROGRAM DEBUG METHOD AND APPARATUS

April 24, 2008

The present invention provides for an apparatus employed to debug a program operating in a supplemental processor when the processor's registers are not readable directly by the debugging operation of a main processor. A program operating in main memory halts due to operational errors. The program code lines save to a cache. In the main processor, a pool of memory is reserved. A copy of the data from the nominally inaccessible supplementary processor registers also transfers to the reserved storage area for processing of the program needing debugging. After the program debugging is complete, a copy of the contents of the memory pool is restored to the memory of the target supplemental processor. A copy of the local store register state and remaining local store data returns to main memory.

USING NO-REFRESH DRAM IN ERROR CORRECTING CODE ENCODER AND DECODER IMPLEMENTATIONS

April 24, 2008

Embodiments of the present invention provide Forward Error Correcting Code encoders and decoder structures that use DRAM in their memory designs. DRAM is a very attractive memory options in many electronic systems due to the high memory density provided by DRAM. However, the DRAM is typically not included in ASIC or FPGA implementations of encoders and decoders due to complex refresh requirements of DRAM that are required to maintain data stored in DRAM and may interfere with user access to the memory space during refresh cycles. Embodiments of the present invention provide FECC encoder and decoder structures that are implemented using DRAM that do not require complex refresh operations to be performed on the DRAM to ensure data integrity. Accordingly, embodiments of the present invention maximize memory density without the added complexity of introduced by the refresh requirements of DRAM.

APPARATUS FOR RANDOM PARITY CHECK AND CORRECTION WITH BCH CODE

April 24, 2008

An apparatus for random parity check and correction with BCH code is provided, including a BCH parity check code encoder, a channel, a BCH parity check code decoder, and a static RAM (SRAM). The BCH parity check code encoder uses the BCH encoding to encode the parity check code in writing to flash memory. The channel is connected to the BCH parity check code encoder to compute the parity check code and the message polynomial into receiving data. The BCH parity check code decoder is connected to the channel for inputting the receiving data and using BCH decoding to compute the eigen value and error address. The SRAM is connected to the BCH parity check code decoder so as to read error address from static RAM, correct the data and restores the corrected data to the SRAM. Therefore, this achieves the object of random parity check and correction with BCH code.

REDUCED SIGNALING INTERFACE METHOD AND APPARATUS

April 24, 2008

This disclosure describes a reduced pin bus that can be used on integrated circuits or embedded cores within integrated circuits. The bus may be used for serial access to circuits where the availability of pins on ICs or terminals on cores is limited. The bus may be used for a variety of serial communication operations such as, but not limited to, serial communication related test, emulation, debug, and/or trace operations of an IC or core design. Other aspects of the disclosure include the use of reduced pin buses for emulation, debug, and trace operations and for functional operations. In a fifth aspect of the present disclosure, an interface select circuit, FIGS. 41 - 49 , provides for selectively using either the 5 signal interface of FIG. 41 or the 3 signal interface of FIG. 8.

METHOD, SYSTEM, AND PROGRAM FOR ERROR HANDLING IN A DUAL ADAPTOR SYSTEM WHERE ONE ADAPTOR IS A MASTER

April 24, 2008

ADAPTIVE RECOVERY FROM SYSTEM FAILURE FOR APPLICATION INSTANCES THAT GOVERN MESSAGE TRANSACTIONS

April 24, 2008

Mechanisms for adaptively entering and exiting recovery mode. When a message is received from a particular message transaction, the appropriate processing instance is loaded from persistent memory to system memory. The processing instance then determines from its own state information whether or not it is in recovery mode. This indication of recovery or normal mode may be set by a system-wide recovery detection module. If the processing instance determines that it is in normal mode, then the processing instance executes code appropriate for normal operation without needing to execute any recovery code at all. If, on the other hand, the processing instance determines that it is in recovery mode, then it executes recovery code. Once the recovery code has completed successfully, the processing instance may then cause its own normal mode.

Multiple Execution-Path System

April 24, 2008

A multiple execution-path flash system includes a main flash image with primary and secondary POST and Boot executable files. The secondary executables are offset from the primary executables by a predetermined offset address. If corrupted data is encountered during Boot, the exception handler sets an offset bit resulting in the predetermined offset address being added to the current instruction address. If corrupted data is encountered in the secondary executables, the offset bit is reset. An optional redundant flash image may also be used. A failure at the same relative address in the primary and secondary executables of the main flash image will cause the exception handler to transfer control to the redundant flash image. A subsequent failure at the same relative address in the primary and secondary executables of the redundant flash image will cause the redundant exception handler to transfer control back to the main flash image.

Detection and mitigation of temporary impairments in a communications channel

April 24, 2008

Systems and methods are disclosed for detecting temporary high level impairments, such as noise or interference, for example, in a communications channel, and subsequently, mitigating the deleterious effects of the dynamic impairments. In one embodiment, the method not only performs dynamic characterization of channel fidelity against impairments, but also uses this dynamic characterization of the channel fidelity to adapt the receiver processing and to affect an improvement in the performance of the receiver. For example, in this embodiment, the method increases the accuracy of the estimation of the transmitted information, or similarly, increases the probability of making the correct estimates of the transmitted information, even in the presence of temporary severe levels of impairment. The channel fidelity history may also be stored and catalogued for use in, for example, future optimization of the transmit waveform.

METHOD AND APPARATUS FOR ACKCH WITH REPETITION IN ORTHOGONAL SYSTEMS

April 24, 2008

A method and apparatus for a wireless communication system, using a repetition factor to determine how many times a acknowledgement should be repeated in response to receiving a first data transmission, selecting an acknowledgement transmission (ACK TX) pattern, wherein the ACK TX pattern comprises of resources information of a plurality of blocks used for transmitting the first acknowledgement, and transmitting, repeatedly, the acknowledgement according to the ACK TX pattern.

System and Method for Analyzing HTTP Sessions

April 24, 2008

Software intended to operate in a clustered environment can be tested for appropriate failover behavior through the use of an automated tool which allows failover to be simulated without requiring that the application be deployed in a cluster environment and observing the effects of actual failover. Such an automated tool can measure the characteristics of one or more session objects created by the application and provide appropriate messages for a developer when those characteristics indicate improper coding for failover.

Net-Layer Parsing and Resynchronization

April 24, 2008

A system, apparatus and method to provide NET layer parsing and resynchronization in a physically segmented downhole network are described herein.

METHOD AND SYSTEM FOR PHYSICAL LAYER AGGREGATION

April 24, 2008

Aspects of a system for physical layer aggregation may include one or more switch ICs and/or physical (PHY) layer ICs that enable reception of data packets via a medium access control (MAC) layer protocol entity. Each of the received data packets may be fragmented into a plurality of fragment payloads. Each of the plurality of fragment payloads may be sent to a PHY layer protocol entity instance a physical layer protocol entity instance selected from a plurality of physical layer protocol entity instances.

Defect Management for Storage Media

April 24, 2008

A write recovery strategy for optical recorders, whereby one good or certified disc extent is searched for once the disc is first loaded. The certified disc extent is reserved and is used as space to rewrite data for which initial writing attempts were unsuccessful. The reserved areas is used for write recovery at times of at the start, real-time AV data will not be lost and recording performance is improved. A series of lists are maintained including a reserved list of extents that are certified as being free of defects and lists for free and written areas of the disc. The defect list used is updated by the defect management scheme so that it is always up-to-date.

System and Method for Embedded Java Memory Footprint Performance Improvement

April 24, 2008

A system and method are provided to allow demand loading and discarding of Java executable image (JXE) files. The virtual machine allocates an address space for a requested JXE program. The read-only portion of the JXE file is memory mapped from its nonvolatile location to the allocated memory space using read-only mapping and the read/write section of the JXE file are loaded into memory. When a page of the JXE program is needed, a page fault occurs if the read-only portion has not been loaded into memory. The operating system's page fault handler retrieves the needed page(s) from the nonvolatile storage location based upon the mapping data that resulted from the previously performed memory mapping. Because the read-only section of the JXE file is memory mapped using read-only mapping, the operating system's paging process is free to discard previously loaded memory pages that contain read-only portions of the JXE file.

Computer platform management unit operating mode arbitration method and system

April 24, 2008

A computer platform management unit operating mode arbitration method and system is proposed, which is designed for use with a computer platform having multiple management units, such as a blade server, and which is characterized by the utilization of a network interface for message exchanges between the management units, and the utilization of a random timer to set a waiting time length for local management unit to wait for a response from neighboring management unit that tells whether its current operating mode is active mode or standby mode. If no response is received, the local management unit is set to active mode; otherwise, it is set to an operating mode other than the current operating mode of the neighboring management unit. This feature allows the mechanism of operating mode arbitration on the blade server to be more simplified such that the implementation thereof is more cost-effective.

COMMUNICATION MANAGEMENT APPARATUS AND COMMUNICATION MANAGEMENT METHOD

April 24, 2008

A transmitting/receiving unit receives a SIP signal after occurrence of trouble in a SIP server and outputs a call ID of the SIP signal to a recovery-file searching unit. A session control unit once again procures a call process resource and an instance for a session corresponding to a recovery file and stores the call process resource data and the instance data in a main storage unit. The main storage unit stores anew session data included in the recovery file. A recovery-file creating unit creates the recovery file. An external storage unit stores therein the recovery file. The recovery-file searching unit retrieves from the external storage unit the recovery file that matches with the call ID output by the transmitting/receiving unit and outputs the recovery file to the session control unit and the main storage unit.