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<title>freepatentsonline.com: Error detection/correction and fault detection/recovery</title>
<link>http://www.freepatentsonline.com/result.html?query_txt=ccl/714%20and%20isd/11/05/2009&amp;usapp=on</link>
<description>USPTO Class 714 Error detection/correction and fault detection/recovery</description>
<language>en-us</language>
<lastBuildDate>Thu, 05 Nov 2009 03:35:44 EST</lastBuildDate>

<item>
<title><![CDATA[Hybrid ARQ Transmission Method With Channel State Information]]></title>
<link>http://www.freepatentsonline.com/y2009/0276679.html</link>
<description><![CDATA[A method for decoding of multiple wireless signals by a chase combining hybrid-automatic-repeat-request CC-HARQ receiver includes demodulating wireless signals received from respective mobile sources using an effective channel matrix and decision statistics; updating log-likelihood-ratios LLRs and decoding the received codewords using the corresponding updated LLRs; determining set of correctly decoded codewords using a cyclic redundancy check; updating the effective channel matrix and decision statistics responsive to the step of determining; and resetting the effective channel matrix and decision statistics in the event that the number of decoding errors for a codeword exceeds its maximum limit after storing the updated LLRs of all remaining erroneously decoded codewords for which the number of decoding errors is below the respective maximum limit.]]></description>
<pubDate>Thu, 05 Nov 2009 08:00:00 EST</pubDate>
</item>

<item>
<title><![CDATA[Method for detecting errors during initialization of an electronic appliance and apparatus therefor]]></title>
<link>http://www.freepatentsonline.com/y2009/0276655.html</link>
<description><![CDATA[The invention concerns a method for detecting problems arising during the launching phase of a resident software of an electronic appliance to be detected. Said detection is carried out by means of data written in the non-volatile memory during said phase. Said data are then erased in case of success. In case of failure, it is then possible, upon the next restart, to use said data to detect the problem.]]></description>
<pubDate>Thu, 05 Nov 2009 08:00:00 EST</pubDate>
</item>

<item>
<title><![CDATA[STORAGE SYSTEM CREATING A RECOVERY REQUEST POINT ENABLING EXECUTION OF A RECOVERY]]></title>
<link>http://www.freepatentsonline.com/y2009/0276661.html</link>
<description><![CDATA[A switch connected to a network system including a computer and a storage apparatus: controlling read/write request from the computer to the storage apparatus and controlling to store journal data in the storage apparatus; wherein the storage apparatus includes a first storage area for storing data to be used by the computer and a second storage area for storing journal data including write data and first update log information corresponding to the write data when there is a write request from the computer for writing data in the first storage area; wherein when the switch detects an event of status change related to the network system, the switch marks a first point of time corresponding to the event as a recovery request point, and creates second update log information corresponding to the recovery request point.]]></description>
<pubDate>Thu, 05 Nov 2009 08:00:00 EST</pubDate>
</item>

<item>
<title><![CDATA[METHODS AND SYSTEMS FOR OPTIMIZING HARQ COMMUNICATION]]></title>
<link>http://www.freepatentsonline.com/y2009/0276673.html</link>
<description><![CDATA[A method and apparatus for optimizing communication in a communication system is provided. The method includes transmitting a plurality of data packets including a first data packet, storing at least one of the plurality of data packets in a first buffer when the first data packet includes an error, determining a remaining storage capacity of the first buffer based on an initial storage capacity of the first buffer and a storage capacity used to store the at least one of the plurality of data packets, and retransmitting the first data packet with additional data, wherein an amount of the additional data is included in the retransmission based on the remaining storage capacity.]]></description>
<pubDate>Thu, 05 Nov 2009 08:00:00 EST</pubDate>
</item>

<item>
<title><![CDATA[APPARATUS AND METHOD FOR CONTROLLING A HYBRID AUTOMATIC REPEAT REQUEST OPERATION IN A WIRELESS MOBILE COMMUNICATION SYSTEM]]></title>
<link>http://www.freepatentsonline.com/y2009/0276676.html</link>
<description><![CDATA[An apparatus and method for controlling a Hybrid Automatic Repeat reQuest (HARQ) operation in a transmitter of a wireless mobile communication system using each frame constituted by a plurality of subframes are provided. In the method for controlling an HARQ operation, indication information indicating a subframe position where transmission of a data burst starts and the number of subframes required for transmission of the data burst is transmitted to a receiver through an i-th frame. When the number of subframes does not exceed a threshold, it is determined that the data burst at the subframe position indicated by indication information of an (i+1)-th frame is retransmitted to the receiver. When the number of subframes exceeds the threshold, it is determined that the data burst at the subframe position indicated by indication information of an (i+n)-th frame, where n is a positive integer exceeding 1, is retransmitted to the receiver.]]></description>
<pubDate>Thu, 05 Nov 2009 08:00:00 EST</pubDate>
</item>

<item>
<title><![CDATA[DATA DECODING APPARATUS, MAGNETIC DISK APPARATUS, AND DATA DECODING METHOD]]></title>
<link>http://www.freepatentsonline.com/y2009/0276685.html</link>
<description><![CDATA[A data decoding apparatus has: a check matrix including a submatrix which indicates a parity restriction and used for LDPC decoding; a first decoding module configured to decode data by using the submatrix so that the parity restriction is satisfied; and a second decoding module configured to LDPC-decode the decoded data by using the check matrix.]]></description>
<pubDate>Thu, 05 Nov 2009 08:00:00 EST</pubDate>
</item>

<item>
<title><![CDATA[METHOD OF ENCODING AND DECODING MULTI-BIT LEVEL DATA]]></title>
<link>http://www.freepatentsonline.com/y2009/0276687.html</link>
<description><![CDATA[A method of encoding multi-bit level data includes: determining a range of an error pattern generated according to a transmission symbol, encoding an M-bit level of a P-bit level corresponding to the transmission symbol based on the range of the error pattern, and excluding encoding of a P-M bit level of the P-bit level. The variable P is a natural number of a value at least two, and the variable M is a natural number less than P.]]></description>
<pubDate>Thu, 05 Nov 2009 08:00:00 EST</pubDate>
</item>

<item>
<title><![CDATA[DATA CONVERTER, INFORMATION RECORDER, AND ERROR DETECTOR]]></title>
<link>http://www.freepatentsonline.com/y2009/0276688.html</link>
<description><![CDATA[A data converter includes: an input module to which a first data series is input, the first data series having a first data sequence and a first error detection code corresponding to a remainder of division of the first data sequence by a predetermined polynomial; a conversion module converting the first data sequence into a second data sequence by processing including one of insertion, exchange, and inversion of a bit or a bit sequence, and exclusive-OR with a predetermined bit or bit sequence; a processing bit sequence generation module generating a processing bit sequence corresponding to the processing; and a code generation module generating a second error detection code corresponding to the second data sequence based on an exclusive-OR of the generated processing bit sequence and the first error detection code.]]></description>
<pubDate>Thu, 05 Nov 2009 08:00:00 EST</pubDate>
</item>

<item>
<title><![CDATA[METHODS AND APPARATUS FOR TRANSMITTING/RECEIVING DATA IN A COMMUNICATION SYSTEM]]></title>
<link>http://www.freepatentsonline.com/y2009/0276671.html</link>
<description><![CDATA[A method of error control, including forming a plurality of first data symbols from a plurality of data bits, transmitting a first signal including the plurality of first data symbols, receiving a request for retransmission, forming a plurality of second data symbols from the plurality of data bits, and transmitting a second signal including the plurality of second data symbols. At least one of the first data symbols is formed from several of the plurality of data bits such that none of the second data symbols is formed from the several of the plurality of data bits.]]></description>
<pubDate>Thu, 05 Nov 2009 08:00:00 EST</pubDate>
</item>

<item>
<title><![CDATA[SYSTEMS AND METHODS FOR IMPLEMENTING FAULT TOLERANT DATA PROCESSING SERVICES]]></title>
<link>http://www.freepatentsonline.com/y2009/0276654.html</link>
<description><![CDATA[Systems and methods are provided to implement fault tolerant data processing services based on active replication and, in particular, systems and methods for implementing actively replicated, fault tolerant database systems in which database servers and data storage servers are run as isolated processes co-located within the same replicated fault tolerant context to provide increased database performance.]]></description>
<pubDate>Thu, 05 Nov 2009 08:00:00 EST</pubDate>
</item>

<item>
<title><![CDATA[Method and apparatus for handling failure in address line]]></title>
<link>http://www.freepatentsonline.com/y2009/0276659.html</link>
<description><![CDATA[An address line failure handling apparatus includes a failed address line specifying unit that examines the address line connected to each bit and specifies a failed address line, an address line substituting unit in which an upper address line connected to an upper bit of the memory is connected with a branch address line branched off from a lower address line connected to a lower bit other than the upper bit, and that switches between an input from the upper address line and an input from the branch address line, and outputs any of the inputs to the upper bit, and an address line substitution instructing unit that instructs the address line substituting unit to switch from the upper address line to the branch address line branched off from the failed address line when the failed address line is specified.]]></description>
<pubDate>Thu, 05 Nov 2009 08:00:00 EST</pubDate>
</item>

<item>
<title><![CDATA[SERVER COMPUTER COMPONENT]]></title>
<link>http://www.freepatentsonline.com/y2009/0276660.html</link>
<description><![CDATA[Processing means for assisting computer programs running in a distributed computer system, the processing means including: detection means ( 530 ) for detecting that a running program ( 510 ) has encountered a problem caused by not having direct access to another piece of code; requisition means ( 530 ) for obtaining the other piece of code from another part of the system ( 550, 560 ); and means for controlling the computer to re-run the program from a point before the problem was encountered, in such a way that it has the necessary direct access to the other piece of code.]]></description>
<pubDate>Thu, 05 Nov 2009 08:00:00 EST</pubDate>
</item>

<item>
<title><![CDATA[Method and arrangement for optimizing test case execution]]></title>
<link>http://www.freepatentsonline.com/y2009/0276663.html</link>
<description><![CDATA[The present invention is a method for optimizing execution of plurality of test cases in a system under test. The method is characterized in that a first set of test cases comprising at least one test case to represent at least one second set of test cases is selected. Then an optimal value for a test execution parameter using data obtained from execution of the first set of test cases is determined. Finally, based on the result of the execution of the first set of test cases, an optimized value of at least one parameter related to execution of the at least one second test case is determined.]]></description>
<pubDate>Thu, 05 Nov 2009 08:00:00 EST</pubDate>
</item>

<item>
<title><![CDATA[APPARATUS, SYSTEM, AND METHOD OF EFFICIENTLY UTILIZING HARDWARE RESOURCES FOR A SOFTWARE TEST]]></title>
<link>http://www.freepatentsonline.com/y2009/0276665.html</link>
<description><![CDATA[Apparatus, system and method of efficiently utilizing hardware resources for a software test in system having at least one redundant component, at least a part of which is used for the software test.]]></description>
<pubDate>Thu, 05 Nov 2009 08:00:00 EST</pubDate>
</item>

<item>
<title><![CDATA[SYSTEM, METHOD, AND ADAPTER FOR CREATING FAULT-TOLERANT COMMUNICATION BUSSES FROM STANDARD COMPONENTS]]></title>
<link>http://www.freepatentsonline.com/y2009/0276666.html</link>
<description><![CDATA[A system, method, and adapter for creating fault-tolerant communication busses from standard components, are described. Fault-tolerant interface logic is provided for transmitting and receiving system health and system management signals to and from a module that is designed to be connected to a single RS-485 bus. The fault-tolerant interface logic enables the module to selectively communicate via at least two redundant half-duplex, multipoint, differential RS-485 busses. The fault-tolerant interface logic includes a first RS-485 transceiver connected to a first RS-485 bus, a second RS-485 transceiver connected to a second RS-485 bus, selector logic responsive to a control signal for selecting one of the first and the second busses to receive signals from and for transmitting the received signals to the module, and software logic executable on a baseboard management controller (BMC) chip. The software logic includes control logic for monitoring the health of the selected bus and for providing the control signal to the selector logic.]]></description>
<pubDate>Thu, 05 Nov 2009 08:00:00 EST</pubDate>
</item>

<item>
<title><![CDATA[SCAN DRIVER]]></title>
<link>http://www.freepatentsonline.com/y2009/0276668.html</link>
<description><![CDATA[A scan driver includes a voltage setting circuit, a counter circuit, a logic circuit, a dynamic decoder, N level shift circuits and N output stage circuits, wherein N is a natural number. The voltage setting circuit sets N voltage signals to a first level. The counter circuit provides count data to the logic circuit, which generates M control signals according to the count data, wherein M is a natural number. The dynamic decoder includes multiple transistors, arranged in N rows, for receiving the respective N voltage signals. The transistors are further arranged in M columns and are controlled by the respective M control signals to determine levels of the N voltage signals. The N level shift circuits lift the levels of the respective N voltage signals, and the N output stage circuits output respective N gate signals based on the N voltage signals whose levels are shifted.]]></description>
<pubDate>Thu, 05 Nov 2009 08:00:00 EST</pubDate>
</item>

<item>
<title><![CDATA[RECEPTION APPARATUS, RECEPTION METHOD, AND PROGRAM]]></title>
<link>http://www.freepatentsonline.com/y2009/0276670.html</link>
<description><![CDATA[A reception apparatus that receives a signal, including, a correction section, an error detection section, a filtering section, and a setting section is provided.]]></description>
<pubDate>Thu, 05 Nov 2009 08:00:00 EST</pubDate>
</item>

<item>
<title><![CDATA[REPETITIVE TRANSMISSIONS IN MULTI-CARRIER BASED WIRELESS ACCESS TECHNIQUES]]></title>
<link>http://www.freepatentsonline.com/y2009/0276672.html</link>
<description><![CDATA[Repetitive transmissions in multi-carrier based wireless access techniques may be achieved by providing multiple cyclic delay values for a plurality of carriers, performing a cyclic delay procedure using the multiple cyclic delay values according to the number of repetitive transmission of data symbols to be transmitted to a receiver, and transmitting the cyclic delayed data symbols to the receiver using the plurality of carriers.]]></description>
<pubDate>Thu, 05 Nov 2009 08:00:00 EST</pubDate>
</item>

<item>
<title><![CDATA[DATA TRANSMISSION SYSTEM, PROGRAM AND METHOD]]></title>
<link>http://www.freepatentsonline.com/y2009/0276678.html</link>
<description><![CDATA[A data transmission system includes a packet missing state data storage unit that stores packet missing state data including distribution of the numbers of consecutive missed packets in a decoder and distribution of intervals of the packet missing in the decoder; an interleave unit determination processing unit that determines, based on the distribution of the numbers of consecutive missed packets, an interleave unit that represents the number of Forward Error Correction (FEC) blocks, wherein the FEC block is a unit for which an FEC packet is generated; an FEC block determination processing unit that determines, based on the distribution of the intervals of the packet missing, the number of data packets included in the FEC block; and a packet communication processing unit that identifies, based on the determined interleave pattern data, a transmission order of the packets to the decoder.]]></description>
<pubDate>Thu, 05 Nov 2009 08:00:00 EST</pubDate>
</item>

<item>
<title><![CDATA[ERROR CORRECTION CIRCUIT AND METHOD THEREOF]]></title>
<link>http://www.freepatentsonline.com/y2009/0276680.html</link>
<description><![CDATA[An error correction method is applicable for accessing a data in a storage medium. The method includes the steps of: encoding a portion of the data and the whole data to produce a partial data parity for that portion of the data and a whole data parity for the whole data; using the partial data parity to decode the corresponding portion of the data and the corresponding partial data parity in order to correct error bits from the corresponding portion of the data and from the partial data parity according to the decoded result; using the whole data parity to decode the whole data and the whole data parity in order to correct the error bit from the whole data and the whole data parity according to the decoded result; and outputting the corrected data.]]></description>
<pubDate>Thu, 05 Nov 2009 08:00:00 EST</pubDate>
</item>

<item>
<title><![CDATA[Upgraded Codeword Lock State Machine]]></title>
<link>http://www.freepatentsonline.com/y2009/0276681.html</link>
<description><![CDATA[An apparatus comprising a Forward Error Correction (FEC) processor coupled to an optical receiver, wherein the FEC processor is configured to compare a plurality of received blocks to a plurality of FEC codeword blocks comprising a plurality of parity blocks, and upon detecting a misaligned block in the received blocks, compare at least some of the remaining received blocks to the parity blocks. Also included is an apparatus comprising at least one component configured to implement a method comprising receiving a plurality of blocks, wherein the quantity of received blocks is equal to a quantity of blocks in a FEC codeword, selecting one of the received blocks, determining whether the selected block is aligned with the FEC codeword, and determining whether the remaining blocks correspond to the FEC codeword when the selected block is not aligned with the FEC codeword.]]></description>
<pubDate>Thu, 05 Nov 2009 08:00:00 EST</pubDate>
</item>

<item>
<title><![CDATA[TURBO LDPC DECODING]]></title>
<link>http://www.freepatentsonline.com/y2009/0276682.html</link>
<description><![CDATA[An iterative low-density parity-check (LDPC) decoding system comprises a first shift register for storing bit estimates, a plurality of parity-check processing node banks configured for processing the bit estimates for generating messages, combiners configured for combining the messages with the bit estimates for generating updated bit estimates, and fixed permuters for permuting the updated bit estimates to facilitate storage and access of the bit estimates. A second shift register is provided for storing the messages, and a subtraction module subtracts messages generated a predetermined number of cycles earlier from the updated bit estimates.]]></description>
<pubDate>Thu, 05 Nov 2009 08:00:00 EST</pubDate>
</item>

<item>
<title><![CDATA[MULTI-ANTENNA CONFIGURATION SIGNALING IN WIRELESS COMMUNICATION SYSTEM]]></title>
<link>http://www.freepatentsonline.com/y2009/0276684.html</link>
<description><![CDATA[A wireless communication infrastructure entity ( 200 ) having a communication configuration is configured to generate parity bits based on an information word and to encode the parity bits based on the communication configuration of the wireless communication infrastructure entity, wherein the encoded parity bits are combined with the information word. A wireless communication user terminal is configured to identify a set of configuration indicator bits used to encode parity bits combined with an information word and to determine a communication configuration of the wireless communication entity from which the combination of the information word and the encoded parity bits were received based on the set of configuration indicator bits used to encode the parity bits.]]></description>
<pubDate>Thu, 05 Nov 2009 08:00:00 EST</pubDate>
</item>

<item>
<title><![CDATA[METHOD TO SUPPORT FORWARD ERROR CORRECTION FOR REAL-TIME AUDIO AND VIDEO DATA OVER INTERNET PROTOCOL NETWORKS]]></title>
<link>http://www.freepatentsonline.com/y2009/0276686.html</link>
<description><![CDATA[A method and apparatus are described for protecting real time media including receiving media packets, generating media bit strings from the media packets, applying a forward error correcting code across the generated media bit strings to generate at least one forward error correcting bit string and generating at least one forward error correcting packet from the at least one forward error correcting bit string. Also described are a method and apparatus for recovering from losses of real time media packets including forming media bit strings from received media packets, forming forward error correcting bit strings from received forward error correcting packets, decoding the formed media bit strings and forward error correcting bit strings to obtain recovered media bit strings and recover lost media packets from the recovered media bit strings. Further described is a data structure for a forward error correcting header on computer readable media.]]></description>
<pubDate>Thu, 05 Nov 2009 08:00:00 EST</pubDate>
</item>

<item>
<title><![CDATA[Using short burst error detector in a queue-based system]]></title>
<link>http://www.freepatentsonline.com/y2009/0276689.html</link>
<description><![CDATA[A system, method, and device for detecting short burst errors in a queue-based system is disclosed. A first detector performs a data detection on a first input data set at a first time and on a second input data set at a second time. A second detector performs a data re-detection on input data sets. A decoder decodes derivations of the outputs of the first and second detector. A short burst error detector may perform a short burst error detection on decoded data and erase any detected errors. An output data buffer stores and orders the decoded data for output.]]></description>
<pubDate>Thu, 05 Nov 2009 08:00:00 EST</pubDate>
</item>

<item>
<title><![CDATA[METHOD AND APPARATUS FOR MONITORING BIT-ERROR RATE]]></title>
<link>http://www.freepatentsonline.com/y2009/0276664.html</link>
<description><![CDATA[A test set for evaluating network performance is described, and which may include an output device, a processor, a power supply, a memory unit, and a control terminal. The test set may be configured to receive a user-entered selection of one of a plurality of different bit-error rate profiles and generate a test signal exhibiting the selected bit-error rate profile. The test set may also supply the test signal exhibiting the selected bit-error rate profile to a network under test. In addition, the test set may receive as an input, an output from the network under test. The output may include the test signal exhibiting the selected bit-error rate. The test set may evaluate the received test signal and determine the performance of the network in response to the received test signal exhibiting the bit-error rate. The test set may then output the results of the evaluation.]]></description>
<pubDate>Thu, 05 Nov 2009 08:00:00 EST</pubDate>
</item>

<item>
<title><![CDATA[SIGNALING OF REDUNDANCY VERSION AND NEW DATA INDICATION]]></title>
<link>http://www.freepatentsonline.com/y2009/0276675.html</link>
<description><![CDATA[Example methods and apparatus for communicating encoded data blocks in wireless communication systems are disclosed. In one example embodiment, a method for receiving an encoded data block includes receiving a data transmission including a subset of a plurality of bits of the encoded data block. The example method also includes receiving a first control signal indicating whether the received subset is a first received subset associated with the encoded data block or whether one or more subsets were previously received for the encoded data block. The example method also further includes receiving a second control signal, the second control signal having a first state and a second state. In the example method, the first state of the second control signal indicates that the received subset includes a first predefined subset of the plurality of bits of the encoded data block and the second state of the second control signal indicates that the received subset includes one of a plurality of other predefined subsets of the plurality of bits of the encoded data block. In this example embodiment, determining which of the other predefined subsets is included in the received subset is based on one or more system parameters of the wireless communication system. Further in this example, the state of the second control signal is selectable between its first state and its second state on a data transmission by data transmission basis, regardless of whether or not one or more subsets of the encoded data block were previously received.]]></description>
<pubDate>Thu, 05 Nov 2009 08:00:00 EST</pubDate>
</item>

<item>
<title><![CDATA[Radio Communications Device And Reception Method]]></title>
<link>http://www.freepatentsonline.com/y2009/0276677.html</link>
<description><![CDATA[A radio communications device includes a first error detection part configured to perform error detection on a header included in a packet; a determination part configured to determine whether there is consistency with respect to the length of the packet based on the header in response to the first error detection part detecting no error in the header; a decryption part configured to decrypt the packet in response to the determination part determining that there is consistency with respect to the length of the packet; and a second error detection part configured to perform error detection on the packet in response to the determination part determining that there is consistency with respect to the length of the packet, wherein the decryption part is configured to start to decrypt the packet before completion of the error detection by the second error detection part.]]></description>
<pubDate>Thu, 05 Nov 2009 08:00:00 EST</pubDate>
</item>

<item>
<title><![CDATA[Method for processing and redirecting misdirected advanced shipping notices (ASNs)]]></title>
<link>http://www.freepatentsonline.com/y2009/0276669.html</link>
<description><![CDATA[A method is disclosed for correcting misdirected Advanced Shipping Notices (ASNs). In one embodiment, the method receives, from a product supplier, a first set of data associated with an ASN, where the first set of data includes an ASN receiving facility identifier. The method also determines a Purchase Order (PO) that is associated with the ASN, where the PO includes a second set of data. The method further compares one or more fields of the first set of data with one or more fields of the second set of data. In addition, the method determines if the ASN was misdirected based on the comparison, and corrects the ASN, when it is determined that the ASN was misdirected.]]></description>
<pubDate>Thu, 05 Nov 2009 08:00:00 EST</pubDate>
</item>

<item>
<title><![CDATA[DISTRIBUTION METHOD, PREFERABLY APPLIED IN A STREAMING SYSTEM]]></title>
<link>http://www.freepatentsonline.com/y2009/0276536.html</link>
<description><![CDATA[The invention relates to a data live streaming system comprising at least one data live streaming broadcaster LSB and at least two live streaming recipients LSR, said at least two live streaming recipients LSR forming at least a part of a peer-to-peer streaming network and said at least two live streaming recipients LSR each comprising means for generation of peer-to peer streaming to other live streaming recipients LSR of said peer-to peer streaming network and wherein said peer-to peer streaming to other streaming recipients LSR comprises loss resilient code representations of data from said at least one live streaming broadcaster LSB.]]></description>
<pubDate>Thu, 05 Nov 2009 08:00:00 EST</pubDate>
</item>

<item>
<title><![CDATA[STORAGE DEVICE AND RECOVERY METHOD]]></title>
<link>http://www.freepatentsonline.com/y2009/0276656.html</link>
<description><![CDATA[A storage device including a plurality of storage units for storing data dispersively among the storage units, includes: a processor for controlling boot-up of the storage units; and a memory for storing operation history indicative of the sequence of any failure causing any of the storage units to become inoperative, the processor controlling reboot-up of the storage units, when a plurality of the storage units becomes inoperative on account of a plurality of failures, in accordance with process including: determining the order of the reboot up of the storage units that is reversal of the sequence of the failures causing the storage units to become inoperative in reference to the operation history in the memory; rebooting the inoperative storage units successively in accordance with the determined order.]]></description>
<pubDate>Thu, 05 Nov 2009 08:00:00 EST</pubDate>
</item>

<item>
<title><![CDATA[MANAGING CLUSTER SPLIT-BRAIN IN DATACENTER SERVICE SITE FAILOVER]]></title>
<link>http://www.freepatentsonline.com/y2009/0276657.html</link>
<description><![CDATA[A central controlling service for datacenter activation/deactivation control in a cluster deployment to assist in preventing a split-brain scenario. The central controlling service provides a central point of control in the datacenter for application servers to periodically query as to whether to go offline, online, or normal. Redundancy of the central service facilitates detection of datacenter failure by the redundant services interacting to resolve the state of control information. This control information is then used to answer the server queries. On startup from a datacenter failure, a single instance of the central service queries other redundant instance(s) to determine if the single instance is starting up from a datacenter-wide failure or from operations other than total datacenter failure. If the failure is datacenter-wide, a central service protocol assists in resolving to the single service keeping the associated datacenter servers offline; otherwise, the server queries are answered to go online.]]></description>
<pubDate>Thu, 05 Nov 2009 08:00:00 EST</pubDate>
</item>

<item>
<title><![CDATA[JAVA VIRTUAL MACHINE HAVING INTEGRATED TRANSACTION MANAGEMENT SYSTEM]]></title>
<link>http://www.freepatentsonline.com/y2009/0276658.html</link>
<description><![CDATA[A computing system is configured to deploy a JAVA application for execution in a distributed manner. The computing system includes a plurality of computing nodes including a domain manager node, the plurality of computing nodes forming a computing domain configured as an administrative grouping of the nodes administered by the domain manager node. The domain manager node is configured to provide, to each of the computing nodes, a main portion of the JAVA application. The main portion defines, for each computing node, a portion of the behavior of the JAVA application to be accomplished by that computing node. Furthermore, each computing node is configured to receive at least one class file having classes appropriate for the portion of the behavior of the JAVA application defined, by the main portion, to be accomplished by that computing node.]]></description>
<pubDate>Thu, 05 Nov 2009 08:00:00 EST</pubDate>
</item>

<item>
<title><![CDATA[SYSTEM AND APPARATUS FOR PROVIDING AN ADAPTIVE CONTROL MECHANISM FOR WIRELESS COMMUNICATIONS]]></title>
<link>http://www.freepatentsonline.com/y2009/0276674.html</link>
<description><![CDATA[A system for providing an adaptive control mechanism may include a mobile station within a multicast broadcast service group and a base station in communication with the mobile station. The base station may be configured to control provision of data to the mobile station, receive feedback with respect to receipt of at least a portion of the data provided, and determine a configuration of the base station for future transmissions based on the feedback received. The mobile station may be configured to determine a status with respect to receipt of data expected to be received from the base station, generate the feedback indicative of the status determined, and provide for communication of the feedback generated to the base station.]]></description>
<pubDate>Thu, 05 Nov 2009 08:00:00 EST</pubDate>
</item>

<item>
<title><![CDATA[DATA TRANSMISSION EQUIPMENT AND GENERATING METHOD FOR TRANSMISSION CODE]]></title>
<link>http://www.freepatentsonline.com/y2009/0276683.html</link>
<description><![CDATA[A transmitter communicates with a receiver and an error corrector corrects bit errors generated during data transmission. The transmitter has a scrambler unit that scrambles data so that a running disparity of 0 and 1 in the input data is substantially zero. A bit-string converting unit  15  that adds bit data for ensuring a maximum run length of a serial bit string of the scrambled data and converts control information to bit data of a fixed value. A synchronization timing generating unit  16  divides the transmitted data by a constant interval and converts the transmission data to a data block. A bit-string converting unit extracts a fixed-value bit pattern of the control data from the bit string of the data block, converts the bit pattern to the control information, and discriminates the data and the control information. A descrambler unit reconverts the data-scrambled data to the data before scrambling.]]></description>
<pubDate>Thu, 05 Nov 2009 08:00:00 EST</pubDate>
</item>

<item>
<title><![CDATA[METHOD AND APPARATUS FOR CONTENTION-FREE INTERLEAVING USING A SINGLE MEMORY]]></title>
<link>http://www.freepatentsonline.com/y2009/0274248.html</link>
<description><![CDATA[A method and apparatus for contention free interleaving are disclosed. A single memory configured to use an address scheme wherein the most significant bits (MSBs) indicate which word in memory stores an interleaved piece of data. The least significant bits (LSBs) are used to calculate an index that identifies a specific soft-in/soft-out (SISO) decoder associated with a sub-word of the retrieved data. Using an interleaved address generator, the extrinsic data may be written into the memory in sequential order, but read out from the memory in interleaved order, effectively de-interleaving the data so it may be decoded. The generated interleaved address is used by SISO selector circuit which controls a multiplexer that routes the sub-word to its appropriate SISO decoder. The same address generator may be used to write interleaved extrinsic data from SISOs by reordering the sub-words, allowing the extrinsic data to be read in sequential order.]]></description>
<pubDate>Thu, 05 Nov 2009 08:00:00 EST</pubDate>
</item>

<item>
<title><![CDATA[DIGITAL BROADCAST TRANSMITTER AND RECEIVER AND METHOD FOR PROCESSING STREAM THEREOF]]></title>
<link>http://www.freepatentsonline.com/y2009/0274242.html</link>
<description><![CDATA[A digital broadcast receiver is provided. The digital broadcast receiver includes a receiver which receives a transport stream transmitted from a digital broadcast transmitter, an additional data stream detector which determines whether the received transport stream includes an additional data stream or not, and a processor which process the additional data stream if the transport stream include the additional data stream, and the transport stream including the additional data stream is a transport stream into which a training signal is inserted by the digital broadcast transmitter which resets memories used for trellis-encoding at predetermined time. Accordingly, it is easily detected whether the transport stream includes the additional data stream or not.]]></description>
<pubDate>Thu, 05 Nov 2009 08:00:00 EST</pubDate>
</item>

<item>
<title><![CDATA[Storage system, data processing method and storage apparatus]]></title>
<link>http://www.freepatentsonline.com/y2009/0276568.html</link>
<description><![CDATA[Proposed are a storage system, data processing method and storage apparatus capable of performing stable data I/O processing. Each of the storage apparatuses configured in the storage group stores group configuration information containing priority information given to each storage apparatus, and the storage apparatus with the highest priority becomes a master and performs virtualization processing and data I/O processing, and another storage apparatus belonging to this storage group performs internal processing of the storage group.]]></description>
<pubDate>Thu, 05 Nov 2009 08:00:00 EST</pubDate>
</item>

<item>
<title><![CDATA[Stored Memory Recovery System]]></title>
<link>http://www.freepatentsonline.com/y2009/0276662.html</link>
<description><![CDATA[Various embodiments of systems and methods for preserving saved memory states to which a computer system can be restored are disclosed. In certain embodiments, the systems and methods intercept write operations to protected memory locations and redirect them to alternate memory locations. Embodiments of the systems and methods include creation of a table for each memory state. Certain embodiments additionally include a recovery capability, by which the protected memory in the computer system is capable of being restored or recovered to a recovery point that represents a saved memory state. Further embodiments relate to systems and methods for preventing protected memory locations from being overwritten that utilize a plurality of memory state values.]]></description>
<pubDate>Thu, 05 Nov 2009 08:00:00 EST</pubDate>
</item>

<item>
<title><![CDATA[Session Broker Extensibility Application Program Interface]]></title>
<link>http://www.freepatentsonline.com/y2009/0276667.html</link>
<description><![CDATA[Described are techniques for providing an application program interface that leverages the terminal services session broker infrastructure to support third party plug-in applications. In a typical scenario, when a user requests for a connection to access third party plug-in applications, the application program interface may override the session broker logic and interacts with the session broker process to identify sessions or suitable servers to which the user can be connected. The user may access the third party plug-in applications through the identified sessions or suitable servers.]]></description>
<pubDate>Thu, 05 Nov 2009 08:00:00 EST</pubDate>
</item>

<item>
<title><![CDATA[METHOD AND APPARATUS FOR FACILITATING BUSINESS PROCESSES]]></title>
<link>http://www.freepatentsonline.com/y2009/0276624.html</link>
<description><![CDATA[A method and apparatus for facilitating a business process communication and managing business processes. First business process data is obtained from at least one first trading participant and processed at a process management platform configured to automatically determine second trading participants to satisfy the first business process data. A second protocol is identified for conducting business transactions used by the second trading participants. Second business process data is generated from the first business process data. The second business process data includes a set of transaction messages having a data format in accordance with the identified second protocol. The second business process data is transmitted from the process management platform to the second trading participants. The first and second trading participants conduct the business transactions in accordance with their respective protocols for conducting business transactions. The process management platform is configured to process at least one proprietary transaction definition format.]]></description>
<pubDate>Thu, 05 Nov 2009 08:00:00 EST</pubDate>
</item>

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