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Method of fabricating recess transistor in integrated circuit device and recess transistor in integrated circuit device fabricated by the same

April 29, 2008

Provided is a method of fabricating a recess transistor in an integrated circuit device. In the provided method, a device isolation region, which contacts to the sidewall of a gate trench and a substrate region remaining between the sidewall of the device isolation region and the sidewall of the gate trench, is etched to expose the remaining substrate region. Thereafter, the exposed portion of the remaining substrate region is removed to form a substantially flat bottom of the gate trench. The recess transistor manufactured by the provided method has the same channel length regardless of the locations of the recess transistor in an active region.

Surface-mount packaging for chip

April 29, 2008

A chip includes a plurality of pins; and a plurality of symbols defined on a surface of the chip, wherein the symbols are arranged as a graduated scale corresponding with the pins. It becomes very easy to find a initial pin from among the plurality of pins of the chip.

Semiconductor device

April 29, 2008

In a semiconductor device adapted to be mounted on a board and to be electrically connected to the board, comprising, at least two semiconductor electric chips, and a substrate on which the semiconductor electric chips are mounted and to which the semiconductor electric chips are electrically connected, in such a manner that the semiconductor electric chips are mounted on and electrically connected to the board through the substrate, according to the present invention, a thickness of each of the semiconductor electric chips in a direction in which the each of the semiconductor electric chips and the substrate are stacked is smaller than a thickness of the substrate in the direction.

Overhang integrated circuit package system

April 29, 2008

An integrated circuit package system is provided attaching a film to a die paddle, applying an adhesive to the film, and attaching an integrated circuit die over the adhesive and the film to the die paddle.

Heat radiation structure of semiconductor element and heat sink

April 29, 2008

According to a heat radiation structure of a semiconductor element of the invention, by providing a recess for a thermal conductive sheet on the bottom surface of a mounting seat of a heat sink, disposing the thermal conductive sheet in this recess, and screwing a source electrode of a power FET on the bottom surface of the mounting seat of the heat sink, it is possible to efficiently radiate the heat generated by the semiconductor element without damaging semiconductor chips in the interior of the semiconductor element and without deteriorating electrical properties.

High-frequency semiconductor device and method of manufacturing the same

April 29, 2008

The object of the present invention is to implement an enhancement in a noise eliminating characteristic of a wiring compatibly with promotion of microfabrication and simplification of a manufacturing process. Upper and side surfaces of a wiring ( 6 ) for transmitting a signal are continuously covered by a conductor layer ( 12 ) with insulators ( 7 ), ( 8 ) and ( 9 ) interposed therebetween in a section crossing a direction of extension thereof, and the conductor layer ( 12 ) is connected to a semiconductor substrate ( 1 ). Moreover, a periphery of a wiring ( 15 ) for transmitting a signal is continuously covered by the conductor layer ( 12 ) and a conductor layer ( 19 ) with insulators ( 14 ), ( 16 ), ( 17 ) and ( 18 ) interposed therebetween in a section crossing a direction of extension thereof. The wiring ( 15 ) is electrically connected to the semiconductor substrate ( 1 ) through a conductive plug ( 13 ) filled in a contact hole ( 24 ) formed in the conductor layer ( 12 ).

Method of wet etching vias and articles formed thereby

April 29, 2008

A method for forming smooth walled, prismatically-profiled through-wafer vias and articles formed through the method. An etch stop material is provided on a wafer, which may be a <110> silicon wafer. A mask material is provided on the etch stop material and patterned in such a way as to lead to the formation of vias that have at least one pair of opposing side walls that run parallel to a <111> plane in the wafer. A wet etchant, such as potassium hydroxide, is used to etch vias in the wafer. The use of a wet etchant leads to the formation of smooth side walls. This method allows an aspect ratio of height versus width of the vias of greater than 75 to 1.

Stackable semiconductor package

April 29, 2008

The present invention relates to a stackable semiconductor package, comprising a first substrate, a chip, a second substrate, a plurality of second wires, a plurality of supporting elements and a molding compound. The chip is disposed on and electrically connected to the first substrate. The second substrate is disposed above the chip, and the area of the second substrate is larger than that of the chip. The second substrate is electrically connected to the first substrate by the second wires. The supporting elements are disposed between the first substrate and the second substrate, and are used for supporting the second substrate. The molding compound encapsulates the first surface of the first substrate, the chip, the second wires, the supporting elements and part of the second substrate, and exposes a surface of the second substrate. The overhang portion of the second substrate will not shake or sway during wire bonding process.

Semiconductor device, semiconductor package for use therein, and manufacturing method thereof

April 29, 2008

A semiconductor package includes a substrate for mounting and fixing a semiconductor chip thereon and a connecting pattern. The substrate is provided with an elongate opening formed therein. The semiconductor chip is fixed with its surface being mounted on the substrate and with its electrode being aligned within the elongate opening. The electrode of the semiconductor chip is electrically connected to the connecting pattern via wires through the elongate opening. The elongate opening and the wires are sealed with resin.

Semiconductor device

April 29, 2008

The semiconductor device comprises a resistance element 26 formed of polysilicon film formed on a silicon substrate 10 , which includes a resistor part 26 a having a resistance value set at a prescribed value, contact parts 26 b formed on both sides of the resistor part 26 a and connected to a line for applying a fixed potential, and a heat radiation part 26 c connected to the contact part 26 b , whereby the semiconductor device can include the resistance element having a small parasitic capacitance and good heat radiation.

Memory cell having enhanced high-K dielectric

April 29, 2008

A semiconductor memory device may include an intergate dielectric layer of a high-K, high barrier height dielectric material interposed between a charge storage layer and a control gate. With this intergate high-K, high barrier height dielectric in place, the memory device may be efficiently erased using Fowler-Nordheim tunneling.

Semiconductor device and method of manufacturing the semiconductor device

April 29, 2008

A semiconductor device having improved reliability is provided. The semiconductor device has a pixel portion. The pixel portion has a TFT and a storage capacitor. The TFT and the storage capacitor has a semiconductor layer which includes first and second regions formed continuously. The TFT has the first region of the semiconductor layer including a channel forming region, a source region and a drain region located outside the channel forming region, a gate insulating film adjacent to the first region of the semiconductor layer, and a gate electrode formed on the gate insulating film. The storage capacitor has the second region of the semiconductor layer, an insulating film formed adjacent to the second region of the semiconductor layer, and a capacitor wiring formed on the insulating film. The second region of the semiconductor layer contains an impurity element for imparting n-type or p-type conductivity. The thickness of the insulating film adjacent to the second region of the semiconductor layer is thinner than that of the film on the region in which the TFT is formed.

Optical sensor with improved planarization

April 29, 2008

In a photodetector where a circuit section, in which an interconnection is formed, is formed adjacent to a light receiving section, photo sensitivity within a light receiving surface is prevented from being non-uniform due to an interlayer insulating film at a periphery of the light receiving section being increased in thickness. In a circuit region, a buffer region is disposed adjacent to a light receiving section. In the buffer region, in order to reduce irregularity of an interlayer insulating film, a density of planarizing pads disposed between the interconnections is gradually reduced from a standard value in a region as it approaches the light receiving section.

Semiconductor device having silicide reaction blocking region

April 29, 2008

A semiconductor device has a silicon substrate, an n-type well region formed in the silicon substrate, first and second source/drain regions constructed of a p-type diffusion layer formed on the n-type well region, a gate insulator formed in a region located between the first source/drain region and the second source/drain region and a polysilicon formed on the gate insulator. The semiconductor device has oxygen-rich layers for blocking a silicide reaction, which layers are formed in an uppermost portion of the silicon substrate on the side of the polysilicon, and has an oxygen-rich layer for blocking the silicide reaction, which layer is formed in an upper portion of the polysilicon.

Memory cell structure

April 29, 2008

An SRAM device includes an SRAM cell in a deep NWELL region in a substrate. PWELL regions in the SRAM cell occupy less than about 65% of the cell area of the SRAM cell. A ratio of a longer side of a cell area of the SRAM cell to a shorter side of the SRAM cell is larger than about 1.8. A total area of the active regions in the plurality of NMOS transistors in the SRAM cell occupies less than about 25% of the SRAM cell area. A ratio of the channel width of a pull up transistor in the SRAM cell to the channel width of a pull down transistor in the SRAM cell is greater than about 0.8. The SRAM cell further includes a boron free inter-layer-dielectric layer, an inter-metal-dielectric layer with dielectric constant less than about 3, and a polyimide layer with a thickness of less than about 20 microns.

Semiconductor device and fabrication method thereof

April 29, 2008

A semiconductor device includes a second insulating film formed on a second surface of a semiconductor substrate whose first surface has been formed with a first insulating film and an electrode pad, and an opening is made in a portion of the second insulating film directly below the electrode pad. By using the second insulating film as a mask, a through hole is formed in the semiconductor substrate in such a manner that the through hole recedes from an opening edge of the first insulating film. A third insulating film is formed only on the inner wall of the through hole.

Semiconductor device with semiconductor components connected to one another

April 29, 2008

The present invention relates to a semiconductor device which provides a shortest possible connection between two semiconductor components 10 a and 10 b arranged in a manner lying opposite on a substrate 2 . The two semiconductor components 10 a and 10 b are in each case arranged with their chip contact-connection regions 11 a and 11 b facing the substrate 2 . A vertical through-plating device 20 connects the two chip contact-connection regions 11 a and 11 b.

Semiconductor device and method for manufacturing the same

April 29, 2008

A method for manufacturing semiconductor device employs an EXTIGATE structure. In accordance with the method, a predetermined thickness of the device isolation film is etched to form a recess. The recess is then filled with a second nitride film. A stacked structure of a barrier metal film, a metal layer and a third nitride film on the second nitride film and the polysilicon film are formed on the entire surface and the etched via a photoetching process to form a gate electrode. An insulating film spacer is deposited on a sidewall of the gate electrode. The exposed portion of the polysilicon film uses the third nitride film pattern and the insulating film spacer as a mask to form a polysilicon film pattern and an oxide film on a sidewall of the polysilicon film pattern.

Semiconductor device and method for manufacturing thereof

April 29, 2008

A semiconductor device having high withstand voltage is provided. An active groove 22 a includes a long and narrow main groove part 26 and a sub groove part 27 connected to a longitudinal side surface of the main groove part, and a buried region 24 of a second conductivity type whose height is lower than the bottom surface of the base diffusion region 32 a of the second conductivity type is provided on the bottom surface of the main groove part 26 . An active groove filling region 25 of the second conductivity type in contact with the base diffusion region 32 a is provided in the sub groove part 27 . The buried region 24 is contacted to the base diffusion region 32 a through the active groove filling region 25 . Since one gate groove 83 is formed by the part above the buried region 24 in one active groove 22 a , the gate electrode plugs 48 are not separated, which allows the electrode pattern to be simplified.

Alternating micro-vias and throughboard vias to create PCB routing channels in BGA interconnect grid

April 29, 2008

A printed circuit board (PCB) assembly having a plurality of circuit layers including outer layers and intervening layers with through-vias and micro-vias used to translate a portion of the signal connections of the grid, thereby creating a set of diagonal routing channels between the vias on internal layers of the board and a BGA package mounted on the printed circuit board.

Multi-chip structure

April 29, 2008

A multi-chip structure at least including a first chip, a second chip and a first thermal-conductive layer is provided. The first chip has a first surface and a plurality of first pads disposed on the first surface. The second chip has a second surface facing the first surface and a plurality of second pads disposed on the second surface. The first thermal-conductive layer is disposed between the first chip and the second chip and includes a thermal-conductive area, a plurality of first electrical connection members and a plurality of first dielectric areas. The first electrical connection members disposed in the first thermal-conductive layer are used to electrically connect the first surface and the second surface. The first dielectric areas surround and insulate the first electrical connection members from the thermal-conductive area.

Two-transistor pixel with buried reset channel and method of formation

April 29, 2008

A two-transistor pixel of an imager has a reset region formed adjacent a charge collection region of a photodiode and in electrical communication with a gate of a source follower transistor. The reset region is connected to one terminal of a capacitor which integrates collected charge of the photodiode. The charge collection region is reset by pulsing the other terminal of the capacitor from a higher to a lower voltage.

High frequency semiconductor device

April 29, 2008

A semiconductor device has a mounting substrate and a semiconductor package mounted on the mounting substrate. The mounting substrate has a substrate body, input/output line conductors on the upper surface of the substrate body, a front-face grounding conductor on the upper surface of the substrate body, spaced from the input/output line conductors, and a lower surface grounding conductor formed on the lower surface of the substrate body and electrically connected to the front-face grounding conductor. The semiconductor package has input/output terminals electrically connected to end portions of the input/output line conductors, a grounding terminal electrically connected to the front-face grounding conductor, and a semiconductor element die-bonded on the grounding terminal and electrically connected to the input/output terminals. The input/output line conductors and the lower surface grounding conductor form micro-strip line conductors; and the front-face grounding conductor surrounds the end portions of the input/output line conductors with arch shapes.

Semiconductor device and manufacturing method for the same

April 29, 2008

To provide a semiconductor device with high performance and reliability, in which peeling off an interconnection layer caused due to peeling off of a resin film at a land part is suppressed and thus electrical break down is prevented, and an efficient method for manufacturing the semiconductor device. The semiconductor device includes a semiconductor substrate (e.g., a silicon wafer 10 ); an insulating film 12 formed on the semiconductor substrate 10; a conductive layer 20 formed on the insulating film 12, the conductive layer 20 formed of an interconnection part 22 and a land part 24 which connects the interconnection part 22 to an external terminal 40; and a resin film 30 covering the conductive layer 20, wherein the resin film 30 is in contact with the insulating film 12 at least at a part of the land part 24 by passing through the conductive layer 20.

LDMOS transistor

April 29, 2008

An LDMOS semiconductor transistor structure comprises a substrate having an epitaxial layer of a first conductivity type, a source region extending from a surface of the epitaxial layer of a second conductivity type, a lightly doped drain region within the epitaxial layer of a second conductivity type, a channel located between the drain and source regions, and a gate arranged above the channel within an insulating layer, wherein the lightly doped drain region comprises an implant region of the first conductivity type extending from the surface of the epitaxial layer into the epitaxial layer covering an end portion of the lightly doped drain region next to the gate.

Reduced power distribution mesh resistance using a modified swiss-cheese slotting pattern

April 29, 2008

Electrical interconnects with a slotting pattern are provided in the present invention. In addition, the masks for making such interconnects and semiconductor devices incorporating such interconnects are also provided in the present invention. The slotting pattern may be designed to minimize dishing effects of the interconnects as a result of planarization. Further, the slotting pattern may be designed to minimize resistance in the interconnects. For instance, the slotting pattern may include slots that are staggered, evenly aligned, or a combination of both staggered and evenly aligned. In addition, the slots may be spaced apart such that electrical paths are shorter across the interconnects. By incorporating such interconnects in semiconductor devices, better performing semiconductor devices can be realized.

Resistance variable memory with temperature tolerant materials

April 29, 2008

A PCRAM memory device having a chalcogenide glass layer, preferably comprising antimony selenide having a stoichiometric formula of about Sb 2 Se 3 , and a metal-chalcogenide layer and methods of forming such a memory device.

Process for fabricating thin film transistors

April 29, 2008

Transistors are formed by depositing at least one layer of semiconductor material on a substrate comprising a polyphenylene polyimide. The substrate permits the use of processing temperatures in excess of 300° C. during the processes used to form the transistors, thus allowing the formation of high quality silicon semiconductor layers. The substrate also has a low coefficient of thermal expansion, which closely matches that of silicon, thus reducing any tendency for a silicon layer to crack or delaminate.

IC chip package with isolated vias

April 29, 2008

An IC chip package includes a substrate ( 2 ), a chip ( 5 ), a plurality of bonding wires ( 52 ), and a cover ( 6 ). The substrate has a top surface, a receiving chamber ( 23 ) having an opening at the top surface, a plurality of solder pads ( 3 ) arranged around the top surface and respectively corresponding to the solder pads arranged at a bottom surface opposite to the top surface, and a plurality of vias ( 4 ) having conductive material electrically connecting the top solder pads with the bottom solder pads defined therein. The chip is mounted in the receiving chamber, and has a plurality of chip solder pads ( 51 ) arranged around a top surface thereof. The bonding wires respectively electrically connect the top solder pads of the substrate with the chip solder pads. The cover is fastened to the top surface of the substrate, and covers the opening.

Non-uniform ion implantation apparatus and method thereof

April 29, 2008

A non-uniform ion implantation apparatus comprises a wide ion beam generator configured to generate a plurality of wide ion beams to irradiate at least two regions on the entire area of a wafer, and a wafer rotating device configured to rotate the wafer in a predetermined direction while the wide ion beams generated by the wide ion beam generator are irradiated to the wafer. Among the wide ion beams, at least one wide ion beam has a different dose from that of at least one different wide ion beam. Since the wide ion beams are irradiated at different doses to the wafer, a smooth circular border is formed between the regions to which the impurity ions are implanted to different concentrations. Since the position of the wafer is suitably changed for the wide ion beams, it is possible to control disposition of the regions implanted with the impurity ions of different concentrations.

Substrate having a penetrating via and wiring connected to the penetrating via and a method for manufacturing the same

April 29, 2008

A disclosed substrate includes a base member having a through-hole, and a conductive metal filling in the through-hole so as to form a penetrating via. The penetrating via contains a conductive core member that is substantially at the central axis of the through-hole.

Light emitting diode package with direct leadframe heat dissipation

April 29, 2008

A packaged circuit and method for packaging an integrated circuit are disclosed. The packaged circuit has a lead frame, an integrated circuit chip, and an encapsulating layer. The lead frame has first and second sections, the first section including a lateral portion, a chip mounting area and a first extension. The integrated circuit chip is mounted in the chip mounting area and is in thermal contact with the chip mounting area. The encapsulating layer has top, bottom, and first and second side surfaces. The first extension is bent to provide a first heat path from the chip mounting area to the bottom surface. The heat path connects the heat chip mounting area to the bottom surface without passing through the first and second side surfaces and provides a heat path that has less thermal resistance than the heat path through either the lateral portion or the second section.

Redistributed solder pads using etched lead frame

April 29, 2008

A semiconductor package has a thinned semiconductor die fixed in a shallow opening in a conductive body. The die electrodes at the bottom of the die are plated with a redistributed contact which overlaps the die bottom contact and an insulation body which fills the annular gap between the die and opening. A process is described for the manufacture of the package in which plural spaced openings in a lead frame body and are simultaneously processed and singulated at the end of the process.

Method of forming an EPROM cell and structure therefor

April 29, 2008

An EPROM cell includes a control gate and a control transistor. A portion of the control transistor is formed as a portion of the control gate.

Nitride semiconductor based light-emitting device and manufacturing method thereof

April 29, 2008

An object of the present invention is to provide a nitride semiconductor based light-emitting device, which is low in operating voltage reduction and is high in performance, and a manufacturing method thereof. A first metal film is formed on a P-type conductive nitride semiconductor formed on a substrate, and then, a film (WO x ) made of tungsten oxide is formed in superimposition, followed by annealing.

Array capacitor with resistive structure

April 29, 2008

An apparatus comprises a first plurality of contacts disposed on a first side of the apparatus, adapted to engage with a first corresponding plurality of contacts on an external integrated circuit package. The apparatus further comprises a plurality of capacitive storage structures selectively coupled to the first plurality of contacts, one or more traces, and a second plurality of contacts disposed on the first side. The second plurality of contacts are adapted to engage with a second corresponding plurality of contacts on the external integrated circuit package, wherein at least two of the second plurality of contacts are adapted to be coupled to at least a first trace of the one or more traces to form a first resistive structure.

Vertical parallel plate capacitor using spacer shaped electrodes and method for fabrication thereof

April 29, 2008

A capacitor structure uses an aperture located within a dielectric layer in turn located over a substrate. A pair of conductor interconnection layers embedded within the dielectric layer terminates at a pair of opposite sidewalls of the aperture. A pair of capacitor plates is located upon the pair of opposite sidewalls of the aperture and contacting the pair of conductor interconnection layers, but not filling the aperture. A capacitor dielectric layer is located interposed between the pair of capacitor plates and filling the aperture. The pair of capacitor plates may be formed using an anisotropic unmasked etch followed by a masked trim etch. Alternatively, the pair of capacitor plates may be formed using an unmasked anisotropic etch only, when the pair of opposite sidewalls of the aperture is vertical and separated by a second pair of opposite sidewalls that is outward sloped.

Method of fabricating a semiconductor multi-package module having inverted land grid array (LGA) package stacked over ball grid array (BGA) package

April 29, 2008

A method is provided for making a semiconductor multi-package module, by providing a lower molded ball grid array package including a lower substrate and a die, affixing an upper molded package including an upper substrate in inverted orientation onto the upper surface of the lower package, and forming z-interconnects between the upper and lower substrates.

Semiconductor device with integrated trench lateral power MOSFETs and planar devices

April 29, 2008

Gate electrodes of a TLPM and gate electrodes of planar devices are formed by patterning a same polysilicon layer. Drain electrode(s) and source electrode(s) of the TLPM and drain electrodes and source electrodes of the planar devices are formed by patterning a same metal layer. Therefore, the TLPM and the planar devices can be connected electrically to each other by resulting metal wiring layers and polysilicon layers without the need for performing wire bonding on a printed circuit board.

Circuit device manufacturing method

April 29, 2008

A circuit device manufacturing method is provided, wherein the adhesion of an overcoat resin, formed on a conductive wiring layer, to a sealing resin layer is improved by irradiating plasma onto the overcoat resin. A first conductive film 23 A and a second conductive film 23 B, which are laminated with an interlayer insulating layer 22 interposed in between, are formed. By selectively removing the first conductive film, a first conductive wiring layer 12 A is formed and the first conductive wiring layer is covered with an overcoat resin 18 . Overcoat resin 18 is irradiated with plasma to roughen its top surface. A sealing resin layer 17 is formed so as to cover the top surface of the roughened overcoat resin 18 and circuit elements 13.

Encapsulation of thin-film electronic devices

April 29, 2008

One embodiment of this invention pertains to multiple encapsulated thin-film electronic devices. These encapsulated devices include a substrate and multiple thin-film electronic devices are on this substrate. Each of the multiple thin-film electronic devices has an active area. The encapsulated devices also include an encapsulation layer that is on the substrate and this encapsulation layer has multiple holes and these multiple holes are over the active areas of the multiple thin-film electronic devices. The encapsulated devices also include multiple substantially flat encapsulation pieces that are on the encapsulation layer and these multiple substantially flat encapsulation pieces cover the multiple holes of the encapsulation layer. An absorbent material is not attached to any of the substantially flat encapsulation pieces.

Metrology structure and methods

April 29, 2008

A method of indicating the progress of a sacrificial material removal process, the method, comprising; freeing a portion of a member, the member being disposed in a cage and laterally surrounded by the sacrificial material; and preventing the freed portion of the member from floating away by retaining the freed member.

Method of bonding a microelectronic die to a substrate and arrangement to carry out method

April 29, 2008

A method and an arrangement to bond a die to a substrate of a die-substrate combination to form a microelectronic package. The method comprises: providing the die-substrate combination including a die, a substrate, pre-connection bumps and an underfill material, the pre-connection bumps and underfill material being disposed between the die and the substrate; forming joints from the pre-connection bumps at a joint formation site to obtain an intermediate package; curing the underfill material of the intermediate package at an underfill curing site to obtain the microelectronic package; using a conveying device to transfer the intermediate package from the joint formation site to the underfill curing site; and applying heat energy to the intermediate package during at least part of a transfer thereof from the joint formation site to the underfill curing site to control a temperature of the intermediate package.

Organic thin film transistor including fluorine-based polymer thin film and method of fabricating the same

April 29, 2008

An organic thin film transistor including a fluorine-based polymer thin film and method of fabricating the same. The organic thin film transistor may include a gate electrode, a gate insulating layer, an organic semiconductor layer, source electrode, and a drain electrode formed on a substrate wherein a fluorine-based polymer thin film may be formed (or deposited) at the interface between the gate insulating layer and the organic semiconductor layer. The organic thin film transistor may have higher charge carrier mobility and/or higher on/off current ratio (I on /I off ). In addition, a polymer organic semiconductor may be used to form the insulating layer and the organic semiconductor layer by wet processes, so the organic thin film transistor may be fabricated by simplified procedure(s) at reduced costs.

Compact SRAMs and other multiple transistor structures

April 29, 2008

A highly dense form of static random-access memory (SRAM) takes advantage of transistor gates on both sides of silicon and high interconnectivity made possible by the complex form of silicon-on-insulator and three-dimensional integration. This technology allows one to form p-channel and n-channel devices very compactly by taking advantage of placement of gates on both sides, making common contacts and dense interconnections in 3D.

Methods of forming dual-damascene interconnect structures on semiconductor substrates using multiple planarization layers having different porosity characteristics

April 29, 2008

Methods of forming integrated circuit devices include patterning an electrically insulating layer to support dual-damascene interconnect structures therein. The steps of patterning the electrically insulating layer include using multiple planarization layers having different porosity characteristics. Forming an interconnect structure within an integrated circuit device may include forming an electrically insulating layer on a substrate and forming at least one via hole extending at least partially through the electrically insulating layer. The at least one via hole is filled with a first electrically insulating material having a first porosity. The filled at least one via hole is then covered with a second electrically insulating material layer having a second porosity lower than the first porosity. The second electrically insulating material layer is selectively etched back to expose a first portion of the first electrically insulating material in the at least one via hole. The electrically insulating layer is selectively etched to define a trench therein that exposes a second portion of the first electrically insulating material in the at least one via hole.

Semiconductor memory having charge trapping memory cells and fabrication method thereof

April 29, 2008

A semiconductor memory having charge trapping memory cells, where the direction of current flow of each channel region of the memory transistors runs transversely with respect to the relevant word line, the bit lines are arranged on the top side of the word lines and in a manner electrically insulated from the latter, and electrically conductive local interconnects of source-drain regions are present, which are arranged in sections in interspaces between the word lines and in a manner electrically insulated from the latter and connected to the bit lines, wherein gate electrodes are arranged in trenches at least partly formed in the memory substrate.

Semiconductor topography including a thin oxide-nitride stack and method for making the same

April 29, 2008

A semiconductor topography is provided which includes a silicon dioxide layer with a thickness equal to or less than approximately 10 angstroms and a silicon nitride layer arranged upon the silicon dioxide layer. In addition, a method is provided which includes growing an oxide film upon a semiconductor topography in the presence of an ozonated substance and depositing a silicon nitride film upon the oxide film. In some embodiments, the method may include growing the oxide film in a first chamber at a first temperature and transferring the semiconductor topography from the first chamber to a second chamber while the semiconductor topography is exposed to a substantially similar temperature as the first temperature. In either embodiment, the method may be used to form a semiconductor device including an oxide-nitride gate dielectric having an electrical equivalent oxide gate dielectric thickness of less than approximately 20 angstroms.

Semiconductor device and fabrication method thereof

April 29, 2008

This invention provides a semiconductor device having high operation performance and high reliability. An LDD region 707 overlapping with a gate wiring is arranged in an n-channel TFT 802 forming a driving circuit, and a TFT structure highly resistant to hot carrier injection is achieved. LDD regions 717, 718, 719 and 720 not overlapping with a gate wiring are arranged in an n-channel TFT 804 forming a pixel unit. As a result, a TFT structure having a small OFF current value is achieved. In this instance, an element belonging to the Group 15 of the Periodic Table exists in a higher concentration in the LDD region 707 than in the LDD regions 717, 718, 719 and 720.

Structure and method to form semiconductor-on-pores (SOP) for high device performance and low manufacturing cost

April 29, 2008

A semiconducting material that has all the advantages of prior art SOI substrates including, for example, low parasitic capacitance and leakage, without having floating body effects is provided. More specifically, the present invention provides a Semiconductor-on-Pores (SOP) material that includes a top semiconductor layer and a bottom semiconductor layer, wherein the semiconductor layers are separated in at least one region by a porous semiconductor material. Semiconductor structures including the SOP material as a substrate as well as a method of fabricating the SOP material are also provided. The method includes forming a p-type region with a first semiconductor layer, converting the p-type region to a porous semiconductor material, sealing the upper surface of the porous semiconductor material by annealing, and forming a second semiconductor layer atop the porous semiconductor material.

Heterojunction bipolar transistor and method of fabricating the same

April 29, 2008

Disclosed are a heterojunction bipolar transistor and a method of fabricating the same. A first dielectric layer easily etched is deposited on the overall surface of a substrate before an isolation region is defined. The first dielectric layer and a sub-collector layer are selectively etched, and then a second dielectric layer etched at a low etch rate is deposited on the overall surface of the substrate. Via holes are formed in the first and second dielectric layers, and then the first dielectric layer is removed using a difference between etch characteristics of the first and second dielectric layers. Accordingly, a reduction in power gain, generated at the interface of a compound semiconductor and a dielectric insulating layer (the second dielectric layer), can be eliminated.

Container for an electronic component

April 29, 2008

A container for an electronic component made of a resin, wherein when the container and an electronic component contained in the container are rubbed 20,000 times, a static electrification voltage of at most 2,000V by the absolute value on the surface of the electronic component is generated.

Microelectronic component assemblies with recessed wire bonds and methods of making same

April 29, 2008

The present disclosure suggests various microelectronic component assembly designs and methods for manufacturing microelectronic component assemblies. In one particular implementation, a microelectronic component assembly includes a microelectronic component, a substrate, and at least one bond wire. The substrate has a reduced-thickness base adjacent terminals of the microelectronic component and a body having a contact surface spaced farther from the microelectronic component than a bond pad surface of the base. The bond wire couples the microelectronic component to a bond pad carried by the bond pad surface and has a maximum height outwardly from the microelectronic component that is no greater than the height of the contact surface from the microelectronic component.

C_xH_ysacrificial layer for cu/low-k interconnects

April 29, 2008

A semiconductor method of manufacturing involving low-k dielectrics is provided. The method includes depositing a hydrocarbon of the general composition C x H y on the surface of a low-k dielectric. The hydrocarbon layer is deposited by reacting a precursor material, preferably C 2 H 4 or (CH 3 ) 2 CHC 6 H 6 CH 3 , using a PECVD process. In accordance with embodiments of this invention, carbon diffuses into the low-k dielectric, thereby reducing low-k dielectric damage caused by plasma processing or etching. Other embodiments comprise a semiconductor device having a low-k dielectric, wherein the low-k dielectric has carbon-adjusted dielectric region adjacent a trench sidewall and a bulk dielectric region. In preferred embodiments, the carbon-adjusted dielectric region has a carbon concentration not more than about 5% less than in the bulk dielectric region.

Semiconductor packages and methods for making and using same

April 29, 2008

A semiconductor package is provided which includes a substrate having a plurality of semiconductor dice mounted thereon. The substrate is divided into segments by grooves formed in the bottom surface of the substrate. Each semiconductor die is electrically connected to the substrate by electrical connections which extend from bond pads on the semiconductor die to corresponding bond pads on the substrate. An encapsulant is formed over each segment and contains grooves which correspond to the grooves of the substrate. Break points are thus formed at the grooves to permit the segments to be easily detached from the substrate to form individual integrated circuits.

Epitaxial crystal growth process in the manufacturing of a semiconductor device

April 29, 2008

First and second preliminary epitaxial layers are grown from single-crystalline seeds in openings in an insulation layer until the first and second epitaxial layers are connected to each other. While the first and second preliminary epitaxial layers are being grown, a connection structure of a material having an amorphous state is formed on a portion of the insulation layer located between the first and second preliminary epitaxial layers. The material having an amorphous state is then changed into material having a single-crystalline state. Thus, portions of the first and second epitaxial layers are connected to each other through the connection structure so that the epitaxial layers and the connection structure constitute a single-crystalline structure layer that is free of voids for use as a channel layer or the like of a semiconductor device.

Semiconductor device and method of manufacturing the same

April 29, 2008

Disclosed herein is a semiconductor device and method of manufacturing the same. A step between a memory cell formed in a cell region and a transistor formed in a peripheral circuit region is minimized, and the height of a gate in the memory cell is minimized. Accordingly, subsequent processes are facilitated and the electrical property of the device is thus improved.

Semiconductor device and method for manufacturing the same

April 29, 2008

A semiconductor device, comprising: a semiconductor substrate in which an integrated circuit is formed, the semiconductor substrate having an electrode electrically connected to the integrated circuit; a resin layer formed on a face in which the electrode of the semiconductor substrate is formed, as to avoid the electrode; a wiring formed as to have a protruding portion projecting upwards on the resin layer, the wiring being electrically connected to the electrode; and a solder formed on the protruding portion of the wiring, wherein the upper face portion of the protruding portion is melt-eroded by the solder and the material of the protruding portion.

Method for forming high reliability bump structure

April 29, 2008

Methods for forming a bump on a semiconductor substrate, the substrate having a contact pad thereon, is provided. In one embodiment, the method comprises depositing a passivation layer over the substrate and the contact pad. The passivation layer is patterned and etched to form a plurality of openings in the passivation layer exposing portions of the contact pad. An under bump metallurgy (UBM) layer is deposited over the etched passivation layer and in the plurality of openings thereof to contact the contact pad. A photoresist layer is formed on the UBM layer and then patterned and etched to form at least one opening substantially overlying the contact pad. An electrically conductive material is deposited into the opening formed in the photoresist layer and overlying the UBM layer and aligned with the contact pad. A portion of the remaining photoresist layer is removed. The UBM layer is etched using the electrically conductive material as a mask. Thereafter, the electrically conductive material is reflowed to provide a bump on the semiconductor substrate.

Semiconductor device fabricating apparatus and semiconductor device fabricating method

April 29, 2008

A semiconductor device fabricating method comprises a substrate forming step of forming a plurality of separate conductive pads 20 on an adhesive layer included in an adhesive sheet 50 , and a semiconductor chip mounting step of bonding semiconductor chips to the adhesive sheet 50 with surfaces thereof not provided with any electrodes in contact with the adhesive sheet 50 , and electrically connecting electrodes 11 formed on the semiconductor chips 10 and upper parts of the conductive pads 20 with wires 30 . The semiconductor chips 10 , the wires 30 and the conductive pads 20 are sealed in a sealing resin molding 40 , and then the adhesive sheet 50 is separated from the sealing resin molding 40 . Each of the conductive pads 20 has a reduced part 20 b , and a jutting part 20 a jutting out from the reduced part 20 b . The conductive pads 20 having such construction can be firmly bonded to the sealing resin molding 40.

Package of leadframe with heatsinks

April 29, 2008

A package of a leadframe with heatsinks, including a leadframe, a die, a first heatsink and a second heatsink. The leadframe has a die pad and a plurality of leads, and the leads are disposed around the die pad. The die is disposed on the die pad. The first heatsink is disposed on a first side of the leadframe and has a plurality of first positioning portions. The second heatsink is disposed on a second side of the leadframe. The second heatsink has a plurality of second positioning portions. The second positioning portions correspond to the first positioning portions of the first heatsink, whereby the warping problem of the leadframe is resolved.

Methods for fabricating solid state image sensor devices having non-planar transistors

April 29, 2008

Methods for fabricating CMOS image sensor devices are provided, wherein active pixel sensors are constructed with non-planar transistors having vertical gate electrodes and channels, which minimize the effects of image lag and dark current.

Trench buried bit line memory devices and methods thereof

April 29, 2008

A memory device includes isolation trenches that are formed generally parallel to and along associated strips of active area. A conductive bit line is recessed within each isolation trench such that the uppermost surface of the bit line is recessed below the uppermost surface of the base substrate. A bit line contact strap electrically couples the bit line to the active area both along a vertical dimension of the bit line strap and along a horizontal dimension across the uppermost surface of the base substrate.

Image sensor and method for forming the same

April 29, 2008

A method for forming an image sensor is provided. The method includes providing a semiconductor substrate having a pixel region and a peripheral circuit region, forming a photoelectric transformation section at the semiconductor substrate of the pixel region, forming a plurality of interlayer dielectrics over the semiconductor substrate with interconnections interposed therebetween, forming a passivation layer, partially patterning the passivation layer at the peripheral circuit region to form a via hole exposing the interconnection and removing the passivation layer and the underlying interlayer dielectric at the pixel region. The method further includes forming a conductive layer to fill the via hole and etching the conductive layer to remove the conductive layer at the pixel region and form a via plug and a conductive pad at the peripheral circuit region. The via plug fills the via hole and the conductive pad protrudes outwardly from the via hole.

Electro-optical device and method of manufacturing the same, element driving device and method of manufacturing the same, element substrate, and electronic apparatus

April 29, 2008

In a circuit to drive driven elements such, as electro-optical elements, an electro-optical device has an element layer, a wire-forming layer, and an electronic component layer in order to suppress variation in characteristics of active elements. The element layer has a plurality of organic EL elements, each of which is arranged in a different position in a plane. The electronic component layer has pixel-driving IC chips. The respective pixel-driving IC chips include a plurality of pixel circuits, each of which drives each organic EL element corresponding to the pixel circuit. The wire-forming layer is positioned between the element layer and the electronic component layer. The wire-forming layer has wires to connect the respective pixel circuits included in the pixel-driving IC chips with the organic EL elements corresponding to the pixel circuits.

Manufacturing method of semiconductor substrate

April 29, 2008

Closure at the opening of a trench with an epitaxial film is restrained, and thereby, filling morphology in the trenches is improved. A method for manufacturing a semiconductor substrate includes a step for growing an epitaxial layer 11 on the surface of a silicon substrate 13 , a step of forming a trench 14 in this epitaxial layer, and a step of filling the inside of the trench 14 with the epitaxial film 12 , wherein mixed gas made by mixing halogenoid gas into silicon source gas is circulated as material gas in filling the inside of the trench with the epitaxial film, and when the standard flow rate of the halogenoid gas is defined as Xslm and the film formation speed of the epitaxial film formed by the circulation of the silicon source gas is defined as Yμm/min, in the case when the aspect ratio of the trench is less than 10, an expression Y<0.2X+0.10 is satisfied, and in the case that the aspect ratio of the trench is between 10 and less than 20, an expression Y<0.2X+0.05 is satisfied, and in the case that the aspect ratio of the trench is 20 or more, an expression Y<0.2X is satisfied.

Method of forming reduced short channel field effect transistor

April 29, 2008

A method for manufacturing a semiconductor device capable of reducing a short channel effect, whereby the semiconductor device includes a pair of impurity regions for a source and a drain formed on a semiconductor substrate, a gate having a gate electrode used to control a drain current, side walls formed on both sides of the gate electrode, and a pair of electrode members formed on both sides of the semiconductor substrate and in contact with the side walls. First impurity regions are formed by thermal diffusion of impurities from each of the electrode members, and second impurity regions each having thickness smaller than the first impurity region and extending below the gate electrode are formed by thermal diffusion of impurities from the side walls.

Heat sink tab for optical sub-assembly

April 29, 2008

The present invention relates to a heat sinking tab for dissipating heat directly from an optical sub-assembly (OSA) to a transceiver housing, within which the optical sub-assembly is located. The heat sinking tab includes a mounting plate for mounting on the rear end of a transistor outline (TO) can, and a finger for extending into contact or close proximity to the transceiver housing. The mounting plate also provides a stiffening plate for flexible conductors used to connect the OSA leads to a transceiver printed circuit board (PCB).

Dressed qubits

April 29, 2008

A quantum computing method comprising constructing a dressing transformation V between a physical Hamiltonian H and an ideal Hamiltonian H ID . The physical Hamiltonian H describes a physical quantum computer that comprises a plurality of qubits, including interactions between the plurality of qubits and a continuum. The ideal Hamiltonian H ID describes the universal quantum computer that corresponds to the physical quantum computer. Each qubit in the plurality of qubits is initialized and quantum calculations are performed using the plurality of qubits. Measurement of the plurality of qubits is performed in the dressed state.

ALD of amorphous lanthanide doped TiO_xfilms

April 29, 2008

The use of atomic layer deposition (ALD) to form an amorphous dielectric layer of titanium oxide (TiO x ) doped with lanthanide elements, such as samarium, europium, gadolinium, holmium, erbium and thulium, produces a reliable structure for use in a variety of electronic devices. The dielectric structure is formed by depositing titanium oxide by atomic layer deposition onto a substrate surface using precursor chemicals, followed by depositing a layer of a lanthanide dopant, and repeating to form a sequentially deposited interleaved structure. Such a dielectric layer may be used as the gate insulator of a MOSFET, as a capacitor dielectric, or as a tunnel gate insulator in flash memories, because the high dielectric constant (high-k) of the film provides the functionality of a thinner silicon dioxide film, and because the reduced leakage current of the dielectric layer when the percentage of the lanthanide element doping is optimized.

Method for filling of a recessed structure of a semiconductor device

April 29, 2008

This invention relates to process sequence by high-speed atomic layer chemical vapor processing that includes deposition for diffusion barriers in the etched features on substrate followed by gap fill and subsequent in-situ removal of the blanket films on the top by plasma enhanced vapor phase processes. The apparatus and process sequences employed in these processing scheme allows the practitioner to complete all vapor phase process sequences of diffusion barrier deposition, gap fill and planarization of copper and diffusion barrier planarization. In case of copper metallization scheme, vapor phase gap fill can be employed to replace electrochemical deposition of copper and removal of copper and the diffusion barrier by vapor phase reactions can replace chemical-mechanical-polishing. Furthermore, such a processing scheme can be employed to deposit gate level dielectric layer, shallow trench isolation and also to form first metal contact plugs with a suitable barrier at the front end of line processing.

Method of enhancing the photoconductive properties of a semiconductor

April 29, 2008

A semiconductor material with photoconductive properties and a method of the semiconductor, wherein a base material is grown and then annealed post-growth at a temperature of 475° C. or less. It has been found that be annealing at temperatures of 475° C., or less the carrier lifetime of the material and the resistivity can be optimized so as to obtain semiconductor with useful photoconductive properties.

Method of making a multi-bit non-volatile memory (NVM) cell and structure

April 29, 2008

A multi-bit non volatile memory cell includes a first floating gate sidewall spacer structure and a second floating gate sidewall spacer structure physically separated from the first floating gate sidewall spacer structure. Each floating gate sidewall spacer structure stores charge for logically storing a bit. The floating gate sidewall spacer structures are formed adjacent to a patterned structure by sidewall spacer formation processes from a layer of floating gate material (e.g. polysilicon). A control gate is formed over the floating gate sidewall spacer structures by forming a layer of control gate material and then patterning the layer of control gate material.

Method of mounting an integrated circuit package in an encapsulant cavity

April 29, 2008

An encapsulant cavity integrated circuit package system including forming a first integrated circuit package with an inverted bottom terminal having an encapsulant cavity and an interposer, and attaching a component on the interposer in the encapsulant cavity.

Methods of manufacturing semiconductor devices having single crystalline silicon layers

April 29, 2008

Methods of manufacturing semiconductor devices having at least one single crystal silicon layer are provided. Pursuant to these methods, a first seed layer that includes silicon is formed. A first non-single crystalline silicon layer is then formed on the first seed layer. The first non-single crystalline silicon layer is irradiated with a laser to transform the first non-single crystalline silicon layer into a first single crystalline silicon layer. Corresponding semiconductor devices are also disclosed.

Method for fabricating semiconductor device

April 29, 2008

Disclosed is a method for fabricating a semiconductor device capable of preventing an inter-layer insulation layer from being damaged during a wet cleaning process due to a density difference created by reliance on a thickness of a SOG layer subjected to a curing process and of overcoming defects caused by an improper contact opening in a certain region and a punch taken place by micro voids of an APL layer. Particularly, the method includes the steps of: forming a plurality of conductive structure on a substrate; forming a spin-on-glass layer; curing the spin-on-glass layer; forming an advanced-planarization-layer on the spin-on-glass layer; and forming a plurality of contact holes by selectively etching the advanced-planarization-layer and the spin-on-glass layer, thereby exposing portions of the substrate.

Method of forming polycrystalline silicon thin film and method of manufacturing thin film transistor using the method

April 29, 2008

A method of forming a polycrystalline silicon thin film with improved electrical characteristics and a method of manufacturing a thin film transistor using the method of forming the polycrystalline silicon thin film. The method includes forming an amorphous silicon thin film on a substrate, partially melting a portion of the amorphous silicon thin film by irradiating the portion of the amorphous silicon thin film with a laser beam having a low energy density, forming polycrystalline silicon grains with a predetermined crystalline arrangement by crystallizing the partially molten portion of the amorphous silicon thin film, completely melting a portion of the polycrystalline silicon grains and a portion of the amorphous silicon thin film by irradiation of a laser beam having a high energy density while repeatedly moving the substrate by a predetermined distance, and growing the polycrystalline silicon grains by crystallizing the completely molten silicon homogeneously with the predetermined crystalline arrangement.

Semiconductor device having carbon-containing metal silicide layer and method of fabricating the same

April 29, 2008

Methods of fabricating semiconductor devices having a carbon-containing metal silicide layer and semiconductor devices fabricated by the methods are provided. A representative method includes the steps of preparing a semiconductor substrate and forming a gate electrode and source/drain regions on the semiconductor substrate, such that the gate electrode has a first metal silicide layer on an upper part thereof which contains carbon and the source/drain regions have second metal silicide layers on their substantially carbon-free upper parts.

Pattern forming method, device, method of manufacture thereof, electro-optical apparatus, and electronic apparatus

April 29, 2008

A method of forming a predetermined pattern by disposing a functional liquid on a substrate, the method includes the steps of forming banks on the substrate, and disposing the functional liquid on a region divided by the banks, wherein a width of the region is partially formed so as to be large.

Method for producing micromechanical and micro-optic components consisting of glass-type materials

April 29, 2008

What is proposed here is a method of structuring surfaces of glass-type materials and variants of this method, comprising the following steps of operation: providing a semiconductor substrate, structuring, with the formation of recesses, of at least one surface of the semiconductor substrate, providing a substrate of glass-type material, joining the semiconductor substrate to the glass-type substrate, with a structured surface of the semiconductor substrate being joined to a surface of the glass-type surface in an at least partly overlapping relationship, and heating the substrates so bonded by annealing in a way so as to induce an inflow of the glass-type material into the recesses of the structured surface of the semiconductor substrate. The variants of the method are particularly well suitable for the manufacture of micro-optical lenses and micro-mechanical components such as micro-relays or micro-valves.

Method for cutting lead terminal of package type electronic component

April 29, 2008

In an electronic component comprising a semiconductor chip packaged in a molded part from which the lead terminals of the semiconductor chip project, a main cutting notch is formed on the obverse surface of each lead terminal before molding the molded part while leaving unnotched portions adjoining both ends of the main notch. Then, each lead terminal is cut at the main notch after molding the molded part, thereby making fewer and smaller cutting burrs occurring at the cut faces.

SOI SRAM products with reduced floating body effect

April 29, 2008

A memory device is formed on a semiconductor-on-insulator (SOI) structure, the SOI structure including a substrate, an insulating layer on the substrate, and a semiconductor film on the insulating layer. The memory device includes a memory array in a memory region of the SOI structure, a plurality of first substrate contacts in the peripheral region of the memory device, and a plurality of second substrate contacts in the memory region of the SOI structure, wherein the first substrate contacts and the second substrate contacts are formed in and over the semiconductor film and in the insulating layer and are electrically connected to the substrate of the SOI structure.

Semiconductor device having multilayer structure and method for manufacturing thereof

April 29, 2008

A semiconductor device having a first wiring layer including first wirings on a substrate, a contact layer on the first wiring layer and including contacts connected to the first wirings, and a second wiring layer on the contact layer and including second wirings connected to the contacts. Contact pitch is larger than the minimum wiring pitch of the first wirings or the minimum wiring pitch of the second wirings.

Semiconductor device fabrication methods

April 29, 2008

Methods of fabricating semiconductor devices are disclosed. In a preferred embodiment, a method of fabricating a semiconductor device includes providing a workpiece including a plurality of active area regions defined therein, and forming at least one trench in the workpiece between at least two of the plurality of active area regions. A first insulating material is deposited over the plurality of active area regions and the at least one trench, partially filling the at least one trench with the first insulating material and forming peaks of the first insulating material over the plurality of active area regions. A masking material is formed over the first insulating material in the at least one trench, leaving the peaks of the first insulating material over the plurality of active area regions completely exposed. At least the peaks of the first insulating material are removed from over the plurality of active area regions.

Multi-domain liquid crystal display and method for manufacturing the same

April 29, 2008

The present invention relates to a multi-domain, specifically 4-domain, liquid crystal display and a method for manufacturing the same. In one aspect, the liquid crystal display includes a pair of opposed substrates and a liquid crystal injected and sealed between the substrates. A first region and a second region on the first substrate have different alignment directions due to a photosensitive alignment film formed on the first substrate. Each pixel on the second substrate exhibits four different liquid crystal alignment directions when an electric field is applied. This occurs because a fringe field is generated by a slit-patterned pixel electrode of the second substrate, and different alignment directions are formed in the first substrate.

Methods of forming storage capacitors for semiconductor devices

April 29, 2008

Methods of forming a storage capacitor include forming an interlayer insulation layer having an opening therethrough on a semiconductor substrate, forming a contact plug in the opening, forming a molding oxide layer on the interlayer insulation layer and the contact plug, selectively removing portions of the molding oxide layer to form a recess above the contact plug, forming a titanium layer on a bottom surface and side surfaces of the recess, forming a titanium nitride layer on the titanium layer, and forming a titanium oxide nitride layer on the titanium nitride layer. A storage capacitor includes a semiconductor substrate, an interlayer insulation layer having a contact plug therein on the substrate, and a storage electrode on the contact plug including a titanium silicide layer, a titanium nitride layer on the titanium silicide layer, and a titanium oxide nitride layer on the titanium nitride layer.

Catalytic nucleation monolayer for metal seed layers

April 29, 2008

A method of forming a copper interconnect on a substrate comprises providing a substrate that includes a dielectric layer and a trench etched into the dielectric layer, depositing a barrier layer within the trench, using a palladium immobilization process to form a metal catalyst layer on the barrier layer, activating the metal catalyst layer, and using a vapor deposition process to deposit a copper seed layer onto the metal catalyst layer. The vapor deposition process may include PVD, CVD, or ALD. An electroplating process or an electroless plating process may then be used to deposit a bulk copper layer onto the copper seed layer to fill the trench. A planarization process may follow to form the final interconnect structure.

Thin semiconductor package having stackable lead frame and method of manufacturing the same

April 29, 2008

Provided is a thin semiconductor package comprising a semiconductor chip and a lead frame, the lead frame including a paddle portion configured for mounting the semiconductor chip in a manner that exposes bonding pads within an aperture formed in a center portion of the lead frame and a peripheral terminal pad portion for establishing external contacts. A plurality of bonding wires are used to establish electrical connection between a lower surface of the paddle part and corresponding bonding pads with intermediate leads providing connection to the terminal pad portions. The semiconductor chip, lead frame and bonding wires may then be encapsulated to form a thin semiconductor package having a thickness substantially equal to that of the terminal pad portions. The thin semiconductor packages may, in turn, be used to form multi-chip stack packages using known good semiconductor chips to form a high-density compound semiconductor packages.

Methods of forming integrated circuitry and methods of forming local interconnects

April 29, 2008

In one implementation, field oxide is grown within bulk semiconductive material in a first circuitry area and not over immediately adjacent bulk semiconductive material in a second circuitry area. The field oxide is etched from the first circuitry area. After the etching, a circuit component is formed in the first circuitry area and a circuit component is formed in the second circuitry area. Dielectric material is formed over the first and second circuitry areas. The dielectric material comprises a conductive contact extending outwardly from the circuit component in the first circuitry area. The dielectric material has a first outermost surface. A portion of the dielectric material and a portion of the conductive contact are removed to form a second outermost surface of the dielectric material which has greater degree of planarity than did the first outermost surface. Other aspects are contemplated.

Structure of metal interconnect and fabrication method thereof

April 29, 2008

A process and structure for a metal interconnect includes providing a substrate with a first electric conductor, forming a first dielectric layer and a first patterned hard mask, using the first patterned hard mask to form a first opening and a second electric conductor, forming a second dielectric layer and a second patterned hard mask, using the second patterned hard mask as an etching mask and using a first patterned hard mask as an etch stop layer to form a second opening and a third electric conductor.

Optical module

April 29, 2008

An optical module has plural optical units each having an optical communication device that performs conversion between an electrical signal and an optical signal, and a socket that the optical communication device is fitted in. The optical units are aligned and detachably connected to each other by a part of the socket in contact with the socket of the adjacent optical unit.

Method and apparatus for creating RFID devices

April 29, 2008

A process is disclosed for creating semiconductor devices such as RFID assemblies wherein an array of dies mounted to a substrate is spaced apart at a first pitch, and the substrate is removed after the positions of the dies in the array is fixed by a solidifiable substance. The solidifiable substance is then removed without changing the relative positions of the dies in the array. All or a selected portion of the array of dies is then electrically attached to a plurality of straps or interposers arranged in a corresponding array. The spacing, or pitch, between the dies in the die array may be changed before or after the substrate is removed to match the pitch of the straps or interposers in the corresponding array. An RFID device created using the process inventive is also disclosed.

Method for finishing metal line for semiconductor device

April 29, 2008

A method for finishing a metal line for a semiconductor device is disclosed, in which polymer generated when forming the metal line including aluminum and its alloy is effectively removed and the metal line is prevented from being eroded. A chlorine radical and a chlorine compound remaining on a surface of the metal line are removed using H 2 O plasma and the polymer is removed using H 2 O gas and HF gas not plasma. Therefore, it is possible to improve reliability and yield of the semiconductor device.

Nonvolatile semiconductor memory device and method for manufacturing the same

April 29, 2008

A method for manufacturing a nonvolatile semiconductor memory device having a step of forming a first gate electrode on a peripheral circuit portion and a second gate electrode on a memory cell portion, a step of introducing impurity into the peripheral circuit portion and memory cell portion, a step of forming a first insulating film above at least the memory cell portion, and a step of annealing the semiconductor substrate into which the impurity has been introduced. The first gate electrode has a first gate length. The second gate electrode has a second gate length shorter than the first gate length.

Semiconductor cooling device and stack of semiconductor cooling devices

April 29, 2008

To prevent occurrence of distortion in a semiconductor cooling device and to prevent a semiconductor chip from being separated away from the semiconductor cooling device in case the semiconductor chip and the semiconductor cooling device are thermally expanded, a semiconductor cooling device includes at least an upper plate, an intermediate plate and a lower plate, and has a coolant inlet portion, an outlet portion and a flow passage portion. The upper plate and the lower plate are composite plates constituted by plating copper maintaining a thickness of not smaller than 0.05 mm on one surface or on both surfaces of auxiliary plates made of a material having a tensile strength of not smaller than 1000 N/mm 2 , a heat conductivity of not smaller than 100 W/m·K and a coefficient of thermal expansion of not larger than 6.0 ppm/° C.

Method for manufacturing SOI substrate

April 29, 2008

The object of the invention is to provide a method for manufacturing an SOI layer which is devoid of damages, has a reduced variation in thickness, and is uniform in thickness. The object is met by providing a method for manufacturing an SOI substrate comprising the steps of forming an oxide film at least on one surface of a first silicon substrate, implanting hydrogen ions from the surface of the first silicon substrate thereby forming an ion-implantation zone in the interior of the first silicon substrate, bonding the first silicon substrate over a second silicon substrate with the oxide film interposed thereby forming a laminated assembly, subjecting the laminated assembly to a first heating treatment consisting of heating at a specified temperature, so that the first silicon substrate is split at the ion-implantation zone thereby manufacturing a bonded substrate, flattening the exposed surface of the SOI layer by subjecting the bonded substrate to wet etching, subjecting the bonded substrate to a second heating treatment consisting of heating at 750 to 900° C. in an oxidative atmosphere thereby reducing damages inflicted to the SOI layer, and subjecting the resulting bonded substrate to a third heating treatment consisting of heating at 900 to 1200° C. thereby enhancing the bonding strength of the bonded substrate.

Capacitor in semiconductor device and manufacturing method

April 29, 2008

The capacitor in a semiconductor device includes a substrate, a lower electrode formed over the substrate, a diffusion barrier formed over the lower electrode, a plurality of agglomerates formed over the diffusion barrier, a dielectric layer formed over the surface of the agglomerates to form an uneven surface, and an upper electrode formed over the dielectric layer.

Semiconductor fabrication process for integrating formation of embedded nonvolatile storage device with formation of multiple transistor device types

April 29, 2008

A semiconductor fabrication process includes forming polysilicon nanocrystals on a tunnel oxide overlying a first region of a substrate. A second dielectric is deposited overlying the first region and a second region. Without providing any protective layer overlying the second dielectric in the first region, an additional thermal oxidation step is performed without oxidizing the nanocrystals. A gate electrode film is then deposited over the second dielectric and patterned to form first and second gate electrodes. The second dielectric may be an annealed, CVD oxide. The additional thermal oxidation may include forming by dry oxidation a third dielectric overlying a third region of the semiconductor substrate. The dry oxidation produces a interfacial silicon oxide underlying the second dielectric in the second region. An upper surface of a fourth region of the substrate may then be exposed and a fourth dielectric formed on the upper surface in the fourth region.

Method for forming a buried digit line with self aligning spacing layer and contact plugs during the formation of a semiconductor device, semiconductor devices, and systems including same

April 29, 2008

A method for use during fabrication of a semiconductor device comprises the formation of buried digit lines and contacts. During formation, a buried bit line layer may be used as a mask to etch one or more openings in a dielectric layer. A conductive layer is then formed in the one or more openings in the dielectric layer, and is then planarized to form one or more individual contact plugs. Next, the buried bit line layer is etched to recess the buried bit line layer, and a capacitor plate is formed to contact the contact plug.

Liquid crystal display device including repair pattern and method for fabricating the same

April 29, 2008

An LCD device including: a gate line on a substrate along a first direction; a data line in a second direction perpendicular to the gate line to define a unit pixel region, wherein the data line has recesses on a first side of the data line; a repair pattern having ends crossing the data line at the recesses of the data line; a thin film transistor adjacent to a crossing of the gate line and the data line, the thin film transistor including a semiconductor layer, a gate electrode, a drain electrode and a source electrode; a passivation layer over an entire surface of the substrate including the thin film transistor; and a pixel electrode connected to the drain electrode through the passivation layer.

Method for manufacturing semiconductor device

April 29, 2008

The present invention provides a manufacturing method of a semiconductor device at low cost and with high reliability. According to one feature of a method for manufacturing a semiconductor device includes the steps of forming a metal film over a substrate; forming a metal oxide film over the surface of the metal film by performing plasma treatment to the metal film in an atmosphere containing oxygen; forming a base film over the metal oxide film; forming an element layer having a thin film transistor over the base film; forming a protective layer over the element layer; forming an opening after selectively removing the metal film, the metal oxide film, the base film, the element layer, and the protective layer; separating the base film, the element layer, and the protective layer from the substrate; and sealing the base film, the element layer, and the protective layer by using flexible first and second films, in which an electron density of plasma around the substrate is 1×10 11 cm −3 or more and 1×10 13 cm −3 or less and an electron temperature of the plasma treatment is 0.5 eV or more and 1.5 eV or less.

Common word line edge contact phase-change memory

April 29, 2008

A method of fabricating a phase-change memory cell is described. The cross-sectional area of a contact with a phase-change memory element within the cell is controlled by a first dimension of a bottom electrode and a second dimension controlled by an etch process. The contact area is a product of the first dimension and the second dimension. The method allows the formation of very small phase-change memory cells.

Active smart antenna system and fabrication method thereof

April 29, 2008

Disclosed are an active smart antenna system and a method thereof. The system comprises: an antenna for receiving a signal; a low noise amplifier for amplifying a signal received through the antenna so as to minimize a noise generation; and a phase shifter for controlling a phase of the amplified signal. The antenna, the low noise amplifier, and the phase shifter are formed on one high resistance substrate.

Flash memory device and method for fabricating the same, and programming and erasing method thereof

April 29, 2008

A flash memory device of SONOS structure and a method for fabricating the same, and programming and erasing operation methods, to improve reliability such as endurance and retention, are disclosed, which includes a first conductive type semiconductor substrate; an ONO layer on the semiconductor substrate; a first control gate on the ONO layer; second and third control gates on the ONO layer at both sides of the first control gate; and source and drain regions in the surface of the semiconductor substrate at both sides of the second and third control gates.

Method of manufacturing gallium nitride based high-electron mobility devices

April 29, 2008

A method of manufacturing a heterojunction device includes forming a first layer of p-type aluminum gallium nitride; forming a second layer of undoped gallium nitride on the first layer; and forming a third layer of aluminum gallium nitride on the second layer, to provide an electron gas between the second and third layers. A heterojunction between the first and second layers injects positive charge into the second layer to compensate and/or neutralize negative charge within the electron gas.

Method for silicon nitride chemical vapor deposition

April 29, 2008

Embodiments of the invention generally provide a method for depositing a film containing silicon (Si) and nitrogen (N). In one embodiment, the method includes heating a substrate disposed in a processing chamber to a temperature less than about 650 degrees Celsius, flowing a nitrogen-containing gas into the processing chamber, flowing a silicon-containing gas into the processing chamber, and depositing a SiN-containing layer on a substrate. The silicon-containing gas is at least one of a gas identified as NR 2 —Si(R′ 2 )—Si(R′ 2 )—NR 2 (amino(di)silanes), R 3 —Si—N═N═N (silyl azides), R′ 3 —Si—NR—NR 2 (silyl hydrazines) or 1,3,4,5,7,8-hexamethytetrasiliazane, wherein R and R′ comprise at least one functional group selected from the group of a halogen, an organic group having one or more double bonds, an organic group having one or more triple bonds, an aliphatic alkyl group, a cyclical alkyl group, an aromatic group, an organosilicon group, an alkyamino group, or a cyclic group containing N or Si.

Fluid-cooled electronic system

April 29, 2008

A fluid-cooled electronic assembly including a base having a fluid inlet and a fluid outlet therein, a cap attached to the base to form a fluid containment chamber therebetween, wherein the fluid containment chamber is in fluid communication with the fluid inlet and the fluid outlet, and an electronic device disposed within the fluid containment chamber and connected to the base, the electronic device having a plurality of microchannels adapted to receive a cooling fluid flow therethrough, wherein the cap is shaped to direct a fluid flow from the fluid inlet to the microchannels such that a pressure drop between the fluid inlet and the fluid outlet is reduced.

Method for creating electrical pathways for semiconductor device structures using laser machining processes

April 29, 2008

A method for creating electrical pathways for semiconductor device structures using laser machining processes is provided. The method of the present invention includes providing a semiconductor substrate and forming one or more depressions in the semiconductor substrate using laser machining processes. Optionally, a film may be deposited over the semiconductor substrate and the depressions may be formed therein. Subsequently, the semiconductor substrate and/or film are etched to smooth out the depressions and the depressions are then filled with an electrically conductive material. The electrically conductive material is then planarized down to the surface of the semiconductor substrate or film thereby isolating the electrically conductive material in the depressions.

Gate-coupled EPROM cell for printhead

April 29, 2008

An EPROM cell in a printhead control circuit for an inkjet printer, having exactly one polysilicon layer and a conductive layer disposed above the polysilicon layer, includes a control transistor and an EPROM transistor. The control and EPROM transistors each have floating gates comprising a portion of the polysilicon layer, and an electrical interconnection, comprising a portion of the conductive layer, interconnects the floating gate of the control transistor and the floating gate of the EPROM transistor.

Method for manufacturing a superjunction device with wide mesas

April 29, 2008

A method of manufacturing a semiconductor device includes providing semiconductor substrate having trenches and mesas. At least one mesa has first and second sidewalls. The method includes angularly implanting a dopant of a second conductivity into the first sidewall, and angularly implanting a dopant of a second conductivity into the second sidewall. The at least one mesa is converted to a pillar by diffusing the dopants into the at least one mesa. The pillar is then converted to a column by angularly implanting a dopant of the first conductivity into a first sidewall of the pillar, and by angularly implanting the dopant of the first conductivity type into a second sidewall of the pillar. The dopants are then diffused into the pillar to provide a P-N junction of the first and second doped regions located along the depth direction of the adjoining trench. Finally, the trenches are filled with an insulating material.

Field sequential LCD device and color image display method thereof

April 29, 2008

In a liquid crystal display device, a field sequential liquid crystal display device includes a liquid crystal panel having an upper substrate, a lower substrate and a liquid crystal layer therebetween; a backlight device under the liquid crystal panel for irradiating light to the liquid crystal panel and having three color light sources; and an image signal processor controlling a sequential lighting order and combination of the three color light sources.

Dual LED board layout for lighting systems

April 29, 2008

Circuit boards for lighting systems have identical LED landing zones printed on the board. Each zone includes at least two sets of LED contact pads. One pad set is configured to mate with contacts of an LED of a first structural type, e.g. from a first product line or manufacturer. The other pad set is configured to mate with contacts of an LED of a second type, e.g. from a different product line or manufacturer. The layout may enable an easy system re-design, e.g. to shift from one type of LED to another. Alternatively, the layout may enable one system to use LEDs of the two different types in a single LED set or array. Exemplary systems disclosed herein include an element for mixing light produced by LEDs mounted to the landing zones, such as an optical integrating cavity.

Silicon phosphor electroluminescence device with nanotip electrode

April 29, 2008

An electroluminescence (EL) device and a method are provided for fabricating said device with a nanotip electrode. The method comprises: forming a bottom electrode with nanotips; forming a Si phosphor layer adjacent the nanotips; and, forming a transparent top electrode. The Si phosphor layer is interposed between the bottom and top electrodes. The nanotips may have a tip base size of about 50 nanometers, or less, a tip height in the range of 5 to 50 nm, and a nanotip density of greater than 100 nanotips per square micrometer. Typically, the nanotips are formed from iridium oxide (IrOx) nanotips. A MOCVD process forms the Ir bottom electrode. The IrOx nanotips are grown from the Ir. In one aspect, the Si phosphor layer is a SRSO layer. In response to an SRSO annealing step, nanocrystalline SRSO is formed with nanocrystals having a size in the range of 1 to 10 nm.

Method for manufacturing semiconductor device

April 29, 2008

In a method of forming a semiconductor device, a copper diffusion-prevention layer is formed underneath a substrate. Impurity regions are formed on the surface of the substrate. A copper wiring is electrically connected to the impurity regions. The copper diffusion-prevention layer is formed before forming the lightly doped source/drain regions to prevent copper atoms from diffusing into the substrate.

Method for manufacturing a MOS transistor

April 29, 2008

A method for manufacturing a MOS transistor integrated into a chip of semi-conductive material comprising a first and a second active region which extend from the inside of the chip to a surface of the chip. The method comprises the steps of: a) forming a layer of insulating material on the surface of the chip and depositing a layer of conductive material on said insulating layer, b) defining an insulated gate electrode of the transistor, from said superimposed insulating and conductive layers, c) defining, from said superimposed insulating and conductive layers, an additional structure arranged on a first surface portion of the first active region, and d) placing between the insulated gate electrode and the additional structure a dielectric spacer placed on a second surface portion of the first active region.

Methods of forming trench isolation in the fabrication of integrated circuitry, methods of fabricating memory circuitry, integrated circuitry and memory integrated circuitry

April 29, 2008

The invention includes methods of forming trench isolation in the fabrication of integrated circuitry, methods of fabricating integrated circuitry including memory circuitry, and integrated circuitry such as memory integrated circuitry.

Magnetic memory

April 29, 2008

A TMR element has a free first magnetic layer, a second magnetic layer with a magnetization direction B fixed, a nonmagnetic insulating layer provided between the first magnetic layer and the second magnetic layer, a third magnetic layer provided above a surface of the first magnetic layer and having a fixed magnetization direction, and a first nonmagnetic conductive layer provided between the first magnetic layer and the third magnetic layer, and an area of a cross section of the first magnetic layer perpendicular to a stack direction is not less than 0.001 μm 2 , and less than 0.02 μm 2 .

Chemical solution coating method and chemical solution coating apparatus

April 29, 2008

A chemical solution coating method includes: a first step of disposing a semiconductor substrate on a substrate supporting unit with a first face to be coated with a chemical solution facing upward; a second step of moving a chemical solution spraying member for spraying the chemical solution to an initial position which is positioned in the vicinity of the first face of the semiconductor substrate and where the chemical solution is to be applied; and a third step of moving the chemical solution spraying member from the initial position in accordance with a predetermined travel pattern and, simultaneously, spraying the chemical solution from the chemical solution spraying member toward the first face of the semiconductor substrate.

Method for fabricating thermally enhanced semiconductor package

April 29, 2008

A thermally enhanced semiconductor package and a fabrication method thereof are provided. A plurality of conductive bumps are formed on bond pads on an active surface of a chip. A heat sink is attached to an inactive surface of the chip and has a surface area larger than that of the chip. An encapsulation body encapsulates the heat sink, chip and conductive bumps, while exposing a bottom or surfaces, not for attaching the chip, of the heat sink and ends of the conductive bumps outside. A plurality of conductive traces are formed on the encapsulation body and electrically connected to the ends of the conductive bumps. A solder mask layer is applied over the conductive traces and formed with a plurality of openings for exposing predetermined portions of the conductive traces. A solder ball is implanted on each exposed portion of the conductive traces.

High efficiency organic electroluminescent display and method for fabricating the same

April 29, 2008

An organic electroluminescent display comprises: anode electrodes of R, G and B unit pixels formed separate from each other on a substrate; organic thin-film layers of the R, G and B unit pixels formed on the anode electrodes; and a cathode electrode formed over an entire surface of the substrate. The anode electrode of at least one unit pixel, among the R, G and B unit pixels, has a thickness different from anode electrodes of the other unit pixels. The anode electrode of each of the unit pixels comprises a first film having a high reflectivity and a second film for adjusting a work function. The second film of at least one unit pixel, among the unit pixels, has a thickness different from the second films of the other unit pixels. The second film of the R unit pixel is thicker than the second films of the other unit pixels.

Cycling LED heat spreader

April 29, 2008

A graphite heat spreader is provided for use with a flash LED light source for a camera of a handheld device such as a cell phone. Dramatically reduced operating temperatures are provided at substantially increased power levels thus providing both improved lighting and improved operating life of the electronic components.

Additive printed mask process and structures produced thereby

April 29, 2008

A digital lithographic process first deposits a mask layer comprised of print patterned mask features. The print patterned mask features define gaps into which a target material may be deposited, preferably through a digital lithographic process. The target material is cured or hardened, if necessary, into target features. The mask layer is then selectively removed. The remaining target features may then be used as exposure or etch masks, physical structures such as fluid containment elements, etc. Fine feature widths, narrower the minimum width of the print patterned mask features, may be obtained while realizing the benefits of digital lithography in the manufacturing process.

Lead frame, optical coupling part using lead frame, and manufacturing method of optical coupling part

April 29, 2008

When a resin 59 to form a molded body 20 is poured and a lead frame 30 is attached to a front end face 21 of the molded body 20 by insert molding, protective leads 32 provided on both outsides of a lead pattern 31 of the lead frame 30 moderate the flow of the resin 59 and the force acting on the lead pattern 31 is decreased, so that misregistration of the lead pattern 31 can be prevented. Accordingly, the inserted and molded lead frame 30 can be wired on the front end face 21 of the molded body 20 for easily accomplishing three-dimensional electric wiring.

Semiconductor device and method of fabrication

April 29, 2008

A semiconductor device having a DRAM has a capacitor in which a dielectric film and an upper electrode are laminated on a lower electrode comprising a polysilicone, in which a natural oxide film oxidized by oxygen in the atmosphere grows to at least 1.5 nm on the surface of a lower electrode of the capacitor. Further, in forming the dielectric film, the dioxide film further grows in the case of using an oxidative raw material. This brings forth a reduction in capacitance, and an increase of a leakage current is caused. Therefore, after a dielectric film having a reduction property has been formed, the reduction property is promoted by a heat treatment to thereby reduce a dioxide film and realize making the dioxide film on the lower electrode surface thinner.

Interconnects with direct metalization and conductive polymer

April 29, 2008

Embodiments include an interconnect or trace of electrically conductive material with a contact surface, and a dielectric layer overlying the contact surface with a via formed on the dielectric layer and to the contact surface. The via sidewalls and perimeter are layered with a manganese oxide (MnO 2 ) layer which is layered over with a conductive polymer material. An interconnect material is formed in the via and in a trench above the perimeter of the via such that the interconnect material is on the conductive polymer material and contacts the contact surface. An additional dielectric layer may be formed over the interconnect material and an additional via may be formed therethrough so that an additional structure having a MnO 2 layer, conductive polymer material, and interconnect material can be formed in the additional via and to the interconnect material.

Methods of fabricating a semiconductor device using an organic compound and fluoride-based buffered solution

April 29, 2008

Methods are provided for fabricating a semiconductor device that include the steps of: sequentially forming a metal interconnection and a protecting layer on a semiconductor substrate; forming a contact hole on the protecting layer; isolating the contact hole by forming a molding layer and an etching stop layer stacked thereon; forming a sacrificial layer on the etching stop layer so as to fill the contact hole; forming a photoresist layer with an opening so as to expose the sacrificial layer and such that the opening of the photoresist layer aligns with the contact hole; forming a trench in the molding layer to penetrate the sacrificial layer and the etching stop layer; and performing a wet etching on the semiconductor substrate having the trench to remove the photoresist layer and the sacrificial layer, wherein the wet etching step is performed using an organic compound and fluoride ion-based buffered solution.

Resistive elements using carbon nanotubes

April 29, 2008

Resistive elements include a patterned region of nanofabric having a predetermined area, where the nanofabric has a selected sheet resistance; and first and second electrical contacts contacting the patterned region of nanofabric and in spaced relation to each other. The resistance of the element between the first and second electrical contacts is determined by the selected sheet resistance of the nanofabric, the area of nanofabric, and the spaced relation of the first and second electrical contacts. The bulk resistance is tunable.

Method for manufacturing semiconductor device having super junction construction

April 29, 2008

A semiconductor device includes a body region, a drift region having a first part and a second part, and a trench gate electrode. The body region is disposed on the drift region. The first and second parts extend in an extending direction so that the second part is adjacent to the first part. The trench gate electrode penetrates the body region and reaches the drift region so that the trench gate electrode faces the body region and the drift region through an insulation layer. The trench gate electrode extends in a direction crossing with the extending direction of the first and second parts. The first part includes a portion near the trench gate electrode, which has an impurity concentration equal to or lower than that of the body region.

Method and apparatus for semiconductor device with improved source/drain junctions

April 29, 2008

A semiconductor device with improved source/drain junctions and methods for fabricating the device are disclosed. A preferred embodiment comprises a MOS transistor with a gate structure overlying a substrate, lightly doped source/drain regions formed in the substrate aligned to the gate structure, sidewall spacers formed on the sidewalls of the gate structure and overlying the lightly doped source/drain regions, deeper source/drain diffusions formed into the substrate aligned to the sidewall spacers and additional pocket implants of source/drain dopants formed at the boundary of the deeper source/drain diffusions and the substrate. In a preferred method, the additional pocket implants are formed using an angled ion implant with the angle being between 4 and 45 degrees from vertical. Additional embodiments include recesses formed in the source/drain regions and methods for forming the recesses.

Method and apparatus for maintaining a multi-chip module at a temperature above downhole temperature

April 29, 2008

Methods and systems for operating integrated circuits at temperatures higher than expected ambient temperatures. The heating may be of entire circuit boards, portions of the circuit boards (such as the components within a multiple-chip module) and/or single devices. Methods and related systems may be used in any high temperature environment such as downhole logging tools, and the devices so heated are preferably of silicon on insulator semiconductor technology.

Method for fabricating semiconductor package

April 29, 2008

A semiconductor package and a fabrication method thereof are proposed. A lead frame is provided between a chip and a substrate in a window ball grid array semiconductor package, wherein an active surface of the chip is electrically connected to the lead frame via bonding wires formed in an opening of the substrate and is electrically connected to the substrate via the lead frame. The provision of lead frame can improve the heat dissipating efficiency and electrical performances. The bonding wires located in the opening of the substrate eliminate the prior-art drawback of requiring different molds in response to different opening structures of a substrate.

CMOS on hybrid substrate with different crystal orientations using silicon-to-silicon direct wafer bonding

April 29, 2008

A method in which semiconductor-to-semiconductor direct wafer bonding is employed to provide a hybrid substrate having semiconductor layers of different crystallographic orientations that are separated by a conductive interface is provided. Also provided are the hybrid substrate produced by the method as well as using the direct bonding method to provide an integrated semiconductor structure in which various CMOS devices are built upon a surface orientation that enhances device performance.

Terminal box for a solar battery module, a rectifying-device unit

April 29, 2008

A terminal box for a solar battery module is provided with a plurality of terminal plates ( 30 ) juxtaposed on a base plate ( 11 ) and connectable with positive and negative electrodes of the solar battery module, cables for external connection connectable with the terminal plates ( 30 ), and rectifying-device units ( 50 ) each of which spans between two corresponding terminal plates ( 30 ). Each rectifying-device unit ( 50 ) includes a bypass diode ( 52 ) connectable with the two corresponding terminal plates ( 30 ) to prevent an inverse current, and a metal-made clip ( 53 ) for resiliently holding the bypass diode ( 52 ). The clip ( 53 ) is held in contact with a heat discharging plate ( 55 ) of the bypass diode ( 52 ) to discharge heat generated by the bypass diode ( 52 ).

Display device and manufacturing method thereof

April 29, 2008

A display device in which a light shielding film is formed so as not to increase the number of steps and its cost, is provided. The display device of the present invention includes a monitor element for controlling influence on a light-emitting element due to temperature change and change with time and a TFT for driving the monitor element, and the TFT for driving the monitor element is provided so as not to be overlapped with the monitor element. The display device of the present invention includes a first light shielding film provided so as not to be overlapped with a first electrode of the monitor element, and a second light shielding film provided so as to be overlapped with an outer edge portion of the first electrode.

Fabrication methods for micro compounds optics

April 29, 2008

Methods for fabricating refractive element(s) and aligning the elements in a compound optic, typically to a zone plate element. The techniques are used for fabricating micro refractive, such as Fresnel, optics and compound optics including two or more optical elements for short wavelength radiation. One application is the fabrication of the Achromatic Fresnel Optic (AFO). Techniques for fabricating the refractive element generally include: 1) ultra-high precision mechanical machining, e.g,. diamond turning; 2) lithographic techniques including gray-scale lithography and multi-step lithographic processes; 3) high-energy beam machining, such as electron-beam, focused ion beam, laser, and plasma-beam machining; and 4) photo-induced chemical etching techniques. Also addressed are methods of aligning the two optical elements during fabrication and methods of maintaining the alignment during subsequent operation.

CMOS APS with stacked avalanche multiplication layer and low voltage readout electronics

April 29, 2008

An image sensor includes a pixel having a protection circuit connected to a charge multiplying photoconversion layer. The protection circuit prevents the pixel circuit from breaking down when the voltage in the pixel circuit reaches the operating voltage applied to the charge multiplying photoconversion layer in response to the image sensor being exposed to a strong light. The protection circuit causes additional voltage entering the pixel circuit from the charge multiplying photoconversion layer over a predetermined threshold voltage level to be dissipated from the storage node and any downstream components.

Active matrix display device

April 29, 2008

In order to provide an active matrix display device in which a thick insulating film is preferably formed around an organic semiconductive film of a thin film luminescent device without damaging the thin film luminescent device, the active matrix display device is provided with a bank layer (bank) along a data line (sig) and a scanning line (gate) to suppress formation of parasitic capacitance in the data line (sig), in which the bank layer (bank) surrounds a region that forms the organic semiconductive film of the thin film luminescent device by an ink-jet process. The bank layer (bank) includes a lower insulating layer formed of a thick organic material and an upper insulating layer of an organic material which is deposited on the lower insulating layer and has a smaller thickness so as to avoid contact of the organic semiconductive film with the upper insulating layer.

Micropin heat exchanger

April 29, 2008

An apparatus including a micropin thermal solution is described. The apparatus comprises a substrate and a number of micropins thermally coupled to the substrate. The micropins are arranged in a pixel like pattern over the substrate.

Damascene replacement metal gate process with controlled gate profile and length using Si_1-xGe_xas sacrificial material

April 29, 2008

A method of forming a metal gate in a wafer. PolySi 1-x Ge x and polysilicon are used to form a tapered groove. Gate oxide, PolySi 1-x Ge x , and polysilicon is deposited on a wafer. A resist pattern is formed. A portion of the polysilicon, PolySi 1-x Ge x , and gate oxide is removed to provide a tapered profile. The resist is removed; a dielectric liner is deposited, and then at least a portion of the dielectric liner is removed, thereby exposing the polysilicon and leaving the dielectric liner in contact with the polysilicon, PolyS 1-x Ge x , and gate oxide. A dielectric is deposited, and a portion is removed thereby exposing the polysilicon. The polysilicon, PolySi 1-x Ge x , and gate oxide is removed from inside the dielectric liner, thereby leaving a tapered gate groove. Metal is then deposited in the groove.

Manufacturing method to construct semiconductor-on-insulator with conductor layer sandwiched between buried dielectric layer and semiconductor layers

April 29, 2008

A method for treating exposed metal in a semiconductor wafer ( 301 ) in wafer processing is disclosed herein. In accordance with the method, a wafer is provided which is equipped with a metal layer ( 307 ) and a substrate ( 303 ), wherein a portion of the metal layer is exposed at the edge of the wafer. The exposed portion of the metal layer is then covered with a dielectric material ( 317 ).

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Method of fabricating recess transistor in integrated circuit device and recess transistor in integrated circuit device fabricated by the same

Surface-mount packaging for chip

Semiconductor device

Overhang integrated circuit package system

Heat radiation structure of semiconductor element and heat sink

High-frequency semiconductor device and method of manufacturing the same

Method of wet etching vias and articles formed thereby

Stackable semiconductor package

Semiconductor device, semiconductor package for use therein, and manufacturing method thereof

Semiconductor device

Memory cell having enhanced high-K dielectric

Semiconductor device and method of manufacturing the semiconductor device

Optical sensor with improved planarization

Semiconductor device having silicide reaction blocking region

Memory cell structure

Semiconductor device and fabrication method thereof

Semiconductor device with semiconductor components connected to one another

Semiconductor device and method for manufacturing the same

Semiconductor device and method for manufacturing thereof

Alternating micro-vias and throughboard vias to create PCB routing channels in BGA interconnect grid

Multi-chip structure

Two-transistor pixel with buried reset channel and method of formation

High frequency semiconductor device

Semiconductor device and manufacturing method for the same

LDMOS transistor

Reduced power distribution mesh resistance using a modified swiss-cheese slotting pattern

Resistance variable memory with temperature tolerant materials

Process for fabricating thin film transistors

IC chip package with isolated vias

Non-uniform ion implantation apparatus and method thereof

Substrate having a penetrating via and wiring connected to the penetrating via and a method for manufacturing the same

Light emitting diode package with direct leadframe heat dissipation

Redistributed solder pads using etched lead frame

Method of forming an EPROM cell and structure therefor

Nitride semiconductor based light-emitting device and manufacturing method thereof

Array capacitor with resistive structure

Vertical parallel plate capacitor using spacer shaped electrodes and method for fabrication thereof

Method of fabricating a semiconductor multi-package module having inverted land grid array (LGA) package stacked over ball grid array (BGA) package

Semiconductor device with integrated trench lateral power MOSFETs and planar devices

Circuit device manufacturing method

Encapsulation of thin-film electronic devices

Metrology structure and methods

Method of bonding a microelectronic die to a substrate and arrangement to carry out method

Organic thin film transistor including fluorine-based polymer thin film and method of fabricating the same

Compact SRAMs and other multiple transistor structures

Methods of forming dual-damascene interconnect structures on semiconductor substrates using multiple planarization layers having different porosity characteristics

Semiconductor memory having charge trapping memory cells and fabrication method thereof

Semiconductor topography including a thin oxide-nitride stack and method for making the same

Semiconductor device and fabrication method thereof

Structure and method to form semiconductor-on-pores (SOP) for high device performance and low manufacturing cost

Heterojunction bipolar transistor and method of fabricating the same

Container for an electronic component

Microelectronic component assemblies with recessed wire bonds and methods of making same

CxHy sacrificial layer for cu/low-k interconnects

Semiconductor packages and methods for making and using same

Epitaxial crystal growth process in the manufacturing of a semiconductor device

Semiconductor device and method of manufacturing the same

Semiconductor device and method for manufacturing the same

Method for forming high reliability bump structure

Semiconductor device fabricating apparatus and semiconductor device fabricating method

Package of leadframe with heatsinks

Methods for fabricating solid state image sensor devices having non-planar transistors

Trench buried bit line memory devices and methods thereof

Image sensor and method for forming the same

Electro-optical device and method of manufacturing the same, element driving device and method of manufacturing the same, element substrate, and electronic apparatus

Manufacturing method of semiconductor substrate

Method of forming reduced short channel field effect transistor

Heat sink tab for optical sub-assembly

Dressed qubits

ALD of amorphous lanthanide doped TiOx films

Method for filling of a recessed structure of a semiconductor device

Method of enhancing the photoconductive properties of a semiconductor

Method of making a multi-bit non-volatile memory (NVM) cell and structure

Method of mounting an integrated circuit package in an encapsulant cavity

Methods of manufacturing semiconductor devices having single crystalline silicon layers

Method for fabricating semiconductor device

Method of forming polycrystalline silicon thin film and method of manufacturing thin film transistor using the method

Semiconductor device having carbon-containing metal silicide layer and method of fabricating the same

Pattern forming method, device, method of manufacture thereof, electro-optical apparatus, and electronic apparatus

C_xH_ysacrificial layer for cu/low-k interconnects

ALD of amorphous lanthanide doped TiO_xfilms

Damascene replacement metal gate process with controlled gate profile and length using Si_1-xGe_xas sacrificial material