freepatentsonline.com

Liquid crystal display device and method of manufacturing liquid crystal display device with color filter layer on thin film transistor

Tue, 03 Nov 2009 08:00:00 EST

A method of fabricating a liquid crystal display device is provided. The method of fabricating a liquid crystal display device includes forming a thin film transistor including a source electrode and a drain electrode on a substrate, forming a first passivation layer on the substrate, forming a black matrix on the first passivation layer, forming a color filter layer on the first passivation layer in the pixel region, and forming a pixel electrode above the color filter layer and the black matrix by using a single mask.

Thin film transistor array panel with enhanced storage capacitors

Tue, 03 Nov 2009 08:00:00 EST

A thin film transistor array panel is provided. The array panel includes a storage capacitance that is substantially uniform, and allows for a relatively large capacitance in a relatively small area. In some embodiments, the panel includes: a substrate; a plurality of semiconductor regions on the substrate, including a plurality of source and drain regions doped with a first impurity type and a dummy region doped with a second impurity type, and an intrinsic region having storage and channel regions; a gate insulating layer covering at least a portion of the semiconductor regions; a gate line including a gate electrode at least partially overlapping the channel region and formed on the gate insulating layer; a storage line including a storage electrode at least partially overlapping the storage region and formed on the gate insulating layer; a data line including a source electrode connected to the source region and formed on the gate insulating layer; a drain electrode connected to the drain region and the dummy region and formed on the gate insulating layer; and a pixel electrode connected to the drain electrode.

Dual-gate device and method

Tue, 03 Nov 2009 08:00:00 EST

A memory circuit having dual-gate memory cells and a method for fabricating such a memory circuit are disclosed. The dual-gate memory cells each include a memory device and an access device sharing a semiconductor layer, with their respective channel regions provided on different surfaces of the semiconductor layer. The semiconductor layer has a thickness, such that when a pass voltage is applied to the gate electrode of the access device, the access device and the memory device remains isolated, such that the charge stored in the memory device is unaffected by the pass voltage. The pass voltage is determined from a range of voltages, when applied to the access device, has no effect on the threshold voltage of the memory device. The dual-gate memory cells can be used as building blocks for a non-volatile memory array, such as a memory array formed by NAND-strings. In such an array, during programming of a nearby memory device in a NAND string, in NAND-strings not to be programmed, if inversion regions are allowed to be formed in the semiconductor layer, or if the semiconductor layer is allowed to electrically float, electrical interaction exists between the access devices and the memory devices to inhibit programming of the memory devices.

Package for an integrated circuit

Tue, 03 Nov 2009 08:00:00 EST

According to various illustrative embodiments of the present invention, a device for an integrated circuit includes a monolithic frame having a plurality of alignment features disposed thereon, the monolithic frame having a mounting surface disposed thereon for the integrated circuit, the monolithic frame also having a thermal interface area disposed thereon for the integrated circuit. The device also includes an electrical interface capable of providing an electrical connection for the integrated circuit, the plurality of alignment features being substantially independent of the electrical interface, and an adhesive layer disposed between the monolithic frame and the electrical interface.

Multi-chip module and single-chip module for chips and proximity connectors

Tue, 03 Nov 2009 08:00:00 EST

A single-chip module is described. The module includes a first semiconductor die having a first surface and a second surface. The first semiconductor die is configured to communicate by capacitive coupling using one or more of a plurality of proximity connectors coupled to the first semiconductor die. A cable coupled to the first semiconductor die is configured to couple power signals to the first semiconductor die. A flexibility compliance of at least one section of the cable is greater than a threshold value thereby allowing the module to be positioned in a mounting structure.

High power light emitting diode device

Tue, 03 Nov 2009 08:00:00 EST

A circuit element having a heat-conducting body having top and bottom surfaces, and a die having an electronic circuit thereon is disclosed. The die includes first and second contact points for powering the electronic circuit. The die is in thermal contact with the heat-conducting body, the die having a bottom surface that is smaller than the top surface of the heat-conducting body. The first contact point on the die is connected to a first trace bonded to the top surface of the heat-conducting body. An encapsulating cap covers the die. The first trace has a first portion that extends outside of the encapsulating cap and a second portion that is covered by the encapsulating cap. The heat-conducting body is preferably constructed from copper or aluminum and includes a cavity having an opening on the first surface in which the die is mounted. The die preferably includes a light-emitting device.

Overlapped stressed liners for improved contacts

Tue, 03 Nov 2009 08:00:00 EST

A semiconductor structure is provided which includes a first semiconductor device in a first active semiconductor region and a second semiconductor device in a second active semiconductor region. A first dielectric liner overlies the first semiconductor device and a second dielectric liner overlies the second semiconductor device, with the second dielectric liner overlapping the first dielectric liner at an overlap region. The second dielectric liner has a first portion having a first thickness contacting an apex of the second gate conductor and a second portion extending from peripheral edges of the second gate conductor which has a second thickness substantially greater than the first thickness. A first conductive via contacts at least one of the first or second gate conductors and the conductive via extends through the first and second dielectric liners at the overlap region. A second conductive via may contact at least one of a source region or a drain region of the second semiconductor device.

Organic bottom emission electronic device

Tue, 03 Nov 2009 08:00:00 EST

An organic electronic device includes a pixel. In one embodiment, the organic electronic device is a bottom emission electronic device. The pixel has an aperture ratio of at least 40%. In another embodiment, the pixel has a first side and a second side opposite the first side. From a plan view, the data line and the first power supply line have lengths that extend along the length of the pixel and lie closer to the first side compared to the second side. In still another embodiment, an organic electronic device includes a substrate, a data line, and a power supply line. The pixel includes a select transistor and a driving transistor. Within the first pixel, each of the data line and the first power supply line lies closer to the substrate compared to the select transistor.

Method and system for laser thermal processing of semiconductor devices

Tue, 03 Nov 2009 08:00:00 EST

Methods and systems for performing laser thermal processing (LTP) of semiconductor devices are disclosed. The method includes forming a dielectric cap atop a temperature-sensitive element, and then forming an absorber layer atop the dielectric layer. A switch layer may optionally be formed atop the absorber layer. The dielectric cap thermally isolates the temperature-sensitive element from the absorber layer. This allows less-temperature-sensitive regions such as unactivated source and drain regions to be heated sufficiently to activate these regions during LTP via melting and recrystallization of the regions, while simultaneously preventing melting of the temperature-sensitive element, such as a poly-gate.

Semiconductor device

Tue, 03 Nov 2009 08:00:00 EST

A systemized active matrix display in which a pixel matrix circuit, a driver circuit and a logic circuit are mounted on the same substrate, is formed. A TFT of the present invention has such characteristics as to be able to operate in a wide driving frequency range of 0.05 to 2 GHz, and by designing a channel length and a film thickness of a gate insulating film of the TFT according to characteristics required by circuits, it is possible to form a high frequency driving circuit and a low frequency driving circuit on the same substrate.

Power semiconductor element with an emitter region and a stop zone in front of the emitter region

Tue, 03 Nov 2009 08:00:00 EST

The power semiconductor element has an emitter region and a stop zone in front of the emitter region. The conductivities of the emitter region and of the stop zone are opposed to one another. In order to reduce not only the static but also the dynamic loss of the power semiconductor foreign atoms are used in the stop-zone. The foreign atoms have at least one energy level within the band gap of the semiconductor and at least 200 meV away from the conduction band and valence band of the semiconductor.

CMOS image sensors

Tue, 03 Nov 2009 08:00:00 EST

CMOS image sensors and methods for fabricating the same are disclosed. A disclosed CMOS image sensor comprises: a semiconductor substrate; a photo diode; a microlens located over the photo diode; and a color filter layer located over the microlens.

Nonvolatile memory semiconductor device and manufacturing method thereof

Tue, 03 Nov 2009 08:00:00 EST

To provide a nonvolatile memory having an excellent data holding property and a technique for manufacturing the memory, a polycrystalline silicon film 7 and an insulating film 8 are sequentially stacked on a gate insulating film 6, then the polycrystalline silicon film 7 and the insulating film 8 are patterned to form gate electrodes 7 A, 7 B, and then sidewall spacers 12 including a silicon oxide film are formed on sidewalls of the gate electrodes 7 A, 7 B. After that, a silicon nitride film 19 is deposited on a substrate 1 by a plasma enhanced CVD process so that the gate electrodes 7 A, 7 B are not directly contacted to the silicon nitride film 19.

Semiconductor device having a conductive portion below an interlayer insulating film and method for producing the same

Tue, 03 Nov 2009 08:00:00 EST

A semiconductor device comprising: a MIS type field effect transistor which comprises a semiconductor raised portion protruding from a substrate plane, a gate electrode extending over the semiconductor raised portion from the top onto the opposite side faces of the semiconductor raised portion, a gate insulation film existing between the gate electrode and the semiconductor raised portion, and source and drain regions provided in the semiconductor raised portion; an interlayer insulating film provided on a substrate including the transistor; and a buried conductor interconnect that is formed by filling in a trench formed in the interlayer insulating film with a conductor, wherein the buried conductor interconnect connects one of the source and drain regions of the semiconductor raised portion and another conductive portion below the interlayer insulating film.

Semiconductor integrated circuit device

Tue, 03 Nov 2009 08:00:00 EST

Prior known static random access memory (SRAM) cells are required that a diffusion layer be bent into a key-like shape in order to make electrical contact with a substrate with a P-type well region formed therein, which would result in a decrease in asymmetry leading to occurrence of a problem as to the difficulty in micro-patterning. To avoid this problem, the P-type well region in which an inverter making up an SRAM cell is formed is subdivided into two portions, which are disposed on the opposite sides of an N-type well region NW 1 and are formed so that a diffusion layer forming a transistor has no curvature while causing the layout direction to run in a direction parallel to well boundary lines and bit lines. At intermediate locations of an array, regions for use in supplying power to the substrate are formed in parallel to word lines in such a manner that one regions is provided per group of thirty two memory cell rows or sixty four cell rows.

Schottky barrier diode and diode array

Tue, 03 Nov 2009 08:00:00 EST

A Schottky barrier diode includes a first semiconductor layer and a second semiconductor layer successively formed above a semiconductor substrate with a buffer layer formed between the first and second semiconductor layers and the semiconductor substrate. A Schottky electrode and an ohmic electrode spaced from each other are formed on the second semiconductor layer, and a back face electrode is formed on the back face of the semiconductor substrate. The Schottky electrode or the ohmic electrode is electrically connected to the back face electrode through a via penetrating through at least the buffer layer.

Electronic device having wiring substrate and lead frame

Tue, 03 Nov 2009 08:00:00 EST

An electronic device includes: a first substrate and a second substrate; a lead frame disposed between the first and the second substrates for electrically connecting therebetween; and a first groove and a second groove disposed on the first and the second substrates, respectively. The first and the second grooves correspond to a connection portion between the first and the second substrates and the lead frame. The lead frame is connected to the first and the second substrates in such a manner that one end of the lead frame is engaged in both of the first and the second grooves through a conductive bonding material.

Reducing resistivity in interconnect structures by forming an inter-layer

Tue, 03 Nov 2009 08:00:00 EST

An integrated circuit structure having improved resistivity and a method for forming the same are provided. The integrated circuit structure includes a dielectric layer, an opening in the dielectric layer, and a damascene structure in the opening. The damascene structure includes a metallic barrier layer in the opening and in physical contact with the dielectric layer, a conductive material filling the remaining part of the opening, and an interlayer between and adjoining the metallic barrier layer and the conductive material. The interlayer is preferably a metal compound layer.

Nitride semiconductor light emitting device

Tue, 03 Nov 2009 08:00:00 EST

A nitride semiconductor light emitting device includes a substrate, and a first n-type nitride semiconductor layer, a light emitting layer, a first p-type nitride semiconductor layer, a second p-type nitride semiconductor layer, a p-type nitride semiconductor tunnel junction layer, an n-type nitride semiconductor tunnel junction layer and a second n-type nitride semiconductor layer that are formed on the substrate. The p-type nitride semiconductor tunnel junction layer and the n-type nitride semiconductor tunnel junction layer form a tunnel junction, and the p-type nitride semiconductor tunnel junction layer has an indium content ratio higher than that of the second p-type nitride semiconductor layer. At least one of the p-type nitride semiconductor tunnel junction layer and the n-type nitride semiconductor tunnel junction layer includes aluminum.

TFT containing coalesced nanoparticles

Tue, 03 Nov 2009 08:00:00 EST

A thin film transistor comprising: (a) an insulating layer; (b) a gate electrode; (c) a semiconductor layer; (d) a source electrode; and (e) a drain electrode, wherein the insulating layer, the gate electrode, the semiconductor layer, the source electrode, and the drain electrode are in any sequence as long as the gate electrode and the semiconductor layer both contact the insulating layer, and the source electrode and the drain electrode both contact the semiconductor layer, and wherein at least one of the source electrode, the drain electrode, and the gate electrode comprise coalesced coinage metal containing nanoparticles and a residual amount of one or both of a stabilizer covalently bonded to the coalesced coinage metal containing nanoparticles and a decomposed stabilizer covalently bonded to the coalesced coinage metal containing nanoparticles.

Method for fabricating a semiconductor device and semiconductor device

Tue, 03 Nov 2009 08:00:00 EST

The present invention discloses a method for fabricating a semiconductor device, comprising: providing a translucent portion; forming a covering layer comprised of one or more metals on the translucent portion by vapor deposition; providing kinetic energy to the covering layer for forming a periodic mask; forming a periodic structure on the translucent portion by using the periodic mask.

Semiconductor device

Tue, 03 Nov 2009 08:00:00 EST

A semiconductor device includes a semiconductor element that is set up on a semiconductor layer, a light shielding wall that is set up around the semiconductor element, a hole that is set up on the light shielding wall, and a wiring layer that is electrically connected to the semiconductor element and is drawn out through the hole to the outside of the light shielding wall. The wiring layer has a pattern including a first part that is located within the hole and a second part that is located on the outside of the hole and has a larger width compared to the width of the first part, the width of the second part being the same with or larger than the width of the hole.

Semiconductor device

Tue, 03 Nov 2009 08:00:00 EST

A semiconductor device includes semiconductor substrate, isolation insulating film, nonvolatile memory cells, each of the cells including tunnel insulating film, FG electrode, CG electrode, interelectrode insulating film between the CG and FG electrodes and including a first insulating film and a second insulating film on the first insulating film and having higher permittivity than the first insulating film, the interelectrode insulating film being provided on a side wall of the floating gate electrode in a cross-section view of a channel width direction of the cell, thickness of the interelectrode insulating film increasing from an upper portion of the side wall toward a lower portion of the side wall, thickness of the second insulating film on an upper corner of the FG electrode being thicker than thickness of the second insulating film on the other portions of the side wall in the cross-section view of the channel width direction.

Fabrication of FinFETs with multiple fin heights

Tue, 03 Nov 2009 08:00:00 EST

A semiconductor structure includes a first semiconductor strip extending from a top surface of the semiconductor substrate into the semiconductor substrate, wherein the first semiconductor strip has a first height. A first insulating region is formed in the semiconductor substrate and surrounding a bottom portion of the first semiconductor strip, wherein the first insulating region has a first top surface lower than a top surface of the first semiconductor strip. A second semiconductor strip extends from a top surface of the semiconductor substrate into the semiconductor substrate, wherein the second semiconductor strip has a second height greater than the first height. A second insulating region is formed in the semiconductor substrate and surrounding a bottom portion of the second semiconductor strip, wherein the second insulating region has a second top surface lower than the first top surface, and wherein the first and the second insulating regions have substantially same thicknesses.

Monolithic power semiconductor structures including pairs of integrated devices

Tue, 03 Nov 2009 08:00:00 EST

Monolithic semiconductor structures having at least two pairs of two lateral semiconductor devices combined on a first surface of a single semiconductor substrate. Embodiments include connected source terminals defining common source terminals.

Inductor fabricated with dry film resist and cavity and method of fabricating the inductor

Tue, 03 Nov 2009 08:00:00 EST

An inductor fabricated with a dry film resist and a cavity and a method of fabricating the inductor. The cavity can be formed in a substrate to minimize a parasitic capacitance generated by structures of upper electrodes, an insulating layer, and a lower electrode and minimize energy loss caused by an eddy current generated through the substrate. Also, a process of forming and planarizing the cavity can be simplified so as to form the cavity to a sufficient depth. As a result, an inductor having a high quality factor and a high self resonant frequency can be fabricated. Also, a scheme for simply forming and planarizing a cavity is contemplated.

Semiconductor package having improved thermal performance

Tue, 03 Nov 2009 08:00:00 EST

A composite semiconductor package is disclosed. The package includes a lead frame having first and second die bonding pads, the first and second die bonding pads having a large lateral separation therebetween, a first device bonded to the first die bonding pad, a second device bonded to the second die bonding pad, a plurality of first leads coupled to the first die bonding pad, a plurality of second leads coupled to the second die bonding pad, and an encapsulant covering the lead frame, the first and second devices and at least a portion of the first and second pluralities of leads. The package may be a TSSOP-8 composite package having a common drain MOSFET pair and an IC.

Semiconductor package with flow controller

Tue, 03 Nov 2009 08:00:00 EST

A semiconductor package can comprise a die stack attached to a substrate, with bond wires electrically connecting the two. Often multiple die stacks are adhered to a single substrate so that several semiconductor packages can be manufactured at once. A molding compound flow controller is optimally associated with the substrate or semiconductor package at one or more various locations. Flow controllers can control or direct the flow of the molding compound during the encapsulation process. Flow controllers can be sized, shaped, and positioned in order to smooth out the flow of the molding compound, such that the speed of the flow is substantially equivalent over areas of the substrate containing dies and over areas of the substrate without dies. In this manner, defects such as voids in the encapsulation, wire sweeping, and wire shorts can be substantially avoided during encapsulation.

Power module having a cooling device and semiconductor devices mounted on a resin substrate, method of producing same, and air conditioner

Tue, 03 Nov 2009 08:00:00 EST

A power module includes a power semiconductor, a non-power semiconductor, one resin substrate, and a cooling device. The power semiconductor and the non-power semiconductor configure a power supply circuit for performing power conversion. Both the power semiconductor and the non-power semiconductor are mounted on the resin substrate. The cooling device is disposed in order to cool the power semiconductor.

N-type group III nitride semiconductor stacked layer structure

Tue, 03 Nov 2009 08:00:00 EST

An n-type Group III nitride semiconductor stacked layer structure including a first n-type layer which includes a layer containing n-type impurity atoms at a high concentration and a layer containing n-type impurity atoms at a low concentration, a second n-type layer containing n-type impurity atoms at an average concentration smaller than that of the first n-type layer, the second n-type layer neighboring the layer containing n-type impurity atoms at a low concentration in the first n-type layer.

Semiconductor device having an interconnect structure and a reinforcing insulating film

Tue, 03 Nov 2009 08:00:00 EST

A semiconductor device includes in an interconnect structure which includes a first interconnect made of a copper-containing metal, a first Cu silicide layer covering the upper portion of the first interconnect, a conductive first plug provided on the upper portion of the Cu silicide layer and connected to the first interconnect, a Cu silicide layer covering the upper portion of the first plug, a first porous MSQ film provided over the side wall from the first interconnect through the first plug and formed to cover the side wall of the first interconnect, the upper portion of the first interconnect, and the side wall of the first plug, and a first SiCN film disposed under the first porous MSQ film to contact with the lower portion of the side wall of the first interconnect and having the greater film density than the first porous MSQ film.

Semiconductor device including a stress buffer

Tue, 03 Nov 2009 08:00:00 EST

An integrated circuit includes a first surface configured for mounting to a carrier, an active area of the integrated circuit spaced from the first surface, a bond pad disposed over and in electrical communication with the active area, and a ceramic inorganic stress-buffering layer disposed between the active area and the bond pad.

Structure to monitor arcing in the processing steps of metal layer build on silicon-on-insulator semiconductors

Tue, 03 Nov 2009 08:00:00 EST

The present invention addresses detection of charge-induced defects through test structures that can be easily incorporated on a wafer to detect charge-induced damage in the back-end-of-line processing of a semiconductor processing line. A test macro is designed to induce an arc from a charge accumulating antenna structure to another charge accumulating antenna structure across parallel plate electrodes. When an arc of a predetermined sufficient strength is present, the macro will experience a voltage breakdown that is measurable as a short. The parallel plate electrodes may both be at the floating potential of the microchip to monitor CMP-induced or lithographic-induced charge failure mechanisms, or have one electrode electrically connected to a ground potential structure to capture charge induced damage, hence having the capability to differentiate between the two.

Semiconductor device with multiple impurity regions and image display apparatus

Tue, 03 Nov 2009 08:00:00 EST

A silicon nitride film and a silicon oxide film are formed on a glass substrate. On the silicon oxide film is formed a thin film transistor including a source region, a drain region, a channel region having a predetermined channel length, an LDD region and GOLD region having an impurity concentration higher than the impurity concentration of the channel region and lower than the impurity concentration of the source and drain regions, a gate insulation film, and a gate electrode. The gate electrode is formed to overlap in plane with the channel region and the GOLD region. Accordingly, a semiconductor device and an image display apparatus directed to improving source-drain breakdown voltage are obtained.

Light emitting device and method of manufacturing the same

Tue, 03 Nov 2009 08:00:00 EST

A light emitting device and a method of manufacturing the same are provided. The light emitting device comprises a first conductive type lower semiconductor layer, a current diffusion layer, a first conductive type upper semiconductor layer, an active layer, and a second conductive type semiconductor layer. The current diffusion layer is formed on the first conductive type lower semiconductor layer. The first conductive type upper semiconductor layer is formed on the current diffusion layer. The active layer is formed on the first conductive type upper semiconductor layer. The second conductive type semiconductor layer is formed on the active layer.

Thyristor optimized for a sinusoidal HF control

Tue, 03 Nov 2009 08:00:00 EST

A vertical thyristor adapted to an HF control, including a cathode region in a P-type base well, a lightly-doped P-type layer next to the base well, a lightly-doped N-type region in the lightly-doped P-type layer, a Schottky contact on the lightly-doped N-type region connected to a control terminal, and a connection between the lightly-doped N-type region and the P-type base well.

Embedded SiGe stressor with tensile strain for NMOS current enhancement

Tue, 03 Nov 2009 08:00:00 EST

MOS devices having localized stressors are provided. Embodiments of the invention comprise a gate electrode formed over a substrate and source/drain regions formed on either side of the gate electrode. The source/drain regions include an embedded stressor and a capping layer on the embedded stressor. Preferably, the embedded stressor has a lattice spacing greater than the substrate lattice spacing. In a preferred embodiment, the substrate is silicon and the embedded stressor is silicon germanium. A method of manufacturing is also provided, wherein strained PMOS and NMOS transistors may be formed simultaneously.

Semiconductor integrated circuit device

Tue, 03 Nov 2009 08:00:00 EST

In a low power consumption mode in which prior data is retained upon power shutdown, the return speed thereof is increased. While use of an existent data retaining flip-flop may be considered, this is not preferred since it increases area overhead such as enlargement of the size of a cell. A power line for data retention for power shutdown is formed with wirings finer than a usual main power line. Preferably, power lines for a data retention circuit are considered as signal lines and wired by automatic placing and mounting. For this purpose, terminals for the power line for data retention are previously designed by providing the terminals therefore for the cell in the same manner as in the existent signal lines. Additional layout for power lines is no longer necessary for the cell, which enables a decrease in the area and design by an existent placing and routing tool.

Semiconductor integrated circuit devices

Tue, 03 Nov 2009 08:00:00 EST

A semiconductor integrated circuit device includes a first interlayer insulation film having a contact therein. The contact has an upper surface and including a void therein having an open upper portion. The device further includes a plasma damage reduction unit including a lower electrode conformably on the void of the contact and on the upper surface of the contact, a dielectric film on the lower electrode, and an upper electrode on the dielectric film. The thickness of the portion of the dielectric film in the void is smaller than the thickness of the portion of the dielectric film on the upper surface of the contact.

Transistor, memory cell array and method of manufacturing a transistor

Tue, 03 Nov 2009 08:00:00 EST

A transistor includes a first and second source/drain regions, a channel connecting the first and second source/drain regions, and a gate electrode to control an electrical current flowing in the channel. The gate electrode is disposed in a gate groove, the gate groove being defined in a top surface of a semiconductor substrate. The first and second source/drain regions extend at least to a depth d 1 , the depth d 1 being measured from the top surface of the substrate. A top surface of the gate electrode is disposed beneath the top surface of the semiconductor substrate. A top surface of the gate electrode is disposed at a depth d 2 which is less than the depth d 1 , the depth d 2 being measured from the substrate surface.

Trenched MOSFET device configuration with reduced mask processes

Tue, 03 Nov 2009 08:00:00 EST

A semiconductor power device comprising a termination area that includes a trenched gate runner electrically connected to a trenched gate of said semiconductor power device. The semiconductor power device further includes a trenched field plate disposed in a trench opened in the termination area and the trenched field plate is electrically connected to the trenched gate runner. A gate runner contact trench and a field plate contact trench opened through an insulation layer covering the gate runner and the trenched field plate for extending into a doped gate dielectric filling in the trenched gate runner and the field plate wherein the gate runner contact trench and the field plate contact trench filled with a gate runner contact plug and a field plate contact plug respectively. A gate metal disposed on top of the insulation layer to electrically contact the gate runner contact plug and the field plate contact plug for electrically interconnecting the trenched gate runner and the trenched field plate.

MOS transistor device

Tue, 03 Nov 2009 08:00:00 EST

The invention relates to a MOS transistor device of the trench type, in which, in a semiconductor region of a first conductivity type, within a deep gate trench extending in the vertical direction of the semiconductor region, a vertical gate electrode and a gate oxide with a field plate step insulating the latter are formed and, in an adjoining mesa region outside and laterally with respect to the deep trench, at the upper section thereof, a source electrode region of the first conductivity type and a body region of a second conductivity type with one or a plurality of assigned body contact are formed, a drain electrode region of the first conductivity type lying opposite the deep trench in the vertical direction. The MOS transistor has a deep body reinforcement of the second conductivity type below the body region at the location of the body contact, said body reinforcement lying deeper than the field plate step.

Trigger device for ESD protection circuit

Tue, 03 Nov 2009 08:00:00 EST

The present invention is a trigger device useful, for example, in triggering an SCR in an ESD protection circuit. Illustratively, an NMOS trigger device comprises a gate and heavily doped P and N regions in a P-well on opposite sides of the gate. A first N type source/drain extension and a first P-type pocket region extend from the P region toward the N region with the pocket region located under the source/drain extension and extending under the gate. A second N-type source/drain extension and a second P-type pocket region extend from the N region toward the P region with the pocket region located under the source/drain extension and extending under the gate. Preferably, the gate itself is heavily doped so that one half of the gate on the side adjacent the heavily doped P region is also heavily doped with dopants of P-type conductivity and the other half of the gate on the side adjacent the heavily doped N region is also heavily doped with dopants of N-type conductivity. Doping the gate increases the threshold voltage by about one Volt due to an increase in the work function on the source side of the gate.

Semiconductor device and manufacturing method thereof

Tue, 03 Nov 2009 08:00:00 EST

A semiconductor device includes a substrate, a p-channel MIS transistor formed on the substrate, the p-channel MIS transistor having a first gate electrode, and an n-channel MIS transistor formed on the substrate separately from the p-channel MIS transistor, the n-channel MIS transistor having a second gate electrode. Each of the first gate electrode and the second gate electrode is formed of an alloy of Ta and C in which a mole ratio of C to Ta (C/Ta) is from 2 to 4.

Image-sensing chip package module adapted to dual-side soldering

Tue, 03 Nov 2009 08:00:00 EST

An image-sensing chip package module adapted to dual-side soldering includes three substrates, an image-sensing chip and a filter lens. The three substrates are stacked together by pressing (using adhesive as adhesion medium), and the image-sensing chip is electrically connected to the top side of the top substrate and the bottom side of the bottom substrate via conductive bodies that are formed on inner surfaces of through holes passing through the three substrates. Hence, the image-sensing chip package module can use the conductive bodies formed on the bottom side of the bottom substrate (positive face electrical conduction) or the conductive bodies formed on the top side of the top substrate (negative face electrical conduction) to electrically connect with a main PCB. Furthermore, the filter lens is received and hidden in an opening of the top substrate in order to prevent the filter lens from being slid, collided and destroyed.

Layered structure for electron device including regions of different wettability, electron device and electron device array that uses such a layered structure

Tue, 03 Nov 2009 08:00:00 EST

A layered structure comprises a variable wettability layer including a material that changes a critical surface tension in response to energy provided thereto, the wettability changing layer including at least a high surface energy part of large critical surface tension and a low surface energy part of low critical surface tension, a conductive layer formed on the variable wettability layer at the high surface energy tension part, and a semiconductor layer formed on the variable wettability layer at the low surface energy part.

Semiconductor device including a strained superlattice layer above a stress layer

Tue, 03 Nov 2009 08:00:00 EST

A semiconductor device may include a stress layer and a strained superlattice layer above the stress layer and including a plurality of stacked groups of layers. More particularly, each group of layers of the strained superlattice layer may include a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.

Semiconductor device and method for fabricating the same

Tue, 03 Nov 2009 08:00:00 EST

A semiconductor device includes at least one thin-film transistor, which includes a semiconductor layer, a gate electrode and a gate insulating film. In the semiconductor layer, a crystalline region, including a channel forming region, a source region and a drain region, is defined. The gate electrode is provided to control the conductivity of the channel forming region. The gate insulating film is provided between the gate electrode and the semiconductor layer. The semiconductor layer includes a gettering region outside of the crystalline region thereof.

Electronic device with dopant diffusion barrier and tunable work function and methods of making same

Tue, 03 Nov 2009 08:00:00 EST

A method of fabricating a semiconductive film stack for use as a polysilicon germanium gate electrode to address problems associated with implant and diffusion of dopants. Achieving a sufficiently high active dopant concentration at a gate-dielectric interface while avoiding gate penetration of dopants such as boron is problematic. A higher gate implant dosage or annealing temperature is needed, and boron penetration through the thin gate oxide is inevitably enhanced. Both problems are exacerbated as the gate dielectric becomes thinner. In order to achieve a high level of active dopant concentration next to the gate dielectric without experiencing problems associated with gate depletion and penetration, a method and procedures of applying a diffusion-blocking layer is described with respect to an exemplary MOSFET application. However, a diffusion-blocking concept is also presented, which is readily amenable to a variety of semiconductor related technologies.

Signal-carrying flexure structure for micro-electromechanical devices

Tue, 03 Nov 2009 08:00:00 EST

A signal-carrying flexure structure for a MEM device comprises at least two conductive flexure segments having respective cross-sectional areas, and at least one crosspiece affixed to the flexure segments to operatively couple the segments together such that the flexure segments and crosspiece form a single flexure structure. The resulting flexure structure's spring constant is less than that of a solid flexure having a comparable total cross-sectional area, while its resistance is approximately equal to that of the solid flexure.

P-type ZnS based semiconductor material having a low resistance due to its high copper content

Tue, 03 Nov 2009 08:00:00 EST

It is an object to provide a p-type ZnS based semiconductor material having a low resistance which can easily form an ohmic contact to a metallic material. Moreover, the invention provides a semiconductor device and a semiconductor light emitting device which include an electrode having a low resistance on a substrate other than a single crystal substrate, for example, a glass substrate. The semiconductor material according to the invention is used as a hole injecting electrode layer of a light emitting device and has a transparent property in a visible region which is expressed in a composition formula of Zn (1-α-β-γ) Cu α Mg β Cd γ S (1-x-y) Se x Te y (0.004≦α≦0.4, β≦0.2, γ≦0.2, 0≦x≦1, 0≦y≦0.2, and x+y≦1).

Method of packaging integrated circuits

Tue, 03 Nov 2009 08:00:00 EST

A method of packaging an integrated circuit die having a plurality of I/O pads is described. The method includes positioning the die within a die attach area of a first leadframe that includes a plurality of first leads. The method also includes positioning a second leadframe that includes a plurality of second leads over the first leadframe. The method further includes electrically connecting each of the second leads to both an associated I/O pad and a first lead.

Active matrix substrate with height control member

Tue, 03 Nov 2009 08:00:00 EST

An active matrix substrate comprises a substrate, a plurality of adhesion parts provided on the substrate so as to have substantially the same height, and a plurality of active elements provided on the plurality of adhesion parts, respectively, each of the plurality of adhesion parts including a height control member and an adhesive.

Inter-chip communication

Tue, 03 Nov 2009 08:00:00 EST

The present invention provides a quilt packaging system for microchip, a method for making such a quilt packaging system, microchips that may be used in a such a quilt packaging system, and methods for making such microchips.

Electronic device, semiconductor device using same, and method for manufacturing semiconductor device

Tue, 03 Nov 2009 08:00:00 EST

An inventive electronic device includes a substrate, a bump of a first metal material provided on a surface of the substrate, a bonding film of a second metal material provided on a top surface of the bump for bonding the electronic device to an electrical connection portion of a second device, the second metal material having a lower melting point in an elemental state than an alloy of the first metal material and the second metal material, and a diffusion prevention film of a third metal material provided between the top surface of the bump and the bonding film as covering at least part of the top surface of the bump, the third metal material having a lower diffusion coefficient than the second metal material with respect to the first metal material.

MOS devices with source/drain regions having stressed regions and non-stressed regions

Tue, 03 Nov 2009 08:00:00 EST

A semiconductor structure includes a semiconductor substrate; a gate stack on the semiconductor substrate; a stressor having at least a portion in the semiconductor substrate and adjacent to the gate stack, wherein the stressor comprises an impurity of a first conductivity type; and a portion of the semiconductor substrate adjoining the stressor and on an opposite side of the stressor from the gate stack, wherein the portion of the semiconductor substrate is doped with an impurity of the first conductivity type.

Memory cell having first and second capacitors with electrodes acting as control gates for nonvolatile memory transistors

Tue, 03 Nov 2009 08:00:00 EST

A nonvolatile memory cell that can be mounted in a CMOS manufacturing process, and is capable of implementing high level of programming, reading and erasing ability. The memory cell is configured by a MOS transistor including two N-type first impurity diffusion layers formed separately on a P-type semiconductor substrate, and a first gate electrode formed above a first cannel region sandwiched by both diffusion layers through a first gate insulation film, a first capacitor comprising P-type second impurity diffusion layers formed on a well, and a second gate electrode formed above the diffusion layer through a second gate insulation film, and a second capacitor comprising the well adjacent to the second impurity diffusion layer, and a third gate electrode formed above the well through a third gate insulation film, wherein a different voltage can be applied to each of the capacitors.

Image sensor with a transparent plate having refractive index changing regions

Tue, 03 Nov 2009 08:00:00 EST

An image sensor includes: a light source that irradiates a light on an object; a lens body that converges a reflection of the light from the object; a plurality of IC chips that receive the reflection passed through the lens body; and a transparent member provided between the IC chips and the lens body. The transparent member includes a refractive index changing region provided at a portion opposite to a gap between adjacent IC chips. A refractive index in the refractive index changing region increases continuously or stepwise toward an inner portion of the transparent member from a surface of the transparent member on an IC chips side so that the refractive index changing region refracts a part of the reflection to be incident into the gap to the IC chips.

CMOS image sensor and method for fabricating the same

Tue, 03 Nov 2009 08:00:00 EST

A CMOS image sensor and a method of fabricating the same are provided. The CMOS image sensor includes: an epitaxial layer of a first conductivity type, formed in a semiconductor substrate of the first conductivity type; a blue photodiode region of a second conductivity type, formed in the epitaxial layer at a first depth; a green photodiode region of the second conductivity type, spaced apart from the blue photodiode region and formed in the epitaxial layer at a second depth larger than the first depth; and a red photodiode region of the second conductivity type, spaced apart from the green photodiode region and formed in the epitaxial layer at a third depth larger than the second depth.

Packaged microelectronic devices with a lead frame

Tue, 03 Nov 2009 08:00:00 EST

Packaged microelectronic devices and methods for manufacturing packaged microelectronic devices are disclosed herein. In one embodiment, a packaged microelectronic device can include a support member and at least one die in a stacked configuration attached to the support member. The support member may include a leadframe disposed longitudinally between first and second ends and latitudinally between first and second sides. The leadframe includes a lead extending between the first end and the first side.

Image sensor with a gate electrode between the photoelectric conversion region and the charge detection region, the gate electrode comprising p-type and n-type regions adjacent to one another and method of fabricating the same

Tue, 03 Nov 2009 08:00:00 EST

Example embodiments relate to an image sensor and a fabrication method thereof. An image sensor may include a semiconductor substrate. A charge transfer structure may be formed on the semiconductor substrate. The charge transfer structure may include a gate insulating film that may be formed on a channel region in the semiconductor substrate between a photoelectric conversion region and charge detection region, and a transfer gate electrode that may be formed on the gate insulating film that may have a region doped with a first conductivity type impurity-doped region and a second conductivity type impurity-doped region which may be adjacent to each other.

Nonvolatile nanochannel memory device using mesoporous material

Tue, 03 Nov 2009 08:00:00 EST

A nonvolatile nanochannel memory device using a mesoporous material. Specifically, a memory device is composed of a mesoporous material that is able to form nanochannels, in which a memory layer having metal nanoparticles or metal ions fed into the nanochannels is disposed between an upper electrode and a lower electrode. Thus, the memory device has high processability, and manifests excellent reproducibility and uniform performance.

Thermal interface

Tue, 03 Nov 2009 08:00:00 EST

An apparatus including an interface having a number of nanostructures is described. The apparatus comprises heat source, a thermal management device, and an interface disposed between the thermal management device and the heat source. The interface a substrate has a number of nanostructures to facilitate heat transfer and adhesion between the heat source and the thermal management device.

Low power non-volatile memory and gate stack

Tue, 03 Nov 2009 08:00:00 EST

Non-volatile memory devices and arrays are described that facilitate the use of band-gap engineered gate stacks with asymmetric tunnel barriers in reverse and normal mode floating node memory cells in NOR or NAND memory architectures that allow for direct tunnel programming and erase, while maintaining high charge blocking barriers and deep carrier trapping sites for good charge retention. The low voltage direct tunneling program and erase capability reduces damage to the gate stack and the crystal lattice from high energy carriers, reducing write fatigue and enhancing device lifespan. The low voltage direct tunnel program and erase capability also enables size reduction through low voltage design and further device feature scaling. Memory cells of the present invention also allow multiple bit storage. These characteristics allow memory device embodiments of the present invention to operate within the definition of a universal memory, capable of replacing both DRAM and ROM in a system.

Structure for dual work function metal gate electrodes by control of interface dipoles

Tue, 03 Nov 2009 08:00:00 EST

Exemplary embodiments provide structures for dual work function metal gate electrodes. The work function value of a metal gate electrode can be increased and/or decreased by disposing various electronegative species and/or electropositive species at the metal/dielectric interface to control interface dipoles. In an exemplary embodiment, various electronegative species can be disposed at the metal/dielectric interface to increase the work function value of the metal, which can be used for a PMOS metal gate electrode in a dual work function gated device. Various electropositive species can be disposed at the metal/dielectric interface to decrease the work function value of the metal, which can be used for an NMOS metal gate electrode in the dual work function gated device.

Semiconductor device having self-aligned contact

Tue, 03 Nov 2009 08:00:00 EST

A method of manufacturing semiconductor devices having self-aligned contacts is provided. Multiple isolation structures are formed on the substrate to define an active area. Multiple gate structures are formed on the substrate. Multiple doped areas are formed in the substrate beside each gate structure. Multiple first spacers are formed on the sidewalls of each of the gate structure. Multiple second spacers are formed on the sidewalls of each of the isolation structure. A dielectric layer is formed on the substrate. Then, a self-aligned process is performed to form multiple contact openings in the dielectric layer between the gate structures. The conductive material is filled in the contact openings.

Thermally enhanced single inline package (SIP)

Tue, 03 Nov 2009 08:00:00 EST

In a method and system for fabricating a thermally enhanced semiconductor device ( 200, 300 ) is packaged as a through hole single inline package (SIP). A leadframe ( 210, 310, 410 ) having a die pad ( 220, 320, 420 ) to attach an IC die ( 230, 330 ), a first plurality of conductive leads ( 240, 340, 430 ) formed from a first portion of metal sheet ( 432 ), and a second portion of metal sheet ( 440 ) disposed on an opposite side of the IC die ( 230, 330 ) as the first plurality of conductive leads is stamped from a metal sheet. The first plurality of conductive leads ( 240, 340, 430 ) are arranged in a single line and are capable of being through hole mounted in accordance with the SIP. The second portion of metal sheet ( 440 ) includes the die pad ( 420 ) to form a heat spreader ( 260, 360 ) in the form of the metal sheet. The heat spreader ( 260, 360 ) provides heat dissipating for the heat generated by the IC die ( 230, 330 ).

Semiconductor devices with layers having extended perimeters for improved cooling and methods for cooling semiconductor devices

Tue, 03 Nov 2009 08:00:00 EST

A semiconductor device is provided, and includes a wafer having first and second opposed metallized major faces and a transistor bonded to the first metallized face of the wafer. The transistor includes a first surface, and the first surface defines a first area. The device further includes a first metal layer bonded to the first surface of the transistor. The first metal layer has a first surface that defines a second area larger than the first area of the transistor. The device further includes a ceramic layer bonded to the first surface of the first metal layer.

Epoxy resin composition for semiconductor encapsulating use, and semiconductor device

Tue, 03 Nov 2009 08:00:00 EST

There is provided an epoxy resin composition for semiconductor encapsulating use comprising: an epoxy resin (A); a phenol resin (B); a curing accelerator (C); and an inorganic filler (D), wherein the inorganic filler (D) contains a spherical fused silica (d1) which contains: metal or semimetal other than silicon; and/or an inorganic compound comprising the metal or semimetal other than silicon.

Semiconductor device and method of fabricating the same

Tue, 03 Nov 2009 08:00:00 EST

A semiconductor device includes (a) a semiconductor layer formed on an electrically insulating layer, (b) a gate insulating film formed on the semiconductor layer, (c) a gate electrode formed on the gate insulating film, and (d) a field insulating film formed on the semiconductor layer for defining a region in which a semiconductor device is to be fabricated. The semiconductor layer includes (a1) source and drain regions formed in the semiconductor layer around the gate electrode, the source and drain regions containing first electrically conductive type impurity, (a2) a body contact region formed in the semiconductor layer, the body contact region containing second electrically conductive type impurity, and (a3) a carrier path region formed in the semiconductor layer such that the carrier path region does not make contact with the source and drain regions, but makes contact with the body contact region, the carrier path region containing second electrically conductive type impurity.

High power light-emitting diode package comprising substrate having beacon

Tue, 03 Nov 2009 08:00:00 EST

Disclosed herein is a package structure including at least one high power light-emitting diode to exhibit excellent heat release properties. In the package structure, a light-emitting diode chip which generates heat is directly attached to a beacon processed to protrude from part of a heat spreader having high heat conductivity, whereby an electrical wiring portion is separated from a heat release portion, thus maximizing heat release properties and realizing high luminance and reliability. The package structure is composed of a beacon formed on a metal or non-metal substrate having high heat conductivity to mount a high power light-emitting diode chip, to increase heat release properties; a wiring portion provided on the same line as the diode to input and output power and signals; and a reflection cup having a cavity, which may be inserted into or attached to the heat spreader or the wiring substrate, including a low temperature co-fired ceramic substrate, a high temperature co-fired ceramic substrate, or a printed circuit board.

Heterojunction transistors including energy barriers

Tue, 03 Nov 2009 08:00:00 EST

A heterojunction transistor may include a channel layer comprising a Group III nitride, a barrier layer comprising a Group III nitride on the channel layer, and an energy barrier comprising a layer of a Group III nitride including indium on the channel layer such that the channel layer is between the barrier layer and the energy barrier. The barrier layer may have a bandgap greater than a bandgap of the channel layer, and a concentration of indium (In) in the energy barrier may be greater than a concentration of indium (In) in the channel layer. Related methods are also discussed.

Silicon bipolar transistor, circuit arrangement and method for producing a silicon bipolar transistor

Tue, 03 Nov 2009 08:00:00 EST

The silicon bipolar transistor ( 100 ) comprises a base, with a first highly-doped base layer ( 105 ) and a second poorly-doped base layer ( 106 ) which together form the base. The emitter is completely highly-doped and mounted directly on the second base layer ( 106 ).

Method for manufacturing a semiconductor device and semiconductor device

Tue, 03 Nov 2009 08:00:00 EST

A method for manufacturing a semiconductor device includes: the first step of forming, in an insulating film provided on a substrate, a recess that is porositized at least at inner walls; the second step of forming an alloy layer made of copper and a metal other than copper so as to cover the inner walls of the recess; the third step of burying a conductive layer made primarily of copper in the recess provided with the alloy layer; the fourth step of subjecting the thus treated substrate to thermal treatment to cause the metal in the alloy layer to react with a constituent component of the insulating film to form a barrier film made of a metal compound having Cu diffusion barrier properties.

Method of fabricating a non-volatile memory device

Tue, 03 Nov 2009 08:00:00 EST

A method of fabricating a non-volatile memory device prevents the threshold voltage of a program-inhibited cell from rising by preventing hot carriers, generated in a semiconductor substrate near a select line, from being injected into a floating gate of the program-inhibited cell. The program-inhibited cell shares a word line adjacent to the select line such that a trench is formed in the semiconductor substrate between the select line and the adjacent word line to increase a distance between the select line and the word line.

Methods of selectively forming epitaxial semiconductor layer on single crystalline semiconductor and semiconductor devices fabricated using the same

Tue, 03 Nov 2009 08:00:00 EST

In methods of selectively forming an epitaxial semiconductor layer on a single crystalline semiconductor and semiconductor devices fabricated using the same, a single crystalline epitaxial semiconductor layer and a non-single crystalline epitaxial semiconductor layer are formed on a single crystalline semiconductor and a non-single crystalline semiconductor pattern respectively, using a main semiconductor source gas and a main etching gas. The non-single crystalline epitaxial semiconductor layer is removed using a selective etching gas. The main gases and the selective etching gas are alternately and repeatedly supplied at least two times to selectively form an elevated single crystalline epitaxial semiconductor layer having a desired thickness only on the single crystalline semiconductor. The selective etching gas suppresses formation of an epitaxial semiconductor layer on the non-single crystalline semiconductor pattern.

Non-volatile memory devices having cell diodes

Tue, 03 Nov 2009 08:00:00 EST

An integrated circuit memory cell includes a substrate having a first semiconductor region of first conductivity type (e.g., N-type) therein, which may define a portion of a word line within the substrate. An electrically insulating layer is provided on the substrate. The electrically insulating layer has an opening therein that extends opposite a recess in the first semiconductor region. A first insulating spacer is provided on a sidewall of the recess in the first semiconductor region. A diode is provided in the opening. The diode has a first terminal electrically coupled to a bottom of the recess in the first semiconductor region. A variable resistivity material region (e.g., phase-changeable material region) is also provided. The variable resistivity material region is electrically coupled to a second terminal of the diode.

Method for defeating reverse engineering of integrated circuits by optical means

Tue, 03 Nov 2009 08:00:00 EST

A method for an electronic device is provided for preventing reverse engineering by monitoring light emissions emitted from transistors and such electrically active devices in the electronic device. The method emits extraneous randomized light emissions in substantial close proximity to the transistors to hide a pattern of light emissions emitted from the transistors. As one feature, the device can include a source of randomized light emissions in substantial close proximity to the transistors to hide a pattern of the emitted light from the transistors in randomized light emissions emitted by the source. As a second feature, the device can emit the randomized light emissions by randomly delaying an electrical signal that is electrically coupled to the transistors and, in response to the randomly delayed electrical signal, the transistors randomly emitting light emissions thereby hiding a separate pattern of light emission emitted from the transistors.

Semiconductor storage device and method of manufacturing the same

Tue, 03 Nov 2009 08:00:00 EST

A semiconductor storage device wherein a plurality of ferroelectric capacitors are sufficiently covered with a hydrogen barrier film formed thereon comprises a field effect transistor formed on one surface side of a semiconductor substrate, a plurality of ferroelectric capacitors formed close to each other above the field effect transistor, an insulting film configured to cover the plurality of ferroelectric capacitors and planarised a space between adjacent ferroelectric capacitors in a self-aligned manner during formation thereof, and a hydrogen barrier film formed on the insulating film.

Wafer, semiconductor chip, and semiconductor device

Tue, 03 Nov 2009 08:00:00 EST

Scribe lines demarcating semiconductor chips comprise, in both the vertical direction and the horizontal direction, first-type scribe lines of the minimum width enabling cutting by dicing or other means, and second-type scribe lines enabling placement of TEGs, alignment marks or other accessories, and a placement pattern is set so that a unit cell which can be exposed in a single shot comprises one second-type scribe line. By this means, the area occupied by scribe lines can be reduced. Further, by decreasing the number of placement of semiconductor chips constituting a unit cell, and by cutting substantially along the center line of second-type scribe lines, the shapes of scribe lines on the periphery of semiconductor chips can be changed, so that the position in the unit cell can be determined.

Optimized power delivery to high speed, high pin-count devices

Tue, 03 Nov 2009 08:00:00 EST

A high-speed semiconductor device includes a substrate having an upper substrate surface, a lower substrate surface, and a periphery bounding the upper and the lower substrate surfaces, the substrate further having an upper substrate ground trace providing an electrical path to the lower substrate surface through a substrate ground via; an array of solder balls attached to the lower substrate surface, the array of solder balls including a plurality of ground solder balls disposed at the periphery and electrically connected to the substrate ground via.

Method for fabricating TFT array substrate

Tue, 03 Nov 2009 08:00:00 EST

An exemplary method for fabricating a thin film transistor (TFT) array substrate includes: providing an insulating substrate; forming a plurality of gate electrodes and a plurality of reflective patterns on the insulating substrate using a first photo-mask process; forming a gate insulating layer, an amorphous silicon layer, a doped amorphous silicon layer, and a source/drain metal layer on the insulating substrate having the gate electrodes and the reflective patterns; forming a plurality of source electrodes and a plurality of drain electrodes on the doped amorphous silicon layer; depositing a passivation layer on the source electrodes, the drain electrodes and the gate insulating layer; and forming a pixel electrode on the passivation layer.

Method of manufacturing semiconductor device

Tue, 03 Nov 2009 08:00:00 EST

The invention provides a method of manufacturing a semiconductor device having a semiconductor resistor layer, which reduces a difference between a theoretical resistance value and a measured resistance value. An interlayer insulation film is formed on the whole surface of a semiconductor substrate, and then the interlayer insulation film is selectively etched to form contact holes partially exposing a polysilicon resistor layer, a source region and a drain region. The patterning size of the polysilicon resistor layer is designed by defining the lengths between the adjacent contact holes on the polysilicon resistor layer as the lengths of resistor elements. Then, ion implantation is performed to the polysilicon resistor layer through the contact holes to form low resistance regions (regions where high concentration of impurities are implanted) on the polysilicon resistor layer. After the ion implantation, heat treatment (annealing) is performed at lower temperature than in heat treatment for forming the source region and the drain region.

Microelectronic devices using sacrificial layers and structures fabricated by same

Tue, 03 Nov 2009 08:00:00 EST

A dielectric layer is formed on a region of a microelectronic substrate. A sacrificial layer is formed on the dielectric layer, and portions of the sacrificial layer and the dielectric layer are removed to form an opening that exposes a portion of the region. A conductive layer is formed on the sacrificial layer and in the opening. Portions of the sacrificial layer and the conductive layer on the dielectric layer are removed to leave a conductive plug in the dielectric layer and in contact with the region. Removal of the sacrificial layer and portions of the conductive layer on the dielectric layer may include polishing to expose the sacrificial layer and to leave a conductive plug in the sacrificial layer and the dielectric layer, etching the sacrificial layer to expose the dielectric layer and leave a portion of the conductive plug protruding from the dielectric layer, and polishing to remove the protruding portion of the conductive plug. Phase-change memory devices formed by such techniques are also discussed.

Method of growing a nitride single crystal on silicon wafer, nitride semiconductor light emitting diode manufactured using the same and the manufacturing method

Tue, 03 Nov 2009 08:00:00 EST

The invention provides a method for growing a nitride single crystal on a silicon wafer and a method for manufacturing a light emitting device using the same. In growing the nitride single crystal according to one aspect of the invention, first, a silicon substrate having a surface in (111) crystal orientation is prepared. A first nitride buffer layer is formed on the surface of the silicon substrate. Then, an amorphous oxide film is disposed on the first nitride buffer layer. A second buffer layer is disposed on the amorphous oxide film. Thereafter, the nitride single crystal is formed on the second nitride buffer layer.

Strained silicon with elastic edge relaxation

Tue, 03 Nov 2009 08:00:00 EST

A thin blanket epitaxial layer of SiGe is grown on a silicon substrate to have a biaxial compressive stress in the growth plane. A thin epitaxial layer of silicon is deposited on the SiGe layer, with the SiGe layer having a thickness less than its critical thicknesses. Shallow trenches are subsequently fabricated through the epitaxial layers, so that the strain energy is redistributed such that the compressive strain in the SiGe layer is partially relaxed elastically and a degree of tensile strain is induced to the neighboring layers of silicon. Because this process for inducing tensile strain in a silicon over-layer is elastic in nature, the desired strain may be achieved without formation of misfit dislocations.

Photovoltaic component and production method therefor

Tue, 03 Nov 2009 08:00:00 EST

The invention relates to an organic component comprising an improved top electrode and to a production method therefor. The top electrode is made of an organic material that is applied by means of printing techniques.

Memory device having a semiconducting polymer film

Tue, 03 Nov 2009 08:00:00 EST

A memory device includes a semiconducting polymer film, which includes an organic dopant. The semiconducting polymer film has a first side and a second side. The memory device also includes a first plurality of electrical conductors substantially parallel to each other coupled to the first side of the semiconducting polymer layer, and a second plurality of electrical conductors substantially parallel to each other, coupled to the second side of the semiconducting polymer layer. The first and second pluralities of electrical conductors are substantially mutually orthogonal to each other. Further, an electrical charge is localized on the organic dopant.

Multi-gate thin film transistor having recrystallized channel regions with different grain sizes

Tue, 03 Nov 2009 08:00:00 EST

An image display system has a multi-gate thin film transistor (TFT) disposed on a transparent substrate. The multi-gate TFT includes a silicon film layer, a first electrode and a reflecting layer. The silicon film layer is formed on the transparent substrate and has a first crystallization zone and a second crystallization zone, which are not adjacent to each other. A grain size of the first crystallization zone is smaller than a grain size of the second crystallization zone. The first electrode corresponding to the first crystallization zone is disposed on the silicon film layer. The reflecting layer corresponding to the second crystallization zone is disposed on the transparent substrate. The silicon film layer is disposed on the transparent substrate and the reflecting layer.

Active photosensitive structure with buried depletion layer

Tue, 03 Nov 2009 08:00:00 EST

An imager pixel has a photosensitive JFET structure having a channel region located above a buried charge accumulation region. The channel region has a resistance characteristic that changes depending on the level of accumulated charge in the accumulation region. During an integration period, incident light causes electrons to be accumulated inside the buried accumulation region. The resistance characteristic of the channel region changes in response to a field created by the charges accumulated in the accumulation region. Thus, when a voltage is applied to one side of the channel, the current read out from the other side is characteristic of the amount of stored charges.

Method of forming semiconductor device

Tue, 03 Nov 2009 08:00:00 EST

Embodiments relate to a method of forming a 90 nm semiconductor device, including forming an isolation film within a semiconductor substrate in which a pMOS region and an nMOS region are defined. A first mask is formed to shield the nMOS region by using a DUV photoresist having a thickness of approximately 0.7 to 0.75 μm. Ions are implanted into the pMOS region to form a p type well. A second mask is formed to shield the pMOS region by using a DUV photoresist having a thickness of approximately 0.7 to 0.75 μm. Ions are implanted into the nMOS region to form an n type well. A gate oxide film and a gate is formed over the semiconductor substrate. A low-concentration impurity may be implanted by using the gate as a mask. An LDD region may be formed. A sidewall spacer may be formed over both sidewalls of the gate. A high-concentration impurity is implanted by using the sidewall spacer as a mask, forming a source/drain region.

Method for doping a fin-based semiconductor device

Tue, 03 Nov 2009 08:00:00 EST

A method for doping a fin-based semiconductor device is disclosed. In one aspect, the method comprises patterning at least one fin, each fin comprising a top surface and a left sidewall surface and a right sidewall surface. The method further comprises providing a first target surface being the right sidewall of a first block of material. The method further comprises scanning a first primary ion beam impinging on the first target surface with an incident angle α different from zero degrees and thereby inducing a first secondary ion beam, and doping at least the left sidewall surface and possibly the top surface of the fin opposite to the first target surface with the first secondary ion beam.

Circuit apparatus and method of fabricating the apparatus

Tue, 03 Nov 2009 08:00:00 EST

The likelihood of exfoliation of a sealing resin layer at a pad electrode part is reduced so that the reliability of a circuit apparatus is improved. A circuit apparatus includes a wiring layer, a gold plating layer, an insulating resin layer, a circuit element, a conductive member and sealing resin layer. The gold plating layer is formed in an wiring layer area for the pad electrode. The surface outside the area is roughened. The insulating resin layer is formed so as to cover the wiring layer and to have an opening in an area in which the pad electrode is formed. The circuit element is mounted on a predetermined area on the insulating resin layer. The sealing resin layer is formed on the insulating resin layer so as to entirely cover the circuit element and the opening for the pad electrode. The sealing resin layer, in the area for the pad electrode, is in contact with the gold plating layer and the wiring layer.

Semiconductor package including dummy board and method of fabricating the same

Tue, 03 Nov 2009 08:00:00 EST

Provided are a semiconductor package and a method of fabricating the same. The semiconductor package includes a semiconductor chip, and a plurality of conductive balls, e.g., solder balls formed on a joint surface of the semiconductor chip. A dummy board includes openings aligned with the solder balls and is bonded to the joint surface of the semiconductor chip. An adhesive material is interposed between the semiconductor chip and the dummy board to adhere the dummy board to the semiconductor chip. The adhesive material is applied on an adhesion surface of the dummy board adhered to a joint surface of the semiconductor chip. The dummy board is adhered to the joint surface of the semiconductor chip such that the solder balls are aligned with the openings. Cheap underfill materials can be selectively used, and a process time for reflow and curing of the adhesive material can be greatly reduced.

Semiconductor device with improved contact fuse

Tue, 03 Nov 2009 08:00:00 EST

One aspect of the invention provides an integrated circuit(IC) [ 400 b ]. The IC comprises transistors [ 410 b ] and contact fuses [ 422 b ]. The contact fuses each comprise a conducting layer [ 424 b ], a frustum-shaped contact [ 426 b ] has a narrower end that contacts the conducting layer and a first metal layer [ 427 b ] that is located over the conducting layer. A wider end of the frustum-shaped contact contacts the first metal layer. The frustum-shaped contact has a ratio of an opening of the wider end to the narrower end that is at least about 1.2. The contact fuses each further include a heat sink [ 432 b ] that is located over and contacts the first metal layer.

Multilayer structure and fabrication thereof

Tue, 03 Nov 2009 08:00:00 EST

A process for fabricating a multilayer structure is provided as well as the structure itself. In accordance with one embodiment, the process includes growing a growth layer on a silicon substrate by epitaxial growth, forming at least one pattern from the growth layer, depositing an oxide layer on the silicon substrate, transferring a silicon active layer onto the oxide layer, forming a cavity in the silicon active layer oxide layer above the pattern, and growing a III-V material in the cavity.

Single spacer process for multiplying pitch by a factor greater than two and related intermediate IC structures

Tue, 03 Nov 2009 08:00:00 EST

Single spacer processes for multiplying pitch by a factor greater than two are provided. In one embodiment, n, where n≧2, tiers of stacked mandrels are formed over a substrate, each of the n tiers comprising a plurality of mandrels substantially parallel to one another. Mandrels at tier n are over and parallel to mandrels at tier n−1, and the distance between adjoining mandrels at tier n is greater than the distance between adjoining mandrels at tier n−1. Spacers are simultaneously formed on sidewalls of the mandrels. Exposed portions of the mandrels are etched away and a pattern of lines defined by the spacers is transferred to the substrate.

Polysilicon dummy wafers and process used therewith

Tue, 03 Nov 2009 08:00:00 EST

Non-production wafers of polycrystalline silicon are placed in non-production slots of a support tower for thermal processing monocrystalline silicon wafers. They may have thicknesses of 0.725 to 2 mm and be roughened on both sides. Nitride may be grown on the non-production wafers to a thickness of over 2 μm without flaking. The polycrystalline silicon is preferably randomly oriented Czochralski polysilicon grown using a randomly oriented seed, for example, CVD grown silicon. Both sides are ground to introduce sub-surface damage and then oxidized and etch cleaned. An all-silicon hot zone of a thermal furnace, for example, depositing a nitride layer, may include a silicon support tower placed within a silicon liner and supporting the polysilicon non-production wafers with silicon injector tube providing processing gas within the liner.

Trench polysilicon diode

Tue, 03 Nov 2009 08:00:00 EST

Embodiments of the present invention include a method of manufacturing a trench transistor. The method includes forming a substrate of a first conductivity type and implanting a dopant of a second conductivity type, forming a body region of the substrate. The method further includes forming a trench in the body region and depositing an insulating layer in the trench and over the body region wherein the insulating layer lines the trench. The method further includes filling the trench with polysilicon forming a top surface of the trench and forming a diode in the body region wherein a portion of the diode is lower than the top surface of the trench.

Methods of manufacturing light emitting diodes including barrier layers/sublayers

Tue, 03 Nov 2009 08:00:00 EST

Semiconductor light emitting devices, such as light emitting diodes, include a substrate, an epitaxial region on the substrate that includes a light emitting region such as a light emitting diode region, and a multilayer conductive stack including a reflector layer, on the epitaxial region. A barrier layer is provided on the reflector layer and extending on a sidewall of the reflector layer. The multilayer conductive stack can also include an ohmic layer between the reflector and the epitaxial region. The barrier layer further extends on a sidewall of the ohmic layer. The barrier layer can also extend onto the epitaxial region outside the multilayer conductive stack. The barrier layer can be fabricated as a series of alternating first and second sublayers.

MIM device and electronic apparatus

Tue, 03 Nov 2009 08:00:00 EST

An MIM device includes a lower electrode of a metal nitride film, a hysteresis film of an oxide film containing Nb formed on the lower electrode, and an upper electrode of a metal nitride film formed on the hysteresis film.

Reflector packages and semiconductor light emitting devices including the same

Tue, 03 Nov 2009 08:00:00 EST

Reflectors for a semiconductor light emitting device include a lower sidewall portion defining a reflective cavity. A substantially horizontal shoulder portion extends outwardly from the sloped lower sidewall portion. The horizontal shoulder portion has a circumferentially extending moat formed therein. An upper sidewall portion extends upwardly from the horizontal shoulder portion.

Non-volatile memory cell

Tue, 03 Nov 2009 08:00:00 EST

A semiconductor device comprises a semiconductor substrate, and a non-volatile memory cell provided on the semiconductor substrate, the non-volatile memory cell comprising a tunnel insulating film having a film thickness periodically and continuously changing in a channel width direction of the non-volatile memory cell, a floating gate electrode provided on the tunnel insulating film, a control gate electrode provided above the floating gate electrode, and an interelectrode insulating film provided between the control gate electrode and the floating gate electrode.

Nanoelectromechanical bistable cantilever device

Tue, 03 Nov 2009 08:00:00 EST

Nano-electromechanical device having an electrically conductive nano-cantilever wherein the nano-cantilever has a free end that is movable relative to an electrically conductive substrate such as an electrode of a circuit. The circuit includes a power source connected to the electrode and to the nano-cantilever for providing a pull-in or pull-out voltage therebetween to effect bending movement of the nano-cantilever relative to the electrode. Feedback control is provided for varying the voltage between the electrode and the nano-cantilever in response to the position of the cantilever relative to the electrode. The device provides two stable positions of the nano-cantilever and a hysteresis loop in the current-voltage space between the pull-in voltage and the pull-out voltage. A first stable position of the nano-cantilever is provided at sub-nanometer gap between the free end of the nano-cantilever and the electrode with a pull-in voltage applied and with a stable tunneling electrical current present in the circuit. A second stable position of the nano-cantilever is provided with a pull-out voltage between the cantilever and the electrode with little or no tunneling electrical current present in the circuit. The nano-electromechanical device can be used in a scanning probe microscope, ultrasonic wave detection sensor, NEMS switch, random access memory element, gap sensor, logic device, and a bio-sensor when the nano-cantilever is functionalized with biomolecules that interact with species present in the ambient environment be them in air or aqueous solutions. In the latest case, the NEMS needs to be integrated with a microfluidic system.

Method of manufacturing semiconductor optical element

Tue, 03 Nov 2009 08:00:00 EST

A method of manufacturing a semiconductor optical element, includes successively stacking a first semiconductor layer of a first conductivity type, an active layer, and a second semiconductor layer of a second conductivity type; applying a resist to the second semiconductor layer and patterning the resist into stripes by photolithography; forming recesses in the second semiconductor layer and a waveguide ridge adjacent to the recesses by dry-etching the second semiconductor layer only partially through the second semiconductor layer, using the resist as a mask; forming an insulating film on the waveguide ridge and in the recesses while leaving the resist; removing the insulating film from the resist so that the resist is exposed while the insulating film in the recess is left; removing the resist exposed; and forming an electrode on the waveguide ridge after removing the resist.

Method for manufacturing CMOS image sensor which improves sensitivity by removing a passivation membrane in a pixel region of the CMOS image sensor

Tue, 03 Nov 2009 08:00:00 EST

A method for manufacturing a CMOS image sensor is disclosed. The method includes the steps of: forming a passivation oxide and a passivation nitride after forming a pad; performing a hydrogen anneal; selectively removing the passivation nitride and cleaning the passivation oxide; opening and cleaning the pad by removing the passivation oxide from the pad region; forming a pad protection membrane; forming color filter array, planarization layer and a plurality of microlenses; and removing the pad protection membrane from the pad region. A circle defect in a pixel region may be removed according to the disclosed method for manufacturing the CMOS image sensor. Accordingly, the sensitivity of the CMOS image sensor may be increased by raising the quality of the CMOS image sensor and reducing reflectance of the light.

Gate straining in a semiconductor device

Tue, 03 Nov 2009 08:00:00 EST

Gate straining techniques as described herein can be utilized during the fabrication of NMOS transistor devices, PMOS transistor devices, or CMOS device structures. For an NMOS device, conductive vias are formed in TEOS oxide regions surrounding the sidewall spacers of a metal gate structure, where the metal gate structure includes compressive nitride material within the gate opening. After forming the conductive vias the remaining TEOS oxide is removed and tensile nitride material is deposited between the sidewall spacers and the conductive vias. The sidewall spacers serve as retaining walls for the tensile nitride material, which preserves the tensile characteristics of the material. A similar fabrication technique is utilized to form a PMOS device. For a PMOS device, however, the metal gate structure includes tensile nitride material within the gate opening, and compressive nitride material between the sidewall spacers and the conductive vias.

Method for manufacturing a memory cell arrangement

Tue, 03 Nov 2009 08:00:00 EST

In an embodiment of the invention, a method for manufacturing a memory cell arrangement includes forming a charge storing memory cell layer stack over a substrate; forming first and second select structures over, respectively, first and second sidewalls of the charge storing memory cell layer stack, wherein the first and second select structures in each case comprise a select gate configured as a spacer and laterally disposed from the respective sidewall of the charge storing memory cell layer stack; and removing a portion of the charge storing memory cell layer stack between the first and second select structures after formation of the first and second select structures, thereby forming first and second charge storing memory cell structures.

Method of manufacturing semiconductor device having side wall spacers

Tue, 03 Nov 2009 08:00:00 EST

Gate insulating films 12 A and 12 B of different thickness are formed in element openings 16 a and 16 b in the isolation film 16 of a wafer 10 . The gate insulating film 12 B is the thinnest gate insulating film. A dummy insulating film having the same thickness as the thinnest gate insulating film 12 B is formed in wafer periphery area WP. Gate electrodes 20 A and 20 B are formed on the gate insulating films 12 A and 12 B, and thereafter an insulating film is deposited on the wafer surface. The deposited insulating film is dry-etched to form side wall spacers 22 a to 22 d on side walls of the gate electrodes 20 A and 20 B. During dry etching, the time when the semiconductor surfaces are exposed in the element opening 16 b and area WP is detected as an etching end point by a change in the emission spectrum intensity of etching byproducts.

Bipolar transistor self-alignment with raised extrinsic base extension and methods of forming same

Tue, 03 Nov 2009 08:00:00 EST

A self-aligned bipolar transistor structure having a raised extrinsic base comprising an outer region and an inner region of different doping concentrations and methods of fabricating the transistor are disclosed. More specifically, the self-alignment of the extrinsic base to the emitter is accomplished by forming the extrinsic base in two regions. First, a first material of silicon or polysilicon having a first doping concentration is provided to form an outer extrinsic base region. Then a first opening is formed in the first material layer by lithography within which a dummy emitter pedestal is formed, which results in forming a trench between the sidewall of the first opening and the dummy pedestal. A second material of a second doping concentration is then provided inside the trench forming a distinct inner extrinsic base extension region to self-align the raised extrinsic base edge to the dummy pedestal edge. Since the emitter is formed where the dummy pedestal existed, the extrinsic base is also self-aligned to the emitter. The silicon or polysilicon forming the inner extrinsic base extension region can also be grown in the trench with selective or non-selective epitaxy.

Semiconductor device having MOS varactor and methods for fabricating the same

Tue, 03 Nov 2009 08:00:00 EST

A semiconductor device with having a MOS varactor and methods of fabricating the same are disclosed. The MOS varactor includes a metal gate electrode, an active semiconductor plate interposed between the metal gate electrode and the semiconductor substrate, and a capacitor dielectric layer interposed between the metal gate electrode and the active semiconductor plate. Further, a lower insulating layer insulates the MOS varactor from the semiconductor substrate. According to the present invention, a metal gate electrode is used to reduce poly depletion, thereby increasing a tuning range of the varactor, and to manufacture a reliable metal resistor without the need of an additional photomask.

Wafer laser processing method and laser beam processing machine

Tue, 03 Nov 2009 08:00:00 EST

A wafer laser processing method for forming deteriorated layers in the inside of a wafer having devices which are formed in a plurality of areas sectioned by a plurality of streets formed in a lattice pattern on the front surface along the streets by applying a laser beam along the streets, comprising: a first deteriorated layer forming step for forming a first deteriorated layer along the streets near the front surface of the wafer by applying a laser beam having a wavelength of 1,064 nm from the rear surface side of the wafer along the streets with its focal spot set to a position near the front surface of the wafer; and a second deteriorated layer forming step for forming a second deteriorated layer along the streets at a position closer to the rear surface of the wafer than the first deteriorated layer by applying a laser beam having a wavelength of 1,342 nm from the rear surface side of the wafer along the streets with its focal spot set to a position closer to the rear surface than the first deteriorated layer.

Imaging apparatus and photoelectric conversion element package retaining unit

Tue, 03 Nov 2009 08:00:00 EST

A photoelectric conversion element package retaining unit includes a photoelectric conversion element package having electrodes formed on a rear surface of a light-receiving surface, a printed circuit board electrically connected to the electrodes, and a retaining member configured to retain the photoelectric conversion element package. The printed circuit board includes a first opening formed in an area corresponding to an inside of the electrodes. The retaining member includes a positioning unit configured to position the photoelectric conversion element package in an axial direction orthogonal to the light-receiving surface by abutting on the photoelectric conversion element package outside the electrodes, and a second opening formed to pour an adhesive into the area corresponding to the inside of the electrodes.

Transition region for use with an antenna-integrated electron tunneling device and method

Tue, 03 Nov 2009 08:00:00 EST

An electron tunneling device includes a first non-insulating strip and a second non-insulating strip spaced apart from one another such that first and second end portions, respectively, of the first and second non-insulating strips cooperate to form an antenna having an antenna impedance. The first and second non-insulating strips include a transition region that extends from the antenna to a tunneling region in which the first and second non-insulating strips are in a confronting relationship. An arrangement cooperates with a portion of each of the first and second non-insulating strips in the tunneling region to form an electron tunneling structure exhibiting a tunneling region impedance. The transition region is configured to match the antenna impedance to the tunneling region impedance. The transition region can provide for changing an electromagnetic field orientation between the antenna and the tunneling region.

Bonding interface for micro-device packaging

Tue, 03 Nov 2009 08:00:00 EST

In one embodiment, a method for making a cover for a micro-device package includes forming a layer of silicon on a transparent substrate and selectively removing parts of the silicon layer to form a bonding ring and an alignment target.

Method of manufacturing a thin film transistor

Tue, 03 Nov 2009 08:00:00 EST

A method of manufacturing a thin film transistor is provided. The method includes forming an amorphous silicon layer on a substrate, forming a source region, a drain region, and a region of a plurality of channels electrically interposed between the source region and the drain region by patterning the amorphous silicon layer, annealing a region of the channels, sequentially forming a gate oxide film and a gate electrode on a channel surface, and doping the source region and the drain region.

Semiconductor device manufactured using a laminated stress layer

Tue, 03 Nov 2009 08:00:00 EST

There is presented a method of forming a semiconductor device. The method comprises forming gate structures including forming gate electrodes over a semiconductor substrate and forming spacers adjacent the gate electrodes. Source/drains are formed adjacent the gate structures, and a laminated stress layer is formed over the gate structure and the semiconductor substrate. The formation of the laminated stress layer includes cycling a deposition process to form a first stress layer over the gate structures and the semiconductor substrate and at least a second stress layer over the first stress layer. After the laminated layer is formed, it is subjected to an anneal process conducted at a temperature of about 900° C. or greater.

CMOS image sensor and manufacturing method thereof

Tue, 03 Nov 2009 08:00:00 EST

Disclosed are a CMOS image sensor and a manufacturing method thereof. The method includes forming an isolation layer in a semiconductor substrate, defining an active region including a photo diode region and a transistor region; forming a gate insulating layer and a gate electrode on the transistor region; forming a first low-concentration diffusion region in the photo diode region; forming a second low-concentration diffusion region in the transistor region; forming an insulating layer over an entire surface of the substrate; implanting fluorine ions in an upper surface of the photo diode region; etching the insulating layer to form insulating sidewalls on sides of the gate electrode; forming a high-concentration diffusion region in the transistor region partially overlapping with the second low-concentration diffusion region; and forming a third low-concentration diffusion region on the upper surface of the photo diode region, the third low-concentration diffusion region having a conductivity type opposite to the first low-concentration diffusion region.

Semiconductor integrated circuit device and a method of manufacturing the same

Tue, 03 Nov 2009 08:00:00 EST

A semiconductor integrated circuit device having a capacitor element, including a lower electrode provided over an element isolation region of a principal surface of a semiconductor substrate, and an upper electrode provided over the lower electrode with a dielectric film interposed therebetween, has oxidation resistant films disposed between the element isolation region of the principal surface of the semiconductor substrate and the lower electrode, and between the lower electrode and the upper electrode.

Method of forming isolation layer of semiconductor memory device

Tue, 03 Nov 2009 08:00:00 EST

The present invention relates to a method of forming an isolation layer of a semiconductor memory device. According to a method of fabricating a semiconductor memory device in accordance with an aspect of the present invention, a tunnel insulating layer and a charge trap layer are formed over a semiconductor substrate. An isolation trench is formed by etching the charge trap layer and the tunnel insulating layer. A passivation layer is formed on the entire surface including the isolation trench. A first insulating layer is formed at a bottom of the isolation trench. Portions of the passivation layer, which are oxidized in the formation process of the first insulating layer, are removed. A second insulating layer is formed on the entire surface including the first insulating layer.

Dual pulsed beam laser micromachining method

Tue, 03 Nov 2009 08:00:00 EST

A method is described for laser scribing or dicing portions of a workpiece using multi-source laser systems. In one embodiment, a first laser melts portions of the workpiece prior to a second laser ablating the portions of the workpiece.

Manufacture method for semiconductor device having improved copper diffusion preventive function of plugs and wirings made of copper or copper alloy

Tue, 03 Nov 2009 08:00:00 EST

(a) A copper alloy film containing at least two types of metal elements in addition to copper is formed on the surface of an insulator containing oxygen and formed on a semiconductor substrate. (b) A metal film made of pure copper or copper alloy is formed on the copper alloy film. (c) After the step (a) or (b), heat treatment is performed under the condition that a metal oxide film is formed on a surface of the insulator through reaction between the oxygen in the insulator and the metal elements in the copper alloy film.

Technique for increasing adhesion of metallization layers by providing dummy vias

Tue, 03 Nov 2009 08:00:00 EST

By providing dummy vias below electrically non-functional metal regions, the risk for metal delamination in subsequent processes may be significantly reduced. Moreover, in some embodiments, the mechanical strength of the resulting metallization layers may be even more enhanced by providing dummy metal regions, which may act as anchors for an overlying non-functional metal region. In addition, dummy vias may also be provided in combination with electrically functional metal lines and regions, thereby also enhancing the mechanical stability and the electrical performance thereof.

Radiation detector crystal and method of formation thereof

Tue, 03 Nov 2009 08:00:00 EST

A radiation detector crystal is made from CdxZn1-xTe, where 0≦x≦1; an element from column III or column VII of the periodic table, desirably in a concentration of about 1 to 10,000 atomic parts per billion; and the element Ruthenium (Ru), the element Osmium (Os) or the combination of Ru and Os, desirably in a concentration of about 1 to 10,000 atomic parts per billion using a conventional crystal growth method, such as, for example, the Bridgman method, the gradient freeze method, the electro-dynamic gradient freeze method, the so-call traveling heater method or by the vapor phase transport method. The crystal can be used as the radiation detecting element of a radiation detection device configured to detect and process, without limitation, X-ray and Gamma ray radiation events.

Ferroelectric rare-earth manganese-titanium oxides

Tue, 03 Nov 2009 08:00:00 EST

Ferroelectric rare-earth manganese-titanium oxides and methods of their manufacture. The ferroelectric materials can provide nonvolatile data storage in rapid access memory devices.

Method of minimizing kerf width on a semiconductor substrate panel

Tue, 03 Nov 2009 08:00:00 EST

A semiconductor die substrate panel is disclosed including a minimum kerf width between adjoining semiconductor package outlines on the panel, while ensuring electrical isolation of plated electrical terminals. By reducing the width of a boundary between adjoining package outlines, additional space is gained on a substrate panel for semiconductor packages.

Reflective electrode for a semiconductor light emitting apparatus

Tue, 03 Nov 2009 08:00:00 EST

A process is disclosed for forming a reflective electrode on a semiconductor light emitting device, the light emitting device having an active layer for generating light and a cladding layer in electrical contact with the active layer. The process involves depositing an intermediate layer of electrically conductive material on the cladding layer and causing at least a portion of the electrically conductive material to diffuse into the cladding layer. The process further involves depositing a reflective layer on the intermediate layer, the reflective layer being electrically conductive and in electrical contact with the intermediate layer.

Organic thin film transistor comprising device insulation film and method of manufacturing the same

Tue, 03 Nov 2009 08:00:00 EST

An organic thin film transistor (OTFT) includes a substrate, a gate electrode formed on the transparent substrate, a gate insulation film formed on the gate electrode, a source electrode and a drain electrode formed spaced apart from each other on the gate insulation film, a device insulation film formed over the gate, source, and drain electrodes, and an organic semiconductor film formed on the device insulation film.

Semiconductor device and boost circuit

Tue, 03 Nov 2009 08:00:00 EST

A semiconductor device, includes: a field-effect transistor that configures a charge-pump circuit; and a supporting substrate that supports the field-effect transistor so that the field-effect transistor provided on the supporting substrate becomes warpable in a channel direction.

Apparatus for confining inductively coupled surface currents

Tue, 03 Nov 2009 08:00:00 EST

A deep n-well is formed beneath the area of an inductor coil. The use of a deep n-well lessens the parasitic capacitance by placing a diode in series with the interlayer dielectric cap. The deep n-well also reduces substrate noise. Once the n-well is implanted and annealed, a cross hatch of shallow trench isolation is patterned over the n-well. The shallow trench isolation reduces and confines the inductively coupled surface currents to small areas that are then isolated from the rest of the chip.

Photonic coupling scheme for photodetectors

Tue, 03 Nov 2009 08:00:00 EST

A room temperature operation polycrystalline infrared responsive photodetector, manufactured by a process, comprising the steps of patterning vacuum-deposited material and dry-etching a photonic crystal structure with resonant coupling tuned to long wavelengths.

Method of making a semiconductor element

Tue, 03 Nov 2009 08:00:00 EST

A method of producing a capacitor that includes producing a first electrode having a first surface; forming a recess in an element, walls of the element and the first surface of the first electrode defining the recess, the element having a first surface exterior of the recess; forming a dielectric layer on the element, the dielectric layer oriented against the first surface of the element and against the walls of the element within the recess; polishing off at least a portion of the dielectric layer oriented against the first surface of the element to electrically isolate the portion of the dielectric layer located in the recess from any portion of the dielectric layer remaining outside the recess; and producing a second electrode, the second electrode oriented at least partially within the recess with the dielectric layer oriented between the first electrode and the second electrode.

Structures to enhance cooling of computer memory modules

Tue, 03 Nov 2009 08:00:00 EST

A spring-like cooling structure for an in-line chip module is formed from a continuous sheet of a thermally conducting material having a front side and a back side, the sheet folded at substantially a one-hundred and eighty degree angle, wherein a length of the structure substantially correlates to a length of the in-line chip module, and a width of the structure is wider than a width of the in-line chip module such that the structure fits over and substantially around the in-line chip module; openings at a left-side, right-side and a bottom of the structure for easily affixing and removing the structure from the in-line chip module; a top part comprising a top surface disposed over a top of the in-line chip module when affixed to the in-line chip module, and comprising an angled surface flaring outward from the in-line chip module, the angled surface positioned directly beneath the top surface; a center horizontal part; a gap between the center horizontal part and the plurality of chips; and a flared bottom area of the structure.

Electronic device and method of manufacturing the same, chip carrier, circuit board, and electronic instrument

Tue, 03 Nov 2009 08:00:00 EST

An external terminal is formed on an interconnect pattern formed on a substrate by using a soldering material. Subsequently, a chip component having an electrode is mounted on the substrate. An interconnect for electrically connecting the electrode and the interconnect pattern is formed at a temperature lower than a melting point of the soldering material.

Method of manufacturing semiconductor device

Tue, 03 Nov 2009 08:00:00 EST

A method of manufacturing a semiconductor device of the present invention consists of forming a trench in a trench-type cell transistor region; forming a gate insulating film and a gate material layer on a semiconductor substrate; forming a photoresist layer on the semiconductor substrate so as to expose extension region formation portions of the trench-type cell transistor region and a high breakdown voltage transistor region; forming extension regions in each region by performing ion implantation in the semiconductor substrate surface of the trench-type cell transistor region and the high breakdown voltage transistor region and then patterning gates, and forming extension regions of an ordinary breakdown voltage transistor by covering the trench-type cell transistor region and the high breakdown voltage transistor region with a photoresist layer and implanting ions in the ordinary breakdown voltage transistor region.

Illumination system comprising a radiation source and a fluorescent material

Tue, 03 Nov 2009 08:00:00 EST

An illumination system includes a radiation source and a fluorescent material including at least one phosphor capable of absorbing a part of light emitted by the radiation source and emitting light of wavelength different from that of the absorbed light. The phosphor includes a yellow red-emitting cerium-activated carbido-nitridosilicate of general formula (RE 1−z ) 2−a EA a Si 4 N 6+a C 1−a :Ce z where 0≦a<1, 0

Oxynitride phosphor and light emitting device

Tue, 03 Nov 2009 08:00:00 EST

The present invention provides an oxynitride phosphor represented by a composition formula M(1) 1-j M(2) j Si b Al c O d N e (composition formula I) or a composition formula M(1) 1-a-j M(2) j Ce a Si b Al c O d N e (composition formula II) and containing 50% or more of a JEM phase, and a light emitting device including a semiconductor light emitting element emitting an excited light, a first phosphor that is the oxynitride phosphor according to the present invention that absorbs the excited light and emits a fluorescence, and a kind or a plurality of kinds of second phosphor(s) that absorb(s) the excited light and emit(s) a fluorescence having a longer wavelength than the fluorescence emitted by the first phosphor. Thereby, a novel oxynitride phosphor being capable of highly efficiently emitting mainly a light having a wavelength of 510 nm or less and a light emitting device using the same can be provided.

Electroluminescent devices and displays with integrally fabricated address and logic devices fabricated by printing or weaving

Tue, 03 Nov 2009 08:00:00 EST

Improved electroluminescent and photonic devices with integrated logic and control circuits are disclosed. Low mobility, contact barrier, space charge limitation and carrier balancing are provided solutions that increase efficiency, reliability and longevity of the devices. Device power loss and power requirements are reduced. True-ohmic contact materials allow a gate-controlled, light emitting organic triode MESFET configuration that eliminates commonly used ITO thereby increasing luminous output, and providing ease of address and control by integrally fabricated complementary MESFET address and control circuitry. The devices can be fabricated by printing or by weaving appropriate materials, and can be configured as color displays.

Method and system for patterning of magnetic thin films using gaseous transformation to transform a magnetic portion to a non-magnetic portion

Tue, 03 Nov 2009 08:00:00 EST

A method (and resulting structure) of patterning a magnetic thin film, includes using a chemical transformation of a portion of the magnetic thin film to transform the portion to be non-magnetic and electrically insulating.

Method and apparatus for forming stacked die and substrate structures for increased packing density

Tue, 03 Nov 2009 08:00:00 EST

A stacked semiconductor apparatus has at least one die attached to a first side of a carrier substrate. A first circuitized substrate is attached to the first side of the carrier substrate and overlying the at least one die in a manner such that the first circuitized substrate serves as an electrical interconnection device and a heat spreading lid. The first circuitized substrate is further configured so as to facilitate cooling of the at least one die by at least a cross flow of a cooling medium therethrough.

Integrated circuit package with chip-side signal connections

Tue, 03 Nov 2009 08:00:00 EST

Embodiments of the present invention include an apparatus, method, and/or system for an integrated circuit package with signal connections on the chip-side of the package structure.

Method of manufacturing display device

Tue, 03 Nov 2009 08:00:00 EST

In a case of forming a bottom-gate thin film transistor, a step of forming a microcrystalline semiconductor film over a gate insulating film by a plasma CVD method, and a step of forming an amorphous semiconductor film over the microcrystalline semiconductor film are performed. In the step of forming the microcrystalline semiconductor film, the pressure in the reaction chamber is set at or below 10 −5 Pa once, the substrate temperature is set in the range of 120° C. to 220° C., plasma is generated by introducing hydrogen and a silicon gas, hydrogen plasma is made to act on a reaction product formed on a surface of the gate insulating film to perform removal while performing film formation. Moreover, the plasma is generated by applying a first high-frequency electric power of an HF band a second high-frequency electric power of a VHF band superimposed on each other.

Method for fabricating semiconductor wafer with enhanced alignment performance

Tue, 03 Nov 2009 08:00:00 EST

A manufacturing method of a semiconductor wafer includes forming a plurality of alignment trenches in the wafer substrate. A dielectric layer is formed over the substrate filling the trenches. A planarization process is performed to remove the dielectric layer above the substrate. A photolithograph process is subsequently performed to selectively remove the dielectric layer formed in the trenches in the alignment area.

Method for fabricating semiconductor device

Tue, 03 Nov 2009 08:00:00 EST

A method for fabricating a semiconductor device can prevent a leakage current and the decrease of threshold voltage by rounding corners of a trench. The method may include the steps of forming a pad insulating layer in a semiconductor substrate defined with an active region and a device isolation region, forming a first trench, forming polymer at inner sidewalls of the first trench, forming a second trench, removing the polymer, forming an oxide layer by thermally oxidizing the semiconductor substrate, and forming insulating layers for device isolation in the first and second trenches.

Semiconductor device and manufacturing method thereof

Tue, 03 Nov 2009 08:00:00 EST

It is an object of the present invention to manufacture, with high yield, semiconductor devices in each of which an element which has a layer containing an organic compound is provided over a flexible substrate. A method for manufacturing a semiconductor device includes: forming a separation layer over a substrate; forming an element-forming layer by forming an inorganic compound layer, a first conductive layer, and a layer containing an organic compound over the separation layer, and forming a second conductive layer which is in contact with the layer containing an organic compound and the inorganic compound layer; and after attaching a first flexible substrate over the second conductive layer, separating the separation layer and the element-forming layer at the separation layer.

Gate electrode dopant activation method for semiconductor manufacturing

Tue, 03 Nov 2009 08:00:00 EST

Embodiments of the invention generally provide a method for forming a doped silicon-containing material on a substrate. In one embodiment, the method provides depositing a polycrystalline layer on a dielectric layer and implanting the polycrystalline layer with a dopant to form a doped polycrystalline layer having a dopant concentration within a range from about 1×10 19 atoms/cm 3 to about 1×10 21 atoms/cm 3 , wherein the doped polycrystalline layer contains silicon or may contain germanium, carbon, or boron. The substrate may be heated to a temperature of about 800° C. or higher, such as about 1,000° C., during the rapid thermal anneal. Subsequently, the doped polycrystalline layer may be exposed to a laser anneal and heated to a temperature of about 1,000° C. or greater, such within a range from about 1,050° C. to about 1,400° C., for about 500 milliseconds or less, such as about 100 milliseconds or less.

Lighting device, image pickup apparatus and portable terminal unit

Tue, 03 Nov 2009 08:00:00 EST

A lighting device including a supporting member, a light emitting element disposed on the supporting member, and emitting light from an upper and side surfaces thereof, a first fluorescent layer containing an organic phosphor and disposed on the supporting member, and a second fluorescent layer containing only an inorganic phosphor and disposed on the supporting member, wherein the second fluorescent layer is disposed to cover the upper and side surfaces of the light emitting element, and the first fluorescent layer is disposed on at least side surface of the light emitting element with the second fluorescent layer being interposed between the light emitting element and the first fluorescent layer.

Semiconductor light emitting element and method of manufacturing the same

Tue, 03 Nov 2009 08:00:00 EST

A semiconductor light emitting element including a conductive substrate, a bonding metal layer formed on the conductive substrate, a barrier layer formed on the bonding metal layer, a reflective layer formed on the barrier layer, an ohmic electrode layer formed on the reflective layer, a second conductivity type semiconductor layer formed on the ohmic electrode layer, a light emitting layer formed on the second conductivity type semiconductor layer, and a first conductivity type semiconductor layer formed on the light emitting layer, wherein outer peripheries of the second conductivity type semiconductor layer, the light emitting layer, and the first conductivity type semiconductor layer are removed, and a method of manufacturing the same are provided.

Thin film transistor array substrate

Tue, 03 Nov 2009 08:00:00 EST

A thin film transistor array (TFT) substrate and a method for manufacturing the same are provided. The manufacturing method needs only or even less than six mask processes for manufacturing the TFT array substrate integrated with a color filter pattern. Therefore, the manufacturing method is simpler and the manufacturing cost is reduced. In addition, the manufacturing method needs not to form a contact window in a relative thick film layer such as a planarization layer or a color filter layer, so as to connect the pixel electrode to the source/drain, thus the difficulty of the manufacturing process is effectively reduced.

Method of fabricating turning mirror using sacrificial spacer layer and device made therefrom

Tue, 03 Nov 2009 08:00:00 EST

The present invention is a method of fabricating a waveguide using a sacrificial spacer layer. The first step in this process is to fabricate the underlying optical semiconductor structure. A trench is then etched in this structure resulting in an underlying L-shaped structure. A sacrificial spacer layer is deposited in the trench. The waveguide is created in the trench on the sacrificial spacer layer using a mask layer to angle the vertex of the L-shaped structure. User-defined portions of the sacrificial spacer layer are subsequently removed to create air gaps between the waveguide and the sidewalls of the trench in the optical semiconductor.

Image sensor and method for manufacturing the same

Tue, 03 Nov 2009 08:00:00 EST

A method for manufacturing an image sensor includes forming first to third photodiodes and first to third color filters corresponding thereto; forming a photoresist film including photosensitive materials on the upper surfaces of the first to third color filters; forming a first exposed part by exposing the photoresist film with a first exposure energy using a first pattern mask with a first light transmitting part having a first width at boundaries between the individual color filters; forming a second exposed part overlapping a portion of the first exposed part by exposing the photoresist film with a second exposure energy smaller than the first exposure energy using a second pattern mask with a second light transmitting part having a second width wider than the first width; and forming microlenses by developing the photoresist film.

Thermosetting die bonding film

Tue, 03 Nov 2009 08:00:00 EST

The thermosetting die bonding film of the invention is a thermosetting die bonding film used to produce a semiconductor device, which contains, as main components, 5 to 15% by weight of a thermoplastic resin component and 45 to 55% by weight of a thermosetting resin component, and has a melt viscosity of 400 Pa·s or more and 2500 Pa·s or less at 100° C. before the film is thermally set.

Process for manufacturing a thin-film transistor (TFT) device and TFT device manufactured by the process

Tue, 03 Nov 2009 08:00:00 EST

A process for manufacturing a thin-film transistor device includes forming a dielectric insulation layer on a substrate, forming an amorphous silicon layer on the dielectric insulation layer, crystallizing the amorphous silicon layer, so as to obtain polycrystalline silicon, forming gate structures on the polycrystalline silicon, and forming first doped regions within the polycrystalline silicon laterally with respect to the gate structures. The crystallizing step includes forming first capping dielectric regions on the amorphous silicon layer, and then irradiating the amorphous silicon layer using a laser so as to form active areas of polycrystalline silicon separated by separation portions of amorphous silicon underlying the first capping dielectric regions.

Method of fabricating metal-oxide-semiconductor transistor

Tue, 03 Nov 2009 08:00:00 EST

A method of fabricating a metal-oxide-semiconductor (MOS) transistor is provided. First, a patterned hard mask layer with an opening therein is formed over the substrate. A spacer is formed on the sidewall of the patterned hard mask layer in the opening. An isotropic etching process is performed on the substrate to form a recess in the substrate. An ion implant process is performed on the substrate in the lower portion of the recess using oxidation-restrained ions. The spacer is removed. Then, a thermal process is performed to form a gate oxide layer on the surface of the substrate within the recess such that the gate oxide layer in the upper portion of the recess is thicker than that in the lower portion of the recess.

Method of fabricating MOS transistor having epitaxial region

Tue, 03 Nov 2009 08:00:00 EST

Example embodiments relate to a method of manufacturing a semiconductor device. Other example embodiments relate to a method of manufacturing a metal-oxide-semiconductor (MOS) transistor having an epitaxial region disposed in a lower portion of sidewalls of a gate pattern. Provided is a method of manufacturing a MOS transistor having an epitaxial region which improves an epitaxial growth rate and which may have fewer defects. The method of manufacturing a MOS transistor having an epitaxial region may include forming a gate pattern on a semiconductor substrate, forming a first ion implantation region having a first damage profile by implanting first impurity ions into the semiconductor substrate using the gate pattern as an ion implantation mask, forming a second ion implantation region having a second damage profile adjacent to the first damage profile by implanting second impurity ions into the semiconductor substrate using the gate pattern as an ion implantation mask and partially etching a lower portion of sidewalls of the gate pattern and forming in-situ an epitaxial region on the etched semiconductor substrate.

Wafer processing method

Tue, 03 Nov 2009 08:00:00 EST

A water processing method for providing a gettering sink effect to a wafer having a plurality of streets which are formed in a lattice pattern on the front surface of a substrate and devices which are formed in a plurality of areas sectioned by the plurality of streets, comprising the steps of removing distortion produced on the rear surface of the substrate of the wafer whose rear surface of the substrate has been ground to a predetermined thickness; forming a gettering sink effect layer by applying a laser beam of a wavelength having permeability for the substrate of the wafer which has undergone the distortion removing step, with its focal point set to the inside of the substrate to form a deteriorated layer in the inside of the substrate; and dividing the wafer which has undergone the gettering sink effect layer forming step, into individual chips along the streets.

Semiconductor devices and methods of manufacture thereof

Tue, 03 Nov 2009 08:00:00 EST

Semiconductor devices and methods of manufacture thereof are disclosed. A preferred embodiment comprises a method of forming an insulating material layer. The method includes forming a barrier layer and forming a rare earth element-containing material layer over the barrier layer.

Process of phosphorus diffusion for manufacturing solar cell

Tue, 03 Nov 2009 08:00:00 EST

This invention discloses a process of phosphorus diffusion for manufacturing solar cell, comprising annealing a mono-crystalline silicon wafer in a nitrogen atmosphere at 900-950° C. for twenty to thirty minutes, carrying oxidation treatment in a hydrogen chloride atmosphere at 850-1050° C. to form a 10 to 30 nm thick oxide layer on the surface of said silicon wafer, diffusing from a phosphorus source at 850-900° C., until a block resistance of a material surface is controlled at 40 to 50 ohms, and the junction depth is at 0.2 to 1.0 microns, and annealing in a nitrogen atmosphere at 700-750° C. for thirty to sixty minutes to complete the phosphorus diffusion of said mono-crystalline silicon wafer. This invention allows the use of 4 N˜5 N mono-crystalline silicon as the material for manufacturing solar cells, so, the low purity material such as metallurgical silicon can be used, which greatly reduces the cost of materials.

Metal gates with low charge trapping and enhanced dielectric reliability characteristics for high-k gate dielectric stacks

Tue, 03 Nov 2009 08:00:00 EST

A multilayered gate stack having improved reliability (i.e., low charge trapping and gate leakage degradation) is provided. The inventive multilayered gate stack includes, from bottom to top, a metal nitrogen-containing layer located on a surface of a high-k gate dielectric and Si-containing conductor located directly on a surface of the metal nitrogen-containing layer. The improved reliability is achieved by utilizing a metal nitrogen-containing layer having a compositional ratio of metal to nitrogen of less than 1.1. The inventive gate stack can be useful as an element of a complementary metal oxide semiconductor (CMOS). The present invention also provides a method of fabricating such a gate stack in which the process conditions of a sputtering process are varied to control the ratio of metal and nitrogen within the sputter deposited layer.

Deposition methods for barrier and tungsten materials

Tue, 03 Nov 2009 08:00:00 EST

Embodiments as described herein provide a method for depositing barrier layers and tungsten materials on substrates. In one embodiment, a method for depositing materials is provided which includes forming a barrier layer on a substrate, wherein the barrier layer contains a cobalt silicide layer and a metallic cobalt layer, exposing the barrier layer to a soak gas containing a reducing gas during a soak process, and forming a tungsten material over the barrier layer. In one example, the barrier layer may be formed by depositing a cobalt-containing material on a dielectric surface of the substrate and annealing the substrate to form the cobalt silicide layer from a lower portion of the cobalt-containing material and the metallic cobalt layer from an upper portion of the cobalt-containing material.

Chip resistor, process for producing the same, and frame for use therein

Tue, 03 Nov 2009 08:00:00 EST

A chip resistor (A 1 ) comprises a first insulation layer ( 2 A) covering the regions between a plurality of electrodes ( 3 ) on a rear surface ( 10 a ) of a resistor ( 1 ), and a second insulation layer covering a pair of side faces of the resistor ( 1 ). Inadvertent adhesion of solder to an improper part of the resistor ( 1 ) can thereby be eliminated. A solder layer ( 4 ) is preferably formed on a pair of end faces ( 10 d ) of the resistor ( 1 ). In so doing, a solder fillet can be formed appropriately.

CMOS image sensor and method of operating the same

Tue, 03 Nov 2009 08:00:00 EST

A complementary metal oxide semiconductor (CMOS) image sensor and a method for operating the same are provided. The CMOS image sensor includes a pixel array unit having a matrix of pixels, wherein each pixel comprises a charge transfer element for transferring charge collected in a photoelectric conversion element to a charge detection element, and a row drive unit for supplying a voltage to the charge transfer element during part of a charge integration period of the photoelectric conversion element, wherein the supplied voltage causes the charge transfer element to have a negative potential.

Mounting device for mounting heat sink onto electronic component

Tue, 03 Nov 2009 08:00:00 EST

A mounting device ( 10 ) for mounting a heat sink ( 40 ) onto a printed circuit board ( 60 ) with a heat generating electronic component ( 50 ) mounted thereon. The mounting device includes a mounting frame ( 101 ) and two resilient clips ( 102 ) attached to the mounting frame. The mounting frame includes two first mounting arms ( 1011 ) and two second mounting arms ( 1012 ) disposed above the first mounting arms. The first mounting arms are configured for being attached to the printed circuit board. The resilient clips are configured for being sandwiched between the second mounting arms of the mounting frame and the heat sink. The resilient clips each include two resilient arms ( 1023 ) configured for providing a resilient force which urges the heat sink toward the heat generating electronic component.

Transistors, integrated circuits, systems, and processes of manufacture with improved work function modulation

Tue, 03 Nov 2009 08:00:00 EST

A process ( 200 ) for making integrated circuits with a gate, uses a doped precursor ( 124, 126 N and/or 126 P) on barrier material ( 118 ) on gate dielectric ( 116 ). The process ( 200 ) involves totally consuming ( 271 ) the doped precursor ( 124, 126 N and/or 126 P) thereby driving dopants ( 126 N and/or 126 P) from the doped precursor ( 124 ) into the barrier material ( 118 ). An integrated circuit has a gate dielectric ( 116 ), a doped metallic barrier material ( 118, 126 N and/or 126 P) on the gate dielectric ( 116 ), and metal silicide ( 180 ) on the metallic barrier material ( 118 ). Other integrated circuits, transistors, systems and processes of manufacture are disclosed.

Underlayer for high performance magnetic tunneling junction MRAM

Tue, 03 Nov 2009 08:00:00 EST

An MRAM structure is disclosed in which the bottom electrode has an amorphous TaN capping layer to consistently provide smooth and dense growth for AFM, pinned, tunnel barrier, and free layers in an overlying MTJ. Unlike a conventional Ta capping layer, TaN is oxidation resistant and has high resistivity to avoid shunting of a sense current caused by redeposition of the capping layer on the sidewalls of the tunnel barrier layer. Alternatively, the α-TaN layer is the seed layer in the MTJ. Furthermore, the seed layer may be a composite layer comprised of a NiCr, NiFe, or NiFeCr layer on the α-TaN layer. An α-TaN capping layer or seed layer can also be used in a TMR read head. An MTJ formed on an α-TaN capping layer has a high MR ratio, high Vb, and a RA similar to results obtained from MTJs based on an optimized Ta capping layer.

Semiconductor structures with body contacts and fabrication methods thereof

Tue, 03 Nov 2009 08:00:00 EST

A semiconductor structure for a dynamic random access memory (DRAM) cell array that includes a plurality of vertical memory cells built on a semiconductor-on-insulator (SOI) wafer and a body contact electrically coupling a semiconductor body and a semiconductor substrate of the SOI wafer. The semiconductor body includes a channel region for the access device of one of the vertical memory cells. The body contact, which extends through a buried dielectric layer of the SOI wafer, provides a current leakage path that reduces the impact of floating body effects upon the vertical memory cell. The body contact may be formed by etching a via that extends through the semiconductor body and buried dielectric layer of the SOI wafer and extends into the substrate and partially filling the via with a conductive material that electrically couples the semiconductor body with the substrate.

Method to control uniformity/composition of metal electrodes, silicides on topography and devices using this method

Tue, 03 Nov 2009 08:00:00 EST

A method for depositing metals on surfaces is provided which comprises (a) providing a substrate ( 103 ) having a horizontal surface ( 107 ) and a vertical surface ( 105 ); (b) depositing a first metal layer ( 109 ) over the horizontal and vertical surfaces; (c) depositing a layer of polysilicon ( 111 ) over the horizontal and vertical surfaces; (d) treating the layer of polysilicon with a plasma such that a residue ( 113 ) remaining from the treatment is preferentially formed over the horizontal surfaces rather than the vertical surfaces, and wherein the residue is resistant to a first metal etch; and (e) exposing the substrate to the first metal etch.

Method and resulting structure for fabricating DRAM capacitor structure

Tue, 03 Nov 2009 08:00:00 EST

A method for forming a capacitor structure for a dynamic random access memory device. The method includes forming a device layer overlying a semiconductor substrate, e.g., silicon wafer. The method includes forming a first interlayer dielectric overlying the device layer and forming a via structure within the first interlayer dielectric layer. The method includes forming a first oxide layer overlying the first interlayer dielectric layer and forming a stop layer overlying the first oxide layer. The method includes forming a second oxide layer overlying the first stop layer and forming a trench region through a portion of the second oxide layer, through a portion of the stop layer, and a portion of the second oxide layer. A bottom electrode structure is formed to line the trench region. The bottom electrode structure includes an inner region. The bottom electrode structure is coupled to the via structure. The method includes protecting the bottom electrode structure with a masking layer and selectively removing the second oxide layer to the stop layer, the stop layer acts as an etch stop, to expose an outer region of the bottom electrode structure. The method includes forming a capacitor dielectric layer overlying the outer region of the bottom electrode structure and overlying the inner region of the bottom electrode structure. The method includes forming an upper capacitor plate overlying the capacitor dielectric layer to form a capacitor structure.

Method for forming shallow trench isolation in semiconductor device

Tue, 03 Nov 2009 08:00:00 EST

A method for forming shallow trench isolation in a semiconductor device. The method includes forming a pad oxide and a pad nitride on a semiconductor substrate in successive order, forming a trench in the substrate by etching the pad nitride, the pad oxide and the substrate, removing a portion of the pad oxide to expose top corners of the trench, and rounding the exposed portion of the top corners of the trench by a wet chemical etch.

Method of forming a bipolar transistor and semiconductor component thereof

Tue, 03 Nov 2009 08:00:00 EST

A semiconductor component is formed using the following processes: (a) forming a first dielectric layer over the semiconductor substrate; (b) forming a base electrode for the bipolar transistor over the dielectric layer; (c) forming an oxide nitride structure over the base electrode; (d) forming a first spacer adjacent to the oxide nitride structure and the base electrode; (e) removing a top layer of the oxide nitride structure; (f) removing a first portion of the dielectric layer; (g) forming an epitaxial layer over the semiconductor substrate; (h) forming a second spacer over the epitaxial layer; and (i) forming an emitter electrode over the epitaxial layer and adjacent to the second spacer.

Method for forming gate electrode of semiconductor device

Tue, 03 Nov 2009 08:00:00 EST

Provided is a method for forming a gate electrode of a semiconductor device which can form a gate electrode having a fine line width. Disclosed method steps include forming a gate oxide film, a polysilicon film for a gate electrode, and a first sacrificial layer on the entire surface of a semiconductor substrate and then forming an opening within the first sacrificial layer. The effective width of the hole is reduced, and an ion implantation layer is formed on the top surface of the polysilicon film in the region exposed through the hole. A gate electrode is formed under the ion implantation layer by using the ion implantation layer as a mask.

Method of forming sheet having foreign material portions used for forming multi-layer wiring board and sheet having foreign portions

Tue, 03 Nov 2009 08:00:00 EST

The present invention relates to a laminated type electronic part and aims at providing a sheet manufacturing method and a sheet that contribute to high integration, downsizing and enhancement of reliability of the electronic part. To accomplish this object, the manufacturing method according to the present invention involves forming a layer composed of a positive resist on a support body, repeatedly executing an exposure process, a developing process and a depositing process of depositing a substance having a desired electrical characteristic into an obtained pattern space with respect to the layer, and thereafter removing the support body. The sheet composed of portions, having three or more types of different physical properties, of which an aspect ratio in pattern is equal to or larger than 1, is provided by this manufacturing method.

Fine patterning method for semiconductor device

Tue, 03 Nov 2009 08:00:00 EST

An insulation film is formed on a semiconductor substrate. A stopper film, which has a large etching selectivity relative to the insulation film and has a first film thickness, is formed on the insulation film. A first mask material, which has a second film thickness that is less than the first film thickness, is formed on the stopper film. A first mask is formed by patterning the first mask material. An opening portion is formed by etching the stopper film using the first mask. The opening portion is filled with a second mask material. A second mask of the second mask material is formed by removing the stopper film. The insulation film is etched using the second mask.

Semiconductor device

Tue, 03 Nov 2009 08:00:00 EST

With this semiconductor device, the distortion and cracking of a thinned portion of a semiconductor substrate are prevented to enable high precision focusing with respect to a photodetecting unit and uniformity and stability of high sensitivity of the photodetecting unit to be maintained. A semiconductor device 1 has a semiconductor substrate 10 , a wiring substrate 20 , conductive bumps 30 , and a resin 32 . A CCD 12 and a thinned portion 14 are formed on semiconductor substrate 10 . Electrodes 16 of semiconductor substrate 10 are connected via conductive bumps 30 to electrodes 22 of wiring substrate 20 . Wiring substrate 20 is subject to a wettability processing by which a region 26 a that surrounds a region opposing thinned portion 14 and regions 26 b that extend to the outer side from region 26 a are lowered in the wettability with respect to the resin. Insulating resin 32 fills a gap between outer edge 15 of thinned portion 14 and wiring substrate 20 in order to reinforce the bonding strengths of conductive bumps 30.

Phase detector device and method thereof

Tue, 03 Nov 2009 08:00:00 EST

A device and method for phase detection are disclosed. The device includes a phase differential module that provides a phase difference signal based on the phase difference between a data signal and a reference signal. The phase difference signal is provided to a first gate of a multi-gate fin-type field effect transistor (multi-gate FinFET) of the device. A second gate of the multi-gate FinFET transistor receives a bias signal that provides a phase detection threshold. A phase adjustment signal is provided at one or both of the FinFET current electrodes based on the phase difference signal and the bias signal.

Input sensor containing display device and method for driving the same

Tue, 03 Nov 2009 08:00:00 EST

An input sensor containing a display device including a group of pixel circuits arranged in a matrix, a group of optical sensor circuits arranged in a matrix, a display driving circuit which provides a display signal to the display element group and which provides a driving signal to the display element group, a read circuit which identifies an optical sensor to read a sense signal from this optical sensor, and a read signal processing section which processes the sense signal output by the read circuit in accordance with a command. The read signal processing section has an interface section which transfers, when the command requesting execution of an application is set to the interface section, the command to a command register.

Semiconductor memory device with dual storage node and fabricating and operating methods thereof

Tue, 03 Nov 2009 08:00:00 EST

A semiconductor memory device with a dual storage node structure as well as methods of fabricating and operating such a device are provided. The semiconductor memory device includes a substrate, a first transistor formed on the substrate, a first storage node connected to a source region of the first transistor, a second storage node connected to a drain region of the first transistor, and a plate line commonly contacting the first storage node and the second storage node.

Solid electrolyte switching element

Tue, 03 Nov 2009 08:00:00 EST

A switching element for reversible switching between an electrically insulating OFF state and an electrically conductive ON state, having two electrodes, namely a reactive electrode and an inert electrode, and also a solid electrolyte arranged between the two electrodes, which is characterized by the fact that the electrical conductivity of the solid electrolyte increases as the temperature thereof rises, but essentially no longer increases below a critical decomposition temperature of the solid electrolyte.

Semiconductor devices having self aligned semiconductor mesas and contact layers

Tue, 03 Nov 2009 08:00:00 EST

Methods of forming a semiconductor device can include forming a semiconductor structure on a substrate, the semiconductor structure having mesa sidewalls and a mesa surface opposite the substrate. A contact layer can be formed on the mesa surface wherein the contact layer has sidewalls and a contact surface opposite the mesa surface and wherein the contact layer extends across substantially an entirety of the mesa surface. A passivation layer can be formed on the mesa sidewalls and on portions of the contact layer sidewalls adjacent the mesa surface, and the passivation layer can expose substantially an entirety of the contact surface of the contact layer. Related devices are also discussed.

Defectivity and process control of electroless deposition in microelectronics applications

Tue, 03 Nov 2009 08:00:00 EST

Methods and compositions for electrolessly depositing Co, Ni, or alloys thereof onto a substrate in manufacture of microelectronic devices. Grain refiners, levelers, oxygen scavengers, and stabilizers for electroless Co and Ni deposition solutions.

Defectivity and process control of electroless deposition in microelectronics applications

Tue, 03 Nov 2009 08:00:00 EST

Apparatus and methods for optically-coupled memory systems

Tue, 03 Nov 2009 08:00:00 EST

Optically-coupled memory systems are disclosed. In one embodiment, a system memory includes a carrier substrate, and a controller attached to the carrier substrate and operable to transmit and receive optical signals, and first and second memory modules. The module substrate of the first memory module has an aperture formed therein, the aperture being operable to provide an optical path for optical signals between the controller and an optical transmitter/receiver unit of the second memory module. Thus, the system memory provides the advantages of “free space” optical connection in a compact arrangement of memory modules. In an alternate embodiment, the first memory module includes a beam splitter attached to the module substrate proximate the aperture. In another embodiment, the first and second memory modules are staged on the carrier substrate to provide an unobstructed path for optical signals. In another embodiment, the optical transmitter/receiver unit projects outwardly from the module substrate to provide an unobstructed path for optical signals.

Method of implanting a substrate and an ion implanter for performing the method

Tue, 03 Nov 2009 08:00:00 EST

An implanter provides two-dimensional scanning of a substrate relative to an implant beam so that the beam draws a raster of scan lines on the substrate. The beam current is measured at turnaround points off the substrate and the current value is used to control the subsequent fast scan speed so as to compensate for the effect of any variation in beam current on dose uniformity in the slow scan direction. The scanning may produce a raster of non-intersecting uniformly spaced parallel scan lines and the spacing between the lines is selected to ensure appropriate dose uniformity.

Heat sink with heat dissipating fins and method of manufacturing heat sink

Tue, 03 Nov 2009 08:00:00 EST

A heat sink comprising: a heat dissipating portion comprising a plurality of metal fins each having a heat receiving portion and a heat dissipating portion having elasticity; a fin fixing member to transfix said plurality of metal fins; a metal plate having a plurality of slits into which said respective heat dissipating portions are inserted and press-connected thereto with use of said elasticity; and a joining portion to join said metal plate and said heat dissipating portions which are inserted into said respective slits and fixed thereto.

High performance transistors with hybrid crystal orientations

Tue, 03 Nov 2009 08:00:00 EST

A method of forming a semiconductor structure having a hybrid crystal orientation and forming MOSFETs having improved performance on the semiconductor structure is provided. The method includes providing a substrate comprising a buried oxide (BOX) on a first semiconductor layer, and a second semiconductor layer on the BOX, wherein the first and second semiconductor layers have a first and a second crystal orientation, respectively, and wherein the substrate comprises a first region and a second region. An isolation structure is formed in the second region extending to the first semiconductor layer. A trench is then formed in the isolation structure, exposing the first semiconductor layer. A semiconductor material is epitaxially grown in the trench. The method further includes forming a MOSFET of a first type on the second semiconductor layer and a MOSFET of an opposite type than the first type on the epitaxially grown semiconductor material.

Semiconductor device having high drive current and method of manufacture therefor

Tue, 03 Nov 2009 08:00:00 EST

A method comprises forming a first semiconductor device in a substrate, where the first semiconductor device comprises a gate structure, a spacer disposed on sidewalls of the gate structure, the spacer having a first thickness, and raised source and drain regions disposed on either side of the gate structure. The method further comprises forming a second semiconductor device in the substrate and electrically isolated from the first semiconductor device, where the second semiconductor device comprises a gate structure, a spacer disposed on sidewalls of the gate structure, the spacer having a second thickness less than the first thickness of the spacer of the first semiconductor device, and recessed source and drain regions disposed on either side of the gate structure.

Integrated circuit fabrication

Tue, 03 Nov 2009 08:00:00 EST

A method for defining patterns in an integrated circuit comprises defining a plurality of features in a first photoresist layer using photolithography over a first region of a substrate. The method further comprises using pitch multiplication to produce at least two features in a lower masking layer for each feature in the photoresist layer. The features in the lower masking layer include looped ends. The method further comprises covering with a second photoresist layer a second region of the substrate including the looped ends in the lower masking layer. The method further comprises etching a pattern of trenches in the substrate through the features in the lower masking layer without etching in the second region. The trenches have a trench width.

Organic electroluminescent device

Tue, 03 Nov 2009 08:00:00 EST

A hole injection layer, a hole transport layer, a blue light emitting layer, an orange light emitting layer, an electron transport layer, an electron injection layer, and a cathode are formed in this order on an anode. The blue light emitting layer is composed of a host material doped with an assisting dopant and a luminescent dopant emitting blue light. A material used for the hole transport layer is used for the assisting dopant. The orange light emitting layer is composed of a host material doped with a luminescent dopant emitting orange light.

Formation of holes in substrates using dewetting coatings

Tue, 03 Nov 2009 08:00:00 EST

Methods and systems for forming holes in a substrate using dewetting coating are described herein.

Dual damascene patterning method

Tue, 03 Nov 2009 08:00:00 EST

A method for patterning a dual damascene structure in a semiconductor substrate is disclosed. The patterning is a metal hardmask based pattering eliminating at least resist poisoning and further avoiding or at least minimizing low-k damage. The method can be used as a full-via-first patterning method or a partial-via-first patterning method.

Plasma display apparatus comprising connector

Tue, 03 Nov 2009 08:00:00 EST

A plasma display apparatus comprising a connector is provided. The plasma display apparatus comprises a plasma display panel comprising an electrode of a predetermined width and a connector comprising an electrode line of a width narrower than the predetermined width of the electrode to supply a driving signal to the electrode. A distance between the electrode line and an adjacent electrode line is longer than a distance between the electrode and an adjacent electrode.

Cooling device for memory chips

Tue, 03 Nov 2009 08:00:00 EST

A cooling device for memory chip includes a first part and a second part which is pivotably connected to the first part at a top thereof. Each of the first and second parts includes an elongate plate and fins extend from each of the elongate plates. Ventilation holes are defined through each the elongate plates and located between the fins. The memory chip is sandwiched between the first and second elongate plates of the first and second parts, and the fins of the two parts are arranged alternatively.

Sense-amplifier assist (SAA) with power-reduction technique

Tue, 03 Nov 2009 08:00:00 EST

A design structure comprising an apparatus which reduces the power in memory devices in general and, in particular, static random access memory (SRAM) arrays featuring sense amplifier assist (SAA) circuitry. The design structure limits the implementation of the SAA circuitry to SRAM array blocks that do not meet the application voltage requirements.

Design of CMOS integrated germanium photodiodes

Tue, 03 Nov 2009 08:00:00 EST

A CMOS processing compatible germanium on silicon integrated waveguide photodiode. Positioning contacts in predicted low optical field regions, establishing side trenches in the silicon layer along the length of the photodiode reduces optical losses. Novel taper dimensions are selected based on the desirability of expected operational modes, reducing optical losses when light is injected from the silicon layer to the germanium layer. Reduced vertical mismatch systems have improved coupling between waveguide and photodiode. Light is coupled into and/or out of a novel silicon ring resonator and integrated waveguide photodiode system with reduced optical losses by careful design of the geometry of the optical path. An integrated waveguide photodiode with a reflector enables transmitted light to reflect back through the integrated waveguide photodiode, improving sensitivity. Careful selection of the dimensions of a novel integrated waveguide microdisk photodiode system results in reduced scattering. Improved sensitivity integrated waveguide photodiodes comprise integrated heaters.

Standard reference component for calibration, fabrication method for the same, and scanning electron microscope using the same

Tue, 03 Nov 2009 08:00:00 EST

The present invention provides a standard reference component for calibration for performing magnification calibration used in the scanning electron microscope with high precision, and provides a scanning electron microscope technique using it. Provided is a standard reference component for calibration for calibrating a scanning electron microscope that measures a length of a pattern in an observation area from information on the intensity of secondary electrons or reflected electrons generated by scanning an incident electron beam in the observation area on a measuring sample, having: a first substrate on which a multiple-layer is laminated and a second substrate with a recess for holding the first substrate, wherein the first substrate is held in the recess of the second substrate so that a normal direction of the multiple-layer surface may be roughly perpendicular to a normal direction of the second substrate surface, and the multiple-layer has a multiple-layer structure of a film containing silicon and a film containing molybdenum.

Switch circuit and method of switching radio frequency signals

Tue, 03 Nov 2009 08:00:00 EST

A novel RF switch circuit and method for switching RF signals is described. The RF switch circuit is fabricated in a silicon-on-insulator (SOI) technology. The RF switch includes pairs of switching and shunting transistor groupings used to alternatively couple RF input signals to a common RF node. A fully integrated RF switch is described including digital control logic and a negative voltage generator integrated together with the RF switch elements. In one embodiment, the fully integrated RF switch includes a built-in oscillator, a charge pump circuit, CMOS logic circuitry, level-shifting and voltage divider circuits, and an RF buffer circuit. Several embodiments of the charge pump, level shifting, voltage divider, and RF buffer circuits are described. The RF switch provides improvements in insertion loss, switch isolation, and switch compression. An improved voltage reducing circuit is described. The improved voltage reducing circuit limits voltages applied to selected nodes within the integrated circuit.