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<title>freepatentsonline.com: Miscellaneous active electrical nonlinear devices, circuits, and systems</title>
<link>http://www.freepatentsonline.com/result.html?query_txt=ccl/327%20and%20isd/11/10/2009&amp;uspat=on</link>
<description>USPTO Class 327 Miscellaneous active electrical nonlinear devices, circuits, and systems</description>
<language>en-us</language>
<lastBuildDate>Tue, 10 Nov 2009 08:53:08 EST</lastBuildDate>

<item>
<title><![CDATA[Sense amplifier for low voltage high speed sensing]]></title>
<link>http://www.freepatentsonline.com/7616028.html</link>
<description><![CDATA[A memory system includes a sense amplifier for detecting content of data memory cells by comparison with a voltage stored in a reference cell. The sense amplifier may comprise a comparator, first and second load circuits, and a low impedance circuit. A first input of the comparator is coupled to the low impedance circuit and a reference voltage node. A second input of the comparator is coupled to a data voltage node. The first load circuit loads a reference cell coupled to the reference voltage node. The second load circuit loads a data cell coupled to the data voltage node.]]></description>
<pubDate>Tue, 10 Nov 2009 08:00:00 EST</pubDate>
</item>

<item>
<title><![CDATA[Hysteresis-based processing for applications such as signal bias monitors]]></title>
<link>http://www.freepatentsonline.com/7616029.html</link>
<description><![CDATA[In one embodiment of the invention, a bias signal monitor has two signal comparators that compare two (power supply) voltages at two different bias points and a logic circuit that processes the outputs from the two signal monitors to generate a bias signal monitor output signal. The logic circuit implements hysteresis-based processing such that (1) if both signal comparators are active (indicating that a first voltage is greater than the second voltage relative to both bias points), then the monitor output is active, (2) if both signal comparators are inactive (indicating that the first voltage is not greater than the second voltage relative to either bias point), then the monitor output is inactive, and (3) if one signal comparator is active and the other is inactive, then the monitor output keeps its previous value. This hysteresis characteristic prevents relatively small oscillations between the voltages from changing the monitor output.]]></description>
<pubDate>Tue, 10 Nov 2009 08:00:00 EST</pubDate>
</item>

<item>
<title><![CDATA[Hard reset and manual reset circuit assembly]]></title>
<link>http://www.freepatentsonline.com/7616031.html</link>
<description><![CDATA[A simple inexpensive hard reset and manual reset circuit assembly that provides a delay time during reset for enabling other matched electronic devices to have sufficient time to reach ready status. The circuit assembly includes a power source, a first resistor, a first electric control switch, which has a control end and two bypasses being respectively connected to a reset terminal and a grounding terminal, a second resistor, a second electric control switch, which has a control end and two bypasses being respectively connected to the control end of the first electric control switch and the grounding terminal, a third resistor, a first capacitor, a second capacitor, a manual switch, which has two opposite ends respectively connected to the second capacitor and the grounding terminal, and a fourth resistor, which has two opposite ends respectively connected to the power source and the second end of the second capacitor.]]></description>
<pubDate>Tue, 10 Nov 2009 08:00:00 EST</pubDate>
</item>

<item>
<title><![CDATA[Programmable strobe and clock generator]]></title>
<link>http://www.freepatentsonline.com/7616036.html</link>
<description><![CDATA[Timing test circuits, including programmable strobe and clock generators, may include at least two DLLs having differing numbers of delay elements thereby producing many timing signals having various phase relationships. A detector circuit can generate many different timing intervals as may be defined by independently selected events in signals arising from both of the DLLs.]]></description>
<pubDate>Tue, 10 Nov 2009 08:00:00 EST</pubDate>
</item>

<item>
<title><![CDATA[Data retention in operational and sleep modes]]></title>
<link>http://www.freepatentsonline.com/7616041.html</link>
<description><![CDATA[A circuit is disclosed for retaining a signal value during a sleep mode while a portion of said circuit is powered down comprising: a clock signal input operable to receive a clock signal; at least one latch clocked by said clock signal; a data input, a data output and a forward data path therebetween, wherein a signal value is operable to be received at said data input, is clocked through said at least one latch and passes to said data output along said forward data path; at least one of said at least one latch comprises a retention latch operable to retain a signal value during said sleep mode, said retention latch not being located on said forward data path; and a tristateable device, said tristateable device being arranged between said forward data path and said retention latch and being operable to selectively isolate said retention latch from said forward data path in response to receipt of a first sleep signal; wherein in response to receipt of a second sleep signal, said second sleep signal being received after said first sleep signal, said circuit is operable to enter said sleep mode such that a voltage difference across said portion of said circuit is reduced such that said portion of said circuit is powered down, and a voltage difference across said retention latch and said tristateable device is maintained.]]></description>
<pubDate>Tue, 10 Nov 2009 08:00:00 EST</pubDate>
</item>

<item>
<title><![CDATA[Methods and apparatus for managing LSI power consumption and degradation using clock signal conditioning]]></title>
<link>http://www.freepatentsonline.com/7616043.html</link>
<description><![CDATA[Methods and apparatus for distributing clock signals to an integrated circuit provide for: producing, in a slow mode of operation, a first clock signal having at least first and second on-pulses of differing first and second on-times each period, respectively, where a sum of the first and second on-times is approximately equal to a sum of off-times each period; distributing the first clock signal through a distribution tree and terminating at a plurality of final buffer circuits that produce respective distributed clock signals from which respective second clock signals are produced to supply at least a portion of the integrated circuit; deleting the second on-pulse from each of the distributed clock signals each period to produce the respective second clock signals, the second clock signals each including at least a portion of the first on-pulse, but none of the second on-pulse each period.]]></description>
<pubDate>Tue, 10 Nov 2009 08:00:00 EST</pubDate>
</item>

<item>
<title><![CDATA[System comprising an electrical bridge for generating an electrical signal for a load and a control unit for such a system]]></title>
<link>http://www.freepatentsonline.com/7616046.html</link>
<description><![CDATA[A System for generating a PWM output voltage signal include a first half bridge having a first set of switches, and a second half bridge having a second set of switches. A control unit is configured to generate a first PWM switch-signal for switching the first set of switches; to generate a second PWM switch-signal for switching the second set of switches; and to vary at least one of pulse widths and phases of the first and second PWM switch-signals relative to each other for varying a pulse width of a PWM output voltage signal so that the PWM output voltage signal equals zero when the pulse widths of the first and second PWM switch-signals are equal to each other.]]></description>
<pubDate>Tue, 10 Nov 2009 08:00:00 EST</pubDate>
</item>

<item>
<title><![CDATA[Transistor arrangement for rectifier and inverter]]></title>
<link>http://www.freepatentsonline.com/7616047.html</link>
<description><![CDATA[A transistor arrangement has first and second terminals and a control terminal which sets a current flow between the first and second terminals, and a signal conditioning device which applies a transistor control voltage to the control terminal in a manner dependent on a differential voltage present between the first and second terminals, and a driving apparatus is assigned to the signal conditioning device and switches the latter between at least two operating modes.]]></description>
<pubDate>Tue, 10 Nov 2009 08:00:00 EST</pubDate>
</item>

<item>
<title><![CDATA[Body biasing control circuit using lookup table and body biasing control method using same]]></title>
<link>http://www.freepatentsonline.com/7616048.html</link>
<description><![CDATA[A body biasing control circuit capable of being shared by a plurality of macro blocks and can independently control body voltages of a plurality of macro blocks. The body biasing control circuit includes a lookup table for storing a plurality of indexes where each index is associated with a body voltage appropriate for an operating state of a corresponding macro block. A control unit receives a corresponding index from the lookup table and generates a plurality of body voltages appropriate for an operating state of a macro block corresponding to the index and supplies the body voltages to the macro block.]]></description>
<pubDate>Tue, 10 Nov 2009 08:00:00 EST</pubDate>
</item>

<item>
<title><![CDATA[Power supply circuit for producing a reference current with a prescribable temperature dependence]]></title>
<link>http://www.freepatentsonline.com/7616050.html</link>
<description><![CDATA[A power supply circuit is provided for producing a reference current with a prescribable temperature dependence. The circuit includes two current sinks, which at their respective input take up a first input current (I 1 ) or a second input current (I 2 ), and in which current sinks at their respective outputs are connected to a node having a reference potential, the output of at least one current sink being connected via a resistor to the node having the reference potential. The resistor is formed by least two reference resistors with prescribable temperature coefficients that are preferably different from one another.]]></description>
<pubDate>Tue, 10 Nov 2009 08:00:00 EST</pubDate>
</item>

<item>
<title><![CDATA[Circuit for controlling data output]]></title>
<link>http://www.freepatentsonline.com/7616034.html</link>
<description><![CDATA[Disclosed is a data output control circuit for controlling data output. The data output control circuit includes a delay lock loop for outputting a first clock by delaying an external clock in response to a control signal, a phase detector for outputting a detection signal by detecting a frequency of the external clock in response to the control signal, a decoder for outputting a selection signal by decoding the detection signal, and a delay unit for outputting a second clock by delaying the first clock or inverting and delaying a phase of the first clock in response to the selection signal.]]></description>
<pubDate>Tue, 10 Nov 2009 08:00:00 EST</pubDate>
</item>

<item>
<title><![CDATA[Internal voltage initializing circuit for use in semiconductor memory device and driving method thereof]]></title>
<link>http://www.freepatentsonline.com/7616032.html</link>
<description><![CDATA[Provided are an internal voltage initializing circuit for use in a semiconductor memory and a driving method thereof, which are capable of preventing a back bias voltage from abnormally increasing due to a pumping operation of a VPP pump according to a change in a level of a power-up signal. The internal voltage initializing circuit includes: a high voltage initializing unit for selectively connecting a power supply voltage terminal an a high voltage terminal in response to a power-up signal; and a back bias voltage initializing unit for selectively connecting a ground terminal and a back bias voltage terminal in response to a signal produced by delaying the power-up signal by a predetermined time.]]></description>
<pubDate>Tue, 10 Nov 2009 08:00:00 EST</pubDate>
</item>

<item>
<title><![CDATA[Apparatus and method for supplying voltage in semiconductor device]]></title>
<link>http://www.freepatentsonline.com/7616033.html</link>
<description><![CDATA[For supplying voltage to at least one main current consuming unit, a voltage supply unit provides the voltage to the at least one main current consuming unit at a supply node. In addition, an auxiliary current consuming unit conducts auxiliary current from/to the supply node for at least a predetermined time period before the at least one main current consuming unit begins to conduct current. Thus, voltage overshoot is prevented at the supply node.]]></description>
<pubDate>Tue, 10 Nov 2009 08:00:00 EST</pubDate>
</item>

<item>
<title><![CDATA[Method and apparatus for controlling power-down mode of delay locked loop]]></title>
<link>http://www.freepatentsonline.com/7616037.html</link>
<description><![CDATA[A method and apparatus for controlling a power-down mode of a delay locked loop (DLL), in which the apparatus includes a first switch unit, a DLL, and a second switch unit. The first switch unit transfers a first clock signal in response to a clock input enable signal. The DLL receives the first clock signal through the first switch unit to generate a second clock signal and is turned off by a power-down signal that is generated from the first clock signal latched by the first switch unit. The second switch unit transfers the second clock signal in response to a clock output enable signal. In a power-down mode, the clock input enable signal is deactivated in response to a clock enable signal and the clock output enable signal is deactivated after a predetermined number of clock cycles that are necessary for the latched first clock signal to be completely transferred through the delay cells of the DLL to an output terminal of the DLL. In a power-down exit mode, the power-down signal is deactivated in response to the clock enable signal and the clock input enable signal and the clock output enable signal are activated after a predetermined number of clock cycles that are necessary for the latched second clock signal to be completely transferred through the delay cells of the DLL to the output terminal of the DLL.]]></description>
<pubDate>Tue, 10 Nov 2009 08:00:00 EST</pubDate>
</item>

<item>
<title><![CDATA[Clock modulation circuit for correcting duty ratio and spread spectrum clock generator including the same]]></title>
<link>http://www.freepatentsonline.com/7616038.html</link>
<description><![CDATA[A clock modulation circuit includes a modulation block that receives a fixed clock generated from a reference clock and buffers the fixed clock so as to generate a modulated clock. A correction unit is provided in the modulation block to correct the duty ratio of the modulated clock.]]></description>
<pubDate>Tue, 10 Nov 2009 08:00:00 EST</pubDate>
</item>

<item>
<title><![CDATA[Logarithmic temperature compensation for detectors]]></title>
<link>http://www.freepatentsonline.com/7616044.html</link>
<description><![CDATA[The intercept of a logarithmic amplifier is temperature stabilized by generating a signal having the form H log H where H is a function of temperature such as T/T 0 . The first H factor is cancelled, thereby generating a correction signal having the form Y log H. The cancellation may be implemented with a transconductance cell having a hyperbolic tangent function. The H log H function may be generated by a pair of junctions biased by one temperature-stable current and one temperature-dependent current. The pair of junctions and the transconductance cell may be coupled together in a translinear loop. A user-accessible terminal may allow adjustment of the correction signal for different operating frequencies.]]></description>
<pubDate>Tue, 10 Nov 2009 08:00:00 EST</pubDate>
</item>

<item>
<title><![CDATA[Flip-flop and semiconductor integrated circuit]]></title>
<link>http://www.freepatentsonline.com/7616040.html</link>
<description><![CDATA[A flip-flop is disclosed which includes: a clock supply circuit configured to output or fix a clock signal alternating between two predetermined states in accordance with a sleep signal; a first holding circuit configured to fetch or hold an input signal in accordance with a state the clock signal indicates; a second holding circuit configured to fetch or hold a first signal output by the first holding circuit in accordance with a state the clock signal indicates; an input switching circuit configured to supply as the input signal a second signal output by the second holding circuit or to supply an external signal as the input signal in accordance with the hold signal; and a power supply control circuit configured to supply or not to supply power to the first holding circuit and the input switching circuit in accordance with a power supply control signal.]]></description>
<pubDate>Tue, 10 Nov 2009 08:00:00 EST</pubDate>
</item>

<item>
<title><![CDATA[Clock generator circuit, signal multiplexing circuit, optical transmitter, and clock generation method]]></title>
<link>http://www.freepatentsonline.com/7616042.html</link>
<description><![CDATA[For the purpose of achieving multiplexing of data signals for the channels of more than four in number in the generating of a frequency-divided clock signal using toggle flip-flop circuits (TFF), while avoiding any possible phase shift relationship between generated frequency-divided clock signals attributed to the indefinite initial state posing the inherent problem of the TFF, there is provided a clock generator circuit comprising a plurality of toggle flip-flop circuits connected in series, capable of outputting a pair of frequency-divided clock signals with different phases; and a delay circuit connected to the toggle flip-flop circuit, capable of outputting a clock signal with a phase shifted with respect to the phases of the pair of frequency-divided clock signal phases by delaying either one or both of the pair of frequency-divided clock signals being outputted from the toggle flip-flop circuits.]]></description>
<pubDate>Tue, 10 Nov 2009 08:00:00 EST</pubDate>
</item>

<item>
<title><![CDATA[System and method for charge-pump with phase-frequency detection capability]]></title>
<link>http://www.freepatentsonline.com/7616065.html</link>
<description><![CDATA[A method of generating a correction signal for a voltage controlled oscillator (VCO) includes receiving a first signal in a correction current generator, changing a state of a first error signal substantially simultaneously with a first changing state of the first signal, receiving a second signal in the correction current generator, changing a state of a second error signal substantially simultaneously with a first changing state of the second signal, changing the state of the first error signal substantially simultaneously with a second changing state of the second signal, changing the state of the second error signal substantially simultaneously with a second changing state of the first signal, combining the first error signal and the second error signal to generate the correction signal substantially equal to a difference between the first error signal and the second error signal and applying the correction signal to a loop filter coupled to a correction signal input of the VCO. A PLL circuit is also described.]]></description>
<pubDate>Tue, 10 Nov 2009 08:00:00 EST</pubDate>
</item>

<item>
<title><![CDATA[Semiconductor device and operation method thereof]]></title>
<link>http://www.freepatentsonline.com/7616030.html</link>
<description><![CDATA[Semiconductor device and operation method thereof includes an aspect of the present invention, there is provided a clock generator configured to receive an external clock signal to generate a first clock signal corresponding to a rising edge of the external clock and a second clock signal corresponding to a falling edge of the external clock, a drive control signal generator configured to restrict an activation period of the first clock signal within a deactivation period of the second clock signal to generate a first drive control signal, and restrict an activation period of the second clock signal within a deactivation period of the first clock signal to generate a second drive control signal and an output driver configured to receive a drive data in response to the first and second drive control signal to drive an output terminal in response to the drive data.]]></description>
<pubDate>Tue, 10 Nov 2009 08:00:00 EST</pubDate>
</item>

<item>
<title><![CDATA[Charge pump for PLL/DLL]]></title>
<link>http://www.freepatentsonline.com/7616035.html</link>
<description><![CDATA[A charge pump for use in a locked loop minimizes static phase error through the use of an operational amplifier. The operational amplifier also mitigates the effects of low power supply voltage. The charge pump further includes a startup circuit to establish a predetermined voltage level at the charge pump output node during startup.]]></description>
<pubDate>Tue, 10 Nov 2009 08:00:00 EST</pubDate>
</item>

<item>
<title><![CDATA[Mixer with balanced local oscillator signal]]></title>
<link>http://www.freepatentsonline.com/7616045.html</link>
<description><![CDATA[A mixer includes a first field effect transistor (FET) having a gate that receives a first signal of a balanced local oscillator (LO) signal, a first source/drain coupled to a ground voltage, and a second source/drain; and a second FET having a gate that receives a second signal of the balanced LO signal, a first source/drain that floats, and a second source/drain connected to the second source/drain of the first FET to form a mixing node, the second signal being out of phase with the first signal. A diplexer is connected between the mixing node and each of a radio frequency (RF) port and an intermediate frequency (IF) port. A first LO leakage caused by the first FET is substantially canceled by a second LO leakage caused by the second FET at the mixing node.]]></description>
<pubDate>Tue, 10 Nov 2009 08:00:00 EST</pubDate>
</item>

<item>
<title><![CDATA[Non-volatile semiconductor memory device]]></title>
<link>http://www.freepatentsonline.com/7616493.html</link>
<description><![CDATA[When a voltage level detector detects that a supply voltage reaches a recovery voltage level that requires a recovery operation, a signal generator generates a recovery operation instructing signal for instructing the recovery operation. The recovery operation instructing signal is invalidated if a certain operation mode is executed and validated in other cases.]]></description>
<pubDate>Tue, 10 Nov 2009 08:00:00 EST</pubDate>
</item>

<item>
<title><![CDATA[Pumping voltage generating apparatus of semiconductor integrated circuit]]></title>
<link>http://www.freepatentsonline.com/7616049.html</link>
<description><![CDATA[A pumping voltage generating apparatus includes a detection signal generating unit that generates a detection signal when a pumping voltage is lower than a reference value. A pumping unit elevates a first external voltage by a second external voltage to be output as the pumping voltage, in response to the detection signal. In this case, the second external voltage is lower than the first external voltage.]]></description>
<pubDate>Tue, 10 Nov 2009 08:00:00 EST</pubDate>
</item>

<item>
<title><![CDATA[Integrated circuit, electronic device and integrated circuit control method]]></title>
<link>http://www.freepatentsonline.com/7616051.html</link>
<description><![CDATA[An integrated circuit ( 10 ) comprises a plurality of functional blocks ( 101, 102, 103 ), each of the functional blocks ( 101, 102, 103 ) being coupled between a first power supply line ( 110 ) and a second power supply line ( 120 ). A first functional block ( 101 ) is coupled to the first power supply line ( 110 ) via a first conductive path including a first switch ( 131 ) and a second functional block ( 102 ) is coupled to the first power supply line ( 110 ) via a second conductive path including a second switch ( 132 ), the first switch ( 131 ) and the second switch ( 132 ) being arranged to respectively disconnect the first functional block ( 101 ) and the second functional block ( 102 ) from the first power supply line ( 110 ) for switching said functional blocks ( 101, 102 ) from an active mode to a standby mode. The IC ( 10 ) comprises a further switch ( 141 ) having a first terminal coupled to a node ( 121 ) of the first conductive path between the first switch ( 131 ) and the first functional block ( 101 ) and a second terminal coupled to a node ( 122 ) of the second conductive path between the second switch ( 132 ) and the second functional block ( 102 ). The further switch ( 141 ) has a control terminal responsive to an enable signal indicating that the first switch ( 131 ) and the second switch ( 132 ) are disabled, thus allowing the recycling of charge between the first functional block ( 101 ) and the second functional block ( 102 ).]]></description>
<pubDate>Tue, 10 Nov 2009 08:00:00 EST</pubDate>
</item>

<item>
<title><![CDATA[Fast adapting filter]]></title>
<link>http://www.freepatentsonline.com/7616052.html</link>
<description><![CDATA[Adjustable gain circuits (AGCs) within serial filter stages are initialized to maximum gain. The output of each AGC is then sampled and converted to digital representation for use by control logic in setting the gain for the respective AGC. The gain adjustment decision for each AGC is performed in one shot, sequentially backwards from the last AGC, such that gain may be adapted simply and quickly within a number of cycles equal to the number of AGCs. Performance is enhanced by a fast-adapting cell in which capacitances are switched into the input path and feedback loop of an amplifier to reduce direct current gain within the transfer function through charge sharing dividing down the output voltage.]]></description>
<pubDate>Tue, 10 Nov 2009 08:00:00 EST</pubDate>
</item>

<item>
<title><![CDATA[System to protect electrical fuses]]></title>
<link>http://www.freepatentsonline.com/7616416.html</link>
<description><![CDATA[A method and system is disclosed for protecting electrical fuse circuitry. A electrical fuse circuit with electrostatic discharge (ESD) protection has at least one electrical fuse, a programming device coupled in series with the electrical fuse having at least a transistor for receiving a control signal for controlling a programming current flowing through the electrical fuse, a voltage source coupled to the fuse and the programming device for providing the programming current, and a protection module coupled to a gate of the transistor at its first end for reducing charges accumulated at the gate of the transistor due to electric static charges arriving at the voltage source, thereby preventing the programming device from accidentally programming the fuse.]]></description>
<pubDate>Tue, 10 Nov 2009 08:00:00 EST</pubDate>
</item>

<item>
<title><![CDATA[Electronic oscillators having a plurality of phased outputs and such oscillators with phase-setting and phase-reversal capability]]></title>
<link>http://www.freepatentsonline.com/7616070.html</link>
<description><![CDATA[Disclosed are multiphase oscillators comprising a plurality of delay stages serially coupled in a loop by a plurality of nodes, with the loop being folded to provide two concentric rings of delay stages with equal numbers of allocated nodes. A second plurality of negative-resistance elements are provided, each element having a first output coupled to a node on the first concentric ring and a second output coupled to a node on the second concentric ring. Each such output switches between first and second voltage levels, and provides a negative resistance to a signal coupled to it during at least a portion of the transition between voltage levels. The outputs of an element switch to opposite voltage levels. With this construction, a high-voltage pulse propagates around the loop of delay stages, with a low-voltage pulse propagating behind it. Also disclosed are circuits to control the direction of pulse propagation.]]></description>
<pubDate>Tue, 10 Nov 2009 08:00:00 EST</pubDate>
</item>

<item>
<title><![CDATA[Adder and current mode switching regulator]]></title>
<link>http://www.freepatentsonline.com/7615973.html</link>
<description><![CDATA[Provided is an adder in which all of circuits can be constituted by CMOS transistors, a process is simplified, and a chip size can be reduced as compared with a conventional art. The adder according to the present invention includes: a first VI converter and a second VI converter that allow a current corresponding to an input voltage to flow therein; and a current addition resistor having one end commonly connected to output terminals of the first VI converter and the second VI converter and another end grounded, which is adjustable in a resistance value. Each of the first VI converter and the second VI converter includes: a prestage VI converter that generates a reference current; a poststage VI converter that generates a current corresponding to the input voltage; a first current mirror circuit whose first terminal on a reference side is connected with the prestage VI converter and whose first output terminal in which a current corresponding to the first terminal flows is connected with the poststage VI converter; and a second current mirror circuit whose second terminal on the reference side is connected to the first output terminal, and which can adjust a current ratio from a second output terminal in correspondence with the current that flows in the second terminal. A voltage at the one end of the current addition resistor is output as an addition voltage.]]></description>
<pubDate>Tue, 10 Nov 2009 08:00:00 EST</pubDate>
</item>

<item>
<title><![CDATA[Memory reset apparatus]]></title>
<link>http://www.freepatentsonline.com/7616039.html</link>
<description><![CDATA[A memory reset apparatus including a first inverse circuit, a logic circuit, and a plurality of second inverse circuits is provided. The first inverse circuit receives a control signal generated by a north bridge and generates a first signal, in which the control signal controls reset of a plurality of memories. The logic circuit performs a logic operation of the first signal and an indicating signal and generates a second signal, in which the indicating signal indicates each component of a computer system completely powered on. The plurality of second inverse circuits is respectively coupled between the logic circuit and the memories. The second inverse circuits inverse the second signal and respectively generate a plurality of reset signals to the memories, so as to reset the memories.]]></description>
<pubDate>Tue, 10 Nov 2009 08:00:00 EST</pubDate>
</item>

<item>
<title><![CDATA[PLL circuit and semiconductor device provided with PLL circuit]]></title>
<link>http://www.freepatentsonline.com/7616071.html</link>
<description><![CDATA[Disclosed is a PLL circuit of a small circuit size capable of generating clock including a jitter component with ease. A phase comparator  11  compares the phase of an input reference clock signal CKR to the phase of a signal fed back from a frequency divider  14  to route an output signal corresponding to the phase difference to a filter unit  12.  The filter unit  12  detects a low frequency component of the output signal of the phase comparator  11  to route the so detected component to a voltage controlled oscillator  13.  The voltage controlled oscillator  13  generates, as an output signal CKF, an oscillation signal of an oscillation frequency which is controlled on the basis of the output voltage of the filter unit  12.  The frequency divider  14  divides the frequency of the output signal CKF to output the resulting signal to the phase comparator  11.  An end A of a wiring of a wiring part  15  is connected to an output P of the filter unit  12  in such a manner that noise will be induced from outside and added to the output signal of the filter unit  12.  The oscillation frequency of the output signal CKF, generated by the voltage controlled oscillator  13,  is subjected to variations by noise.]]></description>
<pubDate>Tue, 10 Nov 2009 08:00:00 EST</pubDate>
</item>

<item>
<title><![CDATA[Optical disk apparatus and PLL circuit]]></title>
<link>http://www.freepatentsonline.com/7616726.html</link>
<description><![CDATA[With the objective of providing a stable PLL circuit and improving readout performance of an optical disk apparatus equipped with PRML, using the PLL circuit, phase detectors are respectively provided with respect to signals prior and subsequent to an FIR filter, and the phase detectors are selectively used according to an operating condition of a PLL to thereby stabilize the operation of the PLL circuit. There can be provided such an optical disk apparatus that readout performance is improved so as to extract an operating limit of a Viterbi decoder.]]></description>
<pubDate>Tue, 10 Nov 2009 08:00:00 EST</pubDate>
</item>

<item>
<title><![CDATA[Method and apparatus for measuring the duty cycle of a digital signal]]></title>
<link>http://www.freepatentsonline.com/7617059.html</link>
<description><![CDATA[The disclosed methodology and apparatus measures the duty cycle of a clock signal. A variable duty cycle circuit receives a clock signal from a clock signal generator. The variable duty cycle circuit adjusts the duty cycle of the clock signal by an amount dependent on a duty cycle index value that it receives. The variable duty cycle circuit supplies a duty-cycle adjusted clock signal to a divider circuit. The apparatus sweeps the frequency of the clock signal from a starting value up to a maximum frequency above which the divider circuit fails. The apparatus then determines the duty cycle of the duty-cycle adjusted clock signal from the maximum frequency.]]></description>
<pubDate>Tue, 10 Nov 2009 08:00:00 EST</pubDate>
</item>

<item>
<title><![CDATA[Oscillation device and controlling method therefor]]></title>
<link>http://www.freepatentsonline.com/7616066.html</link>
<description><![CDATA[An oscillation device includes a reference oscillation unit for generating an oscillating signal of a specific frequency; a voltage-controlled oscillation unit for generating a output oscillation signal whose frequency is dependent on a control voltage; a phase comparing unit for detecting a phase difference based on the oscillating signal and the output oscillation signal; a digital value storage unit for storing therein a phase difference signal corresponding to the phase difference as a digital value; a sample holding unit for intermittently renewing and maintaining a hold signal in accordance with the digital value; and a control unit. The control unit controls the reference oscillation unit, the phase comparing unit and the digital value storage unit to be started or stopped, and also switches the control voltage to the phase difference signal or to the hold signal.]]></description>
<pubDate>Tue, 10 Nov 2009 08:00:00 EST</pubDate>
</item>

<item>
<title><![CDATA[Frequency synthesizer for integrated circuit radios]]></title>
<link>http://www.freepatentsonline.com/7616068.html</link>
<description><![CDATA[An integrated circuit radio transceiver and method therefor includes capacitive loop filter with selectable capacitive elements that are operable to adjust a signal level provided to a voltage controlled oscillator to control a frequency of an output signal of the oscillator. A plurality of switches are controlled by logic to define a discharge mode, a charge mode and charge sharing mode in which a plurality of capacitive elements share charge while generating the input voltage to the oscillator.]]></description>
<pubDate>Tue, 10 Nov 2009 08:00:00 EST</pubDate>
</item>

<item>
<title><![CDATA[Method and system for fast PLL close-loop settling after open-loop VCO calibration]]></title>
<link>http://www.freepatentsonline.com/7616069.html</link>
<description><![CDATA[Aspects of a method and system for a fast phase-locked loop (PLL) close-loop settling after an open-loop voltage controlled oscillator (VCO) calibration are provided. A fractional-N PLL synthesizer may comprise a VCO, a phase-frequency detector (PFD), a D flip-flop, a divider, a charge pump, and a loop filter. The synthesizer may disable the PFD based on a control signal indicating the start of VCO open-loop calibration. After open-loop calibration, the synthesizer may subsequently enable a PLL closed-loop settling and may enable the PFD to control the charge pump when the input reference signal phase lags a phase of a divider signal generated by the divider. The D flip-flop may enable and disable the PFD. During open-loop calibration, the loop filter may be discharged via a leakage current in the charge pump. During closed-loop settling, the loop filter may be charged by the charge pump via control of the PFD.]]></description>
<pubDate>Tue, 10 Nov 2009 08:00:00 EST</pubDate>
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<item>
<title><![CDATA[Signal delay structure in high speed bit stream demultiplexer]]></title>
<link>http://www.freepatentsonline.com/7616725.html</link>
<description><![CDATA[A signal delay structure and method of reducing skew between clock and data signals in a high-speed serial communications interface includes making a global adjustment to the clock signal in the time domain to compensate for a component of the skew that is common between the clock and all data signals. This can include skew caused by the variation in frequency of the input clock from a nominal value, misalignment between the phase of the clock and data generated at the source of the two signals. The global adjustment is made through a delay component that is common to all of the clock signal lines for which skew with data signals is to be compensated. A second level adjustment is made that compensates for the component of the skew that is common to the clock and a subset of the data signals.]]></description>
<pubDate>Tue, 10 Nov 2009 08:00:00 EST</pubDate>
</item>

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