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<title>freepatentsonline.com: Coded data generation or conversion</title>
<link>http://www.freepatentsonline.com/result.html?query_txt=ccl/341%20and%20isd/11/10/2009&amp;uspat=on</link>
<description>USPTO Class 341 Coded data generation or conversion</description>
<language>en-us</language>
<lastBuildDate>Thu, 12 Nov 2009 03:32:00 EST</lastBuildDate>

<item>
<title><![CDATA[Data bus inversion apparatus, systems, and methods]]></title>
<link>http://www.freepatentsonline.com/7616133.html</link>
<description><![CDATA[Apparatus, systems, and methods are disclosed such as those that operate to encode data bits transmitted on a plurality of channels according to at least one of multiple Data Bus Inversion (DBI) algorithms. Additional apparatus, systems, and methods are disclosed.]]></description>
<pubDate>Tue, 10 Nov 2009 08:00:00 EST</pubDate>
</item>

<item>
<title><![CDATA[Code generation and allocation apparatus]]></title>
<link>http://www.freepatentsonline.com/7616135.html</link>
<description><![CDATA[A method of generating and allocating codewords includes allocating one of two selectable codewords b 1  and b 2  as codeword “b” when a preceding codeword “a” and a following codeword “b” form a code stream X, in which the codewords b 1  and b 2  have opposite INV values which are parameters indicating whether the number of ‘1s’ contained in a codeword is an odd number or an even number. When the code stream of the preceding codeword “a” and the following codeword b 1  is X 1 , and when the code stream of the preceding codeword “a” and the following codeword b 2  is X 2 , the codewords are allocated such that the INV values of X 1  and X 2  are maintained to be opposite when the preceding codeword “a” or the following codeword b 1  (b 2 ) (b 1  or b 2 ) should be replaced by another codeword in compliance with a predetermined boundary condition given between codewords. The codewords are allocated so that a DC suppression capability of the code stream can be maintained.]]></description>
<pubDate>Tue, 10 Nov 2009 08:00:00 EST</pubDate>
</item>

<item>
<title><![CDATA[A/D converter preventing results of A/D conversion from being overwritten]]></title>
<link>http://www.freepatentsonline.com/7616140.html</link>
<description><![CDATA[An A/D converter capable of generating an interrupt for requesting a control circuit to read the results of A/D conversion, in desired timing. Analog signals input from channels selected by a channel-selecting section are input to an A/D conversion section, and are sequentially A/D-converted. The results of A/D conversion are sequentially stored in different stages of a FIFO. A stage number-counting section counts the number of the stages of the FIFO where the results of A/D conversion are stored. An interrupt signal-delivering section outputs an interrupt signal for requesting a CPU to read the results of A/D conversion when the number of stages counted by the stage number-counting section is equal to an interrupt-generating stage number set by an interrupt-generating stage number-setting section.]]></description>
<pubDate>Tue, 10 Nov 2009 08:00:00 EST</pubDate>
</item>

<item>
<title><![CDATA[Digital-to-analog converter]]></title>
<link>http://www.freepatentsonline.com/7616141.html</link>
<description><![CDATA[Embodiments of a digital-to-analog converter are disclosed.]]></description>
<pubDate>Tue, 10 Nov 2009 08:00:00 EST</pubDate>
</item>

<item>
<title><![CDATA[Sigma-delta modulated analog-to-digital converter having a changeable coefficient]]></title>
<link>http://www.freepatentsonline.com/7616142.html</link>
<description><![CDATA[A sigma-delta modulated analog-to-digital converter having an integrator with a first changeable coefficient and/or having an excess loop-delay circuit also having a second changeable coefficient. The changeable coefficients enable the converter to account for noise mixed with the input signal, circuit non-linearities, and component variations.]]></description>
<pubDate>Tue, 10 Nov 2009 08:00:00 EST</pubDate>
</item>

<item>
<title><![CDATA[A/D conversion circuit, control method thereof, solid-state imaging device, and imaging apparatus]]></title>
<link>http://www.freepatentsonline.com/7616146.html</link>
<description><![CDATA[An A/D conversion circuit includes: an input capacitance to which an input signal and a reference signal are sequentially applied; an operational amplifier; a first switch connected between the other end of the input capacitance and a first input end of the operational amplifier; a feedback capacitance connected to the first input end of the operational amplifier; a second switch connected between the other end of the feedback capacitance and an output end of the operational amplifier; a third switch selectively applying a predetermined voltage to the other end of the feedback capacitance; a fourth switch selectively causing a short circuit between the first input end and the output end of the operational amplifier; a fifth switch applying the predetermined voltage to a second input end of the operational amplifier; and a sixth switch applying a ramp reference voltage to the second input end of the operational amplifier.]]></description>
<pubDate>Tue, 10 Nov 2009 08:00:00 EST</pubDate>
</item>

<item>
<title><![CDATA[Method and apparatus for compression and decompression of an executable code with a RISC processor]]></title>
<link>http://www.freepatentsonline.com/7616137.html</link>
<description><![CDATA[An embodiment of the invention relates to a process for compression of executable code by a microprocessor, comprising steps consisting of decomposing the executable code into words; compressing each word of executable code, each compressed word of executable code comprising a part of predefined fixed length and a part of variable length whereof the length is defined by the part of fixed length; and combining all the parts of fixed length and all the parts of variable length of the words respectively into a block of parts of fixed length and in a block of parts of variable length, the respective positions of at least certain parts of variable length in the block of parts of variable length being saved in an addressing table.]]></description>
<pubDate>Tue, 10 Nov 2009 08:00:00 EST</pubDate>
</item>

<item>
<title><![CDATA[Message compression methods and systems]]></title>
<link>http://www.freepatentsonline.com/7616136.html</link>
<description><![CDATA[A method for message compression comprises receiving a first text message, acquiring at least one frequent character combination in the first text message, calculating frequencies for the frequent character combination and characters occurring in the first text message, generating multiple representative codes respectively for the frequent character combination and characters, and encoding the first text message to a second text message.]]></description>
<pubDate>Tue, 10 Nov 2009 08:00:00 EST</pubDate>
</item>

<item>
<title><![CDATA[Analog-to-digital conversion (ADC) based on current flow between paired probes and electrodes]]></title>
<link>http://www.freepatentsonline.com/7616139.html</link>
<description><![CDATA[An analog-to-digital converter (ADC) is provided to determine a digital output value according to whether electric current flows between a plurality of probes, to which an input voltage is applied, and a plurality of electrodes. Therefore, high resolution and high speed operation is possible, but with lower power consumption.]]></description>
<pubDate>Tue, 10 Nov 2009 08:00:00 EST</pubDate>
</item>

<item>
<title><![CDATA[Reconfigurable delta sigma analog-to-digital converter and customized digital filters with embedded flash FPGA and flash memory]]></title>
<link>http://www.freepatentsonline.com/7616143.html</link>
<description><![CDATA[An integrated circuit includes at least one analog input. A sample/hold circuit is coupled to the at least one analog input. A reconfigurable delta-sigma ADC is coupled to the sample/hold circuit. A field programmable gate array is coupled to the reconfigurable delta-sigma ADC. A configurable on-chip clock source is coupled to the reconfigurable delta-sigma ADC providing control and reprogrammable oversampling ratio.]]></description>
<pubDate>Tue, 10 Nov 2009 08:00:00 EST</pubDate>
</item>

<item>
<title><![CDATA[Resistor ladder interpolation for PGA and DAC]]></title>
<link>http://www.freepatentsonline.com/7616144.html</link>
<description><![CDATA[A voltage interpolation circuit includes a resistive ladder connected between ground and a voltage input and having a plurality of resistors with voltage taps between the resistors. An amplifier (optionally) has first and second capacitors connected together at their respective first terminals and to an input of the amplifier. A first plurality of switches connect respective taps to a second terminal of the first capacitor. A second plurality of switches connect the respective taps to a second terminal of the second capacitor. An output voltage is interpolated by controlling the first and second pluralities of switches.]]></description>
<pubDate>Tue, 10 Nov 2009 08:00:00 EST</pubDate>
</item>

<item>
<title><![CDATA[Reference circuits for sampled-data circuits]]></title>
<link>http://www.freepatentsonline.com/7616145.html</link>
<description><![CDATA[A switched capacitor circuit includes a first level-crossing detector to generate a level-crossing detection signal when an input signal crosses a first predetermined level. A first waveform generator generates a first predetermined waveform and a second waveform generator generates a second predetermined waveform. A second level-crossing detector generates a second level-crossing detection signal when said second predetermined waveform crosses a voltage reference level a second time. A second switch is coupled to the second level-crossing detector, and a third switch is coupled to the first level-crossing detector. The second switch turns OFF when the second level-crossing detection signal indicates the second predetermined waveform crossed the voltage reference level a second time. The third switch turns OFF when the first level-crossing detection signal indicates the input signal crossed the first predetermined level.]]></description>
<pubDate>Tue, 10 Nov 2009 08:00:00 EST</pubDate>
</item>

<item>
<title><![CDATA[Data compression using a stream selector with edit-in-place capability for compressed data]]></title>
<link>http://www.freepatentsonline.com/7616138.html</link>
<description><![CDATA[A method for encoding an input file into an output file that is compressed so that the number of bits required to represent the output file is less than the number of bits of the input file. The encoding method includes the parsing of the input file into a series of data items, the data items having an order and collectively corresponding to the input file. The encoding method compares the series of data items against a static dictionary having at least mappings between terminal sequence pointers and representations of data items. Each mapping has an associated length, the associated length for a mapping being the length of the data item pointed to by its terminal sequence pointer wherein the terminal sequence pointers are represented by a number of bits that is independent of the particular data items in the input file, the static dictionary being static such that the static dictionary is usable to provide a mapping between a terminal sequence pointer and its corresponding representation of data item independent of mapping of other data items. The encoding method adds to the output file an output file element that is a terminal sequence pointer for data items that map to entries in the static dictionary, each output file including at least one terminal sequence pointer. The encoding method adds to the output file an output file element that is a symbol sequence having one or more symbols for data items that are to be represented directly in the output file, and creates an element mapping for the output file to indicate, for each output file element, whether the output file element corresponds to a terminal sequence pointer or a symbol sequence.]]></description>
<pubDate>Tue, 10 Nov 2009 08:00:00 EST</pubDate>
</item>

<item>
<title><![CDATA[Analog-to-digital converter]]></title>
<link>http://www.freepatentsonline.com/7616147.html</link>
<description><![CDATA[An analog-to-digital converter (ADC) is presented. The ADC includes an error amplifier, a ramp generator, and a counting circuit. The error amplifier is used for receiving an output voltage and a reference voltage, and amplifying a difference between the output voltage and the reference voltage, so as to obtain a first voltage and a second voltage. The ramp generator is used for generating a ramp voltage which is increased along with time. The counting circuit is used for starting counting a digital value when the ramp voltage is larger than or equal to the first voltage, and stopping counting and outputting the digital value when the ramp voltage is larger than or equal to the second voltage.]]></description>
<pubDate>Tue, 10 Nov 2009 08:00:00 EST</pubDate>
</item>

<item>
<title><![CDATA[Method and system for reducing contexts for context based compression systems]]></title>
<link>http://www.freepatentsonline.com/7616132.html</link>
<description><![CDATA[For context based compression techniques, for example Context Based YK compression, a method and system for grouping contexts from a given context model together to create a new context model that has fewer contexts, but retains acceptable compression gains compared to the context model with more contexts is provided. According to an exemplary embodiment a set of files that are correlated to the file to be compressed (hereafter called training files) are read to determine, for an initial context model, the empirical statistics of contexts and symbols. In some embodiments, this includes determining the estimated joint and conditional probabilities of the various contexts and symbols (or blocks of symbols). The initial context model is then reduced to a desired number of contexts, for example, by applying a grouping function g to the original set of contexts to obtain a new and smaller set of contexts. In some embodiments the step of applying a grouping function comprises iteratively grouping a pair of contexts together to form a grouped context, wherein each grouped context represents a local minimum based on the empirical statistics.]]></description>
<pubDate>Tue, 10 Nov 2009 08:00:00 EST</pubDate>
</item>

<item>
<title><![CDATA[Asian language input using keyboard]]></title>
<link>http://www.freepatentsonline.com/7616190.html</link>
<description><![CDATA[A system and process for helping users enter information in an Asian language is described. In some aspects, pinyin input for Chinese is described with respect to dedicated keys of a keyboard.]]></description>
<pubDate>Tue, 10 Nov 2009 08:00:00 EST</pubDate>
</item>

<item>
<title><![CDATA[Image processing method and image processing apparatus]]></title>
<link>http://www.freepatentsonline.com/7616823.html</link>
<description><![CDATA[Information associated with data which was previously transmitted to a client terminal ( 201  or  202 ) is recorded as a history. When a transmission request of data of logical units in tiles required to obtain a desired image is received from the client terminal ( 201 ), the type of progression order used in the client terminal ( 201 ) is discriminated with reference to the history. The transmission order of the data of the logical units in the tiles to be transmitted to the client terminal ( 201 ) is determined in accordance with the discrimination order, and the data of the logical units in the tiles are transmitted to the client terminal ( 201 ) in accordance with the determined transmission order.]]></description>
<pubDate>Tue, 10 Nov 2009 08:00:00 EST</pubDate>
</item>

<item>
<title><![CDATA[TV mute finger ring]]></title>
<link>http://www.freepatentsonline.com/RE40956.html</link>
<description><![CDATA[TV Mute Finger Ring with a hollow C shaped finger ring housing. The housing contains the standard electronics and IR transmitting LED associated with activating the mute function of a standard TV. The housing also contains a battery type electrical power source. The C shaped ring housing has a loop type fastener strip attached to one end of the C shape and a hook type fastening panel affixed to the opposite end of the C shape so that said loop type fastener can removably attach to said hook fastener thereby forming a full ring that can be worn on the user's forefinger. The C shaped housing contains a momentary on-off switch and attached outwardly accessible switch cover located in a position where the user's thumb can easily reach said switch cover. The IR transmitter is covered by a transparent plastic lens that is flush with the outer surface of said C shaped housing. The plastic lens is positioned so that said lens and said IR transmitting LED are pointed outwardly in the general direction of said TV.]]></description>
<pubDate>Tue, 10 Nov 2009 08:00:00 EST</pubDate>
</item>

<item>
<title><![CDATA[Systems and methods for enumerative encoding and decoding of maximum-transition-run codes and PRML (G,I,M) codes]]></title>
<link>http://www.freepatentsonline.com/7616134.html</link>
<description><![CDATA[Systems and methods for encoding/decoding are provided. The systems and methods include encoding a stream of K-bit input sequences into a stream of (G, I, M)-constrained 2N-bit output sequences by transforming each K-bit input bit sequence into two separate data paths including even and odd bits. Enumerative maximum-transition-run (eMTR) encoding of the even bits generates constrained even bits, and enumerative maximum-transition-run (MTR) encoding of the odd bits generates constrained odd bits. The constrained even and constrained odd bits are interleaved to form a stream of (G, I, M)-constrained 2N-bit output sequences where G is a global constraint, I is an interleave constraint, and M is a variable frequency oscillator constraint of a partial-response maximum-likelihood (PRML) codeword. Decoding systems and methods are also provided.]]></description>
<pubDate>Tue, 10 Nov 2009 08:00:00 EST</pubDate>
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