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<title>freepatentsonline.com: Static information storage and retrieval</title>
<link>http://www.freepatentsonline.com/result.html?query_txt=ccl/365%20and%20isd/11/10/2009&amp;uspat=on</link>
<description>USPTO Class 365 Static information storage and retrieval</description>
<language>en-us</language>
<lastBuildDate>Thu, 12 Nov 2009 03:32:01 EST</lastBuildDate>

<item>
<title><![CDATA[Method and apparatus for non-volatile multi-bit memory]]></title>
<link>http://www.freepatentsonline.com/7616472.html</link>
<description><![CDATA[A memory device that selectably exhibits first and second logic levels. A first conductive material has a first surface with a first memory layer formed thereon, and a second conductive material has a second surface with a second memory layer formed thereon. A connective conductive layer joins the first and second memory layers and places the same in electrical contact. The structure is designed so that the first memory layer has a cross-sectional area less than that of the second memory layer.]]></description>
<pubDate>Tue, 10 Nov 2009 08:00:00 EST</pubDate>
</item>

<item>
<title><![CDATA[Dynamic semiconductor storage device and method for operating same]]></title>
<link>http://www.freepatentsonline.com/7616510.html</link>
<description><![CDATA[The object of the present invention is to provide a DRAM, in which the operation speed for a sense amplifier can be increased. Bit line precharging circuits PCt and PCb are arranged to precharge bit lines BLt and /BLt to a ground voltage GND, and reference word lines RWLo and RWLe and reference memory cells RMC are arranged, so that when a word line WL is activated, a potential difference is always generated between the bit lines BLt and /BLt. The sources of transistors N 10  and N 11  of an N-type sense amplifier NSAt are connected directly to a ground terminal GND, and the sources of transistors P 2  and P 3  of a P-type sense amplifier PSA are connected directly to a power source VDD. The gates of the transistors N 10  and N 11  are connected to the bit lines /BLt and BLt, and the drains are connected to the bit lines BLt and /BLt, respectively. Shift word lines SWL and shift memory cells SMC are arranged, so that the N sense amplifier NSAt can amplify the potential difference between the bit lines BLt and /BLt.]]></description>
<pubDate>Tue, 10 Nov 2009 08:00:00 EST</pubDate>
</item>

<item>
<title><![CDATA[Semiconductor device]]></title>
<link>http://www.freepatentsonline.com/7616516.html</link>
<description><![CDATA[A semiconductor device of the present invention has a memory cell array having plural CMOS static memory cells provided at intersecting portions of plural word lines and plural complementary bit lines. In the memory cell array, a switch MOSFET which is in an OFF state in a first operation mode and in an ON state in a second operation mode different from the first operation mode and first-conductivity-type and second-conductivity-type MOSFETs having a diode configuration are provided in parallel between a first source line to which sources of first-conductivity-type MOSFETs constituting first and second CMOS inverter circuits constituting the plural static memory cells are connected and a first power supply line corresponding to the first source line. A second source line to which sources of the second conductivity-type MOSFETs constituting the first and second CMOS inverter circuits are connected is connected to the second power supply line corresponding thereto.]]></description>
<pubDate>Tue, 10 Nov 2009 08:00:00 EST</pubDate>
</item>

<item>
<title><![CDATA[Non-volatile magnetic memory device]]></title>
<link>http://www.freepatentsonline.com/7616477.html</link>
<description><![CDATA[A non-volatile magnetic memory cell having a magnetic element with multiple segments which are not co-linear. Each of the segments is magnetized with a remnant magnetic field using a single write line. The segments can be magnetized in a first direction or a second direction, corresponding to first and second orientations of the memory cell. A sensor is provided to determine the direction in which the segments are magnetized and thereby the orientation of the cell. The segments are oriented such that the magnetic flux fields created by their respective remnant magnetic fields have a cumulative effect at a sensing region of the sensor. The cumulative effect allows a less sensitive sensor to be used than in known device. In various embodiments, the magnetic element can have a number of linear segments or a curved profile. In another embodiment, multiple magnetic elements are magnetized by a single write line. The multiple magnetic elements are arranged such that remnant magnetic field stored in them can be cumulatively sensed. In another embodiment, the magnetic element is arranged to be magnetized in a single general direction, but is shaped such that magnetic flux lines emanate from it in different directions. The different directions are arranged to direct flux lines through the sensing region of a sensor, which measures their cumulative effect.]]></description>
<pubDate>Tue, 10 Nov 2009 08:00:00 EST</pubDate>
</item>

<item>
<title><![CDATA[Offset compensated sensing for magnetic random access memory]]></title>
<link>http://www.freepatentsonline.com/7616474.html</link>
<description><![CDATA[An offset compensated memory element voltage supply including a differential amplifier with a compensation circuit, and a transistor with a gate connected to the output of the differential amplifier. The compensation circuit of the differential amplifier includes a compensation capacitor that stores a compensation voltage during a calibration phase, and applies the stored compensation voltage to a compensation input of the compensation circuit of the amplifier during a measurement phase. Feedback from a source of the transistor controls the output of the differential amplifier to maintain a standard voltage across a resistive memory element connected to the source during measurement of the resistance of the resistive memory element, and the compensation circuit improves the accuracy of the voltage across the resistive memory element by compensating for an offset voltage of the differential amplifier.]]></description>
<pubDate>Tue, 10 Nov 2009 08:00:00 EST</pubDate>
</item>

<item>
<title><![CDATA[NOR flash memory and related read method]]></title>
<link>http://www.freepatentsonline.com/7616497.html</link>
<description><![CDATA[A NOR flash memory is disclosed including a memory cell, sense amplifier output driver, and control circuit. A sense period for a sense operation performed by the sense amplifier is made synchronous with a clock signal so as to avoid power supply or ground signal noise generated by operation of the output driver.]]></description>
<pubDate>Tue, 10 Nov 2009 08:00:00 EST</pubDate>
</item>

<item>
<title><![CDATA[Dynamic voltage adjustment for memory]]></title>
<link>http://www.freepatentsonline.com/7616509.html</link>
<description><![CDATA[A power supply voltage for a memory on an integrated circuit is dynamically adjusted during the operating of the memory. The operating of the memory includes powering the memory at a supply voltage. A test memory of the integrated circuit is concurrently powered while operating the memory. The test memory and the memory each include bit cells of a first bit cell configuration type. A voltage level of the supply voltage is adjusted, while operating the memory, based on the testing of the test memory. The voltage level is adjusted with external variations to assume a value that guarantees no failed operation of the memory but also accurately minimizes the supply voltage. The system and method may be implemented with any type of memory. The memory and test memory may be physically implemented either separated or interspersed on the integrated circuit.]]></description>
<pubDate>Tue, 10 Nov 2009 08:00:00 EST</pubDate>
</item>

<item>
<title><![CDATA[Memory device, current sense amplifier, and method of operating the same]]></title>
<link>http://www.freepatentsonline.com/7616513.html</link>
<description><![CDATA[A memory device, current sense amplifier and method of operating the same are disclosed herein. In accordance with one embodiment, the current sense amplifier circuit may include a pair of cross-coupled transistors, a pair of output nodes and a first pair of load transistors. The pair of cross-coupled transistors may be coupled for receiving a pair of differential currents and for generating a pair of differential voltages, which may then be supplied to the pair of output nodes. The first pair of load transistors may have mutually-connected gate terminals, mutually-connected drain terminals, and a source terminal coupled to a different one of the output nodes. In a unique aspect of the invention, an equalization transistor may coupled between the pair of output nodes for equalizing the pair of differential voltages for a predetermined amount of time at the beginning of a sense cycle. As such, the equalization transistor may be added to prevent the current sense amplifier circuit from generating erroneous results during the predetermined time period.]]></description>
<pubDate>Tue, 10 Nov 2009 08:00:00 EST</pubDate>
</item>

<item>
<title><![CDATA[Ferroelectric memory device]]></title>
<link>http://www.freepatentsonline.com/7616471.html</link>
<description><![CDATA[A ferroelectric memory array includes a plurality of bit lines; a plurality of memory cells connected to the bit lines and storing predetermined data; and a plurality of sense amplifiers provided in correspondence with the bit lines and amplifying data that are read out from the memory cells. The sense amplifiers each include a first n-MOS transistor, a first voltage being supplied to a source of the first n-MOS transistor; a first precharge unit precharging a drain of the first n-MOS transistor to a second voltage, which is a positive voltage that is higher than the first voltage; a transistor control unit that lowers the drain voltage that has been precharged to the second voltage by controlling a resistance between the source and the drain of the first n-MOS transistor in accordance with a voltage on a corresponding bit line, when data stored in the memory cells is read out to that bit line; and a voltage control unit that lowers the voltage of the bit line in accordance with the lowering of the voltage of the drain.]]></description>
<pubDate>Tue, 10 Nov 2009 08:00:00 EST</pubDate>
</item>

<item>
<title><![CDATA[Thin film magnetic memory device suitable for drive by battery]]></title>
<link>http://www.freepatentsonline.com/7616476.html</link>
<description><![CDATA[After a digit line is charged to a power supply voltage by turn-on of a first switching element, the first switching element is turned off and a second switching element is turned on, whereby the digit line is connected to a ground voltage. Similarly, in order to feed data write current, a bit line is charged to a data voltage in accordance with write data through a third switching element. Then, the bit line is connected to a voltage different from the data voltage by a fourth switching element while the third switching element is turned off. Therefore, a load current from a power supply to an MRAM device is supplied during charging of a digit line capacitance and a bit line capacitance, without being consumed when the data write current flows. Consequently, a peak of the load current supplied from the power supply is suppressed.]]></description>
<pubDate>Tue, 10 Nov 2009 08:00:00 EST</pubDate>
</item>

<item>
<title><![CDATA[Magnetic storage device]]></title>
<link>http://www.freepatentsonline.com/7616478.html</link>
<description><![CDATA[A magnetic storage device comprises an array of magnetic memory cells ( 50 ). Each cell ( 50 ) has, in electrical series connection, a magnetic tunnel junction (MTJ) ( 30 ) and a Zener diode ( 40 ). The MTJ ( 30 ) comprises, in sequence, a fixed ferromagnetic layer (FMF) ( 32 ), a non-magnetic spacer layer ( 33 ), a tunnel barrier layer ( 34 ), a further spacer layer ( 35 ), and a soft ferromagnetic layer (FMS) ( 36 ) that can change the orientation of its magnetic moment. The material type and thickness of each layer in the MTJ ( 30 ) is selected so that the cell ( 50 ) can be written by applying a voltage across the cell, which sets the orientation of the magnetic moments of the FMF ( 32 ) and FMS ( 36 ) relative to one another. The switching is effected by means of an induced exchange interaction between the FMS and FMF mediated by the tunneling of spin-polarized electrons in the MTJ ( 30 ). The cell ( 50 ) therefore has low power consumption during write operations allowing for fast writing and dense integration of cells ( 50 ) in an array. The mechanism used to control the array to write and sense the information stored in the cells ( 50 ) is simplified.]]></description>
<pubDate>Tue, 10 Nov 2009 08:00:00 EST</pubDate>
</item>

<item>
<title><![CDATA[Integrated electronic device having a low voltage electric supply]]></title>
<link>http://www.freepatentsonline.com/7616515.html</link>
<description><![CDATA[An integrated electronic device includes at least one supply pin and at least one booster coupled to said at least one supply pin. Moreover, there is at least one integrated circuit powered by the at least one booster and associated therewith in a “system in a package configuration.”]]></description>
<pubDate>Tue, 10 Nov 2009 08:00:00 EST</pubDate>
</item>

<item>
<title><![CDATA[Super leakage current cut-off device for ternary content addressable memory]]></title>
<link>http://www.freepatentsonline.com/7616469.html</link>
<description><![CDATA[A super leakage current cut-off device for a ternary content addressable memory (TCAM) is provided. For various operations of the TCAM, the device uses the high-end and low-end power gating control transistors to turn on/off the don't-care cells to reduce the leakage current passing through the don't-care cells.]]></description>
<pubDate>Tue, 10 Nov 2009 08:00:00 EST</pubDate>
</item>

<item>
<title><![CDATA[Cell array of semiconductor memory device and method of driving the same]]></title>
<link>http://www.freepatentsonline.com/7616486.html</link>
<description><![CDATA[A cell array of a flash memory device includes first and second memory block units, and a voltage generator. Each of the first and second memory block units includes a plurality of memory blocks having a plurality of memory cells. The voltage generator outputs a source voltage, a power supply voltage and a positive bias to the first and second memory block units. The first and second memory block units are connected in parallel through a bit line.]]></description>
<pubDate>Tue, 10 Nov 2009 08:00:00 EST</pubDate>
</item>

<item>
<title><![CDATA[Memory element and memory]]></title>
<link>http://www.freepatentsonline.com/7616475.html</link>
<description><![CDATA[A memory element including a memory layer that retains information based on a magnetization state of a magnetic material is provided. In the memory element, a magnetization pinned layer is provided for the memory layer through an intermediate layer, the intermediate layer is formed of an insulator, spin-polarized electrons are injected in a stacking direction to change a magnetization direction of the memory layer, so that information is recorded in the memory layer. Also, a ferromagnetic layer forming the memory layer has a magnetostriction constant of 1×10 −5  or more.]]></description>
<pubDate>Tue, 10 Nov 2009 08:00:00 EST</pubDate>
</item>

<item>
<title><![CDATA[Memories with alternate sensing techniques]]></title>
<link>http://www.freepatentsonline.com/7616481.html</link>
<description><![CDATA[The present invention presents a scheme for sensing memory cells. Selected memory cells are discharged through their channels to ground and then have a voltage level placed on the traditional source and another voltage level placed on the control gate, and allowing the cell bit line to charge up. The bit line of the memory cell will then charge up until the bit line voltage becomes sufficiently high to shut off any further cell conduction. The rise of the bit line voltage will occur at a rate and to a level dependent upon the data state of the cell, and the cell will then shut off when the bit line reaches a high enough level such that the body effect affected memory cell threshold is reached, at which point the current essentially shuts off. A particular embodiment performs multiple such sensing sub-operations, each with a different control gate voltage, but with multiple states being sensed in each operation by charging the previously discharged cells up through their source.]]></description>
<pubDate>Tue, 10 Nov 2009 08:00:00 EST</pubDate>
</item>

<item>
<title><![CDATA[Method for reducing charge loss in analog floating gate cell]]></title>
<link>http://www.freepatentsonline.com/7616501.html</link>
<description><![CDATA[A voltage reference circuit provides a reference voltage in response to a programmed threshold voltage of a first non-volatile memory (NVM) transistor. The threshold voltage of the first NVM transistor is programmed by applying a programming voltage to commonly connected source/drain regions of a tunneling capacitor, which shares a floating gate with the first NVM transistor. During normal operation of the voltage reference circuit, the source/drain regions of the tunneling capacitor are connected to a second NVM transistor that has the same electrical and thermal characteristics as the floating gate of the first NVM transistor. As a result, charge loss from the floating gate of the first NVM transistor is advantageously minimized.]]></description>
<pubDate>Tue, 10 Nov 2009 08:00:00 EST</pubDate>
</item>

<item>
<title><![CDATA[Microprocessor boot-up controller, nonvolatile memory controller, and information processing system]]></title>
<link>http://www.freepatentsonline.com/7616507.html</link>
<description><![CDATA[A memory system including a nonvolatile semiconductor memory device and a controller. The memory device includes a plurality of word lines; and a plurality of memory cells each connected to a corresponding one of the word lines and each having N threshold voltages for storing multi-valued level, where N is a natural number of 4 or greater; wherein stored data in each of the plurality of memory cells constitutes a plurality of pages, at least only a part of multi-value level is used for storing data, a data “1” is always written to a lower page, a “0” or “1” binary data is written to an upper page, the same data is written in each of the pages when writing in the nonvolatile memory device, and only part of the pages to which the same data is written is accessed when reading out the nonvolatile memory device.]]></description>
<pubDate>Tue, 10 Nov 2009 08:00:00 EST</pubDate>
</item>

<item>
<title><![CDATA[Input/output line sense amplifier and semiconductor memory device using the same]]></title>
<link>http://www.freepatentsonline.com/7616511.html</link>
<description><![CDATA[An input/output (I/O) line sense amplifier includes a buffer unit, a sense amplifier, and a precharge unit. The buffer unit is driven by a first level voltage to buffer a strobe signal, and the sense amplifier is driven by a second level voltage to amplify a signal of an I/O line in response to an output signal of the buffer unit. The precharge unit is driven by the first level voltage to precharge an output signal of the sense amplifier in response to the output signal of the buffer unit.]]></description>
<pubDate>Tue, 10 Nov 2009 08:00:00 EST</pubDate>
</item>

<item>
<title><![CDATA[Multi-port memory device with serial input/output interface]]></title>
<link>http://www.freepatentsonline.com/7616518.html</link>
<description><![CDATA[A multi-port memory device includes a plurality of ports located at a center region of the multi-port memory device, each for performing a data communication with a corresponding external device; a plurality of banks arranged at upper and lower regions of the multi-port memory device in a row direction on the basis of the plurality of ports; and first and second global I/O data buses arranged in the row direction between the banks and the ports, each for independently performing a data transmission between the banks and the ports.]]></description>
<pubDate>Tue, 10 Nov 2009 08:00:00 EST</pubDate>
</item>

<item>
<title><![CDATA[Devices and methods for controlling active termination resistors in a memory system]]></title>
<link>http://www.freepatentsonline.com/7616473.html</link>
<description><![CDATA[A termination resistor is mounted on a memory circuit and provides a termination resistance for the memory circuit. The termination resistor includes a node, a plurality of first termination resistors responsive to a corresponding control signal and connected between a power voltage and the node, and a plurality of second termination resistors responsive to a corresponding control signal and connected between a ground voltage and the node.]]></description>
<pubDate>Tue, 10 Nov 2009 08:00:00 EST</pubDate>
</item>

<item>
<title><![CDATA[System that compensates for coupling based on sensing a neighbor using coupling]]></title>
<link>http://www.freepatentsonline.com/7616480.html</link>
<description><![CDATA[Shifts in the apparent charge stored on a floating gate (or other charge storing element) of a non-volatile memory cell can occur because of the coupling of an electric field based on the charge stored in adjacent floating gates (or other adjacent charge storing elements). To compensate for this coupling, the read or programming process for a given memory cell can take into account the programmed state of an adjacent memory cell. To determine whether compensation is needed, a process can be performed that includes sensing information about the programmed state of an adjacent memory cell (e.g., on an adjacent bit line or other location).]]></description>
<pubDate>Tue, 10 Nov 2009 08:00:00 EST</pubDate>
</item>

<item>
<title><![CDATA[Current or voltage measurement circuit, sense circuit, semiconductor non-volatile memory, and differential amplifier]]></title>
<link>http://www.freepatentsonline.com/7616488.html</link>
<description><![CDATA[In a wire pair  120  including a first signal line  120 a  and a second signal line  120 b , the first signal line  120 a  and the second signal line  120 b  are laid out so that they have substantially the same stray capacitance. Two output terminals of a measured device  1000  and an input terminal of a differential amplifier  110  are connected together by the wire pair  120 . Thus, noise included in the first signal line  120 a  and noise included in the second signal line  120 b  become common-mode noise, which are canceled out by the differential amplification of the differential amplifier  110.]]></description>
<pubDate>Tue, 10 Nov 2009 08:00:00 EST</pubDate>
</item>

<item>
<title><![CDATA[Programming non-volatile memory with dual voltage select gate structure]]></title>
<link>http://www.freepatentsonline.com/7616490.html</link>
<description><![CDATA[A select gate structure for a non-volatile storage system includes a select gate and a coupling electrode which are independently drivable. The coupling electrode is adjacent to a word line in a NAND string and has a voltage applied which reduces gate induced drain lowering (GIDL) program disturb of an adjacent unselected non-volatile storage element. In particular, an elevated voltage can be applied to the coupling electrode when the adjacent word line is used for programming. A reduced voltage is applied when a non-adjacent word line is used for programming. The voltage can also be set based on other programming criterion. The select gate is provided by a first conductive region while the coupling electrode is provided by a second conductive region formed over, and isolated from, the first conductive region.]]></description>
<pubDate>Tue, 10 Nov 2009 08:00:00 EST</pubDate>
</item>

<item>
<title><![CDATA[Semiconductor memory device improved in data writing]]></title>
<link>http://www.freepatentsonline.com/7616491.html</link>
<description><![CDATA[A bit line is shared by first and second NAND units. First and second selection transistors are connected in series between the bit line and the first NAND unit. Third and fourth selection transistors are connected in series between the bit line and the second NAND unit. A control unit changes a first and second signals and a potential of the bit line from a first level to a second level higher than a first level, and changes the potential of the bit line from the second level to the first level after changing the first signal from the second level to the first level.]]></description>
<pubDate>Tue, 10 Nov 2009 08:00:00 EST</pubDate>
</item>

<item>
<title><![CDATA[Retention margin program verification]]></title>
<link>http://www.freepatentsonline.com/7616499.html</link>
<description><![CDATA[Data verification in a memory device using a portion of a data retention margin is provided. A bit count is read from the region to determine whether errors will result in the memory. A read in one or more retention margin portions is performed after the normal program verify sequence and if the number of bits in these regions is more than a pre-set the memory will fail verify status. A method of verifying data in a memory device includes the steps of: defining an retention margin between adjacent data thresholds; programming the memory device with data; determining whether bits are present in the data retention margin; and if the number of bits in the retention margin exceeds a threshold, generating an error.]]></description>
<pubDate>Tue, 10 Nov 2009 08:00:00 EST</pubDate>
</item>

<item>
<title><![CDATA[High speed array pipeline architecture]]></title>
<link>http://www.freepatentsonline.com/7616504.html</link>
<description><![CDATA[A memory device comprising a memory array having a plurality of memory cells, and a plurality of peripheral devices for reading data out of and writing data into the memory array, the peripheral devices include a first write driver connected to a first input/output line, the first input/output line being associated with a digitline connected to certain of the plurality of memory cells, a first read amplifier connected to the first input/output line, a first input/output device responsive to a first column select signal for connecting the first input/output line to the digitline, a second write driver connected to a second input/output line, the second input/output line being associated with the digitline, a second read amplifier connected to the second input/output line, and a second input/output device responsive to a second column select signal for connecting the second input/output line to the digitline.]]></description>
<pubDate>Tue, 10 Nov 2009 08:00:00 EST</pubDate>
</item>

<item>
<title><![CDATA[Semiconductor memory device with hierarchical bit line structure]]></title>
<link>http://www.freepatentsonline.com/7616512.html</link>
<description><![CDATA[A semiconductor memory device has a hierarchical bit line structure. The semiconductor memory device may include first and second memory cell clusters, which share the same bit line pair and are divided operationally; third and fourth memory cell clusters, which are connected respectively corresponding to word lines coupled with the first and second memory cell clusters, and which share a bit line pair different from the bit line pair and are divided operationally; and a column pass gate for switching one of bit line pairs connected with the first to fourth memory cell clusters, to a common sense amplifier, in response to a column selection signal. Whereby an operating speed decrease caused by load of peripheral circuits connected to the bit line is improved, and the number of column pass gates is reduced substantially with a reduction of chip size.]]></description>
<pubDate>Tue, 10 Nov 2009 08:00:00 EST</pubDate>
</item>

<item>
<title><![CDATA[Apparatus and method for generating an imprint-stabilized reference voltage for use in a ferroelectric memory device]]></title>
<link>http://www.freepatentsonline.com/7616514.html</link>
<description><![CDATA[A reference voltage supply apparatus and a driving method thereof in a ferroelectric memory device provide a reference voltage stabilized against the imprint effect thus maintaining reading reliability of the device. In the reference voltage supply apparatus (e.g., using a non-switching capacitance of a ferroelectric capacitor), a reference cell is constructed of a ferroelectric capacitor and an access switch, and provides a reference voltage to read data from a memory cell. In an active mode, the reference cell stores data of a first logic state (e.g., corresponding to the non-switching capacitance of the ferroelectric capacitor), in the reference cell, and then supplies, as a reference voltage, the voltage corresponding to the data of the first logic state to a bit line; and in a stand-by mode, a reference voltage controller stores (writes) data of a second logic state (opposite to the first logic state), into the reference cell.]]></description>
<pubDate>Tue, 10 Nov 2009 08:00:00 EST</pubDate>
</item>

<item>
<title><![CDATA[Semiconductor integrated circuit device]]></title>
<link>http://www.freepatentsonline.com/7616519.html</link>
<description><![CDATA[The present invention provides a technique capable of achieving area reduction on a semiconductor integrated circuit device mounted with a time sharing virtual multi port memory or the like. By providing a configuration including a single port memory, data latch circuit for plural ports, a selector for selecting a port to be connected to the single port memory, a time sharing control signal generating circuit and the like, in which an operation termination signal inside the single port memory (a word line rising signal, a sense amplifier driving signal for data read or the like) is inputted to the time sharing control signal generating circuit to produce a port switching control signal and an operation control signal for the single port memory, a time sharing virtual multi port memory with a reduced area can be realized which requires no clock generating circuit for time sharing control newly.]]></description>
<pubDate>Tue, 10 Nov 2009 08:00:00 EST</pubDate>
</item>

<item>
<title><![CDATA[Method and apparatus for reducing power consumption in a content addressable memory]]></title>
<link>http://www.freepatentsonline.com/7616468.html</link>
<description><![CDATA[Power consumption in a multi-level hierarchical Content Addressable Memory (CAM) circuit is reduced without adversely impacting performance. According to one embodiment of a multi-level hierarchical CAM circuit, the CAM circuit includes a plurality of lower-level match lines, a plurality of higher-level match lines and match line restoration circuitry. The lower-level match lines are configured to be restored to a pre-evaluation state during a pre-evaluation period. The higher-level match lines are configured to capture an evaluation state of respective groups of one or more of the lower-level match lines during an evaluation period and to be restored to a pre-evaluation state during the pre-evaluation period. The match line restoration circuitry is configured to prevent at least one of the lower-level match lines from being restored to the pre-evaluation state responsive to corresponding enable information, e.g., one or more bits indicating whether match line search results are to be utilized.]]></description>
<pubDate>Tue, 10 Nov 2009 08:00:00 EST</pubDate>
</item>

<item>
<title><![CDATA[Data writing method for flash memories]]></title>
<link>http://www.freepatentsonline.com/7616479.html</link>
<description><![CDATA[A data writing method for flash memories suitable for a flash memory using a switching unit to control a bit line thereof is disclosed. The data writing method for flash memories includes applying a square wave signal to a word line of the flash memory and applying a descent wave signal to the switching unit for the bit line of the flash memory to receive a fixed drain voltage.]]></description>
<pubDate>Tue, 10 Nov 2009 08:00:00 EST</pubDate>
</item>

<item>
<title><![CDATA[Evaluation circuit and evaluation method for the assessment of memory cell states]]></title>
<link>http://www.freepatentsonline.com/7616492.html</link>
<description><![CDATA[An electronic circuit arrangement includes a storage unit set up for storing at least two analog electrical quantities. A first evaluation circuit is coupled to the storage unit and is set up in such a way that it assesses the at least two analog electrical quantities and provides a first assessment result. A second evaluation circuit is coupled to the storage unit and is set up in such a way that it assesses at least one of the at least two analog electrical quantities with a predetermined threshold value and provides a second assessment result.]]></description>
<pubDate>Tue, 10 Nov 2009 08:00:00 EST</pubDate>
</item>

<item>
<title><![CDATA[Non-volatile storage apparatus with variable initial program voltage magnitude]]></title>
<link>http://www.freepatentsonline.com/7616495.html</link>
<description><![CDATA[Multiple programming processes are performed for a plurality of non-volatile storage elements. Each of the programming process operates to program at least a subset of said non-volatile storage elements to a set of target conditions using program pulses. In one embodiment, a first programming pass includes soft programming and additional programming passes include the programming of data. In another embodiment, all of the programming process include programming data. For at least a subset of said programming processes, a program pulse associated with achieving a particular result for a respective programming process is identified. The identified program pulse is used to adjust programming for a subsequent programming process.]]></description>
<pubDate>Tue, 10 Nov 2009 08:00:00 EST</pubDate>
</item>

<item>
<title><![CDATA[Non-volatile storage system with resistance sensing and compensation]]></title>
<link>http://www.freepatentsonline.com/7616498.html</link>
<description><![CDATA[When reading data from a non-volatile storage element that is part of a group of connected non-volatile storage elements, resistance information is measured for the group. One or more read parameters are set based on the measured resistance information. The read process is then performed using the one or more parameters.]]></description>
<pubDate>Tue, 10 Nov 2009 08:00:00 EST</pubDate>
</item>

<item>
<title><![CDATA[Non-volatile storage apparatus with multiple pass write sequence]]></title>
<link>http://www.freepatentsonline.com/7616500.html</link>
<description><![CDATA[A set of non-volatile storage elements are erased to an erased threshold voltage distribution. A multi-pass programming process is performed that programs the set of non-volatile storage elements from the erased threshold voltage distribution to a set valid data threshold voltage distributions. Each programming pass has one or more starting threshold voltage distributions and programs non-volatile storage elements to at least two ending threshold voltage distributions.]]></description>
<pubDate>Tue, 10 Nov 2009 08:00:00 EST</pubDate>
</item>

<item>
<title><![CDATA[Nonvolatile semiconductor memory]]></title>
<link>http://www.freepatentsonline.com/7616502.html</link>
<description><![CDATA[A semiconductor memory device comprising: a memory cell array having memory cell units each formed by connecting a plurality of memory cells; a first and a second select gate transistors, the first select gate transistor being connected between one end of the memory cell array and a common source line, the second select gate transistor being connected between the other end of the memory cell array and bit lines; word lines acting also as control gates of the memory cells; a first select gate voltage-generating circuit for generating a first select gate voltage; a second select gate-setting circuit for setting an instructed value of a second select gate voltage; a second select gate voltage-generating circuit for generating the second select gate voltage based on the set, instructed value; a first transfer circuit for transferring the first select gate voltage generated by the first select gate voltage-generating circuit to a second select gate; a discharging circuit for discharging the first select gate voltage transferred to the second select gate; and a discharging characteristics selection circuit for selecting discharging characteristics of the discharging circuit.]]></description>
<pubDate>Tue, 10 Nov 2009 08:00:00 EST</pubDate>
</item>

<item>
<title><![CDATA[Complete word line look ahead with efficient data latch assignment in non-volatile memory read operations]]></title>
<link>http://www.freepatentsonline.com/7616505.html</link>
<description><![CDATA[Shifts in the apparent charge stored by a charge storage region such as a floating gate in a non-volatile memory cell can occur because of electrical field coupling based on charge stored by adjacent cells. To account for the shift, compensations are applied when reading. When reading a selected word line, the adjacent word line is read first and the data stored in a set of data latches for each bit line. One latch for each bit line stores an indication that the data is from the adjacent word line. The selected word line is then read with compensations based on the different states of the cells on the adjacent word line. Each sense module uses the data from the adjacent word line to select the results of sensing with the appropriate compensation for its bit line. The data from the adjacent word line is overwritten with data from the selected word line at the appropriate time and the indication updated to reflect that the latches store data from the selected word line. The efficient use of the data latches eliminates the need for separate latches to store data from the adjacent word line.]]></description>
<pubDate>Tue, 10 Nov 2009 08:00:00 EST</pubDate>
</item>

<item>
<title><![CDATA[Systems for complete word line look ahead with efficient data latch assignment in non-volatile memory read operations]]></title>
<link>http://www.freepatentsonline.com/7616506.html</link>
<description><![CDATA[Shifts in the apparent charge stored by a charge storage region such as a floating gate in a non-volatile memory cell can occur because of electrical field coupling based on charge stored by adjacent cells. To account for the shift, compensations are applied when reading. When reading a selected word line, the adjacent word line is read first and the data stored in a set of data latches for each bit line. One latch for each bit line stores an indication that the data is from the adjacent word line. The selected word line is then read with compensations based on the different states of the cells on the adjacent word line. Each sense module uses the data from the adjacent word line to select the results of sensing with the appropriate compensation for its bit line. The data from the adjacent word line is overwritten with data from the selected word line at the appropriate time and the indication updated to reflect that the latches store data from the selected word line. The efficient use of the data latches eliminates the need for separate latches to store data from the adjacent word line.]]></description>
<pubDate>Tue, 10 Nov 2009 08:00:00 EST</pubDate>
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<item>
<title><![CDATA[Semiconductor memory device selectively enabling address buffer according to data output]]></title>
<link>http://www.freepatentsonline.com/7616521.html</link>
<description><![CDATA[A semiconductor memory device can reduce needless current consumption when addresses are inputted. A semiconductor memory device includes a clock enable buffering unit for receiving a clock enable signal to output a buffer enable signal, an address buffer control unit for generating an address buffer control signal in response to a plurality of data output mode, and an address buffering unit for receiving an address in response to the buffer enable signal and the address buffer control signal.]]></description>
<pubDate>Tue, 10 Nov 2009 08:00:00 EST</pubDate>
</item>

<item>
<title><![CDATA[Multi-state memory cell with asymmetric charge trapping]]></title>
<link>http://www.freepatentsonline.com/7616482.html</link>
<description><![CDATA[A multi-state NAND memory cell includes two drain/source areas in a substrate. An oxide-nitride-oxide structure is formed above the substrate between the drain/source areas. The nitride layer acting as an asymmetric charge trapping layer. A control gate is located above the oxide-nitride-oxide structure. An asymmetrical bias on the drain/source areas causes the drain/source area with the higher voltage to inject an asymmetric distribution hole by gate induced drain leakage injection into the trapping layer substantially adjacent that drain/source area.]]></description>
<pubDate>Tue, 10 Nov 2009 08:00:00 EST</pubDate>
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<item>
<title><![CDATA[Multi-bit-per-cell flash memory device with an extended set of commands]]></title>
<link>http://www.freepatentsonline.com/7616483.html</link>
<description><![CDATA[A multi-bit-per-cell flash memory device supports a command such that each invocation of the command by the device's host changes respective values of one or more types of reference voltage (e.g., all read reference voltages and/or all program verify reference voltages) of the device to respective new values.]]></description>
<pubDate>Tue, 10 Nov 2009 08:00:00 EST</pubDate>
</item>

<item>
<title><![CDATA[Semiconductor memory device having faulty cells]]></title>
<link>http://www.freepatentsonline.com/7616485.html</link>
<description><![CDATA[In response to a read command received by a system interface unit for accessing a plurality of blocks of data stored in said non-volatile semiconductor memory, a controller carries out selective read operations of blocks of data to two memories from the non-volatile semiconductor memory. The controller also carries out parallel operations of data transferring a first block of data, which has already been subjected to error detection and error correction operations by an error correction unit, from one of the two memories to a host system via said system interface unit and of data transferring of a second block of data to be subjected to the error detection and error correction operation, from said non-volatile semiconductor memory to the other of the two memories.]]></description>
<pubDate>Tue, 10 Nov 2009 08:00:00 EST</pubDate>
</item>

<item>
<title><![CDATA[Decoders and decoding methods for nonvolatile semiconductor memory devices]]></title>
<link>http://www.freepatentsonline.com/7616487.html</link>
<description><![CDATA[A decoder for a non-volatile semiconductor memory device includes a level shifter configured to generate a negative first voltage at an output thereof responsive to a first state of a global word line and to generate a second voltage more positive than the first voltage responsive to a second state of the global word line. The decoder further includes a local word line driver having an input coupled to the output of the level shifter and configured to apply a voltage on a partial word line to a local word line when the output of the level shifter is at the first voltage and to apply the first voltage to the local word line when the output of the level shifter is at the second voltage.]]></description>
<pubDate>Tue, 10 Nov 2009 08:00:00 EST</pubDate>
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<item>
<title><![CDATA[Memory array segmentation and methods]]></title>
<link>http://www.freepatentsonline.com/7616489.html</link>
<description><![CDATA[The invention provides methods and apparatus. A memory array has a first well region having a first conductivity type. A plurality of second well regions of a second conductivity type is formed in the first well region. The second well regions are electrically isolated from each other. A plurality of memory cells, arranged in row and column fashion, is formed on each second well region. Corresponding rows of memory cells of the respective second well regions are commonly coupled to a word line.]]></description>
<pubDate>Tue, 10 Nov 2009 08:00:00 EST</pubDate>
</item>

<item>
<title><![CDATA[Charge trap type non-volatile memory device and program method thereof]]></title>
<link>http://www.freepatentsonline.com/7616496.html</link>
<description><![CDATA[A method of programming a charge trap type non-volatile memory device includes applying a program pulse to a selected memory cell, applying a detrap pulse to the selected memory cell, and applying a program verify pulse to the memory cell. The charge trap type non-volatile memory device includes a memory cell array including a charge trap memory cell, and a high voltage generator for supplying a detrap pulse to the charge trap memory cell.]]></description>
<pubDate>Tue, 10 Nov 2009 08:00:00 EST</pubDate>
</item>

<item>
<title><![CDATA[Flash-based FPGA with secure reprogramming]]></title>
<link>http://www.freepatentsonline.com/7616508.html</link>
<description><![CDATA[A flash-based programmable integrated circuit includes programmable circuitry, a flash memory array coupled to the programmable circuitry for configuring it, flash programming circuitry for programming the flash memory array, and an on-chip intelligence, such as a microcontroller or state machine, coupled to the programming circuitry to program the flash memory from off-chip data supplied via an I/O pad, or to refresh the data stored in the flash memory to prevent it from degrading.]]></description>
<pubDate>Tue, 10 Nov 2009 08:00:00 EST</pubDate>
</item>

<item>
<title><![CDATA[Integrated circuit device and electronic instrument]]></title>
<link>http://www.freepatentsonline.com/7616520.html</link>
<description><![CDATA[An integrated circuit device having a display memory which stores data for at least one frame from among image information displayed in a display panel which has a plurality of scan lines and a plurality of data lines, wherein the display memory includes a plurality of RAM blocks each of which includes first and second RAM block regions; wherein each of the RAM blocks includes a wordline control circuit which controls a plurality of wordlines provided in each of the first and second RAM block regions; wherein the wordline control circuit is disposed between the first and second RAM block regions; wherein the first and second RAM block regions are disposed along a first direction; and wherein the wordlines extend along the first direction.]]></description>
<pubDate>Tue, 10 Nov 2009 08:00:00 EST</pubDate>
</item>

<item>
<title><![CDATA[Soft errors handling in EEPROM devices]]></title>
<link>http://www.freepatentsonline.com/7616484.html</link>
<description><![CDATA[Soft errors occur during normal use of a solid-state memory such as EEPROM or Flash EEPROM. A soft error results from the programmed threshold voltage of a memory cell being drifted from its originally intended level. The error is initially not readily detected during normal read until the cumulative drift becomes so severe that it develops into a hard error. Data could be lost if enough of these hard errors swamps available error correction codes in the memory. A memory device and techniques therefor are capable of detecting these drifts and substantially maintaining the threshold voltage of each memory cell to its intended level throughout the use of the memory device, thereby resisting the development of soft errors into hard errors.]]></description>
<pubDate>Tue, 10 Nov 2009 08:00:00 EST</pubDate>
</item>

<item>
<title><![CDATA[Config logic power saving method]]></title>
<link>http://www.freepatentsonline.com/7616517.html</link>
<description><![CDATA[A circuit which includes an IP cell having a function select input signal line, combinatorial logic having an output connected to the function select input signal line of the IP cell, a configuration register having an output connected to an input of the combinatorial logic, wherein a high/low input signal line is also connected to the combinatorial logic, wherein the circuit provided that the configuration register receives configuration data during a start-up sequence, and configuration data is held by the combinatorial logic as the configuration register powers down during a functional mode.]]></description>
<pubDate>Tue, 10 Nov 2009 08:00:00 EST</pubDate>
</item>

<item>
<title><![CDATA[Semiconductor memory device]]></title>
<link>http://www.freepatentsonline.com/7616630.html</link>
<description><![CDATA[A semiconductor memory device resolves skew problem due to delay difference between the case when data that is inputted through data input/output (IO) pin is transferred to one global I/O bus and the case when transferred to another global I/O bus based on data width option. The semiconductor memory device includes a first data IO pad formed at one side of a chip, a second data IO pad formed at the other one, a first global data bus receiving data from the first data IO pad, a second global data bus receiving data from the second data IO pad, a first data path for transferring data from the first data IO pad to the first global data bus, a second data path for transferring data from the first data IO pad to the second global data bus, and a third data path for transferring data inputted to the second data IO pad to the first global data bus depending on data width option, wherein data transfer time of the second data path is substantially equal to data transfer time of the third data path.]]></description>
<pubDate>Tue, 10 Nov 2009 08:00:00 EST</pubDate>
</item>

<item>
<title><![CDATA[Method for achieving very high bandwidth between the levels of a cache hierarchy in 3-dimensional structures, and a 3-dimensional structure resulting therefrom]]></title>
<link>http://www.freepatentsonline.com/7616470.html</link>
<description><![CDATA[A method of electronic computing, and more specifically, a method of design of cache hierarchies in 3-dimensional chips, and a cache hierarchy resulting therefrom, including a physical arrangement of bits in cache hierarchies implemented in 3 dimensions such that the planar wiring required in the busses connecting the levels of the hierarchy is minimized. In this way, the data paths between the levels are primarily the vias themselves, which leads to very short, hence fast and low power busses.]]></description>
<pubDate>Tue, 10 Nov 2009 08:00:00 EST</pubDate>
</item>

<item>
<title><![CDATA[Non-volatile semiconductor memory device]]></title>
<link>http://www.freepatentsonline.com/7616493.html</link>
<description><![CDATA[When a voltage level detector detects that a supply voltage reaches a recovery voltage level that requires a recovery operation, a signal generator generates a recovery operation instructing signal for instructing the recovery operation. The recovery operation instructing signal is invalidated if a certain operation mode is executed and validated in other cases.]]></description>
<pubDate>Tue, 10 Nov 2009 08:00:00 EST</pubDate>
</item>

<item>
<title><![CDATA[Refresh port for a dynamic memory]]></title>
<link>http://www.freepatentsonline.com/7617356.html</link>
<description><![CDATA[A refresh port for a dynamic memory. In one embodiment, an apparatus includes a memory and a refresh command interface to receive a refresh command including a portion indicating signal. Refresh logic performs a refresh to a portion of the memory array specified, at least partially, by the portion specifying signal. Data transfer interfaces receive data transfer commands and transfer memory to and from the apparatus. Another apparatus includes refresh control logic to output a refresh signal and a portion specifying signal via a refresh command interface.]]></description>
<pubDate>Tue, 10 Nov 2009 08:00:00 EST</pubDate>
</item>

<item>
<title><![CDATA[Electro-optical device, method of manufacturing electro-optical device, and electronic apparatus]]></title>
<link>http://www.freepatentsonline.com/7615810.html</link>
<description><![CDATA[An electro-optical device includes first and second substrates that are bonded to each other, the first substrate having an extended portion extended from the second substrate on a first side thereof in plan view, a plurality of pixel units that are disposed in a pixel region on the first substrate and individually have pixel electrodes, a data line driving circuit that is disposed along the first side in a peripheral region around the pixel region so as to supply an image signal to the pixel units, a plurality of external circuit connecting terminals that are arranged along the first side in a region of the peripheral region on the extended portion, an image signal line that is relayed around the data line driving circuit from the plurality of external circuit connecting terminals and has a first wiring line portion wired in a direction along the first side between the data line driving circuit and the pixel region, and a sealant that bonds the first and second substrates to each other in a sealing region around the pixel region. Each of the first wiring line portions is at least partially wired within the sealing region.]]></description>
<pubDate>Tue, 10 Nov 2009 08:00:00 EST</pubDate>
</item>

<item>
<title><![CDATA[Method for at-speed testing of memory interface using scan]]></title>
<link>http://www.freepatentsonline.com/7617425.html</link>
<description><![CDATA[A method and a circuit of testing of a memory interface associated with an embedded memory in a semiconductor circuit involves writing to two memory locations in succession; reading the two memory locations in succession in the same order in which the two memory locations were written; capturing output data from the memory interface; and analyzing captured output data to determine whether said captured output data corresponds to expected data.]]></description>
<pubDate>Tue, 10 Nov 2009 08:00:00 EST</pubDate>
</item>

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