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<title>freepatentsonline.com: Pulse or digital communications</title>
<link>http://www.freepatentsonline.com/result.html?query_txt=ccl/375%20and%20isd/11/10/2009&amp;uspat=on</link>
<description>USPTO Class 375 Pulse or digital communications</description>
<language>en-us</language>
<lastBuildDate>Thu, 12 Nov 2009 03:32:02 EST</lastBuildDate>

<item>
<title><![CDATA[Method and apparatus for searching cells utilizing down link preamble signal]]></title>
<link>http://www.freepatentsonline.com/7616679.html</link>
<description><![CDATA[An apparatus for searching for a cell in a mobile communication system, including: a preamble sequence storage unit storing preamble sequences each of which corresponds to one preamble index, and a cell searching unit correlating a received signal and the stored preamble sequences in a time domain and identifying the preamble index corresponding to the received signal. The cell searching apparatus correlates a received signal and stored preamble sequences in a time domain. The apparatus employs binary quantization of preamble sequences to reduce calculation and memory size. Also, the stored preamble sequences are phase pre-rotated according to a segment number, to prevent from a burden of frequency offset correction caused by three different hypotheses. Accordingly, a complexity of the cell searching apparatus is reduced and cell searching performance becomes more accurate.]]></description>
<pubDate>Tue, 10 Nov 2009 08:00:00 EST</pubDate>
</item>

<item>
<title><![CDATA[Method for processing data in a spread spectrum system]]></title>
<link>http://www.freepatentsonline.com/7616680.html</link>
<description><![CDATA[A method for processing data in a spread spectrum system, including decimating a data rate of received spread spectrum data by a decimation factor to a decimated rate; storing the received spread spectrum data into a memory at the decimated rate; interpolating the decimated rate by an interpolation factor to an interpolated rate; and reading the received spread spectrum data from the memory at the interpolated rate.]]></description>
<pubDate>Tue, 10 Nov 2009 08:00:00 EST</pubDate>
</item>

<item>
<title><![CDATA[System and method to increase sector throughput in a multi-carrier operation]]></title>
<link>http://www.freepatentsonline.com/7616696.html</link>
<description><![CDATA[A multicarrier base transceiver system includes first control circuitry adapted to receive first control data and voice data from a communications network and arrange the received data into a plurality of logical channels including a paging channel and a plurality of traffic channels for transmission on a first carrier. Second control circuitry is adapted to receive second control data and messaging data, arrange the received messaging data into a plurality of logical traffic channels for transmission on a second carrier, and send the received second control data to the first control circuitry. The first control circuitry transmits the first control data and second control data on the paging channel of the first carrier. A multicarrier mobile station includes first control logic for controlling communications on the first carrier, the first control logic operating in accordance with received paging channel data, and second control logic for controlling communications on the second carrier, the second control logic operating in accordance with data received on the paging channel of the first carrier.]]></description>
<pubDate>Tue, 10 Nov 2009 08:00:00 EST</pubDate>
</item>

<item>
<title><![CDATA[Cooperative inter-carrier channel coding apparatus, systems, and methods]]></title>
<link>http://www.freepatentsonline.com/7616697.html</link>
<description><![CDATA[Embodiments of a codation module associated with a global system for mobile communications (GSM) enhanced data rates for GSM evolution (EDGE) radio access network (GERAN) transceiver are described generally herein. The codation module may include a turbo encoder to produce a first turbo-encoded data block, and a channel interleaver may split the first turbo-encoded data block into a first plurality of turbo-encoded data bursts and to interleave the first plurality of turbo-encoded data bursts for individual transmission on a plurality of tonal carriers. The tonal carriers may correspond to independent GERAN frequency channels.]]></description>
<pubDate>Tue, 10 Nov 2009 08:00:00 EST</pubDate>
</item>

<item>
<title><![CDATA[Multiple-input multiple output system and method]]></title>
<link>http://www.freepatentsonline.com/7616698.html</link>
<description><![CDATA[A multiple-input multiple-output (MIMO) system can transmit on multiple antennas simultaneously and receive on multiple antennas simultaneously. Unfortunately, because a legacy 802.11a/g device is not able to decode multiple data streams, such a legacy device may “stomp” on a MIMO packet by transmitting before the transmission of the MIMO packet is complete. Therefore, MIMO systems and methods are provided herein to allow legacy devices to decode the length of a MIMO packet and to restrain from transmitting during that period. These MIMO systems and methods are optimized for efficient transmission of MIMO packets.]]></description>
<pubDate>Tue, 10 Nov 2009 08:00:00 EST</pubDate>
</item>

<item>
<title><![CDATA[Differential decoder followed by non-linear compensator]]></title>
<link>http://www.freepatentsonline.com/7616709.html</link>
<description><![CDATA[A receiver including a (differential-quadrature-) phase-shift-keying demodulator ( 4 ) and a differential detector ( 10 ) having a decoder ( 19 ), is provided with a non-linear compensator ( 20 ) for compensating the decoder output siqnal for (part of) an interference term, to improve the decoding process and to reduce the number of incorrect decisions. The non-linear compensator ( 20 ) includes a channel estimator ( 22 ) for estimating a coefficient of a term of the decoder output siqnal and removers ( 21,23 ) for removing the term from the decoder output signal.]]></description>
<pubDate>Tue, 10 Nov 2009 08:00:00 EST</pubDate>
</item>

<item>
<title><![CDATA[Synchronisation in a receiver]]></title>
<link>http://www.freepatentsonline.com/7616716.html</link>
<description><![CDATA[A radio receiver is suitable for use in an OFDM wireless communications system, in which it is necessary to identify a timing point at a start of a frame. In order to ensure optimum performance of the receiver in multipath environments, it should be synchronised with the first received multipath component, although one or more of the delayed multipath components may be stronger than the first component. A method of determining the time position of the first received multipath component, determines a correlator function from the received signal, and determines the required timing point from a falling edge in a derivative of the correlator function.]]></description>
<pubDate>Tue, 10 Nov 2009 08:00:00 EST</pubDate>
</item>

<item>
<title><![CDATA[Method for symbol timing synchronization and apparatus thereof]]></title>
<link>http://www.freepatentsonline.com/7616723.html</link>
<description><![CDATA[A method for symbol timing synchronization is provided. The method comprises the following steps. First, a correlation between a sample sequence and a delayed sample sequence is calculated to generate a correlation sequence. Wherein, the delayed sample sequence is obtained from delaying the sample sequence by N sampling points, and N is the length of the useful data for a symbol in the sample sequence. Then, a moving average of the correlation sequence is calculated to generate a cross-correlation sequence, and the cross-correlation sequence is differentiated to generate a differentiated sequence. Finally, a moving average of the differentiated sequence is calculated to generate a moving-averaged sequence, and the peak position of the moving-averaged sequence is detected in order to obtain the correct symbol timing for synchronization.]]></description>
<pubDate>Tue, 10 Nov 2009 08:00:00 EST</pubDate>
</item>

<item>
<title><![CDATA[Method and apparatus for multi-modulation frame synchronization in a digital communication system]]></title>
<link>http://www.freepatentsonline.com/7616724.html</link>
<description><![CDATA[A method and apparatus for frame synchronization in digital communication systems using multiple modulation formats perform a search for a differential frame alignment sequence (FAS) to frame-align the received digital stream and determine the polarity of the stream. Embodiments of the invention are compatible with Differential Phase Shift Keying (DPSK), Duobinary Signaling (DBS), and ON/OFF Keying (OOK) modulation formats.]]></description>
<pubDate>Tue, 10 Nov 2009 08:00:00 EST</pubDate>
</item>

<item>
<title><![CDATA[Method and system for slicing a communication signal]]></title>
<link>http://www.freepatentsonline.com/7616700.html</link>
<description><![CDATA[A slicer can receive a communication signal having a level or amplitude that is between two discrete levels of a multilevel digital communication scheme. The slicer can compare the communication signal to a plurality of references such that multiple comparisons proceed essentially in parallel. A summation node can add the results of the comparisons to provide an output signal set to one of the discrete levels. The slicer can process the communication signal and provide the output signal on a symbol-by-symbol basis. A decision feedback equalizer (“DFE”) can comprise the slicer. A feedback circuit of the DFE can delay and scale the output signal and apply the delayed and scaled signal to the communication signal to reduce intersymbol interference (“ISI”).]]></description>
<pubDate>Tue, 10 Nov 2009 08:00:00 EST</pubDate>
</item>

<item>
<title><![CDATA[Methods and apparatus for reducing a sampling rate during a sampling phase determination process]]></title>
<link>http://www.freepatentsonline.com/7616707.html</link>
<description><![CDATA[A received signal is sampled at a sampling period of T+m*(T/n) during a sampling phase determination process. T is a symbol or chip period of the received signal, n is a number of phases of the sampled signal, T/n is a phase resolution period, and m is a fixed non-zero integer value where −n&lt;m&lt;n (e.g. m=1 or −1). By sampling the received signal at the sampling period of T+m*(T/n), a sample set for each one of n phases of the sampled signal is produced. For each sample set, a correlation process is performed between the sample set and a predetermined correlation signal to produce a correlation result. Once an optimal correlation result is identified from the correlation process, the received signal is sampled at a sampling period of T at a phase associated with the optimal correlation result. Advantageously, oversampling at a sampling rate of n/T is not required during the sampling phase determination process, which reduces cost and power consumption.]]></description>
<pubDate>Tue, 10 Nov 2009 08:00:00 EST</pubDate>
</item>

<item>
<title><![CDATA[Clock recovery circuit]]></title>
<link>http://www.freepatentsonline.com/7616708.html</link>
<description><![CDATA[A clock recovery circuit comprising an initial delay select circuit, a delay locked loop and a clock synthesizer circuit is provided. The initial delay select circuit comprises an initial timing generator, a first multiplexer and an initial value generator. The delay locked loop comprises a delay chain, a phase detector, a counter, and a decoder circuit. The delay locked loop delays an input clock signal to generate a first delay signal and several unit delay signals. The initial value generator receives the unit delay signals to generate an initial value used as an initial counting value of the delay locked loop to prevent harmonic lock. The delay locked loop controls the phase difference between the input clock signal and the first delay signal. The output clock signal of the clock recovery circuit is generated by the clock synthesizer circuit based on the input clock signal and the first delay signal.]]></description>
<pubDate>Tue, 10 Nov 2009 08:00:00 EST</pubDate>
</item>

<item>
<title><![CDATA[Frequency domain filtering to improve channel estimation in multicarrier systems]]></title>
<link>http://www.freepatentsonline.com/7616711.html</link>
<description><![CDATA[A channel estimation system comprises a filtering component that selectively scales a plurality of carriers as a function of location of the plurality of carriers within a frequency band, wherein the plurality of carriers comprises at least one data carrier and at least one pilot carrier. A component thereafter extrapolates an observation from the at least one pilot carrier, wherein a channel is estimated as a function of the extrapolated observation. The scaling of the carriers facilitates reducing a flooring effect associated with channel estimation. The filtering component can be employed at a transmitter and/or at a receiver, and can be activated and/or deactivated as a function of a sensed data packet type.]]></description>
<pubDate>Tue, 10 Nov 2009 08:00:00 EST</pubDate>
</item>

<item>
<title><![CDATA[Compensation for residual frequency offset, phase noise and sampling phase offset in wireless networks]]></title>
<link>http://www.freepatentsonline.com/7616719.html</link>
<description><![CDATA[Improved performance, particularly gain in signal-to-noise ratio (SNR), in high-bandwidth Orthogonal Frequency Division Multiplexing (OFDM) receivers, software and systems is achieved by compensating channel estimates not only for carrier frequency offset and phase noise, but also for interference caused by sample phase jitter. At high bandwidths, e.g., using 256 quadrature amplitude modulation (QAM) symbol constellation, significant SNR improvement is gained by determining and applying a corresponding compensation to each data sub-carrier channel, the compensation preferably including a term that increases linearly with the sub-carrier index.]]></description>
<pubDate>Tue, 10 Nov 2009 08:00:00 EST</pubDate>
</item>

<item>
<title><![CDATA[Noise free transceiver circuit]]></title>
<link>http://www.freepatentsonline.com/7616694.html</link>
<description><![CDATA[A noise free transceiver circuit includes a communication line, a power source line, a ground line, an output transistor having output terminals connected between the communication line and the ground line for outputting a communication signal to the communication line, a first circuit for applying a trapezoidal signal to the input terminal of the output transistor to turn on in synchronism with a transmission signal and a second circuit for turning off the output transistor when the level of the transmission signal is high. The output transistor is turned off when the communication signal is outputted. Therefore, noises of the power line are shut out of the output transistor.]]></description>
<pubDate>Tue, 10 Nov 2009 08:00:00 EST</pubDate>
</item>

<item>
<title><![CDATA[MIMO equalizer design: an algorithmic perspective]]></title>
<link>http://www.freepatentsonline.com/7616695.html</link>
<description><![CDATA[A receiver in a MIMO-OFDM system may estimate the transmitted signal by performing a QR decomposition on the channel response matrix. The receiver may utilize Givens rotations to perform the decomposition, which may be performed using coordinate rotation digital computer (CORDIC) modules.]]></description>
<pubDate>Tue, 10 Nov 2009 08:00:00 EST</pubDate>
</item>

<item>
<title><![CDATA[Broadband multicarrier transmitter with subchannel frequency diversity for transmitting a plurality of spatial streams]]></title>
<link>http://www.freepatentsonline.com/7616704.html</link>
<description><![CDATA[A multicarrier transmitter assigns for each of a plurality of spatial channels, sets of the constellation symbols to subcarriers of each subchannel. Constellation symbol assignments to the subchannels are circularly rotated among some of the spatial channels so that subchannels use different sets of subcarriers for each spatial channel for enhanced frequency diversity.]]></description>
<pubDate>Tue, 10 Nov 2009 08:00:00 EST</pubDate>
</item>

<item>
<title><![CDATA[Method and system for performing distance measuring and direction finding using ultrawide bandwidth transmissions]]></title>
<link>http://www.freepatentsonline.com/7616676.html</link>
<description><![CDATA[An identification tag is provided in which radio frequency (RF) circuitry and ultrawide bandwidth (UWB) circuitry are both provided on the same tag, along with some UWB-RF interface circuitry. The RF circuitry is used to detect when the identification tag must be accessed, and is used to connect the UWB circuitry with a power supply. The UWB circuitry then performs the necessary communication functions with a distant device and the power supply is again disconnected. In this way the power supply is only accessed when the UWB circuitry is needed and it's usable lifetime can be maximized.]]></description>
<pubDate>Tue, 10 Nov 2009 08:00:00 EST</pubDate>
</item>

<item>
<title><![CDATA[Method for channel tracking in an LMS adaptive equalizer for 8VSB]]></title>
<link>http://www.freepatentsonline.com/7616685.html</link>
<description><![CDATA[A method and system for channel tracking in an adaptive equalizer for a digital data receiver. The method includes determining a first set of tap weights and a second set of tap weights of the equalizer, and determining a difference between the first and second sets of tap weights. The method also includes determining an error estimate based on symbols received at the receiver, comparing the error estimate with a divergence threshold, and determining a step size factor based on the difference and the comparison.]]></description>
<pubDate>Tue, 10 Nov 2009 08:00:00 EST</pubDate>
</item>

<item>
<title><![CDATA[Method and apparatus for generating one or more clock signals for a decision-feedback equalizer using DFE detected data]]></title>
<link>http://www.freepatentsonline.com/7616686.html</link>
<description><![CDATA[Methods and apparatus are provided for generating one or more clock signals for a decision-feedback equalizer using DFE detected data. A received signal is sampled using a data clock and a transition clock to generate a data sample signal and a transition sample signal, respectively. A DFE correction is obtained for each of the data sample and transition sample signals to generate DFE detected data and a DFE transition data. The DFE detected data and DFE transition data are then applied to a phase detector that generates a signal to adjust a phase of one or more of the data clock and transition clock. In a multi-level implementation, the received signal is sampled using a clock associated with each of the levels and the samples are latched using a vertical slicing technique to generate DFE data associated with each of said levels.]]></description>
<pubDate>Tue, 10 Nov 2009 08:00:00 EST</pubDate>
</item>

<item>
<title><![CDATA[Transmission circuit and communication apparatus comprising the same]]></title>
<link>http://www.freepatentsonline.com/7616702.html</link>
<description><![CDATA[A transmission circuit is provided which can quickly and accurately control an output power of a transmission signal even when the transmission signal is output at a high modulation rate and in a wide dynamic range. A switching control section controls a modulation method changing section to change a modulation method of a modulated signal generating section to a modulation method having a narrow dynamic range before controlling a switching section to switch amplification sections. An output adjustment control section controls output adjusting sections so that a difference in level between a transmission signal which is smoothed by a smoothing circuit and is before the amplification sections are switched, and a transmission signal which is after the amplification sections are switched, is caused to be smaller than a predetermined difference threshold value, when the modulated signal generating section operates in the modulation method having the narrow dynamic range.]]></description>
<pubDate>Tue, 10 Nov 2009 08:00:00 EST</pubDate>
</item>

<item>
<title><![CDATA[Differential multiple-norm transmit diversity with forward error correction and related diversity reception]]></title>
<link>http://www.freepatentsonline.com/7616703.html</link>
<description><![CDATA[To provide transmission and reception diversity schemes for a powerful, flexible and less complex bandwidth-efficient space-time modulation scheme there is proposed a method of and apparatus for differential multiple-norm space-time transmit diversity from a unitary space-time modulation scheme using at least two transmit antennas. In a first step a group of transmission bits is divided into a first sub-group of transmission bits and a second sub-group of transmission bits. In a second step the first sub-group of transmission bits is mapped onto a constellation matrix of a differential unitary space-time modulation scheme. In a third step a scaling factor is determined from the second sub-group of transmission bits. In a fourth step a transmission matrix is sep up through differential encoding of the constellation matrix and a previously determined transmission matrix in combination with scaling by the scaling factor. The differential multiple-norm transmit diversity according to the present invention improves distance properties of the modulation scheme which are relevant for achievable error rates and extends higher order modulation also to the area of differential transmit diversity schemes from unitary designs.]]></description>
<pubDate>Tue, 10 Nov 2009 08:00:00 EST</pubDate>
</item>

<item>
<title><![CDATA[Repetition coding in a satellite-based communications system]]></title>
<link>http://www.freepatentsonline.com/7616706.html</link>
<description><![CDATA[A satellite communications system comprises a transmitter, a satellite transponder and a receiver. The transmitter transmits an uplink multi-level modulated signal (hierarchical modulation or layered modulation) to the satellite transponder, which broadcasts the multi-level modulated signal downlink to one, or more, receivers. The transmitter includes a repetition coder for repetition coding at least one level, e.g., a lower level, of the multi-level modulated signal. In complementary fashion, the receiver includes a repetition decoder for use in decoding the at least one repetition coded level of the received multi-level modulated signal.]]></description>
<pubDate>Tue, 10 Nov 2009 08:00:00 EST</pubDate>
</item>

<item>
<title><![CDATA[Frequency offset estimating method and receiver employing the same]]></title>
<link>http://www.freepatentsonline.com/7616710.html</link>
<description><![CDATA[Provided is a method for estimating carrier wave or doppler frequency offset based on an approximated quadratic non-linear function in fine search, and a receiver employing the method. The method for estimating frequency offset includes the steps of: a) extracting more than three discrete samples in an order where the discrete samples are close to a maximum value of a power spectrum density function; b) inducing a quadratic non-linear function by using the extracted discrete samples; and c) estimating the frequency offset from a maximum point of the quadratic non-linear function. The technology of the present research makes it possible to exactly estimate frequency offset without increasing hardware complexity in estimation of carrier wave or doppler frequency offset.]]></description>
<pubDate>Tue, 10 Nov 2009 08:00:00 EST</pubDate>
</item>

<item>
<title><![CDATA[Systems and methods for detecting discontinuous transmission (DTX) using cyclic redundancy check results to modify preliminary DTX classification]]></title>
<link>http://www.freepatentsonline.com/7616712.html</link>
<description><![CDATA[A received information signal is decoded to obtain the received information and to produce at least one feature of the received information signal. The received information signal is preliminarily classified as containing a normal burst or a truncated burst based upon the at least one feature, to obtain a preliminary classification. Cyclic redundancy checking of the received information that is decoded is performed. The received information signal is then further classified as containing a normal burst or a truncated burst based upon the preliminary classification and whether the cyclic redundancy checking is valid, to obtain a further classification. The received information signal may be still further classified as containing a normal burst or a truncated burst based upon the further classification and at least one transition rule for normal bursts and truncated bursts between the received information signal and a previously received information signal.]]></description>
<pubDate>Tue, 10 Nov 2009 08:00:00 EST</pubDate>
</item>

<item>
<title><![CDATA[Coarse timing synchronization]]></title>
<link>http://www.freepatentsonline.com/7616717.html</link>
<description><![CDATA[A system for determining the burst start timing of a signal includes logic configured to receive the signal, generate correlation moduli and generate a first timing output based on the correlation moduli. The logic may also be configured to receive operating mode information and timing information and generate search controls. The logic may further be configured to identify a maximum of the correlation moduli using the search controls and determine a second timing output associated with the maximum correlation modulus. The second timing output represents a more accurate approximation of a burst start time than the first timing output.]]></description>
<pubDate>Tue, 10 Nov 2009 08:00:00 EST</pubDate>
</item>

<item>
<title><![CDATA[Multirate digital transceiver]]></title>
<link>http://www.freepatentsonline.com/7616720.html</link>
<description><![CDATA[A multirate digital transceiver in which, on reception, signals are simultaneously decimated and coarsely down converted in an iterative process to narrow down a received wideband to a desired channel and, on transmission, signals are interpolated iteratively to achieve a desired sample rate/band width.]]></description>
<pubDate>Tue, 10 Nov 2009 08:00:00 EST</pubDate>
</item>

<item>
<title><![CDATA[Method and circuitry for extracting clock in clock data recovery system]]></title>
<link>http://www.freepatentsonline.com/7616722.html</link>
<description><![CDATA[A method for extracting a clock in a clock data recovery system is provided. The method includes the following steps. First, a serial link transmission data is sampled for a plurality of times, and a plurality of pulse signals are generated and sequentially arranged. Then, a mark is inserted after all pulse signals are generated and had been delayed for a predetermined delay time. The predetermined delay time is less than a period between two adjacent pulse signals, and a period between two adjacent pulse signals is divided into two sub-periods by the predetermined delay time. Then, it is checked whether the data status in each sub-period is changed or not, and this operation is repeated for a predetermined number of times. Finally, the clock is extracted when a pulse signal of no data status change within the predetermined number of times is being generated.]]></description>
<pubDate>Tue, 10 Nov 2009 08:00:00 EST</pubDate>
</item>

<item>
<title><![CDATA[Multi-carrier constant envelope signal scheme for power and bandwidth efficient communications]]></title>
<link>http://www.freepatentsonline.com/7616678.html</link>
<description><![CDATA[A technique for combining a plurality of signals to form a multi-carrier constant-envelope composite signal includes generating a constant-amplitude inphase (I) composite signal based on a majority vote of a first set of signals and generating a constant-amplitude quadrature (Q) composite signal based on a separate majority vote of a second set of signals. The I and Q components of a carrier signal are respectively modulated with the I and Q composite signals and combined to form the constant-envelope composite signal. In the case where a single offset carrier code is a constituent of the constant-envelope composite signal, a scale factor is applied to one of the I and Q composite signals to equalize the power of the I and Q components of the offset carrier code.]]></description>
<pubDate>Tue, 10 Nov 2009 08:00:00 EST</pubDate>
</item>

<item>
<title><![CDATA[Zero excess bandwidth modulation]]></title>
<link>http://www.freepatentsonline.com/7616701.html</link>
<description><![CDATA[ZEB (zero excess bandwidth) modulation. The modulation rate of a signal is increased to the entirety of a communication channel's available bandwidth. Spectral zeroes at the edges of the available bandwidth now coincide with spectral zeroes at the edges of the Nyquist band and lead to ISI (intersymbol interference), which cannot be eliminated by equalization. Thus, in a ZEB system intersymbol interference (ISI) is intentionally allowed and dealt with by the known technique of TH (Tomlinson-Harashima) precoding. Comparison of conventional zero-ISI systems with ZEB systems, both exhibiting identical transmit spectra with finite spectral roll offs towards the edges of the available bandwidth, illustrate significant gains in channel throughput achievable by the ZEB systems. Similar gains can hardly be achieved by more sophisticated channel coding for zero-ISI systems. For ZEB systems an effective spectral shaping involving a simple infinite impulse response (IIR) of the overall channel is proposed.]]></description>
<pubDate>Tue, 10 Nov 2009 08:00:00 EST</pubDate>
</item>

<item>
<title><![CDATA[Method and system for estimating the speed of a mobile device in a network]]></title>
<link>http://www.freepatentsonline.com/7616715.html</link>
<description><![CDATA[A method for estimating the speed of a mobile device in a network is provided that includes selecting a correlation length from a plurality of possible correlation lengths. A correlation result is generated based on the selected correlation length. A speed estimate is generated for the mobile device based on the correlation result.]]></description>
<pubDate>Tue, 10 Nov 2009 08:00:00 EST</pubDate>
</item>

<item>
<title><![CDATA[Apparatus, and associated method, for selecting codes of a code set for coding data communicated during operation of multi-access communication system]]></title>
<link>http://www.freepatentsonline.com/7616609.html</link>
<description><![CDATA[Apparatus, and an associated method, for designing codes to be used to code data that is communicated in a multi-access communication system. A selected code is designed, based upon an initial code. The selected code that is designed is of characteristics that best optimize channel differentiation to minimize interference between concurrently-communicated data coded by different codewords of the selected code.]]></description>
<pubDate>Tue, 10 Nov 2009 08:00:00 EST</pubDate>
</item>

<item>
<title><![CDATA[Method of soft bit metric calculation with direct matrix inversion MIMO detection]]></title>
<link>http://www.freepatentsonline.com/7616699.html</link>
<description><![CDATA[A telecommunication MIMO receiver implements soft bit metric calculation with direct matrix inversion MIMO detection. The receiver has a detector that detects data symbols in a received signal by determining distances between received signal points and constellation points; a scaler that scales the distances using a scaling factor; and a soft bit metric calculator that uses the scaled distances to calculate scaled soft bit metrics. The receiver can also have a decoder that decodes the soft bit metrics to determine data values in the received signals. Preferably, the receiver also has a quantizer that dynamically quantizes the soft bit metrics before decoding by the decoder.]]></description>
<pubDate>Tue, 10 Nov 2009 08:00:00 EST</pubDate>
</item>

<item>
<title><![CDATA[Receiver with decision-directed equalizer]]></title>
<link>http://www.freepatentsonline.com/7616684.html</link>
<description><![CDATA[A circuit is configured to receive and process a signal that includes in-phase and out-of-phase components that correspond to in-phase and out-of-phase components of a time sequence of symbols. A phase sensor in the circuit is configured to determine a phase value in accordance with an equalized version of the in-phase component of the signal and the in-phase component of the time sequence of symbols. The phase sensor is further configured to generate an approximation to the out-of-phase component of the signal in accordance with a Hilbert function of order k greater than 1. Terms in the approximation that correspond to future samples of the in-phase component of the signal are replaced with terms that correspond to past samples of an error that corresponds to a difference between samples of the in-phase component of the signal and an output from a detector.]]></description>
<pubDate>Tue, 10 Nov 2009 08:00:00 EST</pubDate>
</item>

<item>
<title><![CDATA[Method and apparatus for adaptive encoding framed data sequences]]></title>
<link>http://www.freepatentsonline.com/7616690.html</link>
<description><![CDATA[Methods and apparatus for adaptive encoding of at least a part of a current frame of a sequence of frames of framed data are described which operate on a block-by-block coding basis. The methods and apparatus divide at least a part of the current frame into blocks and then perform a first sub-encoding step on a block. Thereafter a second sub-encoding step is performed on the first sub-encoded block whereby the second sub-encoding step is optimized by adapting its encoding parameters based on a quantity of the first sub-encoded part of the current frame. The quantity is determined by prediction from a reference frame. Then the same steps are performed on another block of the part of the current frame. Typically, the framed data will be video frames for transmission over a transmission channel. The adaptation of the parameters for the second sub-encoding step may be made dependent upon the characteristics or limitations, e.g. bandwidth limitation, of the channel. In addition, the current frame may be discarded based on the predicted quantity and/or based on fullness of a buffer.]]></description>
<pubDate>Tue, 10 Nov 2009 08:00:00 EST</pubDate>
</item>

<item>
<title><![CDATA[Optical disk apparatus and PLL circuit]]></title>
<link>http://www.freepatentsonline.com/7616726.html</link>
<description><![CDATA[With the objective of providing a stable PLL circuit and improving readout performance of an optical disk apparatus equipped with PRML, using the PLL circuit, phase detectors are respectively provided with respect to signals prior and subsequent to an FIR filter, and the phase detectors are selectively used according to an operating condition of a PLL to thereby stabilize the operation of the PLL circuit. There can be provided such an optical disk apparatus that readout performance is improved so as to extract an operating limit of a Viterbi decoder.]]></description>
<pubDate>Tue, 10 Nov 2009 08:00:00 EST</pubDate>
</item>

<item>
<title><![CDATA[Apparatus and method for clock synchronization in a multi-point OFDM/DMT digital communications system]]></title>
<link>http://www.freepatentsonline.com/7616553.html</link>
<description><![CDATA[A multi-point communications system is set forth herein. The communications system comprises a transmitter for transmitting OFDM/DMT symbols over a predetermined number of bins across a transmission medium. The OFDM/DMT symbols are generated using at least one timing signal. At least one of the predetermined number of bins includes a pilot tone sub-symbol having a frequency corresponding to the clock signal. The communications system also includes a receiver for receiving the OFDM/DMT symbols from the transmission medium. The receiver demodulates the received symbols using at least one timing signal. The receiver has a first pilot tone search mode of operation in which the receiver adjusts its timing signal to scan the frequency range of the predetermined number of bins looking for the pilot tone sub-symbol and identifies the bin including the pilot tone sub-symbol. The receiver further has a subsequent second pilot tone acquisition mode in which the receiver adjusts the timing signal to receive the identified bin containing the pilot tone sub-symbol and measures phase differences between successive pilot tone sub-symbols to thereby perform a further adjustment of the timing signal so that the pilot tone sub-symbol is received within a frequency range sufficient for subsequent phase locked loop processing thereof.]]></description>
<pubDate>Tue, 10 Nov 2009 08:00:00 EST</pubDate>
</item>

<item>
<title><![CDATA[Calculation of interpolated pixel values]]></title>
<link>http://www.freepatentsonline.com/7616689.html</link>
<description><![CDATA[The invention is related to video compression systems, and in particular to compression/decompression in digital video systems. The present invention discloses an alternative method to calculate values of interpolated pixel positions in a video picture.]]></description>
<pubDate>Tue, 10 Nov 2009 08:00:00 EST</pubDate>
</item>

<item>
<title><![CDATA[Video encoding/decoding method and apparatus]]></title>
<link>http://www.freepatentsonline.com/7616691.html</link>
<description><![CDATA[A video encoding apparatus comprises a frame memory/predictive image generator having a first predictive mode for generating a predictive image signal by selecting a combination from among a plurality combinations of a reference image number and a plurality of predictive parameters, and a second predictive mode for generating a predictive image signal according to a predictive parameter computed based on reference image numbers of reference images and an image-to-image distance, and a variable-length encoder to select one of the first and second prediction modes by the number of reference images, and encode orthogonal transformation coefficient information concerning a predictive error signal of a predictive image signal with respect to input video signal, mode information indicating an encoding mode, motion vector information and combination of selected reference image number with predictive parameter index information indicating combination of selected reference image information.]]></description>
<pubDate>Tue, 10 Nov 2009 08:00:00 EST</pubDate>
</item>

<item>
<title><![CDATA[Hybrid motion vector prediction for interlaced forward-predicted fields]]></title>
<link>http://www.freepatentsonline.com/7616692.html</link>
<description><![CDATA[Techniques and tools for hybrid motion vector prediction for interlaced forward-predicted fields are described. For example, a video decoder determines an initial motion vector predictor for a motion vector of an interlaced forward-predicted field. The decoder then checks a variation condition based at least in part on a predictor polarity selection (e.g., same or opposite), the initial motion vector predictor, and neighbor motion vectors. If the variation condition is satisfied, the decoder uses one of the neighbor motion vectors as a final motion vector predictor. Otherwise, the decoder uses the initial motion vector predictor as the final motion vector predictor. A video encoder performs corresponding processing.]]></description>
<pubDate>Tue, 10 Nov 2009 08:00:00 EST</pubDate>
</item>

<item>
<title><![CDATA[Method and system for detecting motion between video field of same and opposite parity from an interlaced video source]]></title>
<link>http://www.freepatentsonline.com/7616693.html</link>
<description><![CDATA[A method and system for detecting the motion between a video field and its previous and subsequent video fields at a specified position. The motion detection scheme and system allows signal values of one set of vertically adjacent pixels from a video field of one parity and two other sets of vertically adjacent pixels from two neighboring video field of opposite parity to be measured such that when taken together, these pixels represent relevant sample of an image near the vertically and temporal position of the video field. The motion detection scheme also allows the calculation of three motion values between the video field and its previous video field, the video field and its subsequent video field and the previous and subsequent fields of the same video field. The overall level of motion at the field being measured is determined by combining the information from the three motion values calculated at the specified spatial and temporal location.]]></description>
<pubDate>Tue, 10 Nov 2009 08:00:00 EST</pubDate>
</item>

<item>
<title><![CDATA[System and method for forward and backward recursive computation]]></title>
<link>http://www.freepatentsonline.com/7616713.html</link>
<description><![CDATA[A system and method is provided for improved and efficient forward and backward recursive computations that may be used, for example, with turbo code decoding applications. The invention performs the forward computations using a full length of a sequence to be decoded and performs the reverse computations using a sliding window over the sequence.]]></description>
<pubDate>Tue, 10 Nov 2009 08:00:00 EST</pubDate>
</item>

<item>
<title><![CDATA[Cable modem including filtering based on frequency band]]></title>
<link>http://www.freepatentsonline.com/7617517.html</link>
<description><![CDATA[In a Hybrid Fiber Coaxial (HFC) network using a Set Top Box (STB) or a cable modem, the cable STB or the cable modem includes respective High-Pass Filters (HPFs) having different passband frequencies to transmit an upstream signal from the cable STB or the cable modem to the HFC network through paths having different passband frequencies depending on states of the HFC network so that the upstream frequency band of 5 to 42 MHz is available.]]></description>
<pubDate>Tue, 10 Nov 2009 08:00:00 EST</pubDate>
</item>

<item>
<title><![CDATA[Method and device for chronologically synchronizing a location network]]></title>
<link>http://www.freepatentsonline.com/7616682.html</link>
<description><![CDATA[Chronologically synchronizing a unique positing signal generated by a positioning-unit device at a known location with a reference positioning signal generated by a reference transmitter at a known geometric distance. The positioning-unit device receives and interprets a reference positioning signal. It then generates and transmits a unique positioning signal, wherein the unique positioning signal is aligned with a frequency steerable clock. The positioning-unit device then receives the unique positioning signal. The positioning-unit device then adjusts the frequency of the frequency steerable clock by an amount derived from a measured frequency difference. The positioning-unit device then determines a reference positioning signal propagation delay between the reference transmitter and the positioning-unit device. At this stage, a time difference is measured between the received reference positioning signal and the received unique positioning signal. Finally, the frequency steerable clock is offset for a period of time derived from the measured time difference and the determined propagation delay and the unique positioning signal is consequently adjusted.]]></description>
<pubDate>Tue, 10 Nov 2009 08:00:00 EST</pubDate>
</item>

<item>
<title><![CDATA[VSB transmission system for processing supplemental transmission data]]></title>
<link>http://www.freepatentsonline.com/7616688.html</link>
<description><![CDATA[A VSB communication system or transmitter for processing supplemental data packets with MPEG-II data-packets includes a VSB supplemental data processor and a VSB transmission system. The VSB supplemental data processor includes a Reed-Solomon coder for coding the supplemental data to be transmitted, a null sequence inserter for inserting a null sequence to an interleaved supplemental data for generating a predefined sequence, a header inserter for inserting an MPEG header to the supplemental data having the null sequence inserted therein, a multiplexer for multiplexing an MPEG data coded with the supplemental data having the MPEG header added thereto in a preset multiplexing ratio and units. The output of the multiplexer is provided to an 8T-VSB transmission system for modulating a data field from the multiplexer and transmitting the modulated data field to a VSB reception system.]]></description>
<pubDate>Tue, 10 Nov 2009 08:00:00 EST</pubDate>
</item>

<item>
<title><![CDATA[Apparatus and method for checking network synchronization clock signal in communication system]]></title>
<link>http://www.freepatentsonline.com/7616721.html</link>
<description><![CDATA[In an apparatus and method for checking a network synchronization clock signal in a communication system, the apparatus generates a divided clock signal which is the same as an externally inputted network synchronization clock signal, compares the value of one period of the network synchronization clock signal to the value of one period of the divided clock signal, and determines whether the network synchronization clock signal is normal or not. Thus, the reliability of an operation of checking the network synchronization clock signal is enhanced.]]></description>
<pubDate>Tue, 10 Nov 2009 08:00:00 EST</pubDate>
</item>

<item>
<title><![CDATA[Method of reducing a blocking artifact when coding moving picture]]></title>
<link>http://www.freepatentsonline.com/7616831.html</link>
<description><![CDATA[A method of coding a moving picture is provided that reduces blocking artifacts. The method can include defining a plurality of defining pixels S 0 , S 1 , and S 2 , which are centered around a block boundary. If a default mode is selected then frequency information of the surroundings of the block boundary is obtained. A magnitude of a discontinuous component in a frequency domain belonging to the block boundary is adjusted based on a magnitude of a corresponding discontinuous component selected from a pixel contained entirely within a block adjacent the block boundary. The frequency domain adjustment is then applied to a spatial domain. Or, a DC offset mode can be selected to reduce blocking artifacts in smooth regions where there is little motion.]]></description>
<pubDate>Tue, 10 Nov 2009 08:00:00 EST</pubDate>
</item>

<item>
<title><![CDATA[Method of reducing a blocking artifact when coding moving picture]]></title>
<link>http://www.freepatentsonline.com/7616832.html</link>
<description><![CDATA[A method of coding a moving picture is provided that reduces blocking artifacts. The method can include defining a plurality of defining pixels S 0 , S 1 , and S 2 , which are centered around a block boundary. If a default mode is selected then frequency information of the surroundings of the block boundary is obtained. A magnitude of a discontinuous component in a frequency domain belonging to the block boundary is adjusted based on a magnitude of a corresponding discontinuous component selected from a pixel contained entirely within a block adjacent the block boundary. The frequency domain adjustment is then applied to a spatial domain. Or, a DC offset mode can be selected to reduce blocking artifacts in smooth regions where there is little motion.]]></description>
<pubDate>Tue, 10 Nov 2009 08:00:00 EST</pubDate>
</item>

<item>
<title><![CDATA[Method of reducing a blocking artifact when coding moving picture]]></title>
<link>http://www.freepatentsonline.com/7616833.html</link>
<description><![CDATA[A method of coding a moving picture is provided that reduces blocking artifacts. The method can include defining a plurality of defining pixels S 0 , S 1 , and S 2 , which are centered around a block boundary. If a default mode is selected then frequency information of the surroundings of the block boundary is obtained. A magnitude of a discontinuous component in a frequency domain belonging to the block boundary is adjusted based on a magnitude of a corresponding discontinuous component selected from a pixel contained entirely within a block adjacent the block boundary. The frequency domain adjustment is then applied to a spatial domain. Or, a DC offset mode can be selected to reduce blocking artifacts in smooth regions where there is little motion.]]></description>
<pubDate>Tue, 10 Nov 2009 08:00:00 EST</pubDate>
</item>

<item>
<title><![CDATA[Signal compressing system]]></title>
<link>http://www.freepatentsonline.com/7616687.html</link>
<description><![CDATA[A multi-scanner scans a signal according to several different patterns. A scanning pattern selector determines which scanning pattern produced the most efficient coding result, for example, for runlength coding, and outputs a coded signal, coded most efficiently, and a selection signal which identifies the scanning pattern found to be most efficient.]]></description>
<pubDate>Tue, 10 Nov 2009 08:00:00 EST</pubDate>
</item>

<item>
<title><![CDATA[Wireless receiver apparatus]]></title>
<link>http://www.freepatentsonline.com/7616718.html</link>
<description><![CDATA[When carrying out a channel compensation of a data symbol, a channel estimation value of the reference symbol of the frame itself and that of a reference symbol of the preceding frame are used. In this event, if an AGC gain at the time of a channel estimation value by a reference symbol of the frame itself is different from that of a frame of the reference symbol of the preceding frame, and if an AGC gain of the reference symbol of the frame itself is the same as that of a data symbol to be subjected to a transmission compensation, then the channel estimation value by the reference symbol of the preceding frame is corrected so as to cancel the difference of the AGC gains, followed by using it for a channel compensation of the data symbol.]]></description>
<pubDate>Tue, 10 Nov 2009 08:00:00 EST</pubDate>
</item>

<item>
<title><![CDATA[Method for spatially scalable video coding]]></title>
<link>http://www.freepatentsonline.com/7616824.html</link>
<description><![CDATA[A method for decomposing a digital image at resolution R and MR into a set of spatial sub-bands of resolution R and MR where MR&gt;R and where the high-band at resolution MR is calculated by subtracting the filtered and up-sampled image at resolution R from the image at resolution MR and where the spatial low-band at resolution R is calculated by adding the filtered and down-sampled spatial high-band to the image at resolution R and where a rational factor for up-and down-sampling M is determined by the resolution ratio.]]></description>
<pubDate>Tue, 10 Nov 2009 08:00:00 EST</pubDate>
</item>

<item>
<title><![CDATA[Viterbi traceback initial state index initialization for partial cascade processing]]></title>
<link>http://www.freepatentsonline.com/7617440.html</link>
<description><![CDATA[This invention provides the correct Viterbi decode traceback starting index is obtained for all constraint lengths and frame sizes. Reverse transpose operations that depend on the last active add-compare-select unit a cascade block of the state metric update process. This last active add-compare-select unit controls selection of T counter signals used in the decode.]]></description>
<pubDate>Tue, 10 Nov 2009 08:00:00 EST</pubDate>
</item>

<item>
<title><![CDATA[Downlink power control with limit to dynamic range using detection of downlink transmit power]]></title>
<link>http://www.freepatentsonline.com/7616677.html</link>
<description><![CDATA[An apparatus and method is provided for dynamic range power control of a wireless downlink communication signal, such that target signal quality adjustments are held temporarily when it is apparent that transmit power control commands will not produce the desired response at the transmitting station. Comparisons of measured received signals to thresholds are performed to determine whether the transmitting station has either reached the maximum or minimum transmit power, in which case the target signal quality adjustment is controlled accordingly. When normal transmit power is detected, the target signal quality adjustments are allowed to resume as usual.]]></description>
<pubDate>Tue, 10 Nov 2009 08:00:00 EST</pubDate>
</item>

<item>
<title><![CDATA[Method and apparatus for matching receiver carrier frequency]]></title>
<link>http://www.freepatentsonline.com/7616935.html</link>
<description><![CDATA[A carrier recovery method and apparatus using multiple stages of carrier frequency recovery are disclosed. A receiver uses multiple frequency generation sources to generate carrier signals used to downconvert a received signal. An analog frequency reference having a wide frequency range and coarse frequency resolution is used in conjunction with a digital frequency reference having a narrow frequency range and fine frequency resolution. The multiple carrier signals are multiplied by a received signal to effect a multi-stage downconversion, resulting in a baseband signal. A frequency tracking module measures the residual frequency error present in the baseband signal. The measured residual frequency error is then used to adjust the frequencies of the carrier signals generated by the multiple frequency generation sources.]]></description>
<pubDate>Tue, 10 Nov 2009 08:00:00 EST</pubDate>
</item>

<item>
<title><![CDATA[Semiconductor device and operation method thereof]]></title>
<link>http://www.freepatentsonline.com/7616030.html</link>
<description><![CDATA[Semiconductor device and operation method thereof includes an aspect of the present invention, there is provided a clock generator configured to receive an external clock signal to generate a first clock signal corresponding to a rising edge of the external clock and a second clock signal corresponding to a falling edge of the external clock, a drive control signal generator configured to restrict an activation period of the first clock signal within a deactivation period of the second clock signal to generate a first drive control signal, and restrict an activation period of the second clock signal within a deactivation period of the first clock signal to generate a second drive control signal and an output driver configured to receive a drive data in response to the first and second drive control signal to drive an output terminal in response to the drive data.]]></description>
<pubDate>Tue, 10 Nov 2009 08:00:00 EST</pubDate>
</item>

<item>
<title><![CDATA[Charge pump for PLL/DLL]]></title>
<link>http://www.freepatentsonline.com/7616035.html</link>
<description><![CDATA[A charge pump for use in a locked loop minimizes static phase error through the use of an operational amplifier. The operational amplifier also mitigates the effects of low power supply voltage. The charge pump further includes a startup circuit to establish a predetermined voltage level at the charge pump output node during startup.]]></description>
<pubDate>Tue, 10 Nov 2009 08:00:00 EST</pubDate>
</item>

<item>
<title><![CDATA[Monolithic GPS RF front end integrated circuit]]></title>
<link>http://www.freepatentsonline.com/7616705.html</link>
<description><![CDATA[A highly integrated GPS RF Front End, an interface thereto, and a GPS receiver that incorporates the GPS RF front end, which uses a single conversion stage employing an image rejection mixer stage to eliminate the need for an image reject RF bandpass filter. Also a relatively high sample rate A/D is employed which allows a timeless monolithic IF Filter to be used. The disclosure also discusses a GPS Front End topology that is easily integrated from industry standard building blocks. With the broad variation in potential receiver designs, the present invention includes some specific receiver topologies that lend themselves to a high level of integration. The specific designs presented here are comprised of industry standard building blocks and functions that have been described elsewhere in the related art.]]></description>
<pubDate>Tue, 10 Nov 2009 08:00:00 EST</pubDate>
</item>

<item>
<title><![CDATA[Method and apparatus for calculating a device location]]></title>
<link>http://www.freepatentsonline.com/7616965.html</link>
<description><![CDATA[A method and apparatus for calculating a location of a device is provided. A likelihood of the device being located at a particular location point or a particular location floor is determined using a likelihood calculation at each of a plurality of locations. The location point or location floor is then identified as that location having an associated highest likelihood calculation. The likelihood calculation includes calculating a distance from the device to each of a plurality of reference routers including one or more virtual coplanar reference routers, wherein each of the one or more virtual coplanar reference routers comprise a projection of a non-coplanar reference router onto the floor.]]></description>
<pubDate>Tue, 10 Nov 2009 08:00:00 EST</pubDate>
</item>

<item>
<title><![CDATA[System and method for providing accurate time generation in a computing device of a power system]]></title>
<link>http://www.freepatentsonline.com/7617408.html</link>
<description><![CDATA[A system and method provides accurate time generation in a computing device that includes a computing device clock and a microprocessor. The method includes determining a total system latency based on a delay incurred between issuance of a first command by the microprocessor and receipt of a first time-data signal by the microprocessor. The first time-data signal is representative of a master clock output of a master clock device at a first time. The method also includes deriving an accurate time from a second time-data signal. The second time-data signal is representative of the master clock output at a second time known by the microprocessor. The method further includes adjusting the accurate time based on a percentage of the total system latency to form a latency adjusted time, and applying the latency adjusted time to the computing device clock to synchronize the computing device clock to the master clock output.]]></description>
<pubDate>Tue, 10 Nov 2009 08:00:00 EST</pubDate>
</item>

<item>
<title><![CDATA[Techniques for high definition audio modems]]></title>
<link>http://www.freepatentsonline.com/7616627.html</link>
<description><![CDATA[A system, apparatus, method and article for high definition audio modems are described. The apparatus may include a communications path comprising a communications bus and buffers, a codec to couple to the communications bus, and a processor to couple to the communications bus. The processor may be arranged to execute instructions for a software modem to determine a round trip delay value for a communications path, and adjust the round trip delay value by varying input to one of the buffers. Other embodiments are described and claimed.]]></description>
<pubDate>Tue, 10 Nov 2009 08:00:00 EST</pubDate>
</item>

<item>
<title><![CDATA[Method and apparatus to reduce multipath effects on radio link control measurements]]></title>
<link>http://www.freepatentsonline.com/7616927.html</link>
<description><![CDATA[One or more median filter circuits are used to filter radio link control measurements corresponding to one or more radio link parameters of interest, such as received signal quality or round trip delay measurements, such as might be used by a base station to trigger mobile station handoff. As such measurements are particularly susceptible to measurement outliers arising from rapid but short-lived changes in radio link propagation paths, for example, the application of median filtering to such measurements is particularly advantageous. That is, by operation of median filtering, which is a non-linear filtering process, outliers in a stream of control measurements, such as are caused by instantaneous changes in channel fading or other propagation phenomena, are discarded rather than averaged in with the other measurements. Non-linear filtering as implemented by exemplary median filtering does not impair or otherwise limit the bandwidth of the underlying control measurements.]]></description>
<pubDate>Tue, 10 Nov 2009 08:00:00 EST</pubDate>
</item>

<item>
<title><![CDATA[Method and device for receiving data blocks]]></title>
<link>http://www.freepatentsonline.com/7616636.html</link>
<description><![CDATA[Data blocks to be received each comprise a header and a data field including respectively first and second codes for error detection. The decoding of a signal segment received having first and second portions corresponding respectively to the header and to the data field of a block gave rise to a verification of the first code in the first portion. If the first code is correct, a check is made to verify whether the second portion of the decoded signal has a second correct code. A data block is considered to be detected either in the presence of first and second correct codes, or in the presence only of a first correct code when a data likelihood criterion, evaluated during the decoding of the second portion of the signal, is fulfilled.]]></description>
<pubDate>Tue, 10 Nov 2009 08:00:00 EST</pubDate>
</item>

<item>
<title><![CDATA[Pilot signals for synchronization and/or channel estimation]]></title>
<link>http://www.freepatentsonline.com/7616681.html</link>
<description><![CDATA[The frame words of the embodiments are suitable for frame synchronization and/or channel estimation. By adding the autocorrelation and/or cross-correlation functions of frame words, double maximum values equal in magnitude and opposite polarity at zero and middle shifts are obtained. This property can be used to slot-by-slot, double-check frame synchronization timing, single frame synchronization and/or channel estimation and allows reduction of the synchronization search time. Further, the present invention allows a simpler construction of a correlator circuit for a receiver. A frame synchronization apparatus and method using an optimal pilot pattern is used in a wide band code division multiple Access (W-CDMA) next generation mobile communication system.]]></description>
<pubDate>Tue, 10 Nov 2009 08:00:00 EST</pubDate>
</item>

<item>
<title><![CDATA[Automatic switching between DSL and analog on a single RJ-11 DSL/analog combo modem]]></title>
<link>http://www.freepatentsonline.com/7616683.html</link>
<description><![CDATA[A modem for providing both DSL and analog signal connection capability with a single RJ-11 jack via an automatic switching mechanism. The switching mechanism is controlled by software, which is responsive to user connection preference (i.e., for DSL or analog connection) and/or the detection that a DSL service is available. Dependent on whether DSL is detected on the signal line coupled to the jack and/or whether the user selects a DSL connection, the switching mechanism routes the signal received on the RJ-11 jack through either a path having the DSL modem circuitry or a path having analog modem circuitry.]]></description>
<pubDate>Tue, 10 Nov 2009 08:00:00 EST</pubDate>
</item>

<item>
<title><![CDATA[Image processing method and image processing apparatus]]></title>
<link>http://www.freepatentsonline.com/7616823.html</link>
<description><![CDATA[Information associated with data which was previously transmitted to a client terminal ( 201  or  202 ) is recorded as a history. When a transmission request of data of logical units in tiles required to obtain a desired image is received from the client terminal ( 201 ), the type of progression order used in the client terminal ( 201 ) is discriminated with reference to the history. The transmission order of the data of the logical units in the tiles to be transmitted to the client terminal ( 201 ) is determined in accordance with the discrimination order, and the data of the logical units in the tiles are transmitted to the client terminal ( 201 ) in accordance with the determined transmission order.]]></description>
<pubDate>Tue, 10 Nov 2009 08:00:00 EST</pubDate>
</item>

<item>
<title><![CDATA[Mechanism for avoiding triggering silent radio squelch circuits]]></title>
<link>http://www.freepatentsonline.com/7616606.html</link>
<description><![CDATA[A ‘smart’ sub-channel hopping control mechanism executes one or more sub-channel selection discriminators to enable the communications controller of a spectral reuse transceiver to delineate on which of a plurality sub-channels the spectral reuse transceiver may transmit, so as to substantially reduce the likelihood of triggering squelch circuits of silent radios of primary (licensed) channel users.]]></description>
<pubDate>Tue, 10 Nov 2009 08:00:00 EST</pubDate>
</item>

<item>
<title><![CDATA[Process and device for the prediction of noise contained in a received signal]]></title>
<link>http://www.freepatentsonline.com/7616714.html</link>
<description><![CDATA[A device and method for predicting noise in a signal that is received by a digital receiver is provided. The device includes an autocorrelation function determination device and a noise predictor device. Also included in the device is an adaptive filter that produces a prediction error value for the received signal and the adaptive filter adjusts the filter coefficients as a function of a prediction error of the adaptive filter. Using the filter coefficient of the adaptive filter, the method may determine the autocorrelation function of the received signal. The noise estimated values for the noise contained in the received signal may be computed on a basis of the autocorrelation function of the received signal. The embodiment also may facilitate noise prediction when heavy correlated noise is present.]]></description>
<pubDate>Tue, 10 Nov 2009 08:00:00 EST</pubDate>
</item>

<item>
<title><![CDATA[Signal delay structure in high speed bit stream demultiplexer]]></title>
<link>http://www.freepatentsonline.com/7616725.html</link>
<description><![CDATA[A signal delay structure and method of reducing skew between clock and data signals in a high-speed serial communications interface includes making a global adjustment to the clock signal in the time domain to compensate for a component of the skew that is common between the clock and all data signals. This can include skew caused by the variation in frequency of the input clock from a nominal value, misalignment between the phase of the clock and data generated at the source of the two signals. The global adjustment is made through a delay component that is common to all of the clock signal lines for which skew with data signals is to be compensated. A second level adjustment is made that compensates for the component of the skew that is common to the clock and a subset of the data signals.]]></description>
<pubDate>Tue, 10 Nov 2009 08:00:00 EST</pubDate>
</item>

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