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Methods of forming multi-doped junctions on a substrate

Tue, 10 Nov 2009 08:00:00 EST

A method of forming a multi-doped junction on a substrate is disclosed. The method includes providing the substrate doped with boron, the substrate including a first substrate surface with a first surface region and a second surface region. The method also includes depositing a first set of nanoparticles on the first surface region, the first set of nanoparticles including a first dopant. The method further includes heating the substrate in an inert ambient to a first temperature and for a first time period creating a first densified film, and further creating a first diffused region with a first diffusion depth in the substrate beneath the first surface region. The method also includes exposing the substrate to a diffusion gas including phosphorous at a second temperature and for a second time period creating a PSG layer on the first substrate surface and further creating a second diffused region with a second diffusion depth in the substrate beneath the second surface region, wherein the first diffused region is proximate to the second diffused region. The method further includes exposing the substrate to a oxidizing gas at a third temperature and for a third time period, wherein a SiO2 layer is formed between the PSG layer and the substrate surface, wherein the first diffusion depth is substantially greater than the second diffusion depth.

Method for containing a device and a corresponding device

Tue, 10 Nov 2009 08:00:00 EST

A method of enclosing a micromechanical element formed between a base layer and one or more metallization layers includes forming one or more encapsulating layers over the micromechanical element and providing an encapsulating wall surrounding the element extending between the base layer and the one or more encapsulating layers. An electrical connection is provided between the base layers and the one or more metallization layers formed above the micromechanical element.

Method for fabricating thin film transistor

Tue, 10 Nov 2009 08:00:00 EST

The present invention relates to a method for fabricating thin film transistor, more particularly, to a method for fabricating thin film transistor which not only manufactures a polycrystalline silicon layer having large grain size and containing a trace of residual metal catalyst by heat treating thereby crystallizing the metal catalyst layer after forming an amorphous silicon layer on a substrate, forming a capping layer formed of nitride film having 1.78 to 1.90 of the refraction index when crystallizing the amorphous silicon layer and forming a metal catalyst layer on the capping layer, but also controls characteristics of the polycrystalline silicon layer by controlling the refraction index of the capping layer.

Spacer-less low-k dielectric processes

Tue, 10 Nov 2009 08:00:00 EST

A first example embodiment provides a method of removing first spacers from gates and incorporating a low-k material into the ILD layer to increase device performance. A second example embodiment comprises replacing the first spacers after silicidation with low-k spacers. This serves to reduce the parasitic capacitances. Also, by implementing the low-k spacers only after silicidation, the embodiments' low-k spacers are not compromised by multiple high dose ion implantations and resist strip steps. The example embodiments can improve device performance, such as the performance of a rim oscillator.

Semiconductor device and method of manufacture

Tue, 10 Nov 2009 08:00:00 EST

A semiconductor device and method of manufacture and, more particularly, a semiconductor device having strain films and a method of manufacture. The device includes an embedded SiGeC layer in source and drain regions of an NFET device and an embedded SiGe layer in source and drain regions of a PFET device. The PFET device is subject to compressive strain. The method includes embedding SiGe in source and drain regions of an NFET device and implanting carbon in the embedded SiGe forming an SiGeC layer in the source and drain regions of the NFET device. The SiGeC is melt laser annealed to uniformly distribute the carbon in the SiGeC layer, thereby counteracting a strain generated by the embedded SiGe.

Method of stacking and interconnecting semiconductor packages via electrical connectors extending between adjoining semiconductor packages

Tue, 10 Nov 2009 08:00:00 EST

An electronic component is disclosed including a plurality of stacked semiconductor packages. A first such embodiment includes an internal connector for electrically coupling the stacked semiconductor packages. A second such embodiment includes an external connector for electrically coupling the stacked semiconductor packages.

Etch stop layer for silicon (Si) via etch in three-dimensional (3-D) wafer-to-wafer vertical stack

Tue, 10 Nov 2009 08:00:00 EST

A method of forming a silicon (Si) via in vertically stacked wafers is provided with a contact plug extending from selected metallic lines of a top wafer and an etch stop layer formed prior to the contact plug. Such a method comprises selectively etching through the silicon (Si) of the top wafer until stopped by the etch stop layer to form the Si via; depositing an oxide layer to insulate a sidewall of the Si via; forming a barrier layer on the oxide layer and on the bottom of the Si via; and depositing a conduction metal into the Si via to provide electrical connection between active IC devices located on vertically stacked wafers and an external interconnect.

Method of manufacturing gallium nitride semiconductor

Tue, 10 Nov 2009 08:00:00 EST

The present invention provides to a gallium nitride (GaN) semiconductor and a method of manufacturing the same, capable of reducing crystal defects caused by a difference in lattice parameters, and minimizing internal residual stress. In particular, since a high-quality GaN thin film is formed on a silicon wafer, manufacturing costs can be reduced by securing high-quality wafers with a large diameter at a low price, and applicability to a variety of devices and circuit can also be improved.

Method for making a thin film layer

Tue, 10 Nov 2009 08:00:00 EST

A method of making a patterned layer comprises directing a beam of vaporized material toward a reflector such that the beam of vaporized material impinges an impingement surface of the reflector and is redirected from the reflector through one or more apertures in a shadow mask and onto a deposition substrate to form a patterned material layer.

Method of forming low-resistance contact electrodes in semiconductor devices

Tue, 10 Nov 2009 08:00:00 EST

There is formed on a semiconductor substrate a lamination of a first insulating film of nondoped silicon glass or the like and, on this first insulating film, a second insulating film of boron phosphor silicate glass or the like, with a conductor layer between the two insulating films. A hole is first dry-etched in the second insulating film, leaving the substrate surface covered by the first insulating film. Then the second insulating film is heated to a reflow temperature such that the hole is thermally deformed, flaring as it extends away from the insulating film. Then a second hole is dry-etched in the first insulating film through the first recited hole in the second insulating film, with the consequent exposure of the semiconductor surface. Then a contract electrode is fabricated by filling the first and the second hole with an electroconductive material into direct contact with the substrate surface. Being covered by the first insulating film, the substrate surface is not to be contaminated with impurities during the heating of the second insulating film.

Electroluminescent element

Tue, 10 Nov 2009 08:00:00 EST

The main object of the present invention is to provide a method for producing an EL element for realizing the high luminous efficiency, the high light takeout efficiency, the simplicity of the production process, and the formation of highly fine patterns. In order to achieve the above-mentioned object, the present invention provides a method for producing an EL element wherein at least one organic EL layer constituting the EL element is patterned by the use of a photolithography method.

System in package (SIP) integrated circuit and packaging method thereof

Tue, 10 Nov 2009 08:00:00 EST

The present invention discloses a system in package (SIP) integrated circuit and a packaging method thereof. The SIP integrated circuit includes one or more first block dices produced by a first process and one or more second block dices produced by a second process. The first block dices are electrically connected to the second block dices. The first block dices and the second block dices are packaged into a system.

Vertical stack type multi-chip package having improved grounding performance and lower semiconductor chip reliability

Tue, 10 Nov 2009 08:00:00 EST

A vertical stack type multi-chip package is provided having improved reliability by increasing the grounding performance and preventing the decrease in reliability of the multi-chip package from moisture penetration into a lower semiconductor chip. The vertical stack type multi-chip package comprises an organic substrate having a printed circuit pattern on which a semiconductor chip is mounted. A first semiconductor chip is mounted on a die bonding region of the organic substrate and is electrically connected to the organic substrate through a first wire. A metal stiffener is formed on the first semiconductor chip and connected to the organic substrate by a first ground unit around the first semiconductor chip. An encapsulant is used to seal the first semiconductor chip below the metal stiffener. A second semiconductor chip, which is larger in size than that the first semiconductor chip, is mounted on the metal stiffener and connected by a second ground unit. The second semiconductor chip is connected to the organic substrate by a second wire. A mold resin seals the second semiconductor chip and a solder ball is bonded to a solder ball pad below the organic substrate.

Damascene process for carbon memory element with MIIM diode

Tue, 10 Nov 2009 08:00:00 EST

Forming a metal-insulator diode and carbon memory element in a single damascene process is disclosed. A trench having a bottom and a sidewall is formed in an insulator. A first diode electrode is formed in the trench during a single damascene process. A first insulating region comprising a first insulating material is formed in the trench during the single damascene process. A second insulating region comprising a second insulating material is formed in the trench during the single damascene process. A second diode electrode is formed in the trench during the single damascene process. The first insulating region and the second insulating region reside between the first diode electrode and the second diode electrode to form a metal-insulator-insulator-metal (MIIM) diode. A region of carbon is formed in the trench during the single damascene process. At least a portion of the carbon is electrically in series with the MIIM diode.

Activation of CMOS source/drain extensions by ultra-high temperature anneals

Tue, 10 Nov 2009 08:00:00 EST

A method of manufacturing a semiconductor device that includes forming a gate dielectric layer over a semiconductor substrate. A gate electrode is formed over the gate dielectric layer. A dopant is implanted into an extension region of the substrate, with an amount of the dopant remaining in a dielectric layer adjacent the gate electrode. The substrate is annealed at a temperature of about 1000° C. or greater to cause at least a portion of the amount of the dopant to diffuse into the semiconductor substrate.

Creation of high mobility channels in thin-body SOI devices

Tue, 10 Nov 2009 08:00:00 EST

A method for fabricating a strained silicon film to a silicon on insulation (SOI) wafer. A layer of oxide is deposited onto a wafer that has a stack structure of a first base substrate, a layer of relaxed film and a second layer of strained film. The SOI wafer has a stack structure of a second base substrate and a layer of oxidized film. The SOI wafer is attached to the wafer and is heated at a first temperature. This causes a silicon dioxide (SiO 2 ) dangling bond to form on the second base substrate of the SOI wafer, transferring the strained film from one wafer to the other.

Method for manufacturing nitride semiconductor substrate

Tue, 10 Nov 2009 08:00:00 EST

A method for manufacturing a nitride semiconductor substrate includes the steps of growing a first nitride semiconductor on a substrate, patterning the first nitride semiconductor to obtain a pattern surrounded by a plane equivalent to the (11-20) plane and having at least two concave portions that are similar in their planar shape, and growing a second nitride semiconductor layer, using a plane equivalent to the (11-20) plane in the first nitride semiconductor pattern as a growth nucleus.

Method of introducing ion and method of manufacturing semiconductor device

Tue, 10 Nov 2009 08:00:00 EST

When an ion is introduced into a semiconductor on which a resist is formed, the ion and the resist react with each other to generate a gas (dissociated gas) and a component of the thus-generated dissociated gas is introduced into the semiconductor, which becomes a factor to deteriorate properties of the semiconductor. According to the invention, the dissociated gas to be generated from an organic film is treated. Particularly, the dissociated gas is treated before an ion introduction is performed. As a method of performing such a treatment, the ion introduction is performed by dividing ion introduction processing itself into a plurality of times. The dissociated gas is generated in a maximum quantity just after the ion introduction is started. For this reason, it is possible to decrease an introduction of a component of the dissociated gas into the semiconductor or prevent the component of the dissociated gas from being introduced into the semiconductor, when ion introduction processing is divided into a plurality of times and, in each of the thus-divided ion introduction processing after a second time thereof, the ion is introduced while removing the dissociated gas from a treatment chamber by performing evacuation.

Method for fabricating semiconductor device including plug

Tue, 10 Nov 2009 08:00:00 EST

A method for fabricating a semiconductor device includes forming an insulation layer over a substrate, etching the insulation layer using a hard mask pattern to form a contact hole, filling the contact hole with a conductive layer, etching the conductive layer to form a plug in the contact hole, removing the remaining hard mask pattern to expose an upper portion of the plug and have the upper portion protrude above the insulation layer, and forming a metal line over the protruding plug and around the upper portion of the plug.

Double-masking technique for increasing fabrication yield in superconducting electronics

Tue, 10 Nov 2009 08:00:00 EST

A new technique is presented for improving the microfabrication yield of Josephson junctions in superconducting integrated circuits. This is based on the use of a double-layer lithographic mask for partial anodization of the side-walls and base electrode of the junctions. The top layer of the mask is a resist material, and the bottom layer is a dielectric material chosen so as to a) maximize adhesion between the resist and the underlying superconducting layer, b) be etch-compatible with the underlying superconducting layer, and c) be insoluble in the resist and anodization processing chemistries. In a preferred embodiment of the invention, the superconductor is niobium, the material on top of this is silicon dioxide, and the top layer is conventional photoresist or electron-beam resist. The use of this combination results in a substantial increase in the fabrication yield of high-density superconducting integrated circuits due to increase in junction uniformity and reduction in defect density. An additional improvement over the prior art involves the replacement of a wet-etch step with a dry etch more compatible with microlithography.

Pyramidal photonic crystal light emitting device

Tue, 10 Nov 2009 08:00:00 EST

A light-emitting device (LED) is described which exhibits high extraction efficiency and an emission profile which is substantially more directional than from a Lambertian source. The device comprises a light generating layer disposed between first and second layers of semiconductor material, each having a different type of doping. An upper surface of the first layer has a tiling arrangement of pyramidal or frustro-pyramidal protrusions of semiconductor material surrounded by a material of different refractive index which together comprise a photonic band structure. The protrusions and their tiling arrangement are configured for efficient extraction of light from the device via the upper surface of the first layer and in a beam that is substantially more directional than from a Lambertian source An enhanced device employs a reflector beneath the second layer to utilize the microcavity effect. A method for fabricating the device is also described which employs anisotropic wet etching to produce the pyramidal or frustro-pyramidal protrusions

Electrostatically operated tunneling transistor

Tue, 10 Nov 2009 08:00:00 EST

A transistor operated by changing the electrostatic potential of an island disposed between two tunnel junctions. The transistor has an island of material which has a band gap (e.g. semiconductor material). Source and drain contacts are provided. The transistor has a first tunnel junction barrier disposed between island and source, and a second tunnel junction barrier disposed between island and drain. The island is Ohmically isolated from other parts of the transistor as well as a substrate. A gate electrode is capacitively coupled to the island so that a voltage applied to the gate can change the potential of the island. The transistor has n- and p-type embodiments. In operation, applying a gate voltage lowers (e.g., for positive gate bias) or raises (e.g., for negative gate bias) the conduction band and valence band of the island. When the conduction band or valence band aligns with the Fermi energy of the source and drain, tunneling current can pass between the source, island and drain.

Evaluation method of semiconductor device, manufacturing method of the semiconductor device, design management system of device comprising the semiconductor device, dose amount control program for the semiconductor device, computer-readable recording medium recording the program, and dose amount control apparatus

Tue, 10 Nov 2009 08:00:00 EST

There is provided a new method of obtaining the dopant activation rate of a device accurately and simply in a different way from a method of obtaining a carrier density with use of a Hall measurement or CV measurement, and also provided a production method of a device performed with a proper threshold voltage control, that is, a dose amount control, according to the obtained activation rate. The inventor devised a method in which the activated dopant density (first dopant density) in a semiconductor film is obtained from the threshold voltage and the flat band voltage of a device, then the dopant activation rate is obtained from the ratio of the obtained activated dopant density to the added dopant density (second dopant density) obtained by SIMS analysis. The invention allows easily obtaining the dopant activation rate in the channel region and the impurity region of the device.

Field effect transistor and method of manufacturing a field effect transistor

Tue, 10 Nov 2009 08:00:00 EST

The invention relates to a method of manufacturing a field effect transistor, in which a semiconductor body of silicon is provided at a surface thereof with a source region and a drain region of a first conductivity type, which regions are both provided with extensions, and with a gate region situated above the channel region. A pn-junction is formed between the extensions and a neighboring part of the channel region using an amorphizing implantation followed by two implantations of dopants of opposite conductivity type, before the gate region is formed and at an angle with the surface of the semiconductor body which is substantially equal to 90 degrees. A steep and abrupt vertical part of the pn-junction is thus formed with a very low leakage current due to the absence of implantations defects. In some embodiments, a low temperature anneal is used to regrow crystalline silicon.

HDP/PECVD methods of fabricating stress nitride structures for field effect transistors

Tue, 10 Nov 2009 08:00:00 EST

A stress nitride structure is formed on an integrated circuit field effect transistor by high density plasma (HDP) depositing a first stress nitride layer on the integrated circuit field effect transistor and then plasma enhanced chemical vapor depositing (PECVD) a second stress nitride layer on the first stress nitride layer. The first stress nitride layer is non-conformal and the second stress nitride layer is conformal. Related structures also are described.

CMOS device and fabricating method thereof

Tue, 10 Nov 2009 08:00:00 EST

A CMOS device is provided, comprising a substrate, a first-type MOS transistor, a second-type MOS transistor, a first stress layer, a first liner layer, and a second stress layer. The substrate has a first active area and a second active area, which are separated by an isolation structure. Further, the first-type MOS transistor is disposed on the first active area of the substrate, and the second-type MOS transistor is disposed on the second active area of the substrate. The first stress layer is compliantly disposed on the first-type MOS transistor of the first active area. The first liner layer is compliantly disposed on the first stress layer. The second stress layer is compliantly disposed on the second-type MOS transistor of the second active area.

Method for forming semiconductor device

Tue, 10 Nov 2009 08:00:00 EST

A method for forming a semiconductor device is provided. More specifically, a method for forming a bulb-shaped portion of a bulb-shaped recess gate is provided to overcome an etching process margin reduction caused by a spacer oxide film formed on sidewalls of a recess and thickly laminated to a lower part of a recess. In one aspect, a buffer dielectric film pattern is formed additionally by a plasma enhanced chemical vapor deposition (PECVD) process over a hard mask pattern, so that a sufficient process margin used for forming the bulb-shaped portion is ensured and a process margin for forming a semiconductor device is increased.

Method of manufacturing a semiconductor integrated circuit device

Tue, 10 Nov 2009 08:00:00 EST

In the chip with which a plurality of MISFET from which threshold value voltage differs is intermingled, leakage current, such as GIDL current and BTBT current, is suppressed, inhibiting the short channel effect of MISFET. The concentration of the impurity for threshold value voltage adjustment implanted to the region in which n channel type MISFET with relatively low threshold value voltage is formed is made lower than the concentration of the impurity for threshold value voltage adjustment implanted to the region in which n channel type MISFET with relatively high threshold value voltage is formed. Implantation amount of the impurity at the time of forming n − type semiconductor region 19 and punch-through stopper layer 20 in region ALTN is made larger than the implantation amount of the impurity at the time of forming n − type semiconductor region 16 and punch-through stopper layer 17 in region AHTN, respectively.

Manufacturing method for variable resistive element

Tue, 10 Nov 2009 08:00:00 EST

A manufacturing method for a variable resistive element according to which a stable switching operation can be achieved with excellent reproducibility is provided. A conductive thin film is deposited on a semiconductor substrate and patterned to a predetermined form, and after that, a first interlayer insulating film is deposited. An opening is then created in a predetermined location on the first interlayer insulating film in such a manner that the upper surface of the conductive thin film is exposed and the thickness of the conductive thin film formed at the bottom of this opening is reduced through processing, and after that, an oxidation process is carried out on the periphery of the exposed conductive thin film. As a result, a variable resistor film is formed in the peripheral region of the opening, and this variable resistor film divides the conductive thin film into a first electrode and a second electrode.

Fabrication method for electronic system modules

Tue, 10 Nov 2009 08:00:00 EST

This specification describes techniques for manufacturing an electronic system module. The module includes flexible multi-layer interconnection circuits with trace widths as narrow as 5 microns or less. A glass panel manufacturing facility, similar to those employed for making liquid crystal display, LCD, panels is preferably used to fabricate the interconnection circuits. A multi-layer interconnection circuit is fabricated on the glass panel using a release layer. A special assembly layer is formed over the interconnection circuit comprising a thick dielectric layer with openings formed at input/output (I/O) pad locations. Solder paste is deposited in the openings using a squeegee to form wells filled with solder. IC chips are provided with gold stud bumps at I/O pad locations, and these bumps are inserted in the wells to form flip chip connections. The IC chips are tested and reworked. The same bump/well connections can be used to attach fine-pitch cables. Module packaging layers are provided for hermetic sealing and for electromagnetic shielding. A blade server or supercomputer embodiment is also described.

Assembly comprising functional block deposited therein

Tue, 10 Nov 2009 08:00:00 EST

An electronic assembly. The assembly includes a substrate, a plurality of recessed regions, and a plurality of functional blocks. Each functional block is deposited in one of the recessed regions. A substantial amount of the plurality of functional blocks is recessed below a top surface of the substrate. Substantial amount is defined by any one of less than 10% of said functional blocks protrudes above the top surface of the substrate; less than 1% of the functional blocks protrudes above the top surface of the substrate; more than 90% of the functional blocks are recessed below the top surface of the substrate; or more than 99% of the functional blocks are recessed below the top surface of the substrate.

Method for producing multijunction solar cell

Tue, 10 Nov 2009 08:00:00 EST

There is provided a method for producing a multijunction solar cell having four-junctions, the method allowing the area of a device to be increased. On a nucleation site formed on a substrate 2, is grown a semiconductor 2 a comprising the same material as the substrate 2 in the shape of a wire. On the semiconductor 2 a, are successively grown semiconductors 3, 4, 5, and 6 with a narrower band gap in the shape of a wire. The semiconductor 3 may be directly grown in the shape of a wire on the nucleation site formed on the substrate 2. It is preferred to form the nucleation site by forming an amorphous SiO 2 coating 8 a on the substrate 2 and etching a part of the amorphous SiO 2 coating 8 a. Further, it is preferred to form an insulating film 8 in the region except the nucleation sites on the substrate 2 by allowing the amorphous SiO 2 coating 8 a to remain therein. The semiconductor 2 a is GaP; the semiconductor 3 is Al 0.3 Ga 0.7 As; the semiconductor 4 is GaAs; the semiconductor 5 is In 0.3 Ga 0.7 As; and the semiconductor 6 is In 0.6 Ga 0.4 As.

Laser anneal of vertically oriented semiconductor structures while maintaining a dopant profile

Tue, 10 Nov 2009 08:00:00 EST

A method to laser anneal a silicon stack (or a silicon-rich alloy) including a heavily doped region buried beneath an undoped or lightly doped region is disclosed. By F selecting laser energy at a wavelength that tends to be transmitted by crystalline silicon and absorbed by amorphous silicon, crystallization progresses through the silicon layers in a manner that minimizes or prevents diffusion of dopants upward from the doped region to the undoped or lightly doped region. In preferred embodiments, the laser energy is pulsed, and a thermally conductive structure beneath the heavily doped layer dissipates heat, helping to control the anneal and limit dopant diffusion.

Semiconductor display device and method of manufacturing the same

Tue, 10 Nov 2009 08:00:00 EST

A method of manufacturing a semiconductor device with the use of a laser crystallization method is provided which can prevent grain boundaries from being formed in a channel forming region of a TFT and which can avoid substantial reduction in TFT mobility, reduction in on current, and increase in off current due to the grain boundaries, and a semiconductor device manufactured by using the manufacturing method is also provided. Stripe shape or rectangular shape unevenness is formed only in a driver circuit. Continuous wave laser light is irradiated to a semiconductor film formed on an insulating film along the stripe unevenness of the insulating film or along a major axis or minor axis of the rectangular unevenness. Although it is most preferable to use the continuous wave laser light at this point, pulse wave laser light may also be used.

Method of manufacturing semiconductor device

Tue, 10 Nov 2009 08:00:00 EST

An internal connecting terminal 12 is formed on electrode pads 23 of a plurality of semiconductor chips 11 formed on a semiconductor substrate 35 , and there is formed a resin member 13 having a resin member body 13 - 1 and a protruded portion 13 - 2 and covering the semiconductor chips 11 on which the internal connecting terminal 12 is formed, a metal layer 39 is formed on the resin member body 13 - 1 and the protruded portion 13 - 2 is used as an alignment mark to form a resist film 48 covering the metal layer 39 in a part corresponding to a region in which a wiring pattern 14 is formed and to then carry out etching over the metal layer 39 by using the resist layer 48 as a mask, thereby forming the wiring pattern 14 which is electrically connected to the internal connecting terminal 12.

Method of fabrication of normally-off field-effect semiconductor device

Tue, 10 Nov 2009 08:00:00 EST

A normally-off HEMT is made by first providing a substrate having its surface partly covered with an antigrowth mask. Gallium nitride is grown by epitaxy on the masked surface of the substrate to provide an electron transit layer comprised of two flat-surfaced sections and a V-notch-surfaced section therebetween. The flat-surfaced sections are formed on unmasked parts of the substrate surface whereas the V-notch-surfaced section, defining a V-sectioned notch, is created by lateral overgrowth onto the antigrowth mask. Aluminum gallium nitride is then deposited on the electron transit layer to provide an electron supply layer which is likewise comprised of two flat-surfaced sections and a V-notch-surfaced section therebetween. The flat-surfaced sections of the electron supply layer are sufficiently thick to normally generate two-dimensional electron gas layers due to heterojunctions thereof with the first and the second flat-surfaced section of the electron transit layer. The V-notch-surfaced section of the electron supply layer is not so thick, normally creating an interruption in the two-dimensional electron gas layer.

Integrated circuit manufacturing method using hard mask

Tue, 10 Nov 2009 08:00:00 EST

An integrated circuit hard mask processing system is provided including providing a substrate having an integrated circuit; forming an interconnect layer over the integrated circuit; applying a low-K dielectric layer over the interconnect layer; applying a hard mask layer over the low-K dielectric layer; forming a via opening through the hard mask layer and the low-K dielectric layer to the interconnect layer; applying a first fluid and a second fluid in the via opening for removing an overhang of the hard mask layer; depositing an interconnect metal in the via opening; and chemical-mechanical polishing the interconnect metal and the ultra low-K dielectric layer.

Thick oxide film for wafer backside prior to metalization loop

Tue, 10 Nov 2009 08:00:00 EST

A method for reducing wafer backside large particle contamination, comprising: performing front end of line processing of a memory device, depositing a thick oxide on the wafer backside so that at least pre-selected oxide thickness remains after back end of line processing is complete and performing the back end of line processing of the memory device.

Method for fabricating MEMS device package that includes grinding MEMS device wafer to expose array pads corresponding to a cap wafer

Tue, 10 Nov 2009 08:00:00 EST

A package of a micro-electro-mechanical systems (MEMS) device includes a cap wafer, a plurality of bonding bumps formed over the cap wafer, a plurality of array pads arrayed on an outer side of the bonding bumps, and an MEMS device wafer bonded to an upper portion of the cap wafer in a manner to expose the array pads.

Micro-element package and manufacturing method thereof

Tue, 10 Nov 2009 08:00:00 EST

A method of manufacturing a micro-element package which can reduce a manufacturing cost and improve productivity by simplifying its structure and manufacturing process, and also can make contributions to miniaturization and thinness, and the micro-element package are provided. The method of the micro-element package including: providing a substrate having a micro-element on its top surface and a transparent cover having a groove on its bottom surface; attaching the transparent cover on the substrate, wherein the bottom surface of the transparent cover where the groove is formed faces the micro-element; exposing the groove by selectively eliminating the transparent cover; and dicing the substrate along the exposed groove.

Charge trap flash memory device, fabrication method thereof, and write/read operation control method thereof

Tue, 10 Nov 2009 08:00:00 EST

In one aspect, a charge trap flash memory device is provided which includes a semiconductor substrate, source and drain regions which are spaced apart in an active region of the semiconductor substrate to define a channel region therebetween, a tunneling dielectric layer located on the channel region, an organic polymer thin film located on the tunneling dielectric layer, metal or metal oxide nano-crystals embedded in the organic polymer thin film, and a gate located on the organic polymer thin film.

Method of forming low resistance void-free contacts

Tue, 10 Nov 2009 08:00:00 EST

A plug is formed by depositing a first material to partially fill an opening, leaving an unfilled portion with a lower aspect ratio than the original opening. A second material is then deposited to fill the remaining portion of the opening. The first material has good filling characteristics but has higher resistivity than the second material. The second material has low resistivity to give the plug low resistance.

Embedded stressed nitride liners for CMOS performance improvement

Tue, 10 Nov 2009 08:00:00 EST

The present invention provides a semiconducting device including a gate region positioned on a mesa portion of a substrate; and a nitride liner positioned on the gate region and recessed surfaces of the substrate adjacent to the gate region, the nitride liner providing a stress to a device channel underlying the gate region. The stress produced on the device channel is a longitudinal stress on the order of about 275 MPa to about 450 Mpa.

Method of forming pad patterns using self-align double patterning method, pad pattern layout formed using the same, and method of forming contact holes using self-align double patterning method

Tue, 10 Nov 2009 08:00:00 EST

A self-align patterning method for forming patterns includes forming a first layer on a substrate, forming a plurality of first hard mask patterns on the first layer, forming a sacrificial layer on top surfaces and sidewalls of the first hard mask patterns, thereby forming a gap between respective facing portions of the sacrificial layer on the sidewalls of the first hard mask patterns, forming a second hard mask pattern in the gap, etching the sacrificial layer using the second hard mask pattern as a mask to expose the first hard mask patterns, exposing the first layer using the exposed first hard mask patterns and the second hard mask pattern, and etching the exposed first layer using the first and second hard mask patterns.

Lithographic processing cell and device manufacturing method

Tue, 10 Nov 2009 08:00:00 EST

A double processing technique for device manufacture includes performing a first patterning step to form apertures in a resist layer which apertures are filled before the first resist layer is stripped and replaced by a second resist layer to be used in the second exposure.

Method and apparatus for forming expitaxial layers

Tue, 10 Nov 2009 08:00:00 EST

The present invention provides a method of depositing epitaxial layers based on Group IV elements on a silicon substrate by Chemical Vapor Deposition, wherein nitrogen or one of the noble gases is used as a carrier gas, and the invention further provides a Chemical Vapor Deposition apparatus ( 10 ) comprising a chamber ( 12 ) having a gas input port ( 14 ) and a gas output port ( 16 ), and means ( 18 ) for mounting a silicon substrate within the chamber ( 12 ), said apparatus further including a gas source connected to the input port and arranged to provide nitrogen or a noble gas as a carrier gas.

Method for producing insulated gate thin film semiconductor device

Tue, 10 Nov 2009 08:00:00 EST

An amorphous semiconductor film is etched so that a width of a narrowest portion thereof is 100 μm or less, thereby forming island semiconductor regions. By irradiating an intense light such as a laser into the island semiconductor regions, photo-annealing is performed to crystallize it. Then, of end portions (peripheral portions) of the island semiconductor regions, at least a portion used to form a channel of a thin film transistor (TFT), or a portion that a gate electrode crosses is etched, so that a region that the distortion is accumulated is removed. By using such semiconductor regions, a TFT is produced.

Laser irradiation apparatus and method for manufacturing semiconductor device using the laser irradiation apparatus

Tue, 10 Nov 2009 08:00:00 EST

An object of the present invention is to provide a laser irradiation method being able to control the irradiation position of the laser beam accurately compared with the conventional irradiation method. Another object of the present invention is to provide a method for manufacturing a semiconductor device with the use of the laser irradiation method being able to irradiate a large substrate accurately with the laser beam. The irradiation position of the laser beam is controlled by using a laser oscillator emitting a laser beam, an optical system for shaping the laser beam into rectangular on the irradiation object, means for moving the irradiation object relative to the laser beam in the long-side direction and the short-side direction of the beam spot, means for moving the irradiation object more slowly in the long-side direction than in the short-side direction, and a laser positioning mechanism.

Non-volatile memory device and method of manufacturing the same

Tue, 10 Nov 2009 08:00:00 EST

A method of manufacturing a non-volatile memory device includes sequentially depositing a first insulation layer, a charge storage layer, and a second insulation layer on a substrate, forming a first opening through the resultant structure to expose the substrate, forming second and third openings through the second insulation layer to form a second insulation layer pattern, forming a conductive layer on the second insulation layer pattern, forming a photoresist pattern structure on the conductive layer, and forming simultaneously a common source line, at least one ground selection line, at least one string selection line, and a plurality of gate structures on the substrate by etching through the photoresist pattern structure, wherein the common source line and the gate structures are formed simultaneously on a substantially same level and of substantially same components.

Method for fabricating trench metal-oxide-semiconductor field effect transistor

Tue, 10 Nov 2009 08:00:00 EST

A method for fabricating a trench metal-oxide-semiconductor field effect transistor is disclosed. The method comprises steps of providing a substrate with an epitaxy layer thereon and etching the epitaxy layer to form a trench structure; forming a gate oxide layer on the surface of the epitaxy layer and the inner sidewalls of the trench structure and depositing a polysilicon layer to fill the trench structure; introducing a nitrogen gas and performing a driving-in procedure to form a body structure; performing an implantation procedure to form a source layer; forming a dielectric layer on the trench structure and the source layer; etching the dielectric layer and the source layer to define a source structure and form a contact region; filling the contact region with a contact structure layer; and forming a conductive metal layer on the contact structure layer and the dielectric layer.

Method of manufacturing flash memory device

Tue, 10 Nov 2009 08:00:00 EST

Disclosed herein is a method of fabricating a flash memory device. The method includes providing a semiconductor substrate that includes an active region and a field region. A tunnel insulating layer and a first conductive layer are formed in the active region, and an isolation structure is formed in the field region. The method includes forming a dielectric layer along a surface of the first conductive layer and the isolation structure, forming a capping layer along a surface of the dielectric layer, and forming a hard mask layer over the capping layer. The method also includes performing a first etchant process to etch the capping layer and the dielectric layer over the isolation structure forming holes. The method further includes performing a second etch process to remove the hard mask layer to form an undercut in the dielectric layer. Still further, the method includes forming a second conductive layer over a structure in which the holes and the undercut are formed.

Method for manufacturing semiconductor device with reduced damage to metal wiring layer

Tue, 10 Nov 2009 08:00:00 EST

A method for manufacturing a semiconductor device includes (a) forming a conductive film on a first surface having an electrode of a semiconductor substrate having an integrated circuit formed therein, the electrode being electrically coupled to the integrated circuit, such that the electrode is covered, forming a plating resist layer on the conductive film such that the plating resist layer has an opening portion exposing part of the conductive film, and forming a metal layer on the exposed part from the plating resist layer of the conductive film by electrolytic plating, the electrolytic plating being performed by applying an electric current to the conductive film; (b) removing the plating resist layer after the step (a); (c) forming a resin layer on a second surface opposite to the first surface of the semiconductor substrate after the step (a); and (d) removing the exposed part from the metal layer of the conductive film by etching with the metal layer as a mask while etching a surface of the metal layer by the etching, after the steps of (a), (b) and (c).

Method for fabricating landing polysilicon contact structures for semiconductor devices

Tue, 10 Nov 2009 08:00:00 EST

A method for forming an integrated circuit device, e.g., memory, logic. The method includes providing a semiconductor substrate (e.g., silicon wafer) comprising a surface region and forming a polysilicon layer overlying the surface region. Preferably, the polysilicon layer is doped with an impurity to provide conductive characteristics. The method forms a cap layer (e.g., silicon nitride, silicon oxynitride) overlying the polysilicon layer. The method forms an Al 2 O 3 layer using atomic layer deposition overlying the polysilicon layer to form a sandwich structure including the polysilicon layer, cap layer, and Al 2 O 3 layer. The method includes patterning the sandwich layer to form a plurality of gate structures. Each of the gate structures includes a portion of the polysilicon layer, a portion of the cap layer, and a portion of the Al 2 O 3 layer. The method forms an interlayer dielectric material (e.g., BPSG, FSG) having an upper surface overlying the plurality of gate structures. The method also includes patterning the interlayer dielectric material to form an opening in a portion of the interlayer dielectric material to expose each of the gate structures and filling the opening with a polysilicon fill material to a vicinity of the upper surface of the interlayer dielectric material. Preferably, the fill material is doped using an impurity. The method also performs a chemical mechanical polishing process to remove a portion of the interlayer dielectric layer concurrently with a portion of the polysilicon fill material and maintains the chemical mechanical polishing process until a portion of the Al 2 O 3 layer overlying one of the gate structures has been exposed. The method uses portions of the Al 2 O 3 layer as a polish stop while preventing any exposure of any portion of the polysilicon layer.

Electromigration-resistant and compliant wire interconnects, nano-sized solder compositions, systems made thereof, and methods of assembling soldered packages

Tue, 10 Nov 2009 08:00:00 EST

A nano-sized metal particle composite includes a first metal that has a particle size of about 50 nanometer or smaller. A wire interconnect is in contact with a reflowed nanosolder and has the same metal or alloy composition as the reflowed nanosolder. A microelectronic package is also disclosed that uses the reflowed nanosolder composition. A method of assembling a microelectronic package includes preparing a wire interconnect template. A computing system includes a nanosolder composition coupled to a wire interconnect.

Method of manufacture of contact plug and interconnection layer of semiconductor device

Tue, 10 Nov 2009 08:00:00 EST

A method of manufacturing a semiconductor device including forming two first gate electrodes along a first direction on a first surface of a semiconductor substrate and source/drain areas sandwiching a channel region under each of the first gate electrodes, forming a first interlayer insulating layer to fill a region between the first gate electrodes, lowering a top of the first interlayer insulating layer, depositing a second interlayer insulating layer on the first interlayer insulating layer and the first gate electrodes, planarizing a surface of the second interlayer insulating layer, and forming an interconnect layer in the second interlayer insulating layer and a contact plug in the first interlayer insulating layer and the second interlayer insulating layer so that the contact plug is in contact with the interconnect layer and one of the source/drain areas.

Method for forming metal interconnects and reducing metal seed layer overhang

Tue, 10 Nov 2009 08:00:00 EST

A method for forming metal interconnects on a substrate is described. A substrate with a dielectric layer is positioned within a processing chamber. A first barrier layer is deposited on the dielectric layer and within a plurality of vias of the dielectric layer, wherein the first barrier layer includes beveled edges extending from a field of the substrate to a sidewall surface of each via. The first barrier layer and the dielectric layer are etched to form a recess at each beveled edge. A second barrier layer is deposited over the recess. A metal seed layer deposited over the first barrier layer, the second barrier layer, and within the recess.

Forming fine pattern of semiconductor device using three mask layers and CMP of spin-on carbon layer

Tue, 10 Nov 2009 08:00:00 EST

A method for forming a fine pattern of a semiconductor device includes forming a deposition film over a substrate having an underlying layer. The deposition film includes first, second, and third mask films. The method also includes forming a photoresist pattern over the third mask film, patterning the third mask film to form a deposition pattern, and forming an amorphous carbon pattern at sidewalls of the deposition pattern. The method further includes filling a spin-on-carbon layer over the deposition pattern and the amorphous carbon pattern, polishing the spin-on-carbon layer, the amorphous carbon pattern, and the photoresist pattern to expose the third mask pattern, and performing an etching process to expose the first mask film with the amorphous carbon pattern as an etching mask. The etching process removes the third mask pattern and the exposed second mask pattern. The method also includes removing the spin-on-carbon layer and the amorphous carbon pattern, and forming a first mask pattern with the second mask pattern as an etching mask.

Solar cell and method of fabricating the same

Tue, 10 Nov 2009 08:00:00 EST

A method of fabricating a solar cell forms a large number of grooves on a first main surface of a p-type silicon single crystal substrate sliced out from a silicon single crystal ingot as described below. First an edge portion of a groove-carving blade is projected out from a flat substrate feeding surface of a working table by a predetermined height. The p-type silicon single crystal substrate is moved along the substrate feeding surface towards the rotating groove-carving blade while keeping a close contact of the first main surface thereof with the substrate feeding surface. Electrodes are then formed on the inner side face of thus-carved grooves only on one side in the width-wise direction thereof.

Methods and systems for packaging integrated circuits with integrated passive components

Tue, 10 Nov 2009 08:00:00 EST

A method is described for packaging integrated circuit dice such that each package includes a die with an integrated passive component mounted to the active surface of the die.

Secure package with anti-tamper peripheral guard ring

Tue, 10 Nov 2009 08:00:00 EST

A ball grid array (BGA) package (such as one BGA package of a package-on-package (POP) secure module assembly) includes a substrate, and integrated circuit, and array of bond balls. The BGA package further includes a first amount of encapsulant that covers the integrated circuit and a novel second amount of encapsulant. The novel second amount of encapsulant is a peripheral strip that extends along an edge of the substrate to form a peripheral guard ring. The peripheral guard ring provides an additional amount of anti-tamper security to the BGA package. The guard ring can be fabricated with no or very little additional cost if the guard ring is formed in the same encapsulation step employed to encapsulate the integrated circuit. In some embodiments, the peripheral guard ring is made part of and/or is coupled to anti-tamper circuitry such that if the guard ring is disturbed a tamper condition is detected.

Open source/drain junction field effect transistor

Tue, 10 Nov 2009 08:00:00 EST

The disclosure herein pertains to fashioning an n channel junction field effect transistor (NJFET) and/or a p channel junction field effect transistor (PJFET) with an open drain, where the open drain allows the transistors to operate at higher voltages before experiencing gate leakage current. The open drain allows the voltage to be increased several fold without increasing the size of the transistors. Opening the drain essentially spreads equipotential lines of respective electric fields developed at the drains of the devices so that the local electric fields, and hence the impact ionization rates are reduced to redirect current below the surface of the transistors.

Methods of fabricating field effect transistors having multiple stacked channels

Tue, 10 Nov 2009 08:00:00 EST

Integrated circuit field effect transistor devices include a substrate having a surface and an active channel pattern on the surface. The active channel pattern includes channels that are stacked upon one another and are spaced apart from one another to define at least one tunnel between adjacent channels. A gate electrode surrounds the channels and extends through the at least one tunnel. A pair of source/drain regions also is provided. Integrated circuit field effect transistors are manufactured, by forming a pre-active pattern on a surface of a substrate. The pre-active pattern includes a series of interchannel layers and channel layers stacked alternately upon each other. Source/drain regions are formed on the substrate at opposite ends of the pre-active pattern. The interchannel layers are selectively removed to form tunnels. A gate electrode is formed in the tunnels and surrounding the channels.

Composite charge storage structure formation in non-volatile memory using etch stop technologies

Tue, 10 Nov 2009 08:00:00 EST

Semiconductor-based non-volatile memory that includes memory cells with composite charge storage elements is fabricated using an etch stop layer during formation of at least a portion of the storage element. One composite charge storage element suitable for memory applications includes a first charge storage region having a larger gate length or dimension in a column direction than a second charge storage region. While not required, the different regions can be formed of the same or similar materials, such as polysilicon. Etching a second charge storage layer selectively with respect to a first charge storage layer can be performed using an interleaving etch-stop layer. The first charge storage layer is protected from overetching or damage during etching of the second charge storage layer. Consistency in the dimensions of the individual memory cells can be increased.

Power delivery package having through wafer vias

Tue, 10 Nov 2009 08:00:00 EST

An integrated circuit chip package and a method of manufacture thereof are provided. In one embodiment, the integrated circuit chip package comprises a semiconductor die having power and ground routings, a plurality of through wafer vias disposed within the semiconductor die, the through wafer vias connected to the power and ground routings, and a substrate attached to the semiconductor die, the substrate having power and ground leads connected to the through wafer vias for transferring power from the substrate to the semiconductor die.

Method for forming pattern, thin film transistor, display device and method for manufacturing the same, and television device

Tue, 10 Nov 2009 08:00:00 EST

A method for forming a pattern according to the invention comprises the steps of: forming a mask over a substrate having light-transmitting properties; forming a first region having a substance including a light-absorbing material over the substrate and the mask; forming a second region by irradiating the substance with light having a wavelength which is absorbable by the light-absorbing material through the substrate to modify a part of the substance surface; and forming a pattern by discharging a compound including a pattern forming material to the second region.

Organic electroluminescent device, pixel structure, array and driving method thereof

Tue, 10 Nov 2009 08:00:00 EST

An organic electroluminescent device includes a first organic thin film transistor, a second organic thin film transistor and at least an organic functional layer. The organic functional layer is disposed between the second organic thin film transistor and the first organic thin film transistor. By applying voltages in the first organic thin film transistor and the second organic thin film transistor at the same time, a voltage difference between the two transistors is produced to make electrons and electric holes move into the organic functional layer and re-combine therein for emitting light. The integration of the organic thin film transistor and the organic electroluminescent device can widen aperture ratio and increase process reliability.

Methods of manufacturing semiconductor devices and semiconductor devices manufactured using such a method

Tue, 10 Nov 2009 08:00:00 EST

A method of manufacturing a semiconductor device includes forming a pillar-shaped active region by etching a portion of a semiconductor substrate, forming a blocking film selectively exposing a sidewall of a lower portion of the pillar-shaped active region, and forming a bit-line selectively on the exposed sidewall of the lower portion of the pillar-shaped active region.

Film formation apparatus and method of using the same

Tue, 10 Nov 2009 08:00:00 EST

A method of using a film formation apparatus for a semiconductor process includes processing by a cleaning gas a by-product film deposited on an inner surface of a reaction chamber of the film formation apparatus. This step is arranged to supply the cleaning gas into the reaction chamber, and set an interior of the reaction chamber at a first temperature and a first pressure. The by-product film mainly contains a high-dielectric-constant material. The cleaning gas contains chlorine without containing fluorine. The first temperature and the first pressure are set to activate chlorine in the cleaning gas.

Method for manufacturing indium gallium aluminium nitride thin film on silicon substrate

Tue, 10 Nov 2009 08:00:00 EST

The method for manufacturing the indium gallium aluminium nitride (InGaAlN) thin film on silicon substrate, which comprises the following steps: introducing magnesium metal for processing online region mask film, that is, or forming one magnesium mask film layer or metal transition layer; then forming one metal transition layer or magnesium mask layer, finally forming one layer of indium gallium aluminium nitride semiconductor layer; or firstly forming one layer of metal transition layer on silicon substrate and then forming the first indium gallium aluminium nitride semiconductor layer, magnesium mask layer and second indium gallium aluminium nitride semiconductor layer in this order. This invention can reduce the dislocation density of indium gallium aluminium nitride materials and improve crystal quality.

Chip-sized flip-chip semiconductor package and method for making the same

Tue, 10 Nov 2009 08:00:00 EST

A semiconductor package ( 10; 14 ) comprises a semiconductor die ( 2; 2′ ) with a plurality of contact areas ( 4 ) on its active surface and an electrically conductive bump ( 7 ) on each contact area ( 4 ). The die ( 2; 2′ ) and electrically conductive bumps ( 7 ) are encapsulated in a plastic housing ( 11 ) so that the plastic housing ( 11 ) encapsulates at least sides of the die ( 2; 2′ ) and sides of the electrically conductive bumps ( 7 ).

High performance stress-enhance MOSFET and method of manufacture

Tue, 10 Nov 2009 08:00:00 EST

A semiconductor structure and method of manufacturing and more particularly a CMOS device with a stress inducing material embedded in both gates and also in the source/drain region of the PFET. The PFET region and the NFET region having a different sized gate to vary the device performance of the NFET and the PFET.

Manufacturing method of semiconductor device

Tue, 10 Nov 2009 08:00:00 EST

Before applying a resist on a first gate insulating film, a thinner is provided on an entire surface including a surface of the first gate insulating film to wash the surface of the first gate insulating film. Specifically, while a semiconductor substrate is being rotated, onto a central part thereof the thinner is provided from a nozzle, so that the thinner is spread outward in a radial direction of the semiconductor substrate to be applied on an entire surface of the semiconductor substrate by a centrifugal force.

Forming high-k dielectric layers on smooth substrates

Tue, 10 Nov 2009 08:00:00 EST

A buffer layer and a high-k metal oxide dielectric may be formed over a smooth silicon substrate. The substrate smoothness may reduce column growth of the high-k metal oxide gate dielectric. The surface of the substrate may be saturated with hydroxyl terminations prior to deposition.

Semiconductor device and method of manufacturing the same

Tue, 10 Nov 2009 08:00:00 EST

The semiconductor device of the present invention includes a semiconductor substrate, a plurality of floating gate electrodes formed in a memory cell forming region of the semiconductor substrate, a word line electrically connecting the floating gate electrodes and a conductor portion formed on the word line so as to reduce a resistance of the word line.

Design structure for coupling noise prevention

Tue, 10 Nov 2009 08:00:00 EST

A semiconductor structure for preventing coupling noise in integrated circuits and a method of forming the same are provided. The semiconductor structure includes a signal-grounded seal ring. The seal ring includes a plurality of metal lines, each in a respective metal layer and surrounding a circuit region of the semiconductor chip, a plurality of vias connecting respective metal lines, and a plurality of dielectric layers isolating each metal layer from any other metal layers. The seal ring may further include additional seal rings formed inside or outside the seal ring. The semiconductor structure may include laser fuses and protective rings. The protective rings are preferably signal grounded. Cross talk between sub circuits in a chip can be reduced by forming a seal ring extension between the sub circuits.

Image sensor and method of manufacturing thereof

Tue, 10 Nov 2009 08:00:00 EST

An image sensor and a method of manufacturing the image sensor, wherein the image sensor can electrically connect a light receiving portion and a printed circuit board (PCB) including circuits by forming holes and filling the holes with a conductive material, without using a wire for the electrical connection between the light receiving portion and the PCB. The light receiving portion converts lights into electrical signals and the PCB electrically processes signals. That is, since a distance for a wire between a sealing structure and because a filter is unnecessary, a thickness may be reduced. Also, since a space for wire bonding is unnecessary on the outside of an image sensor, a fill factor may increase. Also, since a process that may cause contaminates is removed, average yield may increase and production cost may decrease. The manufacturing productivity may be improved.

Plasma etching methods and contact opening forming methods

Tue, 10 Nov 2009 08:00:00 EST

The invention includes etching and contact opening forming methods. In one implementation, a plasma etching method includes providing a bottom powered plasma chamber that includes a plasma generating electrode powerable at different first and second frequencies, with the first frequency being lower than the second frequency. A substrate is positioned over the electrode. A plasma is generated over the substrate with the electrode from a first applied power at the first frequency and a second applied power at the second frequency. A ratio of the first applied power to the second applied power is from 0 to 0.25 or at least 6.0. Material is etched from the substrate with the plasma.

Triggered silicon controlled rectifier for RF ESD protection

Tue, 10 Nov 2009 08:00:00 EST

An ESD protection circuit is formed at the input/output interface contact of an integrated circuit to protect the integrated circuit from damage caused by an ESD event. The ESD protection circuit has a polysilicon bounded SCR connected between a signal input/output interface contact of the integrated circuit and a power supply connection of the integrated circuit and a biasing circuit. The biasing circuit is connected to the polysilicon bounded SCR to bias the polysilicon bounded SCR to turn on more rapidly during the ESD event. The biasing circuit is formed by at least one polysilicon bounded diode and a first resistance. Other embodiments of the biasing circuit include a resistor/capacitor biasing circuit and a second diode triggering biasing circuit.

Capacitor and method of manufacturing a capacitor

Tue, 10 Nov 2009 08:00:00 EST

In a method of fabricating a semiconductor device, a level of metal is formed within an interval dielectric. The level of metal includes a first metal line separated from a second metal line by a region of the interlevel dielectric. The region of interlevel dielectric is removed between the first metal line and the second metal line. A high-k dielectric is formed between the first metal line and the second metal line in the region where the interlevel dielectric was removed such that a capacitor is formed by the first metal line, the second metal line and the high-k dielectric.

Method of fabricating self-aligned bipolar transistor having tapered collector

Tue, 10 Nov 2009 08:00:00 EST

A method is provided for making a bipolar transistor which includes a tapered, i.e. frustum-shaped, collector pedestal having an upper substantially planar surface, a lower surface, and a slanted sidewall extending between the upper surface and the lower surface, the upper surface having substantially less area than the lower surface. The collector pedestal can be formed on a surface of a collector active region exposed within an opening extending through first and second overlying dielectric regions, where the opening defines vertically aligned edges of the first and second dielectric regions.

Hard mask technique in forming a plug

Tue, 10 Nov 2009 08:00:00 EST

A method for manufacturing a semiconductor device includes the steps of forming a conductive hard mask coupled to the semiconductor substrate via discharge plugs on a thick insulating film, selectively etching the thick insulating film by using the conductive hard mask to form cylindrical holes in the thick insulating film. The resultant cylindrical holes are free form bowing structure.

Method for making thin layers containing microcomponents

Tue, 10 Nov 2009 08:00:00 EST

The invention concerns a method for making thin layers containing microcomponents using a substrate. The method includes the following steps: a) provides a substrate; b) local implantation of at least a gaseous species in said substrate perpendicular to a plurality of implantation zones defined on the surface of the substrate, avoiding, by adequate selection of the depth and the shape of said implantation zones, degradation of said surface of the substrate during the step c); c) producing microcomponents in the surface layer of the substrate delimited by the implanting depth; and d) separating the substrate in two parts, one part containing the surface layer including said microcomponents, and the other the rest of the substrate. The invention is useful for producing microcomponents to be integrate on supports different from the those used for their manufacture.

Edge seal for a semiconductor device and method therefor

Tue, 10 Nov 2009 08:00:00 EST

In one embodiment, an edge seal region of a semiconductor die is formed by forming a first dielectric layer on a surface of a semiconductor substrate near an edge of the semiconductor die and extending across into a scribe grid region of the semiconductor substrate. Another dielectric layer is formed overlying the first dielectric layer. An opening is formed through the first and second dielectric layers. The second dielectric layer is used as a mask for forming a doped region on the semiconductor substrate through the opening. A metal is formed that electrically contacts the doped region and an exterior edge of the first dielectric layer within the opening.

Apparatus and method for integrated surface treatment and deposition for copper interconnect

Tue, 10 Nov 2009 08:00:00 EST

A method and system for depositing films on a substrate for copper interconnect in an integrated system are provided to enable controlled-ambient transitions within an integrated system to limit exposure of the substrate to uncontrolled ambient conditions. The method includes moving the substrate into a processing chamber having a plurality of proximity heads. Within the processing chamber, barrier layer deposition is performed over a surface of the substrate using one of the plurality of proximity heads functioning to perform barrier layer ALD. In addition, the method includes moving the substrate from the processing chamber, through a transfer module of the integrated systems, into a processing module for performing copper seed layer deposition. Within the processing module for performing copper seed layer deposition, copper seed layer deposition is performed over the surface of the substrate. The processing chamber for performing the barrier layer ALD and the processing module for performing the copper seed layer deposition are parts of the integrated system.

Method of manufacturing a semiconductor device

Tue, 10 Nov 2009 08:00:00 EST

A semiconductor device 200 comprises a SiCN film 202 formed on a semiconductor substrate (not shown), a first SiOC film 204 formed thereon, a SiCN film 208 formed thereon, a second SiOC film 210 formed thereon, a SiO 2 film 212 and a SiCN film 214 formed thereon. The first SiOC film 204 has a barrier metal layer 216 and via 218 formed therein, and the second SiOC film 210 has a barrier metal layer 220 and wiring metal layer 222 formed therein. Carbon content of the second SiOC film 210 is adjusted larger than that of the first SiOC film 204 . This makes it possible to improve adhesiveness of the insulating interlayer with other insulating layers, while keeping a low dielectric constant of the insulating interlayer.

Method for oxidizing a layer, and associated holding devices for a substrate

Tue, 10 Nov 2009 08:00:00 EST

A method is presented in which a layer which is to be oxidized is processed, in a single-substrate process. The process temperature during the processing is recorded directly at the substrate or at a holding device for the substrate. The method includes introducing a substrate, which bears a layer to be oxidized uncovered in an edge region in a layer stack, into a heating device, passing an oxidation gas onto the substrate, heating the substrate to a process temperature, which is recorded during the processing via a temperature of a holding device which holds the substrate, and controlling the substrate temperature to a desired temperature or temperature curve during the processing.

Laser processing method and laser processing apparatus

Tue, 10 Nov 2009 08:00:00 EST

A laser beam machining method and a laser beam machining device capable of cutting a work without producing a fusing and a cracking out of a predetermined cutting line on the surface of the work, wherein a pulse laser beam is radiated on the predetermined cut line on the surface of the work under the conditions causing a multiple photon absorption and with a condensed point aligned to the inside of the work, and a modified area is formed inside the work along the predetermined determined cut line by moving the condensed point along the predetermined cut line, whereby the work can be cut with a rather small force by cracking the work along the predetermined cut line starting from the modified area and, because the pulse laser beam radiated is not almost absorbed onto the surface of the work, the surface is not fused even if the modified area is formed.

GaN lasers on ALN substrates and methods of fabrication

Tue, 10 Nov 2009 08:00:00 EST

Ga(In)N-based laser structures and related methods of fabrication are proposed where Ga(In)N-based semiconductor laser structures are formed on AlN or GaN substrates in a manner that addresses the need to avoid undue tensile strain in the semiconductor structure. In accordance with one embodiment of the present invention, a Ga(In)N-based semiconductor laser is provided on an AlN or GaN substrate provided with an AlGaN lattice adjustment layer where the substrate, the lattice adjustment layer, the lower cladding region, the active waveguiding region, the upper cladding region, and the N and P type contact regions of the laser form a compositional continuum in the semiconductor laser. Additional embodiments are disclosed and claimed.

Methods of fabricating multi-layer phase-changeable memory devices

Tue, 10 Nov 2009 08:00:00 EST

A phase-changeable memory device includes a phase-changeable material pattern and first and second electrodes electrically connected to the phase-changeable material pattern. The first and second electrodes are configured to provide an electrical signal to the phase-changeable material pattern. The phase-changeable material pattern includes a first phase-changeable material layer and a second phase-changeable material layer. The first and second phase-changeable material patterns have different chemical, physical, and/or electrical characteristics. For example, the second phase-changeable material layer may have a greater resistivity than the first phase-changeable material layer. For instance, the first phase-changeable material layer may include nitrogen at a first concentration, and the second phase-changeable material layer may include nitrogen at a second concentration that is greater than the first concentration. Related devices and fabrication methods are also discussed.

Semiconductor package including connected upper and lower interconnections, and manufacturing method thereof

Tue, 10 Nov 2009 08:00:00 EST

A semiconductor package includes a base plate, at least one semiconductor constructing body which is formed on one surface of the base plate and has a plurality of external connection electrodes formed on a semiconductor substrate, an insulating layer which is formed on one surface of the base plate around the semiconductor constructing body, upper interconnections which are formed on the insulating layer and each includes at least one interconnection layer, at least some of the upper interconnections are connected to the external connection electrodes of the semiconductor constructing body, lower interconnections which are formed on the other surface of the base plate and each includes at least one interconnection layer, and at least some of the lower interconnections which are electrically connected to the upper interconnections.

Dental intraoral radiological image sensor with a fiber-optic plate

Tue, 10 Nov 2009 08:00:00 EST

The invention relates to dental radiological image sensors for intraoral use. What is described is a method of fabricating an image sensor, comprising steps for the collective production of a structure combining a semiconductor wafer ( 12 ), bearing a series of image detection circuits, and a fiber-optic plate ( 20 ) fixed to one face of the wafer, the semiconductor wafer being thinned in a step subsequent to the formation of the image detection circuits on the wafer, and external access contact pads ( 28 ) are produced on that face of the wafer which is not fixed to the fiber plate, said contact pads being for controlling the circuits and for receiving image signals coming from the sensor, the fiber-optic plate having a thickness such that it provides most of the mechanical integrity of the structure once the wafer has been thinned, and to do so right to the end of the collective fabrication, the assembled structure consisting of the wafer and the plate being subsequently diced into individual chips.

Flip chip package process

Tue, 10 Nov 2009 08:00:00 EST

A flip chip package process is provided. First, a substrate strip including at least one substrate is provided. Next, at least one chip is disposed on the substrate, and the chip is electrically connected to the substrate. Then, a stencil having at least one opening and an air slot hole is disposed on an upper surface of the substrate strip, an air gap is formed between the stencil and the substrate strip, the air gap connects the opening and the air slot hole, and the chip is located in the opening. Finally, a liquid compound is formed into the opening of the stencil to encapsulate the chip, and a vacuum process is performed through the air slot hole and the air gap, so as to prevent the air inside the opening from being encapsulated by the liquid compound to become voids.

Two mask floating gate EEPROM and method of making

Tue, 10 Nov 2009 08:00:00 EST

There is provided a floating gate transistor, such as an EEPROM transistor, and method of making the transistor using two masking steps. The method of making a transistor includes patterning a floating gate layer using a first photoresist mask to form a floating gate rail and doping an active area using the floating gate rail as a mask to form source and drain regions in the active area. The method also includes patterning a control gate layer, a control gate dielectric layer, the floating gate rail, a tunnel dielectric layer and the active area using a second photoresist mask to form a control gate, a control gate dielectric, a floating gate, a tunnel dielectric and a channel island region.

Lanthanide yttrium aluminum oxide dielectric films

Tue, 10 Nov 2009 08:00:00 EST

Electronic apparatus and methods of forming the electronic apparatus include a lanthanide yttrium aluminum oxide dielectric film on a substrate for use in a variety of electronic systems. The lanthanide yttrium aluminum oxide film may be structured as one or more monolayers. The lanthanide yttrium aluminum oxide film may be formed by atomic layer deposition.

Methods of reducing coupling between floating gates in nonvolatile memory

Tue, 10 Nov 2009 08:00:00 EST

A nonvolatile memory array includes floating gates that have an inverted-T shape in cross section along a plane that is perpendicular to the direction along which floating cells are connected together to form a string. Adjacent strings are isolated by shallow trench isolation structures. An array having inverted-T shaped floating gates may be formed in a self-aligned manner.

Method for forming shallow trench isolation of semiconductor device

Tue, 10 Nov 2009 08:00:00 EST

A method for forming a shallow trench isolation (STI) of a semiconductor device comprises forming a nitride film pattern over a semiconductor substrate having a defined lower structure, etching a predetermined thickness of the semiconductor substrate using the nitride film pattern as a mask to form a trench having a vertical sidewall in a portion of the substrate predetermined to be a device isolation region, performing a plasma treatment process on the sidewall of the trench to form a plasma oxide film, forming an oxide film over the resulting structure to fill the trench, and performing a planarization process over the resulting structure.

Method for producing a semiconductor-on-insulator structure

Tue, 10 Nov 2009 08:00:00 EST

The invention relates to a process of treating a structure for electronics or optoelectronics, wherein the structure that has a substrate, a dielectric layer having a thermal conductivity substantially higher than thermal conductivity of an oxide layer made of an oxide of a semiconductor material, an oxide layer made of an oxide of the semiconductor material, and a thin semiconductor layer made of the semiconductor material. The process includes a heat treatment of the structure in an inert or reducing atmosphere with a temperature and a duration chosen for inciting an amount of oxygen of the second oxide layer to diffuse through the semiconductor layer so that the thickness of the second oxide layer decreases by a determined value. The invention also relates to a process of manufacturing a structure for electronics or optoelectronics applications through the use of this type of heat treatment.

Method for fabricating landing plug of semiconductor device

Tue, 10 Nov 2009 08:00:00 EST

A method of fabricating a landing plug of a semiconductor device includes performing a double patterning process to separately form a landing plug contact hole for a storage node and a landing plug contact hole for a bit line, thereby facilitating forming a device having a half pitch of 30 nm.

Method for forming alignment mark

Tue, 10 Nov 2009 08:00:00 EST

A method for forming an alignment mark comprises forming an etch stop film and an interlayer insulating film over a semiconductor substrate including a cell region and a scribe region, etching a predetermined region of the interlayer insulating film and the etch stop film to form a storage node region in the cell region and an alignment mark region in the scribe region, forming a layer for storage node over an entire surface of the resultant including the storage node region in the cell region and the alignment mark region in the scribe region, etching the layer for storage node until the interlayer insulting film is exposed, and removing the interlayer insulating film to form a capacitor in the cell region and an alignment mark in the scribe region.

Semiconductor device and manufacturing method thereof

Tue, 10 Nov 2009 08:00:00 EST

Since VF and IR characteristics of a Schottky barrier diode are in a trade-off relationship, there has heretofore been a problem that an increase in a leak current is unavoidable in order to realize a low VF. Moreover, there has been a known structure which suppresses the leak current in such a manner that a depletion layer is spread by providing P+ regions and a pinch-off effect is utilized. However, in reality, it is difficult to completely pinch off the depletion layer. P+ type regions are provided, and a low VF Schottky metal layer is allowed to come into contact with the P+ type regions and depletion regions therearound. A low IR Schottky metal layer is allowed to come into contact with a surface of a N type substrate between the depletion regions. When a forward bias is applied, a current flows through the metal layer of low VF characteristic. When a reverse bias is applied, a current path narrowed by the depletion regions is formed only in the metal layer portion of low IR characteristic. Thus, a low VF and low IR Schottky barrier diode can be realized.

Multiple RF-port modulator for RFID tag

Tue, 10 Nov 2009 08:00:00 EST

Apparatus and systems may include integrated circuits for use with Radio Frequency Identification (RFID) tags having an antenna structure with at least three coupling ends. The integrated circuits may include three or more nodes corresponding respectively to the at least three coupling ends, and a modulator switch to receive a single modulator switching signal input. Methods may include those used to form and operate such circuits. Additional apparatus, systems, and methods are disclosed.

Method for depositing film and method for manufacturing semiconductor device

Tue, 10 Nov 2009 08:00:00 EST

A method for depositing a film includes: (a) processing a wafer, including forming a high dielectric constant film on a first wafer; and achieving nitridation of the high dielectric constant film formed on the first wafer; and (b) performing coating process including forming a high dielectric constant film on a second wafer; and achieving nitridation of the high dielectric constant film formed on the second wafer. The processing the wafer and the performing the coating process are carried out in the same reaction chamber. The coating process is carried out before the processing the wafer.

Semiconductor device having a recess channel transistor

Tue, 10 Nov 2009 08:00:00 EST

The semiconductor device having a recess channel transistor includes a device isolation structure formed in a semiconductor substrate to define an active region having a recess region at a lower part of sidewalls thereof and a recess channel region formed in the semiconductor substrate under the active region. A method for fabricating the semiconductor device includes forming a device isolation structure in a semiconductor substrate to form an active region having a recess region at a lower part of sidewalls thereof, a gate insulating film formed over the semiconductor substrate including the recess channel region, and a gate electrode formed over the gate insulating film to fill up the recess channel region.

Integrated circuit bipolar transistor

Tue, 10 Nov 2009 08:00:00 EST

A bipolar transistor having a base region resting by its lower surface on a collector region and surrounded with a first insulating layer, a base contact conductive region in contact with an external upper peripheral region of the base region, a second insulating region in contact with an intermediary upper peripheral region of the base region, an emitter region in contact with the central portion of the base region. The level of the central portion is higher than the level of the intermediary portion.

Electronic device package manufacturing method and electronic device package

Tue, 10 Nov 2009 08:00:00 EST

By joining a lid member to a base member, internal electrodes put in contact with the lid member and an electronic device connected to the internal electrodes are placed in an internal space located in between the base member and the lid member. By performing etching from a surface of the lid member on a side opposite from the base member by a prescribed method, through holes that reach the surface of the internal electrodes are formed. A conductive material is applied to the through holes, and external electrodes connected to the internal electrodes are formed in a plane, completing a thin type electronic device package.

Preparing method of CNT-based semiconductor sensitized solar cell

Tue, 10 Nov 2009 08:00:00 EST

A solar cell is prepared. The solar cell is photo-sensitized. The solar cell has a semiconductor layer. And carbon nanotubes are deposited on the semiconductor layer with an arrangement. The solar cell is prepared with a reduced amount of fabrication material, a lowered fabrication cost and a prolonged lifetime.

Semiconductor device and manufacturing method thereof

Tue, 10 Nov 2009 08:00:00 EST

In a semiconductor device having SiC vertical trench MOSFETs, it is aimed to prevent the generation of large scattering in the channel resistance without largely increasing the average value of channel resistance. A 4H-SiC substrate having a major face thereof that is generally a {0001} face and having an off angle α. The trench is formed with the standard deviation σ in scattering of the angle formed by a trench side wall face and a substrate major face within a wafer face. By setting the designed value of the angle formed by the trench side wall face and the substrate major face at an any angle ranging from [(60 degrees)+2σ] to [(90 degrees)−tan −1 (0.87×tan α)−2σ] in forming the trench in the SiC substrate, a semiconductor device in which the angle formed by the trench side wall face and the substrate major face is 60 degrees or more but not more than [(90 degrees)−tan −1 (0.87×tan α)] can be obtained.

Electrode, method for producing same and semiconductor device using same

Tue, 10 Nov 2009 08:00:00 EST

There is provided a technology for obtaining an electrode having a low contact resistance and less surface roughness. There is provided an electrode comprising a semiconductor film 101 , and a first metal layer 102 and a second metal layer 103 sequentially stacked in this order on the semiconductor film 101 , characterized in that the first metal film 102 is formed of Al, and the second metal film 103 is formed of at least one metal selected from the group consisting of Nb, W, Fe, Hf, Re, Ta and Zr.

Photodiode stack for photo MOS relay using junction isolation technology

Tue, 10 Nov 2009 08:00:00 EST

A novel photodiode stack which comprising of more than 3 photodiodes connected in series to produce a large photovoltaic voltage in the presence of light using junction isolation technology.

Method of manufacturing stack-type semiconductor device and method of manufacturing stack-type electronic component

Tue, 10 Nov 2009 08:00:00 EST

A first semiconductor element is bonded on a substrate. A complex film formed of integrated dicing film and adhesive film is affixed on a rear surface of a semiconductor wafer which is to be second semiconductor elements, the dicing film having a thickness within a range of not less than 50 μm nor more than 140 μm and a room temperature elastic modulus within a range of not less than 30 MPa nor more than 120 MPa, and the adhesive film having a thickness of 30 μm or more and a room temperature elastic modulus before curing within a range of not less than 500 MPa nor more than 1200 MPa. The semiconductor wafer together with the adhesive film is divided into the second semiconductor elements. The second semiconductor element is picked up from the dicing film to be bonded on the first semiconductor element.

Double anneal with improved reliability for dual contact etch stop liner scheme

Tue, 10 Nov 2009 08:00:00 EST

A method for forming a device with both PFET and NFET transistors using a PFET compressive etch stop liner and a NFET tensile etch stop liner and two anneals in a deuterium containing atmosphere. The method comprises: providing a NFET transistor in a NFET region and a PFET transistor in a PFET region. We form a NFET tensile contact etch-stop liner over the NFET region. Then we perform a first deuterium anneal. We form a PFET compressive etch stop liner over the PFET region. We form a (ILD) dielectric layer with contact openings over the substrate. We perform a second deuterium anneal. The temperature of the second deuterium anneal is less than the temperature of the first deuterium anneal.

Printed metal mask for UV, e-beam, ion-beam and X-ray patterning

Tue, 10 Nov 2009 08:00:00 EST

A method of forming vias and pillars using printed masks is described. The printed masks are typically made from droplets that include suspended metal nanoparticles. The use of the same metal nanoparticle solution in both the mask formation and the subsequent formation of conducting structures simplifies the fabrication process.

Defectivity and process control of electroless deposition in microelectronics applications

Tue, 10 Nov 2009 08:00:00 EST

Methods and compositions for electrolessly depositing Co, Ni, or alloys thereof onto a substrate in manufacture of microelectronic devices. Grain refiners, levelers, oxygen scavengers, and stabilizers for electroless Co and Ni deposition solutions.

Display device and manufacturing method of the same

Tue, 10 Nov 2009 08:00:00 EST

A plurality of wires and electrodes are formed by forming a first conductive film, selectively forming a resist over the first conductive film, forming a second conductive film over the first conductive film and the resist, removing the second conductive film formed over the resist by removing the resist, forming a third conductive film so as to cover the second conductive film formed over the first conductive film, and selectively etching the first conductive film and the third conductive film. Thus, wires using a low resistance material can be formed in a large-sized panel, and thus, a problem of signal delay can be solved.

Light-emitting device, method of manufacturing the same, and display unit

Tue, 10 Nov 2009 08:00:00 EST

Light-emitting devices capable of preventing separation or alteration of a first electrode to obtain high performance, methods of manufacturing the light-emitting device, and display units are provided. A first electrode as an anode, an insulating film, an organic layer including a light-emitting layer, and a second electrode as a cathode are laminated in this order on a substrate with a planarizing layer as a base layer in between. The first electrode has a structure in which an adhesive layer, a reflective layer and a barrier layer is laminated in this order from the substrate. Alteration of the reflective layer can be prevented by the barrier layer, and the reflective layer can be prevented from being separated from the planarizing layer by the adhesive layer. The first electrode is formed through forming the adhesive layer, the reflective layer and the barrier layer on the planarizing layer, and then patterning them in order from the barrier layer.

Method for forming a semiconductor structure and structure thereof

Tue, 10 Nov 2009 08:00:00 EST

Forming a semiconductor structure includes providing a substrate having a strained semiconductor layer overlying an insulating layer, providing a first device region for forming a first plurality of devices having a first conductivity type, providing a second device region for forming a second plurality of devices having a second conductivity type, and thickening the strained semiconductor layer in the second device region so that the strained semiconductor layer in the second device region has less strain that the strained semiconductor layer in the first device region. Alternatively, forming a semiconductor structure includes providing a first region having a first conductivity type, forming an insulating layer overlying at least an active area of the first region, anisotropically etching the insulating layer, and after anisotropically etching the insulating layer, deposing a gate electrode material overlying at least a portion of the insulating layer.

Transistors with multilayered dielectric films

Tue, 10 Nov 2009 08:00:00 EST

Transistors that include multilayered dielectric films on a channel region are provided. The multilayered dielectric comprises a lower dielectric film that may have a thickness that is at least 50% the thickness of the multilayered dielectric film and that comprises a metal oxide, a metal silicate, an aluminate, or a mixture thereof, and an upper dielectric film on the lower dielectric film, the upper dielectric film comprising a Group III metal oxide, Group III metal nitride, Group XIII metal oxide or Group XIII metal nitride. A gate electrode is provided on the multilayered dielectric film.

Standoff height improvement for bumping technology using solder resist

Tue, 10 Nov 2009 08:00:00 EST

A system to support a die includes a substrate. A solder resist is disposed over the substrate. A first solder bump is disposed in the solder resist to provide electrical connectivity through the solder resist to the substrate. A second solder bump is formed over the solder resist to correspond with a peripheral edge or a corner of the die. The second solder bump provides standoff height physical support to the die.

Semiconductor device

Tue, 10 Nov 2009 08:00:00 EST

A semiconductor device comprises: a package substrate having a plurality of bonding electrodes arranged in a peripheral region of a main surface thereof and wirings connected to the respective bonding electrodes and electrolessly plated; a semiconductor chip mounted on the package substrate; a plurality of wires connecting pads of the semiconductor chip and the bonding electrodes; a sealing body for sealing the semiconductor chip and the wires with resin; and a plurality of solder balls arranged on the package substrate. The wirings are formed only at the inner side of the plurality of bonding electrodes on the main surface of the package substrate, and no solder resist film is formed at the outer side of the plurality of bonding electrodes. With this arrangement, the region outside the bonding electrodes can be minimized and the semiconductor device can be downsized without changing the size of the chip mounted thereon.

Exposure apparatus and method

Tue, 10 Nov 2009 08:00:00 EST

An exposure apparatus including a projection optical system for projecting a pattern of a reticle onto a plate to be exposed, via a liquid that is filled in a space between the projection optical system and the plate, a supply pipe for supplying the liquid to the space between a final surface in the projection optical system and the plate, a recovery pipe for recovering the liquid from the space between the final surface in the projection optical system and the plate, and a measuring apparatus for measuring a refractive index of the liquid. The measuring apparatus includes (i) a cell for accommodating the liquid and transmitting light, wherein the cell is connected to one of the supply pipe and the recovery pipe, and (ii) a detector for detecting an incident position of the light refracted by the liquid in the cell.

Light emitting diode and method of making the same

Tue, 10 Nov 2009 08:00:00 EST

A light emitting diode (LED) and a method of making the same are disclosed. The present invention uses a metal layer of high conductivity and high reflectivity to prevent the substrate from absorbing the light emitted. This invention also uses the bonding technology of dielectric material thin film to replace the substrate of epitaxial growth with high thermal conductivity substrate to enhance the heat dissipation of the chip, thereby increasing the performance stability of the LED, and making the LED applicable under higher current.

Fabrication method of complementary metal oxide semiconductor image sensor

Tue, 10 Nov 2009 08:00:00 EST

A fabrication method of a CMOS image sensor including a light-receiving element, at least one transistor, a first dielectric layer, a reflective layer, a second dielectric layer, a protective layer, a material layer, a transparent material layer, an optical filter, and a converging element is provided. The light-receiving element and the transistor are disposed respectively inside the light sensing region and the transistor region. The first dielectric layer is disposed on the substrate, covering the transistor and the light-receiving element. The reflective layer is disposed on the first dielectric layer inside the light sensing region. The second dielectric layer is disposed on the first dielectric layer outside the reflective layer. The material layer is disposed on the first dielectric layer inside the reflective layer. The optical filter is disposed on the transparent material layer. The converging element is disposed on the optical filter inside the light sensing region.

Transfer method with a treatment of a surface to be bonded

Tue, 10 Nov 2009 08:00:00 EST

A method for minimizing or avoiding contamination of a receiving handle wafer during transfer of a thin layer from a donor wafer. This method includes one step of providing a donor wafer and a receiving handle wafer, each having a first surface prepared for bonding and a second surface, with the donor layer including a zone of weakness that defines a thin layer of donor wafer material to be transferred to the receiving handle wafer. Next, at least one of the first surfaces is treated to provide increased bonding energy when the first surfaces are bonded together; the surfaces are then bonded together to form an intermediate multilayer structure; and the thin layer is transferred to the receiving handle wafer to form a final multilayer structure by detachment at the zone of weakness and removal of remaining material of the donor wafer. This method avoids or minimizes contamination of the second surface of the receiving handle wafer by treating only the first bonding surface of the donor wafer prior to bonding, or by cleaning contamination from the second surface of the handle receiving wafer when present in the intermediate multilayer structure prior to detachment of the thin layer.

Methods for making substrates and substrates formed therefrom

Tue, 10 Nov 2009 08:00:00 EST

A method for making substrates for use in optics, electronics, or opto-electronics. The method may include transferring a seed layer onto a receiving support and depositing a useful layer onto the seed layer. The thermal expansion coefficient of the receiving support may be identical to or slightly larger than the thermal expansion coefficient of the useful layer and the thermal expansion coefficient of the seed layer may be substantially equal to the thermal expansion coefficient of the receiving support. Preferably, the nucleation layer and the intermediate support have substantially the same chemical composition.

Semiconductor wafer and semiconductor device, and method for manufacturing same

Tue, 10 Nov 2009 08:00:00 EST

There is a room for improvement in conventional semiconductor devices in terms of reducing the chip area. A semiconductor device 1 comprises an evaluation transistor 10 (first characteristic evaluation device), an evaluation transistor (second characteristic evaluation device), measurement pads 30 (first measurement pads) and measurement pads 40 (second measurement pads). The measurement pad 30 and the measurement pad 40 are provided in different layers in the interconnect layer.

Semiconductor structure comprising a highly doped conductive channel region and method for producing a semiconductor structure

Tue, 10 Nov 2009 08:00:00 EST

The invention relates to a semiconductor structure for controlling a current (I), comprising a first n-conductive semiconductor region ( 2 ), a current path that runs within the first semiconductor region ( 2 ) and a channel region ( 22 ). The channel region ( 22 ) forms part of the first semiconductor region ( 2 ) and comprises a base doping. The current (I) in the channel region ( 22 ) can be influenced by means of at least one depletion zone ( 23, 24 ). The channel region ( 22 ) contains an n-conductive channel region ( 225 ) for conducting the current, said latter region having a higher level of doping than the base doping. The conductive channel region ( 225 ) is produced by ionic implantation in an epitaxial layer ( 262 ) that surrounds the channel region ( 22 ).

SOI substrate and method of manufacturing the same

Tue, 10 Nov 2009 08:00:00 EST

The SOI substrate includes a supporting substrate, an insulating layer (first insulating layer), another insulating layer (second insulating layer), and a silicon layer (silicon active layer). On a surface of the supporting substrate, which is the surface on the side of the silicon layer, the first insulating layer is provided. On a surface of the silicon layer, which is the surface on the side of the supporting substrate, the second insulating layer is provided. The supporting substrate and the silicon layer are adhered to each other, so that the interface between the first and the second insulating layers constitutes an adhesion plane. The adhesion plane performs as a gettering site in the SOI substrate.

CMOS devices adapted to prevent latchup and methods of manufacturing the same

Tue, 10 Nov 2009 08:00:00 EST

In a first aspect, a first apparatus is provided. The first apparatus is a semiconductor device on a substrate that includes (1) a first metal-oxide-semiconductor field-effect transistor (MOSFET); (2) a second MOSFET coupled to the first MOSFET, wherein portions of the first and second MOSFETs form first and second bipolar junction transistors (BJTs) which are coupled into a loop; and (3) a conductive region that electrically couples a source diffusion region of the first or second MOSFET with a doped well region below the source diffusion region. The conductive region is adapted to prevent an induced current from forming in the loop. Numerous other aspects are provided.

Capacitive micromachined ultrasonic transducer(CMUT) with varying thickness membrane

Tue, 10 Nov 2009 08:00:00 EST

Structure for capacitive micromachined ultrasonic transducer (CMUT) device or other vibrating membrane device having non-uniform membrane so that membrane mass and stiffness characteristics may be substantially independently adjusted. CMUT having trenched membrane and/or membrane with non-uniform thickness or density. Method for operating transducer or vibrating membrane device. Array of devices at least some of which have non-uniform membrane properties. CMUT comprising substrate, support for membrane, and membrane extending over support to create cavity, membrane having non-uniform membrane thickness resulting from at least one of: thickening on upper surface of the membrane outside of cavity, thickening on lower surface of membrane inside cavity, trench on upper surface of membrane, trench on lower surface of the membrane, and any combination of two or more of these. Method for fabricating CMUT or vibrating membrane device having non-uniform membrane. High mechanical sensitivity transducer for sensor, microphone, and/or transmitter.

Vertical memory device and method

Tue, 10 Nov 2009 08:00:00 EST

Method and apparatus are described for a memory cell includes a substrate, a body extending vertically from the substrate, a first gate having a vertical member and a horizontal member and a second gate comprising a vertical member and a horizontal member. The first gate is disposed laterally from the body and the second gate is disposed laterally from the first gate. The horizontal member of the first gate overlaps the horizontal member of the second gate.

Method of forming finFET device

Tue, 10 Nov 2009 08:00:00 EST

The invention discloses a method of forming a finFET device. A hard mask layer is formed on an active area of a semiconductor substrate. A portion of the hard mask layer is etched to form a recess. A conformal gate defining layer is deposited on the recess and a tilt angle ion implantation process is performed. A part of the gate defining layer is removed to define a fin pattern. The fin pattern is subsequently transferred to the hard mask layer. The patterned hard mask layer having the fin pattern is utilized as an etching mask, and the semiconductor substrate is etched to form a fin structure.

Method for manufacturing SOI substrate

Tue, 10 Nov 2009 08:00:00 EST

A method for manufacturing an SOI substrate superior in film thickness uniformity and resistivity uniformity in a substrate surface of a silicon layer having a film thickness reduced by an etch-back method is provided. After B ions is implanted into a front surface of a single-crystal Si substrate 10 to form a high-concentration boron added p layer 11 having a depth L in the outermost front surface, the single-crystal Si substrate 10 is appressed against a quartz substrate 20 to be bonded at a room temperature. Chemical etching is performed with respect to the single-crystal Si substrate 10 from a back surface thereof to set its thickness to L or below. A heat treatment is carried out with respect to an SOI substrate in a hydrogen containing atmosphere to outwardly diffuse B from the high-concentration boron added p layer 11 , thereby acquiring a boron added p layer 12 having a desired resistance value. During this heat treatment, B in an Si crystal is diffused to the outside of the crystal in a state where it is coupled with hydrogen in the atmosphere, and a B concentration in the high-concentration boron added p layer 11 is reduced. In regard to a heat treatment temperature at this time, in view of a softening point of the insulative substrate, an upper limit of the heat treatment temperature is set to 1250° C., and 700° C. is selected as a lower limit of the temperature at which B can be diffused.

Light emitting diode having an electrode buffer layer

Tue, 10 Nov 2009 08:00:00 EST

A light emitting diode (LED) utilizes an adhesive layer to adhere a light emitting layer to a substrate. The LED further comprises an electrode buffer layer to enhance the adhesion between the electrode and the light emitting diode, and thus to improve the yield rate of the LED.

PMOS transistor with discontinuous CESL and method of fabrication

Tue, 10 Nov 2009 08:00:00 EST

A transistor having a discontinuous contact etch stop layer comprising: a substrate having a surface, a gate dielectric on said surface of said substrate, a gate electrode on said gate dielectric, a spacer along a sidewall of said gate dielectric and gate electrode, a source and a drain formed on opposite sides, respectively, of said gate dielectric and said gate electrode, the source and drain defining a channel region having a channel length extending substantially from said source to said drain, in the substrate therebetween, and a contact etch stop layer on said gate and said spacers, and said source and drain. The contact etch stop layer is substantially locally continuous in a direction perpendicular to the channel region length and substantially locally discontinuous in a direction parallel to the channel region length.

Method for forming a capacitor structure

Tue, 10 Nov 2009 08:00:00 EST

A method for forming a capacitor structure, according to which the following consecutive steps are executed: providing a substrate having on its surface contact pads and a dielectric mold provided with at least one trench leaving exposed the contact pads; forming a first conductive layer on side walls of the trench in a top region of the trench the conductive layer being without contact to the contact pads; depositing a first dielectric layer; depositing a second conductive layer on the contact pad and on the side walls of the trench; depositing a second dielectric layer; depositing a third conductive layer; and forming a vertical plug interconnecting the first conductive layer and the third conductive layer.

Method for manufacturing SOI wafer

Tue, 10 Nov 2009 08:00:00 EST

This method for manufacturing an SOI wafer includes: a step of subjecting a mirror-polished active layer wafer to a rapid thermal annealing treatment; a step of forming insulating films in a front surface and a rear surface of the active layer wafer; a step of bonding the active layer wafer and a support wafer with the insulating film therebetween so as to form a bonded wafer; a step of loading the bonded wafer on a wafer boat in a state such that a portion of the active layer wafer is in contact with the wafer boat, and then subjecting the bonded wafer to a heat treatment for bonding enhancement which enhances a bonding strength between the active layer wafer and the support wafer in the bonded wafer; and a step of thinning a portion of the active layer wafer.

Method for producing a tensioned layer on a substrate, and a layer structure

Tue, 10 Nov 2009 08:00:00 EST

The invention relates to a method for producing a tensioned layer on a substrate involving the following steps: producing a defect area in a layer adjacent to the layer to be tensioned, and; relaxing at least one layer adjacent to the layer to be tensioned. Additional layers can be epitaxially deposited. Layer structures formed in this manner are advantageously suited for components of all types.

Method of manufacturing multilevel interconnect structure and multilevel interconnect structure

Tue, 10 Nov 2009 08:00:00 EST

A method of manufacturing a multilevel interconnect structure using a screen printing method is disclosed. In the multilevel interconnect structure, an interlayer insulating film having a through hole with a conductive bump therein, and a second interconnect line are stacked on a substrate with a first interconnect line formed thereon. The first interconnect line is electrically connected to the second interconnect line via the conductive bump. The method includes a step of forming a first region of the interlayer insulating film on the substrate with the first interconnect line formed thereon, the first region including a part of a peripheral wall of the through hole; a step of forming a second region of the interlayer insulating film on the substrate with the first region formed thereon, the second region including a remaining part of the peripheral wall of the through hole; and a step of forming the conductive bump.

Multiple digital printing techniques for fabricating printed circuits

Tue, 10 Nov 2009 08:00:00 EST

Methods of fabricating a printed circuit and printed circuits, including a method comprising: (a) depositing a conductive material to form a first conductive pathway upon a substrate; (b) depositing a dielectric material directly over at least a first portion of the conductive pathway utilizing an electrophotographic process; and (c) depositing a conductive material over at least a portion of the dielectric material to form a second conductive pathway, where the second conductive pathway is in electrical communication with the first conductive pathway.

Semiconductor light-emitting device and manufacturing method thereof

Tue, 10 Nov 2009 08:00:00 EST

A semiconductor light-emitting device comprises a substrate; and an active layer formed over the substrate comprising a well layer having an unintentionally-doped impurities; a first barrier layer; and a second barrier layer, wherein the well layer is disposed between the first barrier layer and the second barrier layer, the first barrier layer comprises an n-type-impurities-intentionally-doped portion near to the well layer, and an n-type-impurities-unintentionally-doped portion distant from the well layer; the second barrier layer comprises an n-type-impurities-unintentionally-doped portion near to the well layer.

Junction field effect transistor and method of manufacturing the same

Tue, 10 Nov 2009 08:00:00 EST

According to a junction FET of the present invention, the depth of a channel region is made shallow by selectively performing ion implantation and diffusion. Since the channel region forms a pn junction together with a p type semiconductor layer with relatively low impurity concentration, the improvement in the high frequency characteristic and the reduction in the amount of the leakage current because of the reduction in a junction capacitance can be achieved. Moreover, the depth of a gate region is also made shallow by ion implantation, and thus the reduction in noise because of the reduction in the internal resistance can be achieved.

Inductor integrated chip

Tue, 10 Nov 2009 08:00:00 EST

An inductor integrated chip and fabrication method thereof is provided. The inductor integrated chip includes a wafer; an inductor bonded on a surface of the wafer; a circuit element formed on the surface of the wafer and coupled to a first end of the inductor; a packaging wafer connected to the surface of the wafer and packaging the inductor and the circuit element; and a connecting electrode formed on the packaging wafer and connected to a second end of the inductor. The method includes forming an inductor and a circuit element on a surface of a wafer, wherein the circuit element is coupled to a first end of the inductor; forming a connecting electrode on a packaging wafer; and packaging the inductor and the circuit element by joining the wafer and the packaging wafer so as to connect the connecting electrode with a second end of the inductor.

Integrated antenna type circuit apparatus

Tue, 10 Nov 2009 08:00:00 EST

An integrated antenna type circuit apparatus which provides excellent circuit characteristics while suppressing an increase in packaging area. The integrated antenna type circuit apparatus includes an insulating base, a semiconductor circuit device, chip parts, a molding resin, an antenna conductor, a ground conductor, and external lead electrodes. The plurality of chip parts are mounted on the insulating base, and are soldered to electrodes of wiring conductors on the top of the insulating base for electric and physical connection. The insulating base has a multilayer structure, being formed by laminating a plurality of insulator layers. The antenna conductor is formed on the bottom of the insulating base. A wiring conductor adjacent to the antenna conductor is provided with the ground conductor so that it overlaps with the antenna conductor.

Heat dissipating package structure and method for fabricating the same

Tue, 10 Nov 2009 08:00:00 EST

A heat dissipating package structure includes a chip carrier; a semiconductor chip mounted and electrically connected to the chip carrier; a heat spreader having a first surface, an opposed second surface and a hollow structure, the second surface of the heat spreader being mounted on the chip, wherein the chip is larger in size than the hollow structure such that the chip is partly exposed to the hollow structure; an encapsulant formed between the heat spreader and the chip carrier, for encapsulating the chip, wherein the first surface and sides of the heat spreader are exposed from the encapsulant to dissipate heat produced from the chip; and a plurality of conductive elements disposed on the chip carrier, for electrically connecting the chip to an external device. The present invention also provides a method for fabricating the heat dissipating package structure.

Methods of post-contact back end of the line through-hole via integration

Tue, 10 Nov 2009 08:00:00 EST

Presented are methods of fabricating three-dimensional integrated circuits that include post-contact back end of line through-hole via integration for the three-dimensional integrated circuits. In one embodiment, the method comprises forming metal plug contacts through a hard mask and a premetal dielectric to transistors in the semiconductor. The method also includes etching a hole for a through-hole via through the hard mask to the semiconductor using a patterned photoresist process, removing the patterned photoresist and using a hard mask process to etch the hole to an amount into the semiconductor. The method further includes depositing a dielectric liner to isolate the hole from the semiconductor, depositing a gapfill metal to fill the hole, and planarizing the surface of the substrate to the hard mask. Another aspect of the present invention includes three-dimensional integrated circuits fabricated according to methods of the present invention.

Method of manufacturing a magnetic slider head

Tue, 10 Nov 2009 08:00:00 EST

Embodiments of the invention relate to manufacturing method of a magnetic head slider which flies stably even with a reduced peripheral speed resulting from a trend toward a magnetic disk having a smaller diameter. According to one embodiment, a method of manufacturing a magnetic head slider comprises forming a leading side rail surface and a trailing side rail surface, a leading stepped bearing surface and a trailing stepped bearing surface, and a negative-pressure groove surface on an air bearing surface through etching, forming a first stepped surface on the leading side rail surface through sputtering, and forming a second stepped surface by forming a carbon layer on the first stepped surface through sputtering. The first stepped surface has a first height with respect to the leading side rail surface and the second stepped surface has a second height with respect to the first stepped surface.

Addition curing silicone composition capable of producing a cured product with excellent crack resistance

Tue, 10 Nov 2009 08:00:00 EST

Provided is a silicone composition, including: (A) an organopolysiloxane represented by an average composition formula R 1 n SiZ [(4−n)/2] (in which, R 1 represents a monovalent hydrocarbon group, an alkoxy group or a hydroxyl group, provided that from 5 to 50 mol % of all R 1 groups are alkenyl groups, and from 10 to 80 mol % of all R 1 groups are aryl groups, Z represents an oxygen atom or a bivalent hydrocarbon group, provided at least 80 mol % of all Z groups are oxygen atoms, and n is a number that satisfies 1=n<2), in which from 5 to 50 mol % of all silicon atoms exist within structures represented by an average formula: —SiR 2 2 —X—(SiR 2 2 O) 1 SiR 2 2 —X—SiR 2 2 O— (in which, R 2 represents a monovalent hydrocarbon group, provided that from 10 to 80 mol % of all R 2 groups are aryl groups, X represents an oxygen atom or a bivalent hydrocarbon group, and l represents an integer of 3 or greater), (B) an organohydrogenpolysiloxane having at least 2 SiH groups within each molecule, and (C) an addition reaction catalyst. The composition is capable of producing a cured product with a high degree of hardness and excellent crack resistance. The composition is useful as a sealing material and an adhesive.

High-contrast laser mark on substrate surfaces

Tue, 10 Nov 2009 08:00:00 EST

As part of a first configured laser operation, a smooth, more reflective marking area is formed at a surface of a substrate (e.g., integral heat spreader, or IHS). In a second configured laser operation, a mark is formed at the surface of the substrate within the marking area. The mark contrasts strongly with the reflective surface of the substrate in the marking area. As a result, the mark may be read with an optoelectronic imaging system with a higher rate of reliability than marks disposed at a substrate surface having a microtopographical profile with greater variation from a nominal surface plane. An IHS with a mark so disposed provides benefits when include as a portion of an integrated circuit package, which in turn provides benefits when included as a portion of an electronic system.

Method of fabricating a BGA package having decreased adhesion

Tue, 10 Nov 2009 08:00:00 EST

Ball Grid Array packages having decreased adhesion of the BGA pad to the laminate surface and methods for producing same are provided.

Quantum dot light emitting layer

Tue, 10 Nov 2009 08:00:00 EST

An inorganic light emitting layer having a plurality of light emitting cores, each core having a semiconductor material that emits light in response to recombination of holes and electrons, each such light emitting core defining a first bandgap; a plurality of semiconductor shells formed respectively about the light emitting cores to form core/shell quantum dots, each such semiconductor shell having a second bandgap wider than the first bandgap; and a semiconductor matrix connected to the semiconductor shells to provide a conductive path through the semiconductor matrix and to each such semiconductor shell and its corresponding light emitting core so as to permit the recombination of holes and electrons.

Versatile system for optimizing current gain in bipolar transistor structures

Tue, 10 Nov 2009 08:00:00 EST

Disclosed are apparatus and methods for designing electrical contact for a bipolar emitter structure. The area of an emitter structure ( 106, 306, 400, 404 ) and the required current density throughput of an electrical contact structure ( 108, 308, 402, 406 ) are determined. A required electrical contact area is determined based on the required current density, and the electrical contact structure is then designed to minimize the required electrical contact area with respect to the emitter structure area.

Magnetic self-assembly for integrated circuit packages

Tue, 10 Nov 2009 08:00:00 EST

An integrated circuit package may include a substrate and an integrated circuit. The substrate may include at least one region, and a first magnetic material associated with the at least one region. The integrated circuit may have a second magnetic material associated therewith. The second magnetic material may be attracted to the first magnetic material to coupled the integrated circuit to the at least one region of the substrate. The IC package may be utilized in an RFID tag of an RFID system. An associated method for assembling an integrated circuit to a substrate is also provided.

Lithography device for semiconductor circuit pattern generation

Tue, 10 Nov 2009 08:00:00 EST

General purpose methods for the fabrication of integrated circuits from flexible membranes formed of very thin low stress dielectric materials, such as silicon dioxide or silicon nitride, and semiconductor layers. Semiconductor devices are formed in a semiconductor layer of the membrane. The semiconductor membrane layer is initially formed from a substrate of standard thickness, and all but a thin surface layer of the substrate is then etched or polished away. In another version, the flexible membrane is used as support and electrical interconnect for conventional integrated circuit die bonded thereto, with the interconnect formed in multiple layers in the membrane. Multiple die can be connected to one such membrane, which is then packaged as a multi-chip module. Other applications are based on (circuit) membrane processing for bipolar and MOSFET transistor fabrication, low impedance conductor interconnecting fabrication, flat panel displays, maskless (direct write) lithography, and 3D IC fabrication.

Active shielding of conductors in MEMS devices

Tue, 10 Nov 2009 08:00:00 EST

An apparatus that reduces parasitic capacitance in a MEMS device includes a dielectric layer on the surface of a silicon-on-insulator (SOI) substrate, a conductor embedded in the substrate and disposed between the dielectric layer and a buried oxide layer, and surface conductors on the dielectric layer and coupled to ends of the embedded conductor. A boundary region surrounds the embedded conductor and separates an inner region and an outer region of substrate, providing a p-n junction between the boundary region and the outer region of SOI substrate which is reverse biased to electrically isolate the inner region from the outer region of SOI substrate. An amplifier has an input connected to one end of the embedded conductor and an output connected to the inner region of the substrate. The amplifier senses a voltage at the input and produces a voltage that approximates the voltage at the output.

Image capturing device

Tue, 10 Nov 2009 08:00:00 EST

An image capturing device is disclosed that includes a light receiving element having a light receiving surface, a plate-like transparent member provided on the light receiving surface of the light receiving element, and resin provided to at least the periphery of the plate-like transparent member. The plate-like transparent member includes a first principal plane positioned on the light receiving element side and a second principal plane opposite the first principal plane. The first principal plane is greater in area than the second principal plane.

Structure and method for porous SiCOH dielectric layers and adhesion promoting or etch stop layers having increased interfacial and mechanical strength

Tue, 10 Nov 2009 08:00:00 EST

Disclosed is a structure and method for forming a structure including a SiCOH layer having increased mechanical strength. The structure includes a substrate having a layer of dielectric or conductive material, a layer of oxide on the layer of dielectric or conductive material, the oxide layer having essentially no carbon, a graded transition layer on the oxide layer, the graded transition layer having essentially no carbon at the interface with the oxide layer and gradually increasing carbon towards a porous SiCOH layer, and a porous SiCOH (pSiCOH) layer on the graded transition layer, the porous pSiCOH layer having an homogeneous composition throughout the layer. The method includes a process wherein in the graded transition layer, there are no peaks in the carbon concentration and no dips in the oxygen concentration.

Method for precision assembly of integrated circuit chip packages

Tue, 10 Nov 2009 08:00:00 EST

An electronic dive and method of fabricating an electronic device. The method including placing a placement guide over a top surface of a module substrate, the placement guide having a guide opening, the guide opening extending from a top surface of the placement guide to a bottom surface of the placement guide; aligning the placement guide to an integrated circuit chip position on the module substrate; fixing the placement guide to the module substrate; placing an integrated circuit chip in the guide opening, sidewalls of the placement guide opening constraining electrically conductive bonding structures on bottom surface of the integrated circuit chip to self-align to an electrically conductive module substrate contact pad on the top surface of the module substrate in the integrated circuit chip position; and bonding the bonding structures to the module substrate contact pads, the bonding structures and the module substrate contact pads in direct physical and electrical contact after the bonding.

Monomer solution for producing polycarbonate

Tue, 10 Nov 2009 08:00:00 EST

A non-reactive monomer mixture contains a monomer component and a diaryl carbonate dispersed in the mixture. The monomer component includes one or more monomer compounds having a melting point below the melting point of the diaryl carbonate. The monomer component has less than 600 ppb alkali metal, an acid stabilizer, or both less than 600 ppb alkali metal and an acid stabilizer. The monomer compounds of the monomer component and the diaryl carbonate are present in a mole ratio of from 0.9 to 1.1. The monomer mixture is at a temperature between the melting temperature of the lowest melting monomer compound and less than 5° C. above the melting point of the diaryl carbonate.

Thin film transistor substrate and liquid crystal display panel having sub-pixels

Tue, 10 Nov 2009 08:00:00 EST

The present invention relates to a thin film transistor substrate and a liquid crystal display panel for use in a liquid crystal display apparatus, and aims to provide a thin film transistor substrate and a liquid crystal display panel with good display quality. The thin film transistor substrate has a first sub-pixel electrode 16 and second sub-pixel electrode 17 arranged on the opposite sides of the gate bus line 12 , a first thin film transistor 20 a that establishes direct electrical connection with the first sub-pixel electrode 16 , and a second thin film transistor 20 b capacitively coupled to the second sub-pixel electrode 17 . Since capacitance is formed where conventionally a source electrode and pixel electrode are connected via a contact hole, excessively opaque wiring is not required, which ensures sufficient effective area and transmittance of a pixel.

Methods of fabricating nanoscale-to-microscale structures

Tue, 10 Nov 2009 08:00:00 EST

Methods for the production of shaped nanoscale-to-microscale structures, wherein a nanoscale-to-microscale template is provided having an original chemical composition and an original shape, and the nanoscale-to-microscale template subjected to a chemical reaction, so as to partially or completely convert the nanoscale-to-microscale template into the shaped nanoscale-to-microscale structure having a chemical composition different than the original chemical composition and having substantially the same shape as the original shape, being a scaled version of the original shape. The shaped nanoscale-to-microscale structure formed comprises an element (such as silicon), a metallic alloy (such as a silicon alloy), or a non-oxide compound (such as silicon carbide or silicon nitride).