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<title>freepatentsonline.com: Electrical computers and digital processing systems: processing architectures and instruction processing (e.g., processors)</title>
<link>http://www.freepatentsonline.com/result.html?query_txt=ccl/712%20and%20isd/11/10/2009&amp;uspat=on</link>
<description>USPTO Class 712 Electrical computers and digital processing systems: processing architectures and instruction processing (e.g., processors)</description>
<language>en-us</language>
<lastBuildDate>Thu, 12 Nov 2009 03:32:06 EST</lastBuildDate>

<item>
<title><![CDATA[Method and apparatus for measuring pipeline stalls in a microprocessor]]></title>
<link>http://www.freepatentsonline.com/7617385.html</link>
<description><![CDATA[A computer implemented method, apparatus, and computer program product for monitoring execution of instructions in an instruction pipeline. The process identifies a number of stall cycles for a group of instructions to complete execution. The process retrieves a deterministic latency pattern corresponding to the group of instructions. The process compares the number of stall cycles to the deterministic execution latency pattern. The process identifies the instruction as a dependent instruction in response to a determination that an instruction in the group of instructions completed a deterministic number of cycles after an antecedent instruction completed.]]></description>
<pubDate>Tue, 10 Nov 2009 08:00:00 EST</pubDate>
</item>

<item>
<title><![CDATA[Methods and system for resolving simultaneous predicted branch instructions]]></title>
<link>http://www.freepatentsonline.com/7617387.html</link>
<description><![CDATA[A method of resolving simultaneous branch predictions prior to validation of the predicted branch instruction is disclosed. The method includes processing two or more predicted branch instructions, with each predicted branch instruction having a predicted state and a corrected state. The method further includes selecting one of the corrected states. Should one of the predicted branch instructions be mispredicted, the selected corrected state is used to direct future instruction fetches.]]></description>
<pubDate>Tue, 10 Nov 2009 08:00:00 EST</pubDate>
</item>

<item>
<title><![CDATA[Virtual instruction expansion using parameter selector defining logic operation on parameters for template opcode substitution]]></title>
<link>http://www.freepatentsonline.com/7617388.html</link>
<description><![CDATA[An extendable instruction set architecture is provided. In an embodiment, a microprocessor includes a memory, a virtual instruction expansion store, and substitution logic. The memory stores at least one virtual instruction that includes an index and at least one parameter. The virtual instruction expansion store includes at least one instruction template and at least one parameter selector. The substitution logic forms a sequence of at least one expanded instruction. In an example, each expanded instruction is based on an instruction template and includes a new parameter for use with the instruction template. The new parameter is generated by performing a logical operation from the parameter selector on one or more parameter of the virtual instruction.]]></description>
<pubDate>Tue, 10 Nov 2009 08:00:00 EST</pubDate>
</item>

<item>
<title><![CDATA[Circular register arrays of a computer]]></title>
<link>http://www.freepatentsonline.com/7617383.html</link>
<description><![CDATA[A stack processor comprises a data stack with a T register, an S register, and eight hardwired bottom registers which function in a circular repeating pattern. The stack processor also comprises a return stack containing an R register, and eight hardwired bottom registers which function in a circular repeating pattern. The circular register arrays described herein eliminate overflow and underflow stack conditions.]]></description>
<pubDate>Tue, 10 Nov 2009 08:00:00 EST</pubDate>
</item>

<item>
<title><![CDATA[Structured programming control flow using a disable mask in a SIMD architecture]]></title>
<link>http://www.freepatentsonline.com/7617384.html</link>
<description><![CDATA[One embodiment of a computing system configured to manage divergent threads in a SIMD thread group includes a stack configured to store state information for processing control instructions. A parallel processing unit is configured to perform the steps of determining if one or more threads diverge during execution of a conditional control instruction. Threads that exit a program are identified as idle by a disable mask. Other threads that are disabled may be enabled once the divergent threads reach an instruction that enables the disabled threads. Use of the disable mask allows for the use of conditional return and break instructions in a multithreaded SIMD architecture.]]></description>
<pubDate>Tue, 10 Nov 2009 08:00:00 EST</pubDate>
</item>

<item>
<title><![CDATA[Event notifying method, event notifying device and processor system permitting inconsistent state of a counter managing number of non-notified events]]></title>
<link>http://www.freepatentsonline.com/7617389.html</link>
<description><![CDATA[An event notifying method notifies one or a plurality of events from a device to a processor by queuing to a queue in a processor system having one or a plurality of processors. A number of non-notified events existing in the queue is managed by a counter unit, and an inconsistent state of the counter unit caused by differences in updating timings of the counter unit from the device and the processor is temporarily permitted.]]></description>
<pubDate>Tue, 10 Nov 2009 08:00:00 EST</pubDate>
</item>

<item>
<title><![CDATA[Macroscalar processor architecture]]></title>
<link>http://www.freepatentsonline.com/7617496.html</link>
<description><![CDATA[A macroscalar processor architecture is described herein. In one embodiment, a processor receives instructions of a program loop having a vector block and a sequence block intended to be executed after the vector block, where the processor includes multiple slices and each of the slices is capable of executing an instruction of an iteration of the program loop substantially in parallel. For each iteration of the program loop, the processor executes an instruction of the sequence block using one of the slices while executing instructions of the vector block using a remainder of the slices substantially in parallel. Other methods and apparatuses are also described.]]></description>
<pubDate>Tue, 10 Nov 2009 08:00:00 EST</pubDate>
</item>

<item>
<title><![CDATA[Scheduling thread upon ready signal set when port transfers data on trigger time activation]]></title>
<link>http://www.freepatentsonline.com/7617386.html</link>
<description><![CDATA[A processor has an interface portion and an interior environment. The interface portion comprises: at least one port arranged to receive a current time value; a first register associated with the port and arranged to store a trigger time value; and comparison logic configured to detect whether the current time value matches the trigger time value and, provided that said match is detected, to transfer data between the port and an external environment and alter a ready signal to indicate the transfer. The internal environment comprises: an execution unit for transferring data between the at least one port and the internal environment; and a thread scheduler for scheduling a plurality of threads for execution by the execution unit, each thread comprising a sequence of instructions. The scheduling includes scheduling one or more of said threads for execution in dependence on the ready signal.]]></description>
<pubDate>Tue, 10 Nov 2009 08:00:00 EST</pubDate>
</item>

<item>
<title><![CDATA[Process for running programs with selectable instruction length processors and corresponding processor system]]></title>
<link>http://www.freepatentsonline.com/7617494.html</link>
<description><![CDATA[The program to be executed is compiled by translating it into native instructions of the instruction-set architecture of the processor system, organizing the instructions deriving from the translation of the program into respective bundles in an order of successive bundles, each bundle grouping together instructions adapted to be executed in parallel by the processor system. The bundles of instructions are ordered into respective sub-bundles, said sub-bundles identifying a first set of instructions, which must be executed before the instructions belonging to the next bundle of said order, and a second set of instructions, which can be executed both before and in parallel with respect to the instructions belonging to said subsequent bundle of said order. There is defined a sequence of execution of the instructions in successive operating cycles of the processor system, assigning each sub-bundle to an operating cycle, thus preventing simultaneous assignment to the same operating cycle of two sub-bundles belonging to the first set of two successive bundles. The instructions of the sequence may be executed by the various processors of the system in conditions of binary compatibility.]]></description>
<pubDate>Tue, 10 Nov 2009 08:00:00 EST</pubDate>
</item>

<item>
<title><![CDATA[Data processing system, data processing method and program]]></title>
<link>http://www.freepatentsonline.com/7617334.html</link>
<description><![CDATA[In the host, an IP issues CCW, and a CH encodes the CCW and a CCW chain by the encode program to create a code including the description of controlling a conditional branch with the DKC and transmits the code to a PORT in the DKC. In the DKC, the PORT decodes the code by the decode program, and a CP sequentially processes each command obtained by the decoding and returns a return code representing the end state of the processing. The host receives the return code to recognize the end state of the processing.]]></description>
<pubDate>Tue, 10 Nov 2009 08:00:00 EST</pubDate>
</item>

<item>
<title><![CDATA[Interpage prologue to protect virtual address mappings]]></title>
<link>http://www.freepatentsonline.com/7617088.html</link>
<description><![CDATA[In a computer which translates instructions from a target instruction set to a host instruction set, a method for determining validity of a translation of a target instruction linked to an earlier translation including the steps of testing a memory address of a target instruction to be executed against a copy of the memory address of the target instruction from which a translation of the target instruction was made, executing the translation if the addresses compare, and generating an exception if the addresses do not compare.]]></description>
<pubDate>Tue, 10 Nov 2009 08:00:00 EST</pubDate>
</item>

<item>
<title><![CDATA[Method and apparatus for controlling heat generation in a multi-core processor]]></title>
<link>http://www.freepatentsonline.com/7617403.html</link>
<description><![CDATA[The disclosed methodology and apparatus may reduce heat generation in a multi-core processor. In one embodiment, a multi-core processor cycles selected processor cores off in a predetermined pattern across the processor die over time to reduce the average heat generation by the processor. The disclosed multi-core processor may reduce or avoid undesirable hot spots that impact processor life.]]></description>
<pubDate>Tue, 10 Nov 2009 08:00:00 EST</pubDate>
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