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<title>freepatentsonline.com: Error detection/correction and fault detection/recovery</title>
<link>http://www.freepatentsonline.com/result.html?query_txt=ccl/714%20and%20isd/11/10/2009&amp;uspat=on</link>
<description>USPTO Class 714 Error detection/correction and fault detection/recovery</description>
<language>en-us</language>
<lastBuildDate>Thu, 12 Nov 2009 03:32:07 EST</lastBuildDate>

<item>
<title><![CDATA[Cluster system and failover method for cluster system]]></title>
<link>http://www.freepatentsonline.com/7617411.html</link>
<description><![CDATA[Provided is a failover method for a cluster system for realizing smooth failover of the guest OS's, even when there are many guest OS's, while reducing consumption of computer resources of a server. Smooth failover is realized by preventing competition during failover even when the number of guest OS's is increased. In a cluster configuration in which a slave/master cluster program is operated in a guest OS/host OS, the master cluster program ( 510 ) collects and transmits heartbeats of the slave cluster program, thereby realizing failure monitoring through the certain amount of heartbeats without depending on the number of guest OS's. Further, when the master cluster program monitors failures of the slave cluster program of its own computer to find a normal operation of the guest OS, the amount of communication through heartbeats is reduced by eliminating the necessity of communication to a standby system slave cluster program.]]></description>
<pubDate>Tue, 10 Nov 2009 08:00:00 EST</pubDate>
</item>

<item>
<title><![CDATA[Apparatus and method for managing random-directional scratches on hard disk]]></title>
<link>http://www.freepatentsonline.com/7617419.html</link>
<description><![CDATA[An apparatus and method for managing random-directional scratches on a hard disk. The apparatus includes a scratch determination unit and an alleged defect setting unit. The scratch determination unit determines that predetermined sectors are affected by a single continuous scratch if the predetermined sectors are defective and a distance therebetween is not larger than the length of a single continuous scratch. The alleged defect setting unit sets sectors between the predetermined sectors and around each of the predetermined sectors as alleged defective sectors if the defective sectors are determined to be affected by the single continuous scratch.]]></description>
<pubDate>Tue, 10 Nov 2009 08:00:00 EST</pubDate>
</item>

<item>
<title><![CDATA[Method and apparatus for reporting failure conditions during transactional execution]]></title>
<link>http://www.freepatentsonline.com/7617421.html</link>
<description><![CDATA[One embodiment of the present invention provides a system that reports reasons for failure during transactional execution. During operation, the system transactionally executes a block of instructions in a program. If the transactional execution of the block of instructions completes successfully, the system commits changes made during the transactional execution, and resumes normal non-transactional execution of the program past the block of instructions. Otherwise, if transactional execution of the block of instructions fails, the system discards changes made during the transactional execution, and records failure information indicating why the transactional execution failed.]]></description>
<pubDate>Tue, 10 Nov 2009 08:00:00 EST</pubDate>
</item>

<item>
<title><![CDATA[Method, system, and program product for managing data decay]]></title>
<link>http://www.freepatentsonline.com/7617422.html</link>
<description><![CDATA[The present invention provides a method, system, and program product for managing data decay. Specifically, under the present invention, usage information describing how data should be accessed is obtained. Thereafter, resource information describing resources available for accessing the data is obtained. Then, a data decay potential of the data is computed based on the usage information and the resource information. When the data decay potential exceeds a predetermined threshold, an indicator such as a report, an alarm, an error message, or an event and be communicated, and a remediation action such as a format transformation, a software archiving, or an environment archiving can be initiated.]]></description>
<pubDate>Tue, 10 Nov 2009 08:00:00 EST</pubDate>
</item>

<item>
<title><![CDATA[Hierarchical design and layout optimizations for high throughput parallel LDPC decoders]]></title>
<link>http://www.freepatentsonline.com/7617432.html</link>
<description><![CDATA[High throughput parallel LDPC decoders are designed and implemented using hierarchical design and layout optimization. In a first level of hierarchy, the node processors are grouped on the LDPC decoder chip, physically co-locating the processing elements in a small area. In a second level of hierarchy, clusters, e.g., subsets, of the processing elements are grouped together and a pipeline stage including pipeline registers is introduced on the boundaries between clusters. Register to register path propagating signals are keep localized as much as possible. The switching fabric coupling the node processors with edge message memory is partitioned into separate switches. Each separate switch is split into combinational switching layers. Design hierarchies are created for each layer, localizing the area where the interconnect is dense and resulting in short interconnect paths thus limiting signal delays in routing.]]></description>
<pubDate>Tue, 10 Nov 2009 08:00:00 EST</pubDate>
</item>

<item>
<title><![CDATA[Implementation of LDPC (low density parity check) decoder by sweeping through sub-matrices]]></title>
<link>http://www.freepatentsonline.com/7617433.html</link>
<description><![CDATA[Implementation of LDPC (Low Density Parity Check) decoder by sweeping through sub-matrices. A novel approach is presented by which an LDPC coded signal is decoded processing the columns and rows of the individual sub-matrices of the low density parity check matrix corresponding to the LDPC code. The low density parity check matrix can partitioned into rows and columns according to each of the sub-matrices of it, and each of those sub-matrices also includes corresponding rows and columns. For example, when performing bit node processing, the same columns of at 1 or more sub-matrices can be processed together (e.g., all 1 st  columns in 1 or more sub-matrices, all 2 nd  columns in 1 or more sub-matrices, etc.). Analogously, when performing check node processing, the same rows of 1 or more sub-matrices can be processed together (e.g., all 1 st  rows in 1 or more sub-matrices, all 2 nd  rows in 1 or more sub-matrices, etc.).]]></description>
<pubDate>Tue, 10 Nov 2009 08:00:00 EST</pubDate>
</item>

<item>
<title><![CDATA[Adaptive error correction]]></title>
<link>http://www.freepatentsonline.com/7617434.html</link>
<description><![CDATA[A method for transferring and correcting communication data is provided. The communication data include data frames, wherein each data frame includes data packets logically arranged in a number of rows and columns. Each data frame also includes error correction packets associated with the data packets. The error correction packets are generated according to an error correction scheme based on the number of rows and columns. The data frames are transmitted and received. The error correction packets are processed to correct errors in the data packets. Information regarding the errors in the data packets is generated. This information is processed to alter at least one of the number of rows and the number of columns.]]></description>
<pubDate>Tue, 10 Nov 2009 08:00:00 EST</pubDate>
</item>

<item>
<title><![CDATA[Method, device, and system for forward channel error recovery in video sequence transmission over packet-based network]]></title>
<link>http://www.freepatentsonline.com/7617436.html</link>
<description><![CDATA[Accelerated video decoding makes use of FEC-repaired media packets that become available through FEC decoding later than their intended decoding time, so to re-establish the integrity of the prediction chain between predicted pictures. The decoder state may be stored at the time of reception of an erroneous packet or at the time of identification of a lost packet, and decoding continued. After FEC repair, the last known state of the decoder is restored after the lost/damaged packet(s) is (are) resurrected through FEC, and accelerated decoding accordingly is used. Cycles “reserved” for decoding of a sub-sequence may be utilized. By freezing the decoded frame at the begin of a sub-sequence and decoding coded pictures of the main sequence that are part of the previous FEC block the integrity of the main prediction chain may be established again. Alternatively, cycles from enhancement layer decoding may be used.]]></description>
<pubDate>Tue, 10 Nov 2009 08:00:00 EST</pubDate>
</item>

<item>
<title><![CDATA[Error correction device and method thereof]]></title>
<link>http://www.freepatentsonline.com/7617437.html</link>
<description><![CDATA[A device for error correction includes a memory control module to disable error processing for a memory location depending on the state of a status indicator. The status indicator can be set so that error processing is disabled when valid error correction and detection information for the memory location is not available, such as after a reset or power-on event. In addition, the memory control module can promote partial write requests to full write requests when error processing is disabled to ensure that valid error detection and correction data is calculated for the memory location. By disabling error processing until valid error detection and correction information is available, the number of unnecessary or invalid error processing operations is reduced, thereby conserving device resources.]]></description>
<pubDate>Tue, 10 Nov 2009 08:00:00 EST</pubDate>
</item>

<item>
<title><![CDATA[Method and apparatus for supporting checksum offload in partitioned data processing systems]]></title>
<link>http://www.freepatentsonline.com/7617438.html</link>
<description><![CDATA[A method, apparatus, and computer instructions for processing a data packet in an interpartition virtual network in the logical partitioned data processing system. A state of a first flag and a state of a second flag is identified in the data packet, in response to receiving the data packet at a first partition in the interpartition virtual network from a second partition in the interpartition virtual network in the logical partitioned data processing system. A checksum is selectively verified for the data packet based on the state of the first flag and the state of the second flag.]]></description>
<pubDate>Tue, 10 Nov 2009 08:00:00 EST</pubDate>
</item>

<item>
<title><![CDATA[Efficient construction of LDPC (Low Density Parity Check) codes with corresponding parity check matrix having CSI (Cyclic Shifted Identity) sub-matrices]]></title>
<link>http://www.freepatentsonline.com/7617442.html</link>
<description><![CDATA[Efficient construction of LDPC (Low Density Parity Check) codes with corresponding parity check matrix having CSI (Cyclic Shifted Identity) sub-matrices. These constructed LDPC codes can be implemented in multiple-input-multiple-output (MIMO) communication systems. One LDPC code construction approach uses CSI sub-matrix shift values whose shift values are checked instead of non-zero element positions within the parity check matrix (or its corresponding sub-matrices). When designing an LDPC code, this approach is efficient to find and avoid cycles (or loops) in the LDPC code's corresponding bipartite graph. Another approach involves GRS (Generalized Reed-Solomon) code based LDPC code construction. These LDPC codes can be implemented in a wide variety of communication devices, including those implemented in wireless communication systems that comply with the recommendation practices and standards being developed by the IEEE 802.11n Task Group (i.e., the Task Group that is working to develop a standard for 802.11 TGn (High Throughput)).]]></description>
<pubDate>Tue, 10 Nov 2009 08:00:00 EST</pubDate>
</item>

<item>
<title><![CDATA[System, method, and apparatus for firmware code-coverage in complex system on chip]]></title>
<link>http://www.freepatentsonline.com/7617416.html</link>
<description><![CDATA[Presented herein is a system, method, and apparatus for firmware code-coverage in complex system on chip. A circuit for analyzing code coverage of firmware by test inputs comprises an input and a memory. The input receives an address from a code address bus. The memory stores recorded addresses from the code address bus. The memory comprises a plurality of memory locations, each of the memory locations mapped to a particular one of a corresponding plurality of addresses associated with the firmware. The contents of the memory location associated with the address received from the code address bus being incremented responsive to receipt of the address.]]></description>
<pubDate>Tue, 10 Nov 2009 08:00:00 EST</pubDate>
</item>

<item>
<title><![CDATA[Hard-decision iteration decoding based on an error-correcting code with a low undetectable error probability]]></title>
<link>http://www.freepatentsonline.com/7617435.html</link>
<description><![CDATA[A decoding system decodes forward error correction (FEC) encoded data. Factor graph circuitry (such as trellis decoder circuitry) processes the FEC encoded data according to at least one factor graph. Order restoring circuitry (such as convolutional deinterleaver circuitry) is coupled to an output of the factor graph circuitry and restores ordering of symbols in the encoded data. Error detection and correction circuitry is coupled to an output of the order restoring circuitry and processes block-based error correcting codes to detect and correct errors in the FEC encoded data and to provide a hard-decision output to an output of the decoding system. Feedback circuitry (such as convolutional interleaver circuitry and symbol interleaver circuitry) is coupled to process the hard-decision output from the error correction and detection circuitry and to provide the processed hard-decision output to the factor graph circuitry.]]></description>
<pubDate>Tue, 10 Nov 2009 08:00:00 EST</pubDate>
</item>

<item>
<title><![CDATA[Algebraic construction of LDPC (Low Density Parity Check) codes with corresponding parity check matrix having CSI (Cyclic Shifted Identity) sub-matrices]]></title>
<link>http://www.freepatentsonline.com/7617439.html</link>
<description><![CDATA[Algebraic method to construct LDPC (Low Density Parity Check) codes with parity check matrix having CSI (Cyclic Shifted Identity) sub-matrices. A novel approach is presented by which identity sub-matrices undergo cyclic shifting, thereby generating CSI sub-matrices that are arranged forming a parity check matrix of an LDPC code. The parity check matrix of the LDPC code may correspond to a regular LDPC code, or the parity check matrix of the LDPC code may undergo further modification to transform it to that of an irregular LDPC code. The parity check matrix of the LDPC code may be partitioned into 2 sub-matrices such that one of these 2 sub-matrices is transformed to be a block dual diagonal matrix; the other of these 2 sub-matrices may be modified using a variety of means, including the density evolution approach, to ensure the desired bit and check degrees of the irregular LDPC code.]]></description>
<pubDate>Tue, 10 Nov 2009 08:00:00 EST</pubDate>
</item>

<item>
<title><![CDATA[Method for at-speed testing of memory interface using scan]]></title>
<link>http://www.freepatentsonline.com/7617425.html</link>
<description><![CDATA[A method and a circuit of testing of a memory interface associated with an embedded memory in a semiconductor circuit involves writing to two memory locations in succession; reading the two memory locations in succession in the same order in which the two memory locations were written; capturing output data from the memory interface; and analyzing captured output data to determine whether said captured output data corresponds to expected data.]]></description>
<pubDate>Tue, 10 Nov 2009 08:00:00 EST</pubDate>
</item>

<item>
<title><![CDATA[Safety timer crosscheck diagnostic in a dual-CPU safety system]]></title>
<link>http://www.freepatentsonline.com/7617412.html</link>
<description><![CDATA[A dual-processing unit with single clock source CPUs safety I/O module having a safety timer crosscheck diagnostic to enable each CPU to verify the accuracy of the clock source of the other CPU. The diagnostic works by having the first CPU act as a controlling CPU and the second CPU act as a monitoring CPU. Both CPUs are synchronized to begin one cycle of their respective safety functions at the same time. As part of the diagnostic, the controlling CPU is set to be interrupted after a pre-determined time period while the monitoring CPU is set to be interrupted slightly after that. When the controlling CPU is interrupted after the pre-determined time has passed as determined by that CPU's clock source, it sends a signal to the monitoring CPU which then verifies that the perceived time is within an expected range. To verify that the clock source of the monitoring CPU is accurate, the first CPU swaps roles to become the monitoring CPU while the second CPU becomes the controlling CPU. The CPUs are loaded again and execute one cycle of their respective safety functions. The first, now monitoring, CPU then ensures the accuracy of the clock source of the second, now controlling, CPU.]]></description>
<pubDate>Tue, 10 Nov 2009 08:00:00 EST</pubDate>
</item>

<item>
<title><![CDATA[Method of preventing erroneous take-over in a dual redundant server system]]></title>
<link>http://www.freepatentsonline.com/7617413.html</link>
<description><![CDATA[The present invention discloses a method for preventing erroneous take-over in a redundant server system, and the method is used for a server system having a primary server for continuously producing heartbeat packets and sending the heartbeat packets to a redundant server of the server system. If the redundant server has not received any heartbeat packet, a redundant external transmission unit of the redundant server will send a detecting signal to the primary server. If the redundant external transmission unit has not received an acknowledged signal from the primary server, the redundant server will take over the primary server to continue providing network services.]]></description>
<pubDate>Tue, 10 Nov 2009 08:00:00 EST</pubDate>
</item>

<item>
<title><![CDATA[System and method for restoring data on a data storage system]]></title>
<link>http://www.freepatentsonline.com/7617414.html</link>
<description><![CDATA[A backup computer storage system that protects and/or recovers data on a primary computer storage system is disclosed. The backup computer system may be used to backup databases, files, and/or applications. In some embodiments, the backup system may be used to backup an image of the primary computer system. In other embodiments, the backup system may be used to backup one or more databases. In some embodiments of the present invention, the backup system replicates an image of data that is on a primary computer system. The backup system may also be used to restore data from the backup system to the primary computer system. In some embodiments, the backup system may restore data to a database while non-affected portions of the database are available and can be used. In some embodiments, the backup system records all transactions in real time without overwriting any previously stored backup data. In some embodiments of the present invention, the backup system maintains historical and/or chronological information related to the backed up data.]]></description>
<pubDate>Tue, 10 Nov 2009 08:00:00 EST</pubDate>
</item>

<item>
<title><![CDATA[Trace analyzing apparatus, trace analyzing method, and processor]]></title>
<link>http://www.freepatentsonline.com/7617420.html</link>
<description><![CDATA[A trace analyzing apparatus, which includes a trace analysis table, an instruction reconstruction unit that reconstructs and sends an execution address and an instruction code of trace information, and an object code list storage unit, reads out an object code list and trace information, captures each piece of information in reverse order from the last stored address information stored in an address register, and then registers them in the trace analysis table.]]></description>
<pubDate>Tue, 10 Nov 2009 08:00:00 EST</pubDate>
</item>

<item>
<title><![CDATA[Error monitoring for serial links]]></title>
<link>http://www.freepatentsonline.com/7617424.html</link>
<description><![CDATA[Methods, apparatuses and systems for physical link error data capture and analysis.]]></description>
<pubDate>Tue, 10 Nov 2009 08:00:00 EST</pubDate>
</item>

<item>
<title><![CDATA[Method and apparatus for detecting defects in integrated circuit die from stimulation of statistical outlier signatures]]></title>
<link>http://www.freepatentsonline.com/7617427.html</link>
<description><![CDATA[A method and computer program for detecting and locating defects in integrated circuit die from stimulation of statistical outlier signatures includes receiving as input a test value of an electrical parameter measured for each of a plurality of identically designed electrical circuits, identifying one of the identically designed electrical circuits as an outlier for which the test value of the electrical parameter varies from a mean test value of the electrical parameter for the plurality of identically designed electrical circuits by at least a selected difference, monitoring the test value while subjecting a location on the outlier to a stimulus to detect a change in the test value as a function of the location, and generating as output the location for which the change in the test value is detected to identify a defect in the outlier.]]></description>
<pubDate>Tue, 10 Nov 2009 08:00:00 EST</pubDate>
</item>

<item>
<title><![CDATA[Automatable scan partitioning for low power using external control]]></title>
<link>http://www.freepatentsonline.com/7617429.html</link>
<description><![CDATA[Scan architectures are commonly used to test digital circuitry in integrated circuits. The present invention describes a method of adapting conventional scan architectures into a low power scan architecture. The low power scan architecture maintains the test time of conventional scan architectures, while requiring significantly less operational power than conventional scan architectures. The low power scan architecture is advantageous to IC/die manufacturers since it allows a larger number of circuits (such as DSP or CPU core circuits) embedded in an IC/die to be tested in parallel without consuming too much power within the IC/die. Since the low power scan architecture reduces test power consumption, it is possible to simultaneously test more die on a wafer than previously possible using conventional scan architectures. This allows wafer test times to be reduced which reduces the manufacturing cost of each die on the wafer.]]></description>
<pubDate>Tue, 10 Nov 2009 08:00:00 EST</pubDate>
</item>

<item>
<title><![CDATA[Local and global address compare with tap interface TDI/TDO lead]]></title>
<link>http://www.freepatentsonline.com/7617430.html</link>
<description><![CDATA[This disclosure describes a reduced pin bus that can be used on integrated circuits or embedded cores within integrated circuits. The bus may be used for serial access to circuits where the availability of pins on ICs or terminals on cores is limited. The bus may be used for a variety of serial communication operations such as, but not limited to, serial communication related test, emulation, debug, and/or trace operations of an IC or core design. Other aspects of the disclosure include the use of reduced pin buses for emulation, debug, and trace operations and for functional operations.]]></description>
<pubDate>Tue, 10 Nov 2009 08:00:00 EST</pubDate>
</item>

<item>
<title><![CDATA[Efficient construction of LDPC (Low Density Parity Check) codes with corresponding parity check matrix having CSI (Cyclic Shifted Identity) sub-matrices]]></title>
<link>http://www.freepatentsonline.com/7617441.html</link>
<description><![CDATA[Efficient construction of LDPC (Low Density Parity Check) codes with corresponding parity check matrix having CSI (Cyclic Shifted Identity) sub-matrices. These constructed LDPC codes can be implemented in multiple-input-multiple-output (MIMO) communication systems. One LDPC code construction approach uses CSI sub-matrix shift values whose shift values are checked instead of non-zero element positions within the parity check matrix (or its corresponding sub-matrices). When designing an LDPC code, this approach is efficient to find and avoid cycles (or loops) in the LDPC code's corresponding bipartite graph. Another approach involves GRS (Generalized Reed-Solomon) code based LDPC code construction. These LDPC codes can be implemented in a wide variety of communication devices, including those implemented in wireless communication systems that comply with the recommendation practices and standards being developed by the IEEE 802.11n Task Group (i.e., the Task Group that is working to develop a standard for 802.11 TGn (High Throughput)).]]></description>
<pubDate>Tue, 10 Nov 2009 08:00:00 EST</pubDate>
</item>

<item>
<title><![CDATA[Verification method and apparatus]]></title>
<link>http://www.freepatentsonline.com/7617426.html</link>
<description><![CDATA[A method for verifying whether a recording/reproducing apparatus properly produces disc management information and records the disc management information on a disc includes preparing a test disc; issuing reading commands to a recording/reproducing apparatus to be tested on which the test disc is loaded and verifying the disc in order to verify the reading operation; and issuing recording commands to the recording/reproducing apparatus to be tested on which the test disc is loaded and checking whether a temporary disc management area (TDMA) structure is properly updated on the disc in order to verify the modification operation.]]></description>
<pubDate>Tue, 10 Nov 2009 08:00:00 EST</pubDate>
</item>

<item>
<title><![CDATA[Circuits and associated methods for improved debug and test of an application integrated circuit]]></title>
<link>http://www.freepatentsonline.com/7617428.html</link>
<description><![CDATA[Circuits and associated methods for testing internal operation of an application integrated circuit. Features and aspects hereof add configurable test interrupt circuits to an application circuit design to permit dynamic, configurable interrupt generation from an integrated circuit based on conditions determined from monitoring of internal signals of the application circuit. The internal signals that may be tested and used to generate test interrupts are those not exposed to the external processor interface of the integrated circuit and thus may be configured to interrupt based on any internal state of the application specific functional circuits of the integrated circuit.]]></description>
<pubDate>Tue, 10 Nov 2009 08:00:00 EST</pubDate>
</item>

<item>
<title><![CDATA[Method and apparatus for analyzing delay defect]]></title>
<link>http://www.freepatentsonline.com/7617431.html</link>
<description><![CDATA[The apparatus for analyzing a delay defect of the present invention obtains the RC of the maximal incidence among region codes (RCs) to which check circuits detecting errors caused with gradual increase in the frequency of an operational clock pulse fed to an integrated circuit belongs. The apparatus obtains information on latch in which an error is caused with the RC of the maximal incidence, with reference to a mapping table that describes the mapping relationship between an RC and a latch. The apparatus extracts a circuit portion in which an error can be captured with the region code of the maximal incidence by exhaustively tracing back circuit portions connected with each obtained latch, from the latch to the latch described in the mapping table. The apparatus gives delay defects to the input and the output pin of each of logic elements included in the extracted circuit portion, generates test patterns for detecting the given delay defects, and performs delay tests.]]></description>
<pubDate>Tue, 10 Nov 2009 08:00:00 EST</pubDate>
</item>

<item>
<title><![CDATA[Method and system for reducing contexts for context based compression systems]]></title>
<link>http://www.freepatentsonline.com/7616132.html</link>
<description><![CDATA[For context based compression techniques, for example Context Based YK compression, a method and system for grouping contexts from a given context model together to create a new context model that has fewer contexts, but retains acceptable compression gains compared to the context model with more contexts is provided. According to an exemplary embodiment a set of files that are correlated to the file to be compressed (hereafter called training files) are read to determine, for an initial context model, the empirical statistics of contexts and symbols. In some embodiments, this includes determining the estimated joint and conditional probabilities of the various contexts and symbols (or blocks of symbols). The initial context model is then reduced to a desired number of contexts, for example, by applying a grouping function g to the original set of contexts to obtain a new and smaller set of contexts. In some embodiments the step of applying a grouping function comprises iteratively grouping a pair of contexts together to form a grouped context, wherein each grouped context represents a local minimum based on the empirical statistics.]]></description>
<pubDate>Tue, 10 Nov 2009 08:00:00 EST</pubDate>
</item>

<item>
<title><![CDATA[Reduction of the transport capacity of a virtual concatenation group]]></title>
<link>http://www.freepatentsonline.com/7616558.html</link>
<description><![CDATA[The transport capacity of a Virtual Concatenation Group (VCG) can be reduced under control of a Link Capacity Adjustment Scheme (LCAS). The VCG comprises link members, in which payload data are transmitted. A first control message comprising a fail message (R FAIL ) for a link member is transmitted from sink to source, while the sink continues reception of payload data. On reception of the first control message at the source, a second control message is transmitted comprising a message (F DNU ) indicating that payload data of the link member shall not be used, and transmission of payload data is discontinued. On reception of the second control message at the sink reception of payload data is discontinued, and the link member is removed. This allows a reduction of the transport capacity of a Virtual Concatenation Group to be performed in a hitless manner, even when initiated at the sink side.]]></description>
<pubDate>Tue, 10 Nov 2009 08:00:00 EST</pubDate>
</item>

<item>
<title><![CDATA[Wavefront detection and disambiguation of acknowledgments]]></title>
<link>http://www.freepatentsonline.com/7616638.html</link>
<description><![CDATA[One or more flow control modules, implemented on various types of network topologies, provide a number of functionalities for controlling the flow of IP packets (such as TCP/IP packets) over a network connection. The flow control modules may be implemented within a sender and/or receiver or may be deployed into a network as a separate device without requiring significant additional resources.]]></description>
<pubDate>Tue, 10 Nov 2009 08:00:00 EST</pubDate>
</item>

<item>
<title><![CDATA[System and method for forward and backward recursive computation]]></title>
<link>http://www.freepatentsonline.com/7616713.html</link>
<description><![CDATA[A system and method is provided for improved and efficient forward and backward recursive computations that may be used, for example, with turbo code decoding applications. The invention performs the forward computations using a full length of a sequence to be decoded and performs the reverse computations using a sliding window over the sequence.]]></description>
<pubDate>Tue, 10 Nov 2009 08:00:00 EST</pubDate>
</item>

<item>
<title><![CDATA[System and method for updating hard disk write parameters in the field]]></title>
<link>http://www.freepatentsonline.com/7617357.html</link>
<description><![CDATA[Systems and methods are provided for updating a temperature table for a disk subsystem in a client system using information provided by a server system. In one embodiment, among others, the client receives an update command from the server system. The update command comprises instructions to update the temperature table. The client updates the temperature table in the disk subsystem in accordance with the update command. The client selects one of the write current values in the temperature table based on a disk subsystem temperature, and writes data to the disk subsystem using the selected write current values.]]></description>
<pubDate>Tue, 10 Nov 2009 08:00:00 EST</pubDate>
</item>

<item>
<title><![CDATA[Method for reading input/output port data]]></title>
<link>http://www.freepatentsonline.com/7617417.html</link>
<description><![CDATA[A method for reading input/output port data is provided. In the present method, a write trap procedure is enabled so that the data is stored in a buffer first when there is data to be written in the input/output port. Then, a read trap procedure is enabled so that the data stored in the buffer is read out and used as the data of the input/output port when there is a need to read the data of the input/output port. Therefore, the defect in the prior art that the basic input/output system (BIOS) in a direct input/output mode can only be written in but cannot be read out is resolved.]]></description>
<pubDate>Tue, 10 Nov 2009 08:00:00 EST</pubDate>
</item>

<item>
<title><![CDATA[Method and system for verifying and storing documents during a program failure]]></title>
<link>http://www.freepatentsonline.com/7617418.html</link>
<description><![CDATA[Method and system for verifying and storing documents during a failure in a program module. Once a failure is detected in the program module, control passes to an exception handler that determines whether the open files have been modified. If so, a crash handler is executed, which verifies and stores the documents by detecting and repairing any discovered corruption. The program module is then terminated and restarted. Upon restarting the program module, the repaired document is opened and displayed to the user with a list of repairs.]]></description>
<pubDate>Tue, 10 Nov 2009 08:00:00 EST</pubDate>
</item>

<item>
<title><![CDATA[Viterbi traceback initial state index initialization for partial cascade processing]]></title>
<link>http://www.freepatentsonline.com/7617440.html</link>
<description><![CDATA[This invention provides the correct Viterbi decode traceback starting index is obtained for all constraint lengths and frame sizes. Reverse transpose operations that depend on the last active add-compare-select unit a cascade block of the state metric update process. This last active add-compare-select unit controls selection of T counter signals used in the decode.]]></description>
<pubDate>Tue, 10 Nov 2009 08:00:00 EST</pubDate>
</item>

<item>
<title><![CDATA[Soft errors handling in EEPROM devices]]></title>
<link>http://www.freepatentsonline.com/7616484.html</link>
<description><![CDATA[Soft errors occur during normal use of a solid-state memory such as EEPROM or Flash EEPROM. A soft error results from the programmed threshold voltage of a memory cell being drifted from its originally intended level. The error is initially not readily detected during normal read until the cumulative drift becomes so severe that it develops into a hard error. Data could be lost if enough of these hard errors swamps available error correction codes in the memory. A memory device and techniques therefor are capable of detecting these drifts and substantially maintaining the threshold voltage of each memory cell to its intended level throughout the use of the memory device, thereby resisting the development of soft errors into hard errors.]]></description>
<pubDate>Tue, 10 Nov 2009 08:00:00 EST</pubDate>
</item>

<item>
<title><![CDATA[Method and device for receiving data blocks]]></title>
<link>http://www.freepatentsonline.com/7616636.html</link>
<description><![CDATA[Data blocks to be received each comprise a header and a data field including respectively first and second codes for error detection. The decoding of a signal segment received having first and second portions corresponding respectively to the header and to the data field of a block gave rise to a verification of the first code in the first portion. If the first code is correct, a check is made to verify whether the second portion of the decoded signal has a second correct code. A data block is considered to be detected either in the presence of first and second correct codes, or in the presence only of a first correct code when a data likelihood criterion, evaluated during the decoding of the second portion of the signal, is fulfilled.]]></description>
<pubDate>Tue, 10 Nov 2009 08:00:00 EST</pubDate>
</item>

<item>
<title><![CDATA[Adaptive wireless parameter control method, QoS control device and wireless communication system]]></title>
<link>http://www.freepatentsonline.com/7616658.html</link>
<description><![CDATA[A QoS information identification unit receives a packet to be transmitted and based on QoS information, identifies the QoS type of the packet, and outputs the obtained QoS type to an adaptive wireless parameter controller as requested QoS information. The adaptive wireless parameter controller adaptively defines a retransmission parameter, an encoding scheme and a modulation scheme, based on the requested QoS information received from the QoS information identification unit, observed QoS information at the receiving side notified from the receiving side, and transmission path information. A transmission sequencing controller performs retransmission control for the packet based on the retransmission parameter defined therebefore. A data encoder encodes the packet based on the encoding scheme defined therebefore. A data modulator modulates the packet based on the modulation scheme defined therebefore.]]></description>
<pubDate>Tue, 10 Nov 2009 08:00:00 EST</pubDate>
</item>

<item>
<title><![CDATA[Monitoring simulating device, method, and program]]></title>
<link>http://www.freepatentsonline.com/7617086.html</link>
<description><![CDATA[A design data storage unit stores design data of constituent elements constituting a computer system to be monitored. A monitoring condition storage unit stores monitoring conditions of abnormal detection of the object to be monitored and error information to be outputted when the object meets particular monitoring conditions. A constituent component simulated failure setting unit causes the constituent elements in the design data to simulate failure one by one. A monitoring condition check unit checks if each monitoring condition is met when one constituent element is set in a failed state by instructing a network examining unit to examine the design data and extracts all the error information relevant to the met monitoring conditions. According to the results, information on the correspondence between the failed constituent elements and all extracted error information is stored in a monitoring simulation result storage unit.]]></description>
<pubDate>Tue, 10 Nov 2009 08:00:00 EST</pubDate>
</item>

<item>
<title><![CDATA[Code coverage quality estimator]]></title>
<link>http://www.freepatentsonline.com/7617415.html</link>
<description><![CDATA[A method for estimating a quality of code coverage of a test is described. The method includes training a neural network, using the neural network to generate a risk factor for each code element, and determining a coverage quality based on risk factors of executed code elements and risk factors of unexecuted code elements. The neural network is trained by inputting suggestive data as input and error severity data as output. Suggestive data may be data that correlates to a likelihood that a code element contains an error, and the error severity data is an evaluation of a severity of any error that was present in the code element. A coverage quality can be determined based on the risk factors of the code elements tested during the test and the risk factors of the code elements not tested during the test.]]></description>
<pubDate>Tue, 10 Nov 2009 08:00:00 EST</pubDate>
</item>

<item>
<title><![CDATA[System and method for detecting, reporting, and repairing of software defects for a wireless device]]></title>
<link>http://www.freepatentsonline.com/7617423.html</link>
<description><![CDATA[A system and method for detecting, reporting, and repairing software defects in a wireless device is disclosed. The system has a wireless subscriber unit for communicating to a support server. The wireless subscriber unit maintains an action file indicative of the historical operation of the wireless subscriber unit. When the wireless subscriber unit detects a local defect or error, the action list is transmitted to the support server. The action file is used by support staff to identify and fix the error, and to prepare a repaired software file. The repaired software file is received at the wireless subscriber unit, and the user is notified that the defect has been fixed. Also, the wireless subscriber unit may receive status updates from the central server to inform the user of repair progress.]]></description>
<pubDate>Tue, 10 Nov 2009 08:00:00 EST</pubDate>
</item>

<item>
<title><![CDATA[Suppressing repeated events and storing diagnostic information]]></title>
<link>http://www.freepatentsonline.com/7617074.html</link>
<description><![CDATA[Events that repeatedly occur during a detection period are intercepted and suppressed before being written to a log. When the same error has been detected a predetermined number of times within the detection period, the event logging for the event is suppressed for a suppression period. At the end of the suppression period an entry is made in the log summarizing the events during the suppression period. Additionally, diagnostic information relating to an application is collected and then stored within a high speed memory. Upon the occurrence of a triggering event, the diagnostic information from the high speed memory is stored within a data store for later use.]]></description>
<pubDate>Tue, 10 Nov 2009 08:00:00 EST</pubDate>
</item>

<item>
<title><![CDATA[Parity-scanning and refresh in dynamic memory devices]]></title>
<link>http://www.freepatentsonline.com/7617355.html</link>
<description><![CDATA[A method and apparatus that coordinates refresh and parity-scanning in DRAM-based devices such that parity-scan operations substitute for refresh operations when both operations are required in the system. The process of parity-scanning automatically refreshes the entries being scanned, subject to refresh and parity-scan interval requirements. As such, refresh and parity-scan operations may be performed in a single operation, which bolsters the scheduling and performance of the two operations.]]></description>
<pubDate>Tue, 10 Nov 2009 08:00:00 EST</pubDate>
</item>

<item>
<title><![CDATA[Method for automatic maximization of coverage in constrained stimulus driven simulation]]></title>
<link>http://www.freepatentsonline.com/7617468.html</link>
<description><![CDATA[A computer increases coverage in simulation of a design of a circuit by processing goals for coverage differently depending on whether or not the goals are on input signals of the circuit. Specifically, goals on input signals are used to automatically formulate constraints (“directly-derived constraints”) on values of input signals in test vectors. Goals on non-input signals (e.g. internal/output signals) are used with correlations to automatically formulate more additional constraints (“correlation-derived constraints”), by use of goals on non-input signals. The correlations indicate which non-input signals are associated with which input signals. The correlations are received from, for example, a human designer of the circuit. Depending on the embodiment, one or more of the automatically derived constraints are used with human-supplied constraints, to generate test vectors e.g. using a constraints solver, such as a satisfiability (SAT) engine. The test vectors are supplied to a simulator for functional verification.]]></description>
<pubDate>Tue, 10 Nov 2009 08:00:00 EST</pubDate>
</item>

<item>
<title><![CDATA[Method and system for debugging individual threads in a productive environment]]></title>
<link>http://www.freepatentsonline.com/7617487.html</link>
<description><![CDATA[A system and method to debug a thread without affecting other threads in a virtual machine. A virtual machine (VM) may execute a thread subject to debugging and another thread. An interface to the VM permits only debugging command that are specific to the thread subject to debugging to affect the VM.]]></description>
<pubDate>Tue, 10 Nov 2009 08:00:00 EST</pubDate>
</item>

<item>
<title><![CDATA[Method and apparatus for recording write-once type optical recording medium having defective management areas]]></title>
<link>http://www.freepatentsonline.com/7616541.html</link>
<description><![CDATA[A write-once-type recording medium ( 10 ) is provided with: a data area ( 11 ) to record therein record data; and a plurality of management areas in which a plurality of types of management information for managing the record data and index information for indicating newest management information can be recorded a plurality of times, each of the plurality of management areas having a setup area for recording therein a management information block including a plurality of types of management information constructed from the newest management information and the index information indicating the plurality of types of management information constructed from the newest management information.]]></description>
<pubDate>Tue, 10 Nov 2009 08:00:00 EST</pubDate>
</item>

<item>
<title><![CDATA[Method and apparatus for debugging protocol traffic between devices in integrated subsystems]]></title>
<link>http://www.freepatentsonline.com/7616631.html</link>
<description><![CDATA[A method, apparatus, and computer instructions for a storage subsystem. This subsystem includes controller devices, storage devices, and a communications network. The communications network connects the controller devices and the storage devices. The communications network also includes a set of diagnostic outputs. The set of diagnostic outputs is configured to output data sent between two devices from the controller devices and the storage devices for monitoring.]]></description>
<pubDate>Tue, 10 Nov 2009 08:00:00 EST</pubDate>
</item>

<item>
<title><![CDATA[Mechanism and method for simultaneous processing and debugging of multiple programming languages]]></title>
<link>http://www.freepatentsonline.com/7617084.html</link>
<description><![CDATA[Disclosed is a method, mechanism, and computer usable medium for simultaneous processing or debugging of multiple programming languages. A particularly disclosed approach provides a method and mechanism for resolving the issue of simultaneous debugging of hardware represented by an HDL, e.g., Verilog or VHDL, and software, e.g., represented by C, C++, SystemC code. This approach overcomes the problem of the HDL portion of the design being inaccessible when C, C++ or SystemC code is debugged.]]></description>
<pubDate>Tue, 10 Nov 2009 08:00:00 EST</pubDate>
</item>

<item>
<title><![CDATA[Method and mechanism for relational access of recovery logs in a database system]]></title>
<link>http://www.freepatentsonline.com/7617254.html</link>
<description><![CDATA[The present invention is directed to a method and mechanism for accessing recovery log information in a database system. The data stored in the recovery log is presented as a relational database “view,” which can be queried and accessed using relational database statements even though the underlying recovery log data may be stored in a non-relational format. According to an aspect of the invention, the recovery log data is thus encapsulated by the view presented to users of that data.]]></description>
<pubDate>Tue, 10 Nov 2009 08:00:00 EST</pubDate>
</item>

<item>
<title><![CDATA[System and method of double address detection]]></title>
<link>http://www.freepatentsonline.com/7617331.html</link>
<description><![CDATA[A plurality of detectors can be evaluated to determine if more than one has been assigned the same address. Responsive thereto, such detectors could be identified for follow-up maintenance, or service.]]></description>
<pubDate>Tue, 10 Nov 2009 08:00:00 EST</pubDate>
</item>

<item>
<title><![CDATA[Hard disk testing method under extensible firmware interface]]></title>
<link>http://www.freepatentsonline.com/7617374.html</link>
<description><![CDATA[A hard disk testing method under an extensible firmware interface (EFI) is provided, which includes the following steps. A system file is backed up from the EFI of the hard disk into a storage area of a memory. The backup area of the system file is mapped as a real hard disk. A non-system file storage area is established in the memory, so as to store the non-system files of a hard disk test. Information of the system and non-system files of the hard disk test is acquired, so as to generate a system and a non-system file link table. When performing the test, the non-system files are backed up into the non-system file storage area. The system file link table and/or the non-system file link table is accessed, so as to load the system file and/or the non-system files directly from the storage area of the memory.]]></description>
<pubDate>Tue, 10 Nov 2009 08:00:00 EST</pubDate>
</item>

<item>
<title><![CDATA[Self-test circuit for high-definition multimedia interface integrated circuits]]></title>
<link>http://www.freepatentsonline.com/7617064.html</link>
<description><![CDATA[A high-definition multimedia interface circuit uses a high-definition multimedia interface encoder to produce a plurality of channels of data. An output circuit, connected to the high-definition multimedia interface encoder, produces a plurality of channels of high frequency data from the data produced by the high-definition multimedia interface encoder. A multiplexer selects a channel for sampling, and a capacitive coupler capacitively couples the multiplexer to a sampling circuit. The sampling circuit produces sampled data corresponding to the high frequency data having a clock rate less than a clock rate of the high frequency data. A test circuit compares the sampled data with the data produced by the high-definition multimedia interface encoder.]]></description>
<pubDate>Tue, 10 Nov 2009 08:00:00 EST</pubDate>
</item>

<item>
<title><![CDATA[Systems and methods for enumerative encoding and decoding of maximum-transition-run codes and PRML (G,I,M) codes]]></title>
<link>http://www.freepatentsonline.com/7616134.html</link>
<description><![CDATA[Systems and methods for encoding/decoding are provided. The systems and methods include encoding a stream of K-bit input sequences into a stream of (G, I, M)-constrained 2N-bit output sequences by transforming each K-bit input bit sequence into two separate data paths including even and odd bits. Enumerative maximum-transition-run (eMTR) encoding of the even bits generates constrained even bits, and enumerative maximum-transition-run (MTR) encoding of the odd bits generates constrained odd bits. The constrained even and constrained odd bits are interleaved to form a stream of (G, I, M)-constrained 2N-bit output sequences where G is a global constraint, I is an interleave constraint, and M is a variable frequency oscillator constraint of a partial-response maximum-likelihood (PRML) codeword. Decoding systems and methods are also provided.]]></description>
<pubDate>Tue, 10 Nov 2009 08:00:00 EST</pubDate>
</item>

<item>
<title><![CDATA[Method and system for estimating the speed of a mobile device in a network]]></title>
<link>http://www.freepatentsonline.com/7616715.html</link>
<description><![CDATA[A method for estimating the speed of a mobile device in a network is provided that includes selecting a correlation length from a plurality of possible correlation lengths. A correlation result is generated based on the selected correlation length. A speed estimate is generated for the mobile device based on the correlation result.]]></description>
<pubDate>Tue, 10 Nov 2009 08:00:00 EST</pubDate>
</item>

<item>
<title><![CDATA[Signal delay structure in high speed bit stream demultiplexer]]></title>
<link>http://www.freepatentsonline.com/7616725.html</link>
<description><![CDATA[A signal delay structure and method of reducing skew between clock and data signals in a high-speed serial communications interface includes making a global adjustment to the clock signal in the time domain to compensate for a component of the skew that is common between the clock and all data signals. This can include skew caused by the variation in frequency of the input clock from a nominal value, misalignment between the phase of the clock and data generated at the source of the two signals. The global adjustment is made through a delay component that is common to all of the clock signal lines for which skew with data signals is to be compensated. A second level adjustment is made that compensates for the component of the skew that is common to the clock and a subset of the data signals.]]></description>
<pubDate>Tue, 10 Nov 2009 08:00:00 EST</pubDate>
</item>

<item>
<title><![CDATA[Scalable bus structure]]></title>
<link>http://www.freepatentsonline.com/7617343.html</link>
<description><![CDATA[A processing system is disclosed with a sending component and a receiving component connected by a bus. The bus may be configured with transmit and receive channels. The transmit channel may have a plurality of sub-channels. The sending component may be configured to broadcast on each of the sub-channels information comprising read and write address locations, read and write control signals, and write data on each of the sub-channels. The receiving component may be configured to store the write data and retrieve read data in response to the information broadcast on any of the sub-channels, and broadcast the retrieved read data on the receive channel to the sending component. The sending component may further be configured to provide to the receiving component independent signaling for each of the sub-channels, the independent signaling being sufficient to allow the receiving component to determine the type of information broadcast on each of the sub-channels.]]></description>
<pubDate>Tue, 10 Nov 2009 08:00:00 EST</pubDate>
</item>

<item>
<title><![CDATA[Memory controller, flash memory system having memory controller and method for controlling flash memory device]]></title>
<link>http://www.freepatentsonline.com/7617352.html</link>
<description><![CDATA[A memory controller includes decision means responsive to a request to write user data issued by a host computer for determining whether progressive data writing for writing user data to a target page designated by a host address is possible, and write means responsive to an affirmative determination by the decision means for writing user data to the target page without performing an inter-block data transfer. Thus, a series of data write operations for completing data writing can be performed at high speed because the frequency of inter-block data transfers is low.]]></description>
<pubDate>Tue, 10 Nov 2009 08:00:00 EST</pubDate>
</item>

<item>
<title><![CDATA[Fast failover with multiple secondary nodes]]></title>
<link>http://www.freepatentsonline.com/7617369.html</link>
<description><![CDATA[A method, system, computer system, and computer program product to quickly synchronize replicas of data stored at multiple secondary nodes upon failure of a primary node. Secondary nodes to which an update to data is sent are identified. The secondary nodes insert the update into a respective log of updates to a respective copy of the data. When all of the secondary nodes have acknowledged the update, a notification is sent to each of the secondary nodes. In response to receiving the notification, each of the secondary nodes clears the update from the respective log. Data at one secondary node can be synchronized with data at another secondary node when one of the nodes has received updates from the primary node that the other secondary node has not yet received.]]></description>
<pubDate>Tue, 10 Nov 2009 08:00:00 EST</pubDate>
</item>

<item>
<title><![CDATA[Method of soft bit metric calculation with direct matrix inversion MIMO detection]]></title>
<link>http://www.freepatentsonline.com/7616699.html</link>
<description><![CDATA[A telecommunication MIMO receiver implements soft bit metric calculation with direct matrix inversion MIMO detection. The receiver has a detector that detects data symbols in a received signal by determining distances between received signal points and constellation points; a scaler that scales the distances using a scaling factor; and a soft bit metric calculator that uses the scaled distances to calculate scaled soft bit metrics. The receiver can also have a decoder that decodes the soft bit metrics to determine data values in the received signals. Preferably, the receiver also has a quantizer that dynamically quantizes the soft bit metrics before decoding by the decoder.]]></description>
<pubDate>Tue, 10 Nov 2009 08:00:00 EST</pubDate>
</item>

<item>
<title><![CDATA[System and method for using a data replication service to manage a configuration repository]]></title>
<link>http://www.freepatentsonline.com/7617289.html</link>
<description><![CDATA[A mechanism for making changes consistently across an application server domain or a cluster. Server configuration consistency is absolutely necessary for cluster deployments. The invention allows changes to the configuration repository and to the application deployment process to be managed via a Data Replication Service (DRS). The former requires that the configuration repository be version aware, while the latter breaks down the application deployment process into two phases—one for data distribution and processing as far as possible, and the second to expose the changes through the Java Naming and Directory Interface (JNDI).]]></description>
<pubDate>Tue, 10 Nov 2009 08:00:00 EST</pubDate>
</item>

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