DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0036] Embodiments of this invention will now be explained with reference to the accompanying drawings below.

[0037] [Embodiment 1]

[0038] FIG. 1 shows a block configuration of an EEPROM chip of the NAND type in accordance with one embodiment. A memory cell array 1 is arranged by layout of NAND cell units using electrically rewritable nonvolatile memory cells in a way as will be described in detail later. A sense amplifier and data latch circuit 2 functions as a sense amp circuit for sensing bit-line data of the memory cell array 1 and also as a data latch which retains write data.

[0039] Bit lines of the memory cell array 1 are subjected to selection by a column decoder 3 ; word lines thereof are selected and driven by a row-decoder/word-line driver 5 . Row and column addresses are supplied to the row-decoder/wordline driver 5 and column decoder 3 through an input/output (I/O) buffer 4 and also via an address register 6 . Data transfer and receipt are performed between the bit lines and external I/O terminals.

[0040] A control circuit 7 is provided for performing sequence control of data write and erase operations. High voltages required for write and erase sessions are generated by a high-voltage generation circuit a in accordance with an operation mode, wherein the high-voltage generator 8 is controlled by the controller 7 .

[0041] FIG. 2 shows an equivalent circuit of the memory cell array 1 . Memory cells MC (MC 0 to MC 15 ) are such that each has a metal oxide semiconductor (MOS) transistor structure with its floating gate and a control gate insulatively stacked over the floating gate. A plurality of (sixteen, in the illustrative example) such memory cells MC are connected in series to thereby make up a NAND cell unit. A select gate transistor SG 1 is inserted between one end of the NAND cell unit and a bit line BL; similarly, a select gate transistor SG 2 is inserted between the other end and a source line SL.

[0042] In this embodiment, the NAND cell unit further includes a dummy cell DC 0 which is inserted between the select gate transistor SG 1 on the bitline side and a memory cell MC 0 neighboring upon this transistor SG 1 , and a dummy cell DC 1 which is between the select gate transistor SG 2 on the source line side and a memory cell MC 15 adjacent thereto. While these dummy cells DC 0 -DC 1 are principally the same in structure as the memory cells MC 0 -MC 15 , data write and read operations are not performed at the dummy cells DC 0 - 1 . In other words, dummy cells DC 0 - 1 are not used as data storage elements

[0043] Each memory cell MC within the NAND cell unit has its control gate which is connected to a corresponding one of word lines WL (WL 0 to WL 15 ). A word line WL is commonly connected to control gates of a plurality of memory cells aligned in a dir ction parallel thereto. The select gate transistors SG 1 and SG 2 have their gates which are provided and fabricated as select gate lines SGD and SGS extending in parallel to the word lines WL. Similarly, the dummy cells DC 0 -DC 1 have control gates that are continuously formed as dummy word lines DWL 0 and DWL 1 in parallel to wordlines WL.

[0044] FIG. 3 shows a plan view of a single NAND cell unit. Also see FIG. 4 , which is its cross-sectional view as taken along line I-I′. In a silicon substrate 10 of n type conductivity, a semiconductive well region 11 of p type conductivity is formed. In this p-type well 11 , a plurality of NAND cell units are formed in the wordline direction. The range of such multiple NAND cell units formed within the p-type well 11 becomes a block which is a unit for “all-at-a-time” or “all-at-once” data erase.

[0045] A memory cell MC has a floating gate 13 which is a first-layer polycrystalline silicon film as formed above the p-type well 1 with a tunnel dielectric film 12 interposed therebetween and a control gate 15 which is a second-layer polysilicon film as stacked over the floating gate 13 with a dielectric film sandwiched therebetween. Control gate 15 is continuously formed in a one direction and becomes a word line WL. Dummy cells DC 0 and DC 1 are the same in structure as memory cells MC so that their control gates 15 are similarly formed continuously to become dummy word lines DWL 0 and DWL 1 .

[0046] Select gate transistors SG 1 -SG 2 have gate electrodes which are formed by patterning techniques as control gate lines SGD-SGS, wherein a first-layer polysilicon film which is the same as that of the memory cell floating gate 13 and a second-layer polysilicon film same as that of memory cell control gate 14 are electrically connected together at an appropriate position. Gate electrodes 15 d and 15 a of these select gate transistors SG 1 -SG 2 are formed so that each is wider than the individual one of control gates 15 of memory cells MC and dummy cells DC. After having formed and patterned these word lines WL and select gate lines, n-type diffusion layers 16 are formed. The n-type diffusions 16 are for use as source/drain regions.

[0047] The memory cell array is covered or coated with an interlayer dielectric film 20 . On this film 20 , a source lines (SL) 21 is formed. Further, bit lines (BL) 23 are formed via an interlayer dielectric film 22 .

[0048] Bias conditions for data read, erase and write operations in the EEPROM of this embodiment are shown in FIG. 5 .

[0049] Data erase within a selected cell block is as follows. Let a bit line BL and select gate lines SGD and SGS be set in a floating state, set all the word lines WL at 0V, and apply an erase voltage Vera-18V to a p-type well. At this time, set dummy word lines DWL 0 -DWL 1 also at 0V.

[0050] Whereby, electrons are drawn out of the floating gate of the memory cells within the selected block so that data are erased. While a write state high in threshold voltage with electrons stored on the floating gate is regarded as data “0” an erase state is defined as a data “1” state which is lower in threshold voltage than the former.

[0051] In the above-noted erase mode, the two dummy cells DC also are applied with the same voltage as the voltage being applied to the sixteen memory cells MC. Accordingly, this ensures that certain ones of the sixteen memory cells MC 0 -MC 15 for use as real data storage cells—i.e., the memory cell MC 0 nearest to the bit line BL, and memory cell MC 15 nearest to the source line SL—are also identically the same in erase operation conditions as the remaining memory cells MC 1 to MC 14 . More specifically, unlike the prior art, these memory cells MC 0 and MC 15 become free from the influence of the capacitive coupling from the select gate lines SGD and SGS so that their floating gates are applied with the same voltage as that at the other memory cells. In other words, the resultant erase speed or rate stays constant with respect to all the memory cells MC. This makes it possible to reduce any possible variation in erase threshold voltages within the NAND cells.

[0052] During data reading, precharge the bit line BL at Vb 1 =0.5V, for example. Thereafter, apply to a selected word line of the sixteen word lines a read voltage Vr which provides an ability to determine the threshold voltage distributions of data “0” and “1” shown in FIG. 10 . Apply a pass voltage Vread to the remaining non-selected word lines and the dummy word lines DWL. This pass voltage Vread causes turn-on irrespective of whether the data is a logic “0” or “1.” Apply to the select gate lines SGD and SGS a power supply voltage Vcc (or alternatively an appropriate intermediate voltage higher than the supply voltage Voc) by way of example. With such voltage application, in case a selected memory cell turns on, its associated bit line potentially drops down; if the cell turns off, then the bitline potential is retained. Thus it is possible at the bitline to detect whether the selected memory cell turns on or off, thereby making it possible to achieve data determination.

[0053] At the time of data writing, apply a write voltage Vpgm to a selected word line while applying an appropriate mid-level voltage Vpass to the other nonselected word lines and the dummy word lines DWL. The mid voltage Vpass is higher than the supply voltage Vcc. Note here that prior to this write voltage application, either Vss or Voc is given to the bit line BL in accordance with write data “0,” “1” while setting the bitline side select gate line SGD at Vcc and the source-line side select gate line SGS at 0V, thereby precharging the NAND cell channels. A channel with “0” data given thereto becomes at Vss, whereas a “1” data-channel becomes in the floating state of Vcc-Vth (Vth is the threshold voltage of select gate transistor). By application of the above-stated write voltage Vpgm in this state, a “0” data-given memory cell experiences electron injection from its channel onto floating gate. In a “1” data-given cell, its channel potentially rises up due to the presence of capacitive coupling so that no electrons are injected to its floating gate. In this way, any memory cell with “0” data given thereto along a word line becomes in the “0” write state that is high in threshold voltage as shown in FIG. 10 .

[0054] In this data write mode also, with the use of the dummy cells DC 0 -DC 1 which are applied with the same mid voltage Vpass as that of nonselected word lines, the same write condition is establishable even when any one of the sixteen memory cells is selected. Accordingly, variation or deviation of write data within the NAND cell unit is lowered, thereby enabling improvement in uniformity of write threshold voltage values.

[0055] Also note that in the case of this embodiment, any complicated operations different from the prior art are not required with respect to the erase/write/read operations. Thus, the intended operations may be performed successfully under much similar operating conditions to the prior art.

[0056] Another advantage of this embodiment is that the NAND cell units decrease in influenceability of variations in on-chip element characteristics in manufacturing processes thereof. This point will be explained in detail below. Generally in semiconductor memories, it is becoming more difficult to perform pattern formation at terminate end portions of a cell array which exhibit disturbance of periodicity with an increase in miniaturization of memory cells. In NAND-EEPROMs, one end of a NAND cell unit is connected to a source line SL, and the other end is coupled to a bit line BL. Select gate transistors are inserted between these source and bit lines and a cell array. It is thus required that the select gate transistors SG be designed so that each is cut off deeply enough to enable the NAND cell unit to be completely electrically disconnected or isolated from its associated source line and bit line when the need arises. In view of this, transistors are used which are greater in gate length than normal memory calls. As a result, the distance or layout pitch f two select gate lines interposing contact portions of the bit line and source line is different from the distance of word lines; further, a select gate line width is different from the wordline width. Therefore, the periodicity of the cell array disturbs at here. In this way, the memory cell array looses the periodicity at its end portions. This results in occurrence of an event that any required exposure and micro-patterning processes are no longer achievable with desired feature sizes.

[0057] In this embodiment, the dummy cells are disposed between the select gate transistors and the memory cells. Thus the periodicity becomes excellent in the range of the memory cell array used for actual data storage. This makes the feature size uniform, resulting in on-chip elements being equivalent in characteristics to one another. The dummy cells are encountered with no serious problems even when their sizes are little deviated from a desired size, because these are not operated as real data storage cells.

[0058] More specifically, in cases where such dummy cells are not disposed, a need is felt to contrive a scheme for designing the distance between select gate lines and word lines and also the wordline width in order to maintain the wordline width constantly among cells. For example, make the distance between a select gate line and its neighboring word line larger than the distance between other word lines. In contrast, this invention is such that the dummy cell is laid out in close proximity to the select gate line. With this “dummy cell layout” feature, disturbance of the periodicity within the cell array becomes no longer occurrable. In addition, since the dummy cell is free from problems even when its line width deviates slightly, it becomes possible to achieve the pattern layout with the minimum feature size. At this time, an area loss occurring due to the dummy cell layout is less in a practical sense.

[0059] [Embodiment 2]

[0060] A cell array equivalent circuit of a NAND-EEPROM in accordance with an embodiment 2 is shown in FIG. 6 . A plan view and its cross-sectional view along line I-I′ are shown in FIGS. 7 and 8 . Parts or components corresponding to those of the previous embodiment 1 are denoted by the same reference characters, with a detailed explanation eliminated herein.

[0061] In this embodiment, a NAND cell unit has sixteen memory cells MC 0 to MC 15 and is similar to the prior art in cell array configuration and structure. This embodiment does not employ dummy cells such as those used in the embodiment 1. In such the NAND cell array, the wordline dependency takes place in erase and write threshold voltage values when using the same erase and write methods as those in the prior art, as has been stated previously.

[0062] Consequently in this embodiment, for the memory cells next to the select gate transistors, apply a different bias voltage condition from the other cells to thereby remove the above-noted wordline dependency.

[0063] To be more concrete, FIG. 9 shows a bias relationship in each operation mode of this embodiment. Although the same 0-V voltage is ordinarily applied to every word line within a NAND cell unit at the time of data erase, this embodiment is arranged to apply 0V only to certain word lines WL 0 and WL 15 adjacent to the select gate lines SGD and SGS while applying to the remaining word lines WL 1 -WL 14 a 0.7-V voltage higher than the former. Note here that 0.7V is equivalent to a difference in threshold voltage between the word lines WL 0 and WL 15 and the wordlines WL 1 -WL 14 in view of the wordline dependency of erase threshold voltage shown in FIG. 14 . The other conditions are similar to those of the prior art: set the select gate lines SGD-SGS and source line SL plus bit line BL in the floating state; and, apply an erase voltage Vera=18V to the p-type well of an erase block.

[0064] By setting the low level voltage to be given to the control gates of the memory cells on the select gate side so that this voltage is lower than that given to the remaining memory cells in this way, it becomes possible to make the after-erase threshold voltage distribution uniform. Furthermore, it becomes possible to narrow the after-erase threshold voltage distribution, by comparing average values of the threshold voltages on a per-wordline basis after having erased by setting each wordline at 0V and then letting a voltage corresponding to a deviation of the threshold voltage of a respective word line be the wordline voltage at the time of erase. At this time, with the threshold voltage of a memory cell which is the highest in erase threshold voltage (and thus is difficult to be erased) being as a reference value, apply a voltage that is potentially equivalent to a difference of such threshold voltage to a wordline during erasing.

[0065] As for data write, let the write pulse voltage step-up condition be different between when the word line WL 0 or WL 15 next to the select gate line SGD, SGS is selected and when any one of the other wordlines WL 1 -WL 14 is selected. Although the “step write” technique is not specifically explained in the previous embodiment, standard NAND-EEPROMs are designed to use a method for forcing a wordline voltage to potentially change in short and essentially uniform steps rather than continuously while at the same time confirming or checking write data of a plurality of memory cells (a page of cells) along a single wordline—that is, while verifying the resultant write state on a per-bit basis.

[0066] More specifically, as shown in FIG. 12 , set write data (S 1 ), make certain that the writing of all bits is not completed yet (S 2 ), and set an initial value of the write pulse voltage Vpgm (S 3 ). Then, apply a write pulse (S 4 ); thereafter, perform verify-read determination for verification of the resulting write state on a per-bit basis (S 5 ). If the judgment is NO, then cause the write pulse voltage to step up and then repeat similar write and verify-read operations. When the verify test is passed, invert a corresponding bit of the write data being held, and ensure that no write is done to such bit at later stages. And, determine that writing of all the bits corresponding to a page is completed (S 2 ); then, terminate the write cycle.

[0067] FIG. 11 shows step-up voltages upon execution of the write cycle control stated above in two events: when any one of the word lines WL 1 -WL 14 is selected, and when wordline WL 0 , WL 15 is selected. More specifically, when one of the wordlines WL 1 -WL 14 is selected, let the initial value of a write pulse voltage be Set at Vpgm0. When wordline WL 0 , WL 15 is selected, make use of an initial value Vpgm0+ΔV, which is little higher than the value Vpgm0. As shown in FIG. 15 , the memory cells on the select gate transistor side tend to delay in write when compared to the remaining cells under the same write conditions. In contrast, with the write pulse initial value setting feature stated above, it is possible to permit the execution number of write loops to stay constant regardless of any wordline, thus making it possible to obtain a uniform write threshold voltage distribution.