DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0039] Preferred embodiments of the present invention will be described herein below with reference to the accompanying drawings. In the following description, well-known functions or constructions are not described in detail since they would obscure the invention in unnecessary detail. It is to be appreciated herein that an EX-OR gate and an adder are used in the same sense and operate on input data on a bit-by-bit basis.

[0040] In the present invention, a transmitter-selected mask sequence is detected using a CRC in a mask sequence-based SLM. Therefore, the SLM is effectively implemented in an OFDM system without transmitting additional information about the selected mask sequence.

[0041] A CRC is cyclic block code used on a transmission side, for error correction. An input signal is shifted at shift registers and the shifted signals are fed back to EX-OR gates in a CRC generator.

[0042] Before describing the present invention, a CRC generator applied to the present invention will first be described.

[0043] FIG. 3 is a block diagram of a CRC generator applied to embodiments of the present invention.

[0044] The CRC generator usually comprises a plurality of shift registers and a plurality of EX-OR gates. Referring to FIG. 3, the CRC generator includes four shift registers 300 to 306 and four EX-OR gates 310 to 316. Obviously, the CRC generator can be configured in different ways according to a general CRC generator implementation method.

[0045] If 12 information bits, 101000110110 are input to the CRC generator, 4 zeroes are added to the information bits because a CRC generator polynomial is a fourth-order polynomial in the CRC generator.

[0046] The CRC generator polynomial in defined as g(x)=x⁴+x³ +x²+x+1. Since it is a fourth-order polynomial, 4 zeroes are appended to the information bits. Hence,

[0047] CRC generator input bits=1010001101100000

[0048] The CRC generator input bits are sequentially applied to the CRC generator, starting from the leftmost bit. It is assumed that a bit is moved from a shift register to the following shift register at time t1 and a bit is moved from the following shift register to the second following shift register at time t2. The shift registers 300 to 306 are all set to 0s, initially.

[0049] At t1, the EX-OR gate 310 exclusive-OR operates the first input bit 1 and the initial value 0 at the shift register 306 and the shift register 300 has the resulting value 1. The EX-OR gate 312 exclusive-OR operates the initial value 0s at the shift registers 300 and 306 and the shift register 302 has the resulting value 0. The EX-OR gate 314 exclusive-OR operates the initial value 0s at the shift registers 302 and 306 and the shift register 304 has the resulting value 0. The EX-OR gate 316 exclusive-OR operates the initial value 0s at the shift registers 304 and 306 and the shift register 306 has the resulting value 0. Therefore, 1, 0, 0, 0 are stored in the shift registers 300 to 306 at t1.

[0050] At t2, the EX-OR gate 310 exclusive-OR operates the second input bit 0 and the value 0 stored at the shift register 306 at t1 and the shift register 300 has the resulting value 0. The EX-OR gate 312 exclusive-OR operates the value 1 stored at the shift register 300 at t1 with the value 0 stored at the shift register 306 at t1 and the shift register 302 has the resulting value 0. The EX-OR gate 314 exclusive-OR operates the value 0 stored at the shift register 302 at t1 with the value 0 stored at the shift register 306 at t1 and the shift register 304 has the resulting value 0. The EX-OR gate 316 exclusive-OR operates the value 0 stored at the shift register 304 at t1 with the value 0 stored at the shift register 306 at t1 and the shift register 306 has the resulting value 0. Therefore, 0, 1, 0, 0 are stored in the shift registers 300 to 306 at t2.

[0051] At t3, the EX-OR gate 310 exclusive-OR operates the third input bit 1 and the value 0 stored at the shift register 306 at t2 and the shift register 300 has the resulting value 1. The EX-OR gate 312 exclusive-OR operates the value 0 stored at the shift register 300 at t2 with the value 0 stored at the shift register 306 at t2 and the shift register 302 has the resulting value 0. The EX-OR gate 314 exclusive-OR operates the value 1 stored at the shift register 302 at t2 with the value 0 stored at the shift register 306 at t2 and the shift register 304 has the resulting value 1. The EX-OR gate 316 exclusive-OR operates the value 0 stored at the shift register 304 at t2 with the value 0 stored at the shift register 306 at t2 and the shift register 306 has the resulting value 0. Therefore, 1, 0, 1, 0 are stored in the shift registers 300 to 306 at t3. Table 1 below lists values stored at the shift registers for the input of the CRC generator input bits. 1

[0052] As noted from Table 1, the CRC generator has 1, 1, 0, 1 at the respective shift registers 300 to 306 after the final exclusive-OR operation.

[0053] Embodiment 1

[0054] FIG. 4 is a block diagram of an OFDM transmitter based on the mask sequence-based SLM according to an embodiment of the present invention.

[0055] Referring to FIG. 4, information bits, for example, 101000110110, are applied as a binary signal to the input of a CRC generator 400. The CRC generator 400 appends the CRC bits, 1101 generated in the manner as described with reference to FIG. 3 to the information bits. Therefore,

Information bits+CRC bits=1010001101101101

[0056] The information bits attached with the CRC bits are copied to a plurality of same information bit streams and applied to a plurality of (e.g. U) adders 420 to 426. Meanwhile, a mask generator 410 generates a plurality of mask sequences. If the mask generator 410 generates 4 mask sequences (i.e. U=4), they are defined as

M₁ =1 0 0 1 0 0 1 1 0 1 1 1 0 0 0 1

M₂ =0 1 0 1 1 0 0 0 1 0 1 0 0 1 1 1

M₃ =1 0 1 1 0 0 0 1 0 1 0 0 1 0 1 1

M₄ =0 1 0 1 1 0 1 0 0 1 0 1 1 1 0 1

[0057] In accordance with the embodiment of the present invention, the output of the CRC generator 400 and the mask sequence M₁ are applied to the input of a first adder 420, the output of the CRC generator 400 and the mask sequence M₂ are applied to the input of a second adder 422, the output of the CRC generator 400 and the mask sequence M₃ are applied to the input of a third adder 424, and the output of the CRC generator 400 and the mask sequence M_U are applied to the input of a Uth adder 426. The adders 420 to 426 exclusive-OR operate the CRC output bits with the respective input mask sequences.

[0058] If U=4, the exclusive-OR operation results of the adders 420 to 426 are

[0059] First adder 420=0 0 1 1 0 0 0 0 0 0 0 1 1 1 0 0

[0060] Second adder 422=1 1 1 1 1 0 1 1 1 1 0 0 1 0 1 0

[0061] Third adder 424=0 0 0 1 0 0 1 0 0 0 1 0 0 1 1 0

[0062] Fourth adder 426=1 1 1 1 1 0 0 1 0 0 1 1 0 0 0 0

[0063] Channel encoders 430 to 436 encode the signals received from the adders 420 to 426 at a code rate of ½, for example, and each channel encoder outputs 32 code symbols. Symbol mappers 440 to 446 map the code symbols on a signal constellation of QPSK, 8PSK, 16QAM or 64QAM. The number of bits per symbol depends on a modulation scheme used. One symbol has 2 bits in QPSK, 3 bits in 8PSK, 4 bits in 16QAM, and 6 bits in 64QAM. If each of the symbol mappers 440 to 446 uses QPSK, it maps two sets of 16 code symbols, separately.

[0064] IFFTs 450 to 456 inverse-fast-Fourier-transform the mapped symbols. A selector 460 calculates the PAPR of the symbols received from the IFFTs 450 to 456 and selects symbols having the lowest PAPR. While the single selector 460 performs PAPR calculation and comparison and symbol selection, the operations can be implemented by use of two devices, that is, a PAPR calculator and a comparator & selector.

[0065] The selector 460 calculates the PAPRs of the received code symbols and selects code symbols having the lowest of U PAPRs. For example, if the code symbols corresponding to the mask sequence M₁ generated from the mask generator 410 has the lowest PAPR, the code symbols output from the IFFT 450 are selected for transmission to a receiver.

[0066] FIG. 5 is a block diagram of a receiver being the counterpart of the transmitter illustrated in FIG. 4.

[0067] Referring to FIG. 5, an FFT 500 fast-Fourier-transforms a signal received from the transmitter illustrated in FIG. 4. A symbol demapper 510, having the same signal constellation as that in the symbol mappers 440 to 446 of FIG. 4, converts the IFFT symbols to a binary signal according to the signal constellation. The symbol demapping depends on the symbol mapping. For example, if the modulation is QPSK, the demodulation is carried out based on QPSK. If the modulation is 8PSK, the demodulation is carried out based on 8PSK. After the symbol demapping, the received signal becomes a binary 32-bit signal.

[0068] A channel decoder 520 decodes the binary signal by a decoding method in correspondence with the coding method of the channel encoders 430 to 436. The decoded signal is copied to a plurality of (e.g. U) same signals and applied to adders 540 to 546. Meanwhile, a mask generator 530 generates a plurality of mask sequences and feeds them to adders 540 to 546. The mask generator 530 of the receiver has the same configuration as the mask generator 410 of the transmitter. The decoded signal and the mask sequence M₁ are applied to the input of a first adder 540, the decoded signal and the mask sequence M₂ are applied to the input of a second adder 542, the decoded signal and the mask sequence M₃ are applied to the input of a third adder 544, and the decoded signal and the mask sequence M_U are applied to the input of a Uth adder 546.

[0069] The adders 540 to 546 exclusive-OR operate the decoded signal with the respective input mask sequences, thereby eliminating the masks generated from the mask generator 410 of FIG. 4.

[0070] If U=4, the exclusive-OR operation results of the adders 540 to 546 are

[0071] First adder 540=1 0 1 0 0 0 1 1 0 1 1 0 1 1 0 1

[0072] Second adder 542=0 1 1 0 1 0 0 0 1 0 1 1 1 0 1 1

[0073] Third adder 544=1 0 0 0 0 0 0 1 0 1 0 1 0 1 1 1

[0074] Fourth adder 546=0 1 1 0 1 0 1 0 0 1 0 0 0 0 0 1

[0075] CRC checkers 550 to 556, configured in the same manner as the CRC generator 400 of FIG. 4, sequentially perform shifts and exclusive-OR operations on the bit streams received from the adders 540 to 546. The CRC checkers 550 to 556 operate in the same manner as the CRC generator 400 except for attachment of as many zeroes as the order of the CRC generator polynomial. The operation of the CRC checker 550 will be described with reference to FIG. 3.

[0076] The bits from the adder 540 are sequentially applied to the CRC checker 550, starting from the leftmost bit. It is assumed that a bit is moved from a shift register to the following shift register at time t1 and a bit is moved from the following shift register to the second following shift register at time t2 in the CRC checker 550. The shift registers 300 to 306 are all set to 0s, initially.

[0077] At t1, the EX-OR gate 310 exclusive-OR operates the first input bit 1 of the CRC checker 550 and the initial value 0 at the shift register 306 and the shift register 300 has the resulting value 1. The EX-OR gate 312 exclusive-OR operates the initial value 0s at the shift registers 300 and 306 and the shift register 302 has the resulting value 0. The EX-OR gate 314 exclusive-OR operates the initial value 0s at the shift registers 302 and 306 and the shift register 304 has the resulting value 0. The EX-OR gate 316 exclusive-OR operates the initial value 0s at the shift registers 304 and 306 and the shift register 306 has the resulting value 0. Therefore, 1, 0, 0, 0 are stored in the shift registers 300 to 306 at t1.

[0078] At t2, the EX-OR gate 310 exclusive-OR operates the second input bit 0 of the CRC checker 550 and the value 0 stored at the shift register 306 at t1 and the shift register 300 has the resulting value 0. The EX-OR gate 312 exclusive-OR operates the value 1 stored at the shift register 300 at t1 with the value 0 stored at the shift register 306 at t1 and the shift register 302 has the resulting value 0. The EX-OR gate 314 exclusive-OR operates the value 0 stored at the shift register 302 at t1 with the value 0 stored at the shift register 306 at t1 and the shift register 304 has the resulting value 0. The EX-OR gate 316 exclusive-OR operates the value 0 stored at the shift register 304 at t1 with the value 0 stored at the shift register 306 at t1 and the shift register 306 has the resulting value 0. Therefore, 0, 1, 0, 0 are stored in the shift registers 300 to 306 at t2.

[0079] At t3, the EX-OR gate 310 exclusive-OR operates the third input bit 1 of the CRC checker 550 and the value 0 stored at the shift register 306 at t2 and the shift register 300 has the resulting value 1. The EX-OR gate 312 exclusive-OR operates the value 0 stored at the shift register 300 at t2 with the value 0 stored at the shift register 306 at t2 and the shift register 302 has the resulting value 0. The EX-OR gate 314 exclusive-OR operates the value 1 stored at the shift register 302 at t2 with the value 0 stored at the shift register 306 at t2 and the shift register 304 has the resulting value 1. The EX-OR gate 316 exclusive-OR operates the value 0 stored at the shift register 304 at t2 with the value 0 stored at the shift register 306 at t2 and the shift register 306 has the resulting value 0. Therefore, 1, 0, 1, 0 are stored in the shift registers 300 to 306 at t3. Table 2 below lists values stored at the shift registers for the input bits of the CRC checker. 2

[0080] As noted from Table 2, the CRC checker 550 has 0,0,0,0 at the respective shift registers 300 to 306 after the final exclusive-OR operation. Therefore, the CRC checkers 552 to 556 have the final values listed in Table 3. 3

[0081] The CRC checkers 550 to 556 output the final values at their shift registers and the bit streams from the adders 540 to 546. A selector 560 checks the shift register values of the CRC checkers 550 to 556. If the output of a CRC checker is 0, the selector 560 selects an adder output corresponding to a mask sequence resulting in the CRC check result, considering the mask sequence was selected in the transmitter.

[0082] That is, since the shift register values of the CRC checker 550 are all 0s, the selector 560 considers that they have no errors. On the other hand, since the shift register values of the CRC checkers 552 to 556 contain 1, the selector 560 considers that they have errors. Thus, the selector 560 determines that the bit stream received from the CRC checker 550 is the signal transmitted by the transmitter and selects 12 bits of the bit stream except for the last 4 CRC bits as the information bits. In the illustrated case, the receiver determines that the mask sequence M₁ generated from the mask generator 530 was selected by the transmitter.

[0083] Embodiment 2

[0084] FIG. 6 is a block diagram of an OFDM transmitter based on the mask sequence-based SLM according to a second embodiment of the present invention. The transmitter uses a CRC generator like the transmitter of the first embodiment. However, while masking precedes channel encoding of information bits with CRC bits in the first embodiment, the masking follows channel encoding and symbol mapping of the information bits with CRC bits in the second embodiment. Therefore, the masking relies on exclusive-OR operation of the information bits with mask sequences on a bit basis in adders in the first embodiment, while the masking is carried out by multiplication of mapped symbols by the mask sequences on a bit basis in multipliers in the second embodiment.

[0085] Referring to FIG. 6, information bits are applied as a binary signal to the input of a CRC generator 600. The CRC generator 600 appends CRC bits generated in the manner as described with reference to FIG. 3 to the information bits. A channel encoder 610 encodes the binary bits received from the CRC generator 600. A symbol mapper 620 maps the code symbols on a signal constellation of QPSK, 8PSK, 16QAM or 64QAM. The number of bits per symbol depends on a modulation scheme used. One symbol has 2 bits in QPSK, 3 bits in 8PSK, 4 bits in 16QAM, and 6 bits in 64QAM. If each of the symbol mappers 440 to 446 uses QPSK, it maps two sets of 16 code symbols, separately. The mapped symbols are copied to a plurality of same signals, for example, U symbols in FIG. 6.

[0086] A mask generator 630 generates a plurality of independent mask sequences M₁ to M_U. The symbols from the symbol mapper 620 and the mask sequence M₁ are applied to the input of a first multiplier 640, the symbols and the mask sequence M₂ are applied to the input of a second multiplier 642, the symbols and the mask sequence M₃ are applied to the input of a third multiplier 644, and the symbols and the mask sequence M_U are applied to the input of a Uth multiplier 646.

[0087] The multipliers 640 to 646 multiply the received symbols by the respective mask sequences. Modulation symbols from the multiplier 640 are fed to a first IFFT 650, modulation symbols from the multiplier 642 are fed to a second IFFT 652, modulation symbols from the multiplier 644 are fed to a third IFFT 654, and modulation symbols from the multiplier 646 are fed to a Uth IFFT 656.

[0088] The IFFTs 650 to 656 inverse-fast-Fourier-transform the received symbols. A selector 660 calculates the PAPR of the symbols received from the IFFTs 650 to 656 and selects symbols having the lowest of the U PAPRs.

[0089] FIG. 7 is a block diagram of a receiver being the counterpart of the transmitter illustrated in FIG. 6. Referring to FIG. 7, an FFT 700 fast-Fourier-transforms a signal received from the transmitter illustrated in FIG. 6.

[0090] A mask generator 710 generates a plurality of independent mask sequences M₁ to M_U. The FFT signal and the mask sequence M₁ are applied to the input of a first multiplier 720, the FFT signal and the mask sequence M₂ are applied to the input of a second multiplier 722, the FFT signal and the mask sequence M₃ are applied to the input of a third multiplier 724, and the FFT signal and the mask sequence M_U are applied to the input of a Uth multiplier 726. The multipliers 720 to 726 multiply the FFT signal by the mask sequences M₁ to M_U, respectively.

[0091] Symbol demappers 730 to 736, having the same signal constellation as that in the symbol mapper 620 of FIG. 6, convert the symbols received from the multipliers 720 to 726 to binary signals according to the signal constellation. The symbol demapping depends on the symbol mapping. For example, if the modulation is QPSK, the demodulation is carried out based on QPSK. If the modulation is 8PSK, the demodulation is carried out based on 8PSK.

[0092] Channel decoders 740 to 746 decode the binary signals by a decoding method in correspondence with the coding method of the channel encoder 610.

[0093] CRC checkers 750 to 756, configured in the same manner as the CRC generator 600 of FIG. 6, sequentially perform shifts and exclusive-OR operations on the decoded signals. The CRC checkers 750 to 756 operate in the same manner as the CRC generator 600 except for attachment of as many zeroes as the order of the CRC generator polynomial.

[0094] The CRC checkers 750 to 756 operate in the same manner as the CRC checkers 450 to 456 illustrated in FIG. 5. The CRC checkers 750 to 756 output final values at their shift registers and the decoded binary signals from the decoders 740 to 746 to a selector 760. The selector 760 checks the shift register values of the CRC checkers 750 to 756. If the output of a CRC checker is all 0s, the selector 760 considers that it has no errors. If the output of a CRC checker contains 1, the selector 760 considers that it has errors. Thus, the selector 760 determines the output of a CRC checker with all 0s as a signal transmitted by the transmitter and selects 12 bits of a corresponding decoded signal except for the last 4 CRC bits as the information bits. The receiver also determines that a mask sequence corresponding to the selected decoded signal is the one selected by the transmitter.

[0095] Embodiment 3

[0096] FIG. 8 is a block diagram of an OFDM receiver based on the mask sequence-based SLM according to a third embodiment of the present invention. In accordance with the third embodiment of the present invention, a transmitter is configured in the same manner as the transmitter illustrated in FIG. 4 where a CRC generator output is applied to a plurality of adders. The receiver according to the first embodiment operates a received signal with all mask sequences used in the transmitter to search for a selected mask sequence, whereas the receiver according to the third embodiment searches for a selected mask sequence using a single CRC checker.

[0097] Although a PAPR associated with the mask sequence M₁ is lowest in FIG. 4, it is assumed in FIG. 8 that the mask sequence M₂ is lowest. Therefore, the transmitter transmits a signal masked with the mask sequence M₂. If U=4, the mask sequences and (information bits+CRC bits) are defined as

Information bits+CRC=1 0 1 0 0 0 1 1 0 1 1 0 1 1 0 1

M₁ =1 0 0 1 0 0 1 1 0 1 1 1 0 0 0 1

M₂ =0 1 0 1 1 0 0 0 1 0 1 0 0 1 1 1

M₃ =1 0 1 1 0 0 0 1 0 1 0 0 1 0 1 1

M₄ =0 1 0 1 1 0 1 0 0 1 0 1 1 1 0 1

[0098] Referring to FIG. 8, an FFT 800 fast-Fourier-transforms a signal received from the transmitter illustrated in FIG. 4. A symbol demapper 810, having the same signal constellation as that in the symbol mappers 440 to 446 of FIG. 4, converts the IFFT symbols to a binary signal according to the signal constellation. The symbol demapping depends on the symbol mapping. For example, if the modulation is QPSK, the demodulation is carried out based on QPSK. If the modulation is 8PSK, the demodulation is carried out based on 8PSK. After the symbol demapping, the received signal becomes a binary 32-bit signal.

[0099] A channel decoder 820 decodes the binary signal by a decoding method in correspondence with the coding method of the channel encoders 430 to 436. The decoded signal, which is applied to adders 840 and 870, is

(Information bits+CRC)⊕M₂=1 1 1 1 1 0 1 1 1 1 0 0 1 0 1 0

[0100] The mask sequence M₂ generated from a mask generator 830 is detected as a mask sequence selected by the transmitter in a controller 860 in a manner described later. Hereinbelow, a description is made of an operation for detecting the mask sequence M₂ selected by the transmitter in a single CRC checker according to the third embodiment of the present invention.

[0101] One of a plurality of mask sequences generated from the mask generator 830 is applied to the input of the first adder 840. Let the input mask sequence be M₁. The first adder 840 exclusive-OR operates the decoded signal with the mask sequence M₁ and outputs

((information bits+CRC)⊕M2)⊕M1)=0 1 1 0 1 0 0 0 1 0 1 1 1 0 1 1

[0102] A CRC checker 850, configured in the same manner as the CRC generator 400 of FIG. 4, sequentially performs shifts and exclusive-OR operations on the bit stream received from the adder 840. The CRC checker 850 operates in the same manner as the CRC generator 400 except for attachment of as many zeroes as the order of the CRC generator polynomial. The CRC check result is 0100, which is fed to the controller 860. The controller 860 has the CRC result values of (M₁⊕M₂), (M₁⊕M₃), (M₁⊕M₄). If the mask sequence M₂ is applied to the first adder 840, the controller 860 has the CRC result values of (M₂⊕M₁), (M₂⊕M₃), (M₂⊕M₄). Table 4 below lists the CRC result values of (M₁⊕M₂), (M₁⊕M₃), (M₁⊕M₄). 4

[0103] The controller 860 compares the input binary CRC check result with a corresponding stored CRC check result. The input CRC check result and the stored CRC check result for M₁⊕M₂ are equal to 0100. Therefore, the controller 860 determines that a signal transmitted from the transmitter was masked with the mask sequence M₂ generated the mask generator 410. Hence, the controller 860 controls the mask generator 830 to generate the mask sequence M₂ and feed it to the second adder 870. The second adder 870 exclusive-OR operates the decoded signal with the mask sequence M₂, thereby eliminating the mask sequence M₂ from the transmitted signal. Consequently, 12 bits of the resulting 16-bit signal except for the last 4 CRC bits are selected as the information bits.

[0104] If the transmitted signal was masked with the mask sequence M₁ in the transmitter, the CRC checker 850 outputs 0000 as the CRC check result of the transmitted signal. In this case, the controller 860 finds out that the transmitter masked the transmitted signal with the mask sequence M₁. The controller 860 then controls the mask generator 830 to generate the mask sequence M₁ and feed it to the second adder 870.

[0105] In accordance with the present invention as described above, PAPR is effectively reduced without the need for transmitting additional information in an OFDM system, thereby resulting in effective use of limited channel resources, as compared to the conventional technology requiring transmission of the additional information. In addition, system complexity and implementation cost are reduced.

[0106] While the invention has been shown and described with reference to certain preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.