DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0080] Preferred embodiments of the present invention will be described in detail below while referring to the drawings attached.

[0081] As shown in FIG. 1, a redundant-memory system 50 according to an embodiment of the invention comprises five DIMMs 1 - 0 , 1 - 1 , 1 - 2 , 1 - 3 , and 1 - 4 , five DIMM slots 2 - 0 , 2 - 1 , 2 - 2 , 2 - 3 , and 2 - 4 receiving respectively the DIMMs 1 - 0 , 1 - 1 , 1 - 2 , 1 - 3 , and 1 - 4 , and a memory controller 3 electrically connected to all the slots 2 - 0 to 2 - 4 . Each of the DIMMs 1 - 0 to 1 - 4 serves as a memory module. The memory controller 3 , which is used to control the entire operation of the memory system 50 , is electrically connected to a Central Processing Unit (CPU) 10 by way of a CPU bus 20 . The CPU 20 is an upper system of the system 50 . All the DIMM slots 2 - 0 to 2 - 4 are capable of hot plugging operation according to the definition by JEDEC.

[0082] The memory controller 3 comprises five ECC/CHIPKILL circuits 4 - 0 , 4 - 1 , 4 - 2 , 4 - 3 , and 4 - 4 , a parity generation/check/reconfiguration circuit 5 , a bypass circuit 6 , and an error count register circuit 7 . According to the instruction from the CPU 10 , the controller 3 controls the operations to write data into the respective DIMMs 1 - 0 to 1 - 4 inserted into the slots 2 - 0 to 2 - 4 , to read the data from the respective DIMMs 1 - 0 to 1 - 4 , and the other operations explained below.

[0083] The ECC/CHIPKILL circuits 4 - 0 to 4 - 4 , which are electrically connected to the slots 2 - 0 to 2 - 4 , respectively, conducts the operations of ECC (Error Checking and Correction) code generation, ECC check, and ECC data reconfiguration, and ChipKill error correction. The detailed configuration and operation of the ECC/CHIPKILL circuits 4 - 0 to 4 - 4 are well known and they do not relate to the invention. Therefore, no further explanation about them is presented here.

[0084] The parity-generation/check/reconfiguration circuit 5 is electrically connected to the ECC/CHIPKILL circuits 4 - 0 to 4 - 4 . The circuit 5 defines one of the five DIMMs 1 - 0 to 1 - 4 as a parity memory and the remainder thereof as data memories. Here, the DIMM 1 - 4 is defined as the parity memory and the remaining four DIMMs 1 - 0 to 1 - 3 are defined as the data memories. Moreover, in the data writing operation, the circuit 5 divides input data into four parts of data and generates a first parity code from these parts of data. Then, the circuit 5 writes the four parts of data into the four data memories (i.e., the DIMM 1 - 0 to 1 - 3 ), respectively, and writes the first parity code into the parity memory (i.e., the DIMM 1 - 4 ) (see FIG. 2 ). In the data reading operation, the circuit 5 reads out the parts of data from the four data memories (DIMMs 1 - 0 to 1 - 3 ) and the first parity data from the parity memory (i.e., the DIMM 1 - 4 ). Then, the circuit 5 generates a second parity code by using the four parts of data read from the four data memories (DIMMs 1 - 0 to 1 - 3 ). Thereafter, the circuit 5 compares the first and second parity codes to each other, thereby conducting the parity check operation (see FIG. 3 ). If an error is found in one of the data memories in the said parity check operation, the circuit 5 conducts the error correction operation using the other parts of data store in the remaining three data memories and the first parity code (see FIG. 4 ), thereby recovering the part of data stored in the failed data memory (i.e., one of the DIMMs 1 - 0 to 1 - 3 ). Finally, the circuit 5 combines the four parts of data together to generate the correct input data.

[0085] The bypass circuit 6 is used to select one of the “RAIMM (or redundancy) mode” where the desired data is sent by way of the parity-generation/check/reconfiguration circuit 5 , and the “bypass mode” where the desired data is sent to bypass the circuit 5 (i.e., sent without passing through the circuit 5 ) according to an instruction from the CPU 10 .

[0086] Referring to FIG. 5 , the error count register circuit 7 includes a generation count register 71 , a threshold register 72 , a comparator 73 , and an interrupt signal line 74 .

[0087] The generation count register 71 is used to store the generation counts of ECC 1-bit errors, ECC 2-bit errors, ChipKill errors, and read errors. The threshold register 72 is used to store the threshold for ECC 1-bit errors, ECC 2-bit errors, ChipKill errors, and read errors. The comparator 73 compares the generation counts stored in the generation count register 71 and the threshold stored in the threshold counter 72 and then, outputs an interrupt signal if one of the counts stored in the generation count register 71 exceeds the threshold stored in the threshold counter 72 . The interrupt signal line 74 is a line through which the interrupt signal from the comparator 73 is sent when one of the generation counts stored in the register 71 exceeds the threshold.

[0088] Referring to FIG. 6 , the power-on operation of the memory system 50 according to the embodiment of the invention comprises the step A 1 of setting the bypass mode, the step A 2 of memory checking, the step A 3 of error judgment, the step A 4 of notifying the error to the operator or user of the system 50 , and the step A 5 of setting the RAIMM or redundancy mode.

[0089] Referring to FIG. 7 , the data writing operation of the memory system 50 according to the embodiment of the invention comprises the step B 1 of generating the first parity code, the step B 2 of generating an ECC code and arranging a ChipKill correction code, and the step B 3 of writing the four parts of the input data into the four data memories and the first parity code into the parity memory, respectively.

[0090] Referring to FIG. 8 , the data reading operation of the memory system 50 according to the embodiment of the invention comprises the step C 1 of reading the four parts of the data from the four data memories and the first parity code from the parity memory, the step C 2 of judging the existence of a read error, the step C 3 of judging the existence of an ECC error, the step C 4 of outputting the data from the memory system 50 , the step C 5 of incrementing the generation count of the error count register circuit 1 , the step C 6 of reconfiguring the data using the parity code, the step C 7 of judging whether the ECC error found is correctable, the step C 8 of incrementing the generation count of the error count register circuit 7 , the step C 9 of judging the existence of a ChipKill error, the steps C 10 and C 11 of respectively incrementing the generation counts of the error count register circuit 7 , and the step C 12 of reconfiguring the data using the parity code.

[0091] Referring to FIG. 9 , the data reconfiguration operation of the memory system 50 according to the embodiment of the invention comprises the step D 1 of removing a failed one of the incorporated DIMMs 1 - 0 to 1 - 5 (i.e., a failed one of the data and parity memories), the step D 2 of inserting a new DIMM into the corresponding slot 2 - 0 , 2 - 1 , 2 - 2 , 2 - 3 , or 2 - 4 , the step D 3 of clearing all the counts of the generation count register 71 in the error count register circuit 7 to zero, the step D 4 of reading the parts of the data and the parity code from the normal DIMMs 1 - 1 to 1 - 5 (i.e., the four data memories and the parity memory) in the background, the step D 5 of reconfiguring the data using the parts of the correct data and the parity code thus read out, and the step D 6 of writing the corresponding part of the data thus reconfigured into the new DIMM 1 - 0 .

[0092] Next, the overall operation of the redundant memory system 50 according to the embodiment of the invention is explained in more detail below.

[0093] When the power is turned on, as shown in FIG. 6 , the bypass circuit 6 is initially set to select the bypass mode (Step A 1 ). Therefore, the CPU 10 conducts the initial memory check operation for all the DIMMs 1 - 0 to 1 - 4 without using the parity-generation/check/reconfiguration circuit 5 (Step A 2 ). At this time, if an error is found in one of the DIMMs 1 - 0 to 1 - 4 (Step A 3 ), the error is notified to the user or operator in a specific way according to the design of the computer system using the memory system 50 (Step A 5 ) by, for example, displaying a specific error message on the display screen and emitting an error sound-If no error is found in all the DIMMs 1 - 0 to 1 - 4 , in other words, the initial memory check is normally completed (Step A 3 ), the CPU 10 instructs the bypass circuit 6 to switch from the bypass mode to the RAIMM or redundancy mode (Step A 5 ).

[0094] When the data is written into the memory system 50 according to the embodiment of the invention, as shown in FIG. 7 , the parity-generation/check/reconfiguration circuit 5 divides the input data into four parts of data and generates the first parity code from the four parts of data thus formed (Step B 1 ). Then, the ECC/CHIPKILL circuits 4 - 0 to 4 - 4 generate the error correction code and arrange the ChipKill correction code for the DIMMs 1 - 0 to 1 - 4 (Step B 2 ). Subsequently, the circuits 4 - 0 to 4 - 3 write the four parts of data into the respective DIMMs 1 - 0 to 1 - 3 (Step B 3 ), while the circuit 4 - 4 writes the first parity code into the DIMM 1 - 4 (Step B 3 )

[0095] For example, as shown in FIG. 2 , when the input data is 64-bit data, the parity-generation/check/reconfiguration circuit 5 deblocks the 64-bit input data, which are expressed by (α1+α2 +α3+α4), into the four 16-bit deblocked data (i.e., parts of data) α1, α2, α3, and α4 to be written respectively into the four DIMMs 1 - 0 to 1 - 3 . On the other hand, the circuit 5 generates the 16-bit first parity code p 1 through an Exclusive OR operation of the four parts of 16-bit data α1, α2, α3, and α4. Thereafter, the circuit 5 sends the parts of data α1, α2, α3, and α4 and the first parity code p 1 thus generated to the five ECC/CHIPKILL circuits 4 - 0 to 4 - 4 , respectively (Step B 1 ). In response, the ECC/CHIPKILL circuits 4 - 0 to 4 - 4 generate the ECC code and arrange the ChipKill correction code (Step B 2 ). Subsequently, the circuits 4 - 0 to 4 - 4 actually write the parts of data α1, α2, α3, and α4 into the corresponding DIMMs 1 - 0 to 1 - 3 and the first parity code p 1 into the DIMM 1 - 4 (Step B 3 ).

[0096] Next, when the input data is read from the memory system 50 according to the embodiment of the invention, as shown in FIG. 8 , the memory controller 3 reads out the parts of the 16-bit data α1, α2, α3,and α4 from the respective DIMMs 1 - 0 to 1 - 3 and at the same time, the 16-bit first parity code p 1 from the DIMM 1 - 4 (Step C 1 ). Thereafter, the ECC/CHIPKILL circuits 4 - 0 to 4 - 4 judge whether a read error is found or not (Step C 2 ).

[0097] When no read error is found in the Step C 2 , each of the circuits 4 - 0 to 4 - 4 judges whether an ECC error is found or not (Step C 3 ). When no ECC error is found in the Step C 3 , the parity-generation/check/reconfiguration circuit 5 reconfigures or blocks the 16-bit parts of the data α1, α2, α3, and α4 thus read, thereby forming the 64-bit data (α1+α2+α3+α4) and outputting the same to the CPU 10 by way of the CPU bus 20 (Step C 4 ). On the other hand, when an ECC error is found in the Step C 3 , the flow is jumped to the step C 7 where the ECC error is judged correctable or not.

[0098] For example, as shown in FIG. 3 , the parity-generation/check/reconfiguration circuit 5 reads the four 16-bit data α1, α2, α3,and α4 from the corresponding DIMMs 1 - 0 to 1 - 3 , respectively, and reads the 16-bit first parity code from the DIMM 1 - 4 (Step C 1 ). Thereafter, the circuit 5 blocks or combines the 16-bit data α1, α2, α3,and α4 together to reconstitute the 64-bit input data ( 60 1+α2+α3+α4). At this time, the circuit 5 generates a second parity code p 1 ′ through an Exclusive OR operation of the four parts of the data α1, α2, α3,and α4 thus read. Thereafter, the circuit 5 compares the second parity code p 1 ′ thus generated with the first parity code p 1 read from the DIMM 1 - 4 . If the circuit 5 judges that no parity error exists at this time through the comparison of the first and second parity codes, the 64-bit input data (α1+α2+α3+α4) thus reconstituted are judged correct, and outputted to the CPU 10 by way of the CPU bus 20 (Step C 4 ).

[0099] On the other hand, when a read error is found in one of the DIMMs 1 - 0 to 1 - 4 in the Step C 2 , the memory controller 3 increments the generation count of the read error in the generation count register 71 of the error count register 7 (Step C 5 ) Thereafter, the parity-generation/check/reconfiguration circuit 5 reconfigures the 16-bit data α1, α2, α3, and α4 thus read using the first parity code p 1 , thereby forming the 64-bit correct data (α1+α2+α3+α4) (Step C 6 ). The circuit 5 outputs the 64-bit data (α1+α2+α3+α4) thus generated toward the CPU 10 by way of the CPU bus 20 (Step C 4 ).

[0100] For example, as shown in FIG. 4 , it is supposed that the parity-generation/check/reconfiguration circuit 5 judges a correctable 1-bit error exists in the 16-bit faulty sub-data B 1 read from the DIMM 1 - 0 (which corresponds to the slot No. 1 ) (Step C 2 ). In this case, the circuit 5 generates the 16-bit correct data α1 through an Exclusive OR operation of the 16-bit data α2, α3, and α4 and the 16-bit first parity code p 1 . Thereafter, the circuit 5 blocks or combines the data al thus generated with the data α2, α3, and α4, thereby reconstituting the 64-bit data (α1+α2+α3 +α4) (Step C 6 ). Then, the circuit 5 outputs the 64-bit data (α1 +α2+α3+α4) thus obtained toward the CPU 10 by way of the CPU bus 20 (Step C 4 ).

[0101] When the ECC error found in the step C 3 is judged correctable (Step C 7 ), the memory controller 3 increments the generation count of the ECC 1-bit error of the generation count register 71 in the error count register 7 (Step C 8 ). The ECC 1-bit error is corrected by a corresponding one the ECC/CHIPKILL circuits 4 - 0 to 4 - 4 . Thereafter, the parity-generation/check/reconfiguration circuit 5 reconfigures the 16-bit data α1, α2, α3,and α4 thus corrected, thereby forming the 64-bit data (α1+α2+α3+α4). The circuit 5 outputs the 64-bit data (α1+α2+α3+α4) toward the CPU 10 by way of the CPU bus 20 (Step C 4 ).

[0102] When the ECC error found in the step C 3 is judged non-correctable (Step C 7 ), the corresponding one of the ECC/CHIPKILL circuits 4 - 0 to 4 - 4 judges whether the said error is correctable by the ChipKill correction operation (Step C 9 ). When the error is judged correctable by the ChipKill correction operation in the step C 9 , the parity-generation/check/reconfiguration circuit 5 increments the generation count of the ChipKill error of the generation count register 71 in the error count register 7 (Step C 10 ). Thereafter, the circuit 5 reconfigures the 16-bit sub-data α1, α2, α3, and α4 thus corrected, thereby forming the 64-bit data (α1+α2+α3+α4). The circuit 5 outputs the 64-bit data (α1+α2+α3+α4) toward the CPU 10 by way of the CPU bus 20 (Step C 4 ).

[0103] When the error is judged non-correctable by the ChipKill correction operation in the step CD, the memory controller 3 increments the generation count of the 2-bit error of the generation count register 71 in the error count register 7 (Step C 11 ). Thereafter, the circuit 5 reconfigures the 16-bit data α1, α2, α3, and α4 using the first parity code, thereby forming the 64-bit data (α1+α2+α3+α4) (Step C 12 ). The circuit 5 outputs the 64-bit data (α1+α2+α3+α4) thus formed toward the CPU 10 by way of the CPU bus 20 (Step C 4 ).

[0104] When one of the generation counts of the ECC 1-bit error, the ECC 2-bit error, the ChipKill error, and the read error of the generation counter 71 for the DIMM slots 2 - 0 to 2 - 4 (i.e., the slot Nos. 0 , 1 , 2 , 3 , and 4 ) exceeds the predetermined threshold value in the threshold counter 72 through the comparison operation of the comparator 73 , the comparator 73 of the error count register circuit 7 outputs an interrupt signal to the CPU 10 by way of the interrupt signal line 74 .

[0105] In the following explanation, it is supposed that one of the generation counts of the ECC 1-bit error, the ECC 2-bit error, the ChipKill error, and the read error of the generation counter 71 for the DIMM slot 2 - 0 (i.e., the slot No. 0 , the DIMM 1 - 0 ) has exceeded the predetermined threshold value in the threshold counter 72 .

[0106] When the CPU 10 receives the interrupt signal from the error count register circuit 7 , a predetermined fault detection alarm is emitted to the operator of the computer system. The alarm contains some information identifying the slot No. where the fault has occurred, in other words, one of the generation counts of the generation counter 71 has exceeded the predetermined threshold value stored in the threshold register 72 .

[0107] In response to the fault detection alarm thus emitted, the operator knows the occurrence of the fault in the memory system 50 and the faulty slot No. Then, the operator removes the faulty DIMM 1 - 0 from the corresponding slot 2 - 0 (Step D 1 ). While the DIMM 1 - 0 is being removed from the slot 2 - 0 , the memory controller 3 treats the state like a read error has occurred in the slot 2 - 0 , in which the steps C 2 , C 5 , C 6 , and C 4 in FIG. 8 are carried out.

[0108] Subsequently, a new, normal DIMM is inserted into the slot 2 - 0 (Step D 2 ). At this time, in response to this insertion, the memory controller 3 clears the generation counts of the ECC 1-bit error, the ECC 2-bit error, the ChipKill error, and the read error of the generation counter 71 for the DIMMs 1 - 0 to 1 - 4 . In other words, the controller 3 assigns the value of zero to the respective counts of the counter 71 (Step D 3 ). Then, in the background of the access of the CPU 10 , the parity-generation/check/reconfiguration circuit 5 reads the parts of the 16-bit correct data α2, α3, and α4 from the three normal QIMMs 1 - 1 to 1 - 3 , respectively, and the 16-bit first parity code p 1 from the normal DIMM 1 - 4 (Step D 4 ). Thereafter, the circuit 5 reconfigures the 16-bit data al using the other 16-bit data α2, α3, and α4 and the parity code p 1 (Step D 5 ) and then, writes the correct data α1 thus obtained into the newly-inserted DIMM 1 - 0 (Step D 6 ).

[0109] In this way, the four parts of the correct data ail, α2, α3, and α4 and the parity code p 1 are written into the normal DIMMs 1 - 0 to 1 - 4 , respectively. This means that the 16-bit data (α1, α2, α3, and α4 and the parity code pi are equal to those written in the respective DIMMs 1 - 0 to 1 - 4 before the fault occurred. As a result, the data stored in the redundant memory system 50 according to the embodiment of the invention can be recovered, even if all the slots 2 - 0 to 2 - 4 are being energized, i.e., electric power is being supplied to the system 50 .

[0110] It is supposed that a correctable 1-bit error exists in the 16-bit faulty sub-data B 1 from the DIMM 1 - 0 (i.e., the slot No. 1 ) in the above-described embodiment. However, it is needless to say that the same operation as above is carried out when an error exists in one of the other DIMMs 1 - 1 to 1 - 4 .

[0111] With the redundant memory system 50 according to the embodiment of the invention, as explained above in detail, the following advantages are obtainable.

[0112] (i) Redundancy can be given to the DIMMs 1 - 0 to 1 - 4 , because the parts of the data α1, α2, α3,and α4 and the parity code p 1 are generated from the input data (α1+α2+α3+α4), and the correct data α1, α2, α3,and α4 can be recovered using the parity code p 1 as necessary.

[0113] (ii) A failed one of the DIMMs 1 - 0 to 1 - 4 (i.e., the memory modules) is replaceable with a new one during the in-service state even if the OS used in the computer system does not support the memory redundancy function. This is because the reading and writing operations can be carried out in the memory space where the OS is operating even if one of the DIMMs 1 - 0 to 1 - 4 is failed.

[0114] (iii) Dynamic replacement of the DIMMs 1 - 0 to 1 - 4 is realizable during the in-service or energized state by simply using hot-plugging DIMM slots according to the definition by JEDEC.

[0115] (iv) The system availability is improved because dynamic replacement of the DIMMs 1 - 0 to 1 - 4 is realizable.

VARIATIONS

[0116] It is needless to say that the invention is not limited to the above-described embodiment. Any modification is applicable to the embodiment. For example, the memory modules used in the above embodiment are in the form of the DIMM. However, any other form (e.g., SIMM) of memory modules may be used if it is replaceable in the energized state of a computer system.

[0117] While the preferred forms of the present invention have been described, it is to be understood that modifications will be apparent to those skilled in the art without departing from the spirit of the invention. The scope of the present invention, therefore, is to be determined solely by the following claims.